Method for controlling flash memory module and related flash memory controller and memory device
By determining whether there are data pages in the block with unwritten data in the flash memory module and writing them to redundant data, the problem of erasing half-full blocks affecting subsequent write operations is solved, and the data quality is improved. Avoid data page corruption.
Patent Information
- Application Number
- CN202410114945.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-07
- Filing Date
- 2024-01-26
- Publication Date
- 2025-02-14
AI Technical Summary
In the flash memory module, if some blocks whose data pages have not been written to have data, it may affect the subsequent write operations of this block, thereby reducing the quality of the data.
A method of accessing flash memory modules is proposed, by first determining whether the block has unwritten data pages and writing them to redundant data to ensure that the block is fully full before erasing.
It effectively avoids the impact of erasing half-full blocks on subsequent write operations, improves the quality of data, and avoids the possible damage to data pages due to repeated writes.
Smart Images
Figure CN119440389A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to flash memory. Background Art
[0002] In a flash memory module, a block is used as an erase unit, that is, the erase operation can only be performed on a block basis, and the data of the memory cells of all data pages in the block will be erased together. However, for some flash memory modules, if the erase operation is performed on a block where some data pages have not been written, it may affect the subsequent writing operation of this block, thereby reducing the quality of the data stored in the block. Summary of the invention
[0003] Therefore, one of the purposes of the present invention is to provide a method for accessing a flash memory module, which can efficiently determine whether a block has data pages with unwritten data before the block is erased, and write redundant data into the data pages with unwritten data to solve the problems described in the prior art.
[0004] In one embodiment of the present invention, a method for controlling a flash memory module is disclosed, wherein the flash memory module includes a plurality of dies, each of which includes a plurality of blocks, each of which includes a plurality of data pages, and the method includes: selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; for each first block in the super block, determining whether the first block is a full block or a completely empty block; and if the first block is not the full block or the completely empty block, writing a redundant data into the first block so that the first block becomes the full block; and erasing the plurality of first blocks in the super block so that the plurality of first blocks become a plurality of blank blocks.
[0005] In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of dies, each of the dies includes a plurality of blocks, each of the blocks includes a plurality of data pages, and the flash memory controller includes a read-only memory and a microprocessor, and the microprocessor is used to perform the following operations: selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; for each first block in the super block, determining whether the first block is a full block or a full empty block; and if the first block is not the full block or the full empty block, writing a redundant data into the first block so that the first block becomes the full block; and erasing the plurality of first blocks in the super block so that the plurality of first blocks become a plurality of blank blocks.
[0006] In one embodiment of the present invention, a memory device is disclosed, which includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of dies, each of which includes a plurality of blocks, and each of which includes a plurality of data pages. The flash memory controller is used to access the flash memory module, and the flash memory controller performs the following operations: selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; for each first block in the super block, determining whether the first block is a full block or a full empty block; and if the first block is not the full block or the full empty block, writing a redundant data into the first block so that the first block becomes the full block; and erasing the plurality of first blocks in the super block so that the plurality of first blocks become a plurality of blank blocks. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 FIG. 4 is a schematic diagram of a memory device according to an embodiment of the present invention.
[0008] Figure 2 FIG. 4 is a schematic diagram of a super block according to an embodiment of the present invention.
[0009] Figure 3 A schematic diagram of multiple data pages contained in a block.
[0010] Figure 4 FIG. 4 is a flow chart of a control method of a memory device according to an embodiment of the present invention.
[0011]
Explanation of symbols
[0012] 100: Memory device
[0013] 110: Flash memory controller
[0014] 112: Microprocessor
[0015] 112M: Read-only memory
[0016] 112C: Programming code
[0017] 114: Control Logic
[0018] 116: Buffer memory
[0019] 118: Interface Logic
[0020] 120: Flash memory module
[0021] 130: Main device
[0022] 132: Encoder
[0023] 134:Decoder
[0024] 136: Randomizer
[0025] 138:De-Randomizer
[0026] 140: DRAM
[0027] 202,204:Super Block
[0028] 300: Block
[0029] 400~416: Steps
[0030] B1~BK: Block
[0031] P1~P448: Data page DETAILED DESCRIPTION
[0032] Figure 1 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The ROM 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the flash memory module 120. The control logic 114 includes an encoder 132, a decoder 134, a randomizer 136, and a de-randomizer 138, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or error correction code, ECC), the decoder 134 is used to decode the data read from the flash memory module 120, the randomizer 136 is used to perform a randomization operation on the data written into the flash memory module 120, and the de-randomizer 138 is used to perform a de-randomization operation on the data read from the flash memory module 120.
[0033] In a typical case, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks. The flash memory controller 110 performs operations such as copying, erasing, and merging data on the flash memory module 120 in units of blocks. In addition, a block can record a specific number of data pages, and the flash memory controller 110 performs operations such as writing data to the flash memory module 120 in units of data pages. In other words, a block is a minimum erase unit in the flash memory module 120, and a data page is a minimum write unit in the flash memory module 120.
[0034] In practice, the flash memory controller 110 that executes the program code 112C through the microprocessor 112 can use its own internal components to perform many control operations, such as: using the control logic 114 to control the access operation of the flash memory module 120 (especially the access operation to at least one block or at least one data page), using the buffer memory 116 and / or a dynamic random access memory (DRAM) 140 to perform the required buffer processing, and using the interface logic 118 to communicate with a host device 130.
[0035] In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card that complies with SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device that can be connected to the memory device, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage device that complies with Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and is disposed in an electronic device, such as a mobile phone, a watch, a portable medical detection device (e.g., a medical bracelet), a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.
[0036] Figure 2 FIG. 1 is a schematic diagram of a super block according to an embodiment of the present invention. Figure 2As shown, it is assumed that the flash memory module 120 includes four dies (die 1 to die 4), and each die includes a plurality of blocks B1 to BK. At this time, the microprocessor 112 can configure the blocks belonging to different data planes or different dies in the flash memory module 120 as a super block to facilitate the management of data access. In this embodiment, it is illustrated that a die has only one data plane, but the present invention is not limited to this. Figure 2 As shown, die 1 to die 4 include blocks B1 to BK respectively, and the microprocessor 112 can configure the block B1 of each die as a super block 202, and the block B2 of each die as a super block 204, and so on, and the flash memory controller 110 is similar to a general block when accessing the super blocks 202 and 204. For example, the super block 202 itself is an erase unit, that is, although the four blocks B1 included in the super block 202 can be erased separately, the flash memory controller 110 will definitely erase the four blocks B1 together.
[0037] In addition, reference Figure 3 Schematic diagram of block 300 shown, where block 300 may be Figure 2 Any of the blocks B1 to BK shown, and the block 300 includes multiple data pages, such as 448 data pages shown. When writing data to the super block 202, the data can be written sequentially from the first data page P1 of the block B1 of the die 1, the first data page P1 of the block B1 of the die 2, the first data page P1 of the block B1 of the die 3, and the first data page P1 of the block B1 of the die 4, and then the data is sequentially written to the second data page P2 of the block B1 of the die 1, the second data page P2 of the block B1 of the die 2, ..., and so on. In other words, the flash memory controller 110 will write the data to the first data page P1 of each block B1 in the super block 202, and then write the data to the second data page P2 of each block B1 in the super block 202. The super block is a logically set block, not a physical set block, by the flash memory controller 110 for convenient management of the flash memory module 120. In addition, when performing garbage collection, calculating block valid pages, and calculating the length of block write time, calculations can also be performed using super blocks as units.
[0038] In the present embodiment, the flash memory module 120 is a 3D NAND-type flash memory module, wherein each block is composed of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Since the 3D NAND-type flash memory architecture is well known to those skilled in the art, it will not be described in detail in the specification.
[0039] Figure 4 4 is a flow chart of a control method of a memory device 100 according to an embodiment of the present invention. In step 400, the process starts and the memory device 100 is powered on. In step 402, the microprocessor 112 in the flash memory controller 110 determines whether there is a super block that needs to be erased. If so, the process proceeds to step 404; if not, the process stays at step 402 and continues to determine whether there is a super block that needs to be erased. For example, the microprocessor 112 may record in the buffer memory 116 which super blocks in the flash memory module 120 are currently in an erasable state (i.e., all data in the super blocks are invalid data), and when the microprocessor 112 needs to write data from the host device 130 to the flash memory module 120, or needs to perform a garbage collection operation on some blocks in the flash memory module 120, or any other operation that requires a blank block for data writing, the microprocessor 112 determines that there is a super block that needs to be erased to generate at least one blank super block for subsequent use, and the microprocessor 112 selects at least one of the super blocks that are in an erasable state. In the following description, it is assumed that the super block 202 needs to be erased.
[0040] In step 404 , the microprocessor 112 selects a block from the super block 202 , such as block B1 of die 1 . In step 406 , the microprocessor 112 determines whether the selected block is a full block or a blank block. If so, the process proceeds to step 412 ; otherwise, the process proceeds to step 408 . Specifically, the microprocessor 112 may first read the first data page P1 of the selected block to determine whether the first data page P1 has written data. For example, since the microprocessor 112 obtains a logic value "1" when reading each memory cell of the blank data page, the microprocessor 112 may determine whether the first data page P1 has written data by determining whether the proportion of the logic value "1" in the content of the first data page P1 is higher than a threshold value. In another example, the microprocessor 112 may read the content of the spare region of the first data page P1 to determine whether there is written data, that is, if the spare region of the first data page P1 contains valid data, it is determined that there is written data, and if the spare region of the first data page P1 only contains invalid data (for example, all logic values "1"), it is determined that the first data page P1 is a blank data page. Then, the microprocessor 112 reads the last data page P448 of the selected block to determine whether the last data page P448 has written data. If both the first data page P1 and the last data page P448 have written data, the selected block is determined to be a full block and the process proceeds to step 412, and if both the first data page P1 and the last data page P448 are blank, the selected block is determined to be a blank block and the process proceeds to step 412. In addition, if the first data page P1 has written data, but the last data page P448 is blank, the selected block is determined to be neither a full block nor a blank block (i.e., half-full state), and the process proceeds to step 408.
[0041] In step 408, the microprocessor 112 uses a binary search method or any other suitable search method to search for the last data page with data written in the selected block. In step 410, the microprocessor 112 writes redundant data (dummy data) to all blank data pages after the last data page with data written in the selected block, so that all data pages of the selected block have written data and become a full block, wherein the redundant data can be invalid data with any data pattern and does not correspond to any logical address of the host device 130. Figure 3 To illustrate, if the microprocessor 112 determines that the last data page in the block 300 to which data is written is PA, the microprocessor 112 will write redundant data into all the data pages P(A+1)-PK.
[0042] In step 412 , the microprocessor 112 determines whether all blocks in the super block 202 have been processed (ie, through step 40 ). If so, the process proceeds to step 416 ; if not, the process proceeds to step 414 .
[0043] In step 414 , the microprocessor 112 selects the next unprocessed block in the super block 202 , such as block B1 of die 2 , and then the process returns to step 406 .
[0044] In step 416, since all blocks in the super block 202 are full blocks or blank blocks, the microprocessor 112 can generate a control signal to the flash memory module 120 to erase all blocks in the super block 202, so that all blocks in the super block 202 become blank blocks for subsequent use.
[0045] exist Figure 4 In the embodiment, since all blocks in the super block 202 are already full blocks or blank blocks when erasing, the problem in the prior art that erasing a half-full block affects subsequent write operations on this block can be avoided.
[0046] In addition, since some flash memory modules do not allow double programming, that is, a data page that has been written with data cannot be written again before being erased, the above steps 408 and 410 can avoid the problem of data pages being permanently damaged due to double programming.
[0047] In another embodiment, if the flash memory module 120 itself allows repeated writing, step 408 can be automatically Figure 4 The process is removed, and step 410 is modified to the microprocessor 112 directly writing the data redundancy data to all data pages in the selected block, that is, Figure 3 The data pages P1 to P448 will all be written with redundant data in sequence.
[0048] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.
Claims
1. A method for controlling a flash memory module, wherein the flash memory module comprises a plurality of dies, each of which comprises a plurality of blocks, each of which comprises a plurality of data pages, and the method comprises: Selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; For each first block in the super block, determining whether the first block is a full block or a completely empty block; and if the first block is not the full block or the empty block, writing redundant data into the first block so that the first block becomes the full block; as well as The first blocks in the super block are erased to make the first blocks become blank blocks.
2. The method according to claim 1, characterized in that The steps to select the superblock include: When the flash memory module needs one or more blank blocks for data writing operation, the super block is selected from a plurality of super blocks in an erasable state.
3. The method according to claim 1, characterized in that For each first block in the super block, the step of determining whether the first block is the full block or the empty block comprises: Reading a first data page of the first block to determine whether the first data page has written data; Reading the last data page of the first block to determine whether the last data page has written data; If both the first data page and the last data page have written data, determining that the first block is the full block; and If the first data page and the last data page have no data written therein, it is determined that the first block is the completely empty block.
4. The method according to claim 1, characterized in that If the first block is not the full block or the empty block, the step of writing the redundant data into the first block so that the first block becomes the full block comprises: The redundant data is sequentially written into all the blank data pages starting from the first blank data page of the first block, so that the first block becomes the full block.
5. The method according to claim 1, characterized in that If the first block is not the full block or the empty block, the step of writing the redundant data into the first block so that the first block becomes the full block comprises: The redundant data is sequentially written from the first data page of the first block to the last data page of the first block, so that the first block becomes the full block.
6. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of dies, each of which includes a plurality of blocks, each of which includes a plurality of data pages, and the flash memory controller includes: A read-only memory for storing a program code; a microprocessor for executing the program code to control access to the flash memory module; The microprocessor is used to perform the following operations: Selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; For each first block in the super block, determining whether the first block is a full block or a completely empty block; and if the first block is not the full block or the empty block, writing redundant data into the first block so that the first block becomes the full block; as well as The first blocks in the super block are erased to make the first blocks become blank blocks.
7. The flash memory controller according to claim 6, wherein: The steps to select the superblock include: When the flash memory module needs one or more blank blocks for data writing operation, the super block is selected from a plurality of super blocks in an erasable state.
8. The flash memory controller according to claim 6, wherein: For each first block in the super block, the step of determining whether the first block is the full block or the empty block comprises: Reading a first data page of the first block to determine whether the first data page has written data; Reading the last data page of the first block to determine whether the last data page has written data; If both the first data page and the last data page have written data, determining that the first block is the full block; and If the first data page and the last data page have no data written therein, it is determined that the first block is the completely empty block.
9. The flash memory controller according to claim 6, wherein: If the first block is not the full block or the empty block, the step of writing the redundant data into the first block so that the first block becomes the full block comprises: The redundant data is sequentially written into all the blank data pages starting from the first blank data page of the first block, so that the first block becomes the full block.
10. The flash memory controller according to claim 6, wherein: If the first block is not the full block or the empty block, the step of writing the redundant data into the first block so that the first block becomes the full block comprises: The redundant data is sequentially written from the first data page of the first block to the last data page of the first block, so that the first block becomes the full block.
11. A memory device comprising: A flash memory module comprising a plurality of dies, each of which comprises a plurality of blocks, each of which comprises a plurality of data pages; and a flash memory controller for accessing the flash memory module; The flash memory controller performs the following operations: Selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; For each first block in the super block, determining whether the first block is a full block or a completely empty block; and if the first block is not the full block or the empty block, writing redundant data into the first block so that the first block becomes the full block; as well as The first blocks in the super block are erased to make the first blocks become blank blocks.
12. The memory device of claim 11, wherein the step of selecting the super block comprises: When the flash memory module needs one or more blank blocks for data writing operation, the super block is selected from a plurality of super blocks in an erasable state.
13. The memory device according to claim 11, characterized in that For each first block in the super block, the step of determining whether the first block is the full block or the empty block comprises: Reading a first data page of the first block to determine whether the first data page has written data; Reading the last data page of the first block to determine whether the last data page has written data; If both the first data page and the last data page have written data, determining that the first block is the full block; and If the first data page and the last data page have no data written therein, it is determined that the first block is the completely empty block.
14. The memory device according to claim 11, wherein: If the first block is not the full block or the empty block, the step of writing the redundant data into the first block so that the first block becomes the full block comprises: The redundant data is sequentially written into all the blank data pages starting from the first blank data page of the first block, so that the first block becomes the full block.
15. The memory device according to claim 11, characterized in that If the first block is not the full block or the empty block, the step of writing the redundant data into the first block so that the first block becomes the full block comprises: The redundant data is sequentially written from the first data page of the first block to the last data page of the first block, so that the first block becomes the full block.