Management command techniques for stacked memory architectures

Abstract

The invention relates to management command techniques for stacked memory architectures. For example, a system may be configured to support management command signaling between a controller (e.g., of a host system) of a first semiconductor die and interface circuitry (e.g., of a memory system), the first semiconductor die is configured for accessing one or more memory arrays of one or more second semiconductor dies (e.g., of a memory system). The interface circuitry may be configured to schedule or otherwise determine that a management operation is to be performed, and may indicate aspects requesting the controller to schedule the management operation. In response, the controller may indicate one or more commands to the interface circuitry to perform the management operation.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 771,865, entitled “MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES,” filed by Liu et al. on July 12, 2024, and U.S. patent application No. 63 / 516,193, entitled “MANAGEMENT COMMAND TECHNIQUES FOR STACKED MEMORY ARCHITECTURES,” filed by Liu et al. on July 28, 2023, each of which is assigned to its assignee and the entire contents of each of which are expressly incorporated herein by reference.

[0003] The technical field relates to one or more systems for memory, including management command techniques for stacked memory architectures. Background Art

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored by the memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described according to volatile configurations or non-volatile configurations. Memory cells in non-volatile configurations can maintain a stored logic state for a long time, even in the absence of external power. Memory cells in volatile configurations lose their stored state when disconnected from external power. Summary of the invention

[0006] A method is described. The method may include: transmitting a request from an interface of a second semiconductor die to a controller of the second semiconductor die to cause the controller to schedule the interface to perform a management operation associated with a memory array of one or more first semiconductor die coupled to the second semiconductor die; receiving a sequence of a plurality of first commands for the management operation from the controller at the interface based on the request; and transmitting one or more second commands from the interface to at least one of the one or more first semiconductor die to perform the management operation on the memory array, the one or more second commands each corresponding to one of the first commands.

[0007] A method is described. The method may include: receiving, at a controller of a second semiconductor die, a request from an interface of the second semiconductor die to cause the controller to schedule the interface to perform a management operation associated with one or more memory arrays of one or more first semiconductor die coupled to the second semiconductor die; determining, at the controller, a sequence of a plurality of commands for the management operation based on the request; and transmitting, from the controller to the interface, the sequence of a plurality of commands for the management operation based on the determination.

[0008] An apparatus is described. The apparatus may include a second semiconductor die including a controller and an interface coupled to the controller, the interface including circuitry operable to: transmit a request to the controller to cause the controller to schedule the interface to perform a management operation associated with one or more memory arrays of one or more first semiconductor dies coupled to the second semiconductor die; receive a sequence of a plurality of first commands for the management operation from the controller based on the request; and transmit one or more second commands to at least one of the one or more first semiconductor dies to perform the management operation on the memory array, the one or more second commands each corresponding to one of the first commands.

[0009] An apparatus is described. The apparatus may include a second semiconductor die including a controller and an interface coupled to the controller, the controller including circuitry operable to: receive a request for the controller to schedule the interface to perform a management operation associated with one or more memory arrays of one or more first semiconductor dies coupled to the second semiconductor die; determine a sequence of a plurality of commands for the management operation based on the request; and transmit the sequence of a plurality of commands for the management operation from the controller to the interface based on the determination.

[0010] A system is described. The system may include: one or more first semiconductor dies including: one or more memory arrays; and one or more first interfaces, each of which includes a first circuit system operable to access at least one corresponding memory array of the one or more memory arrays; and a second semiconductor die coupled to the one or more first semiconductor dies. The second semiconductor die may include one or more controllers, each controller operable to: receive a command to access the one or more memory arrays; and schedule access to the one or more memory arrays based on receiving the access command. The second semiconductor die may also include one or more second interfaces coupled to the one or more controllers, each second interface including a second circuit system, the second circuit system operable to: transmit a request to the corresponding controller to have the corresponding controller schedule the second interface to perform a management operation associated with a memory array of the one or more memory arrays; receive a sequence of a plurality of first commands for the management operation from the corresponding controller based on the request; and transmit one or more second commands to the first interface corresponding to the memory array to perform the management operation on the memory array, the one or more second commands each corresponding to one of the first commands. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system supporting management command techniques for a stacked memory architecture according to examples disclosed herein is presented.

[0012] Figure 2 An example of a system supporting management command techniques for a stacked memory architecture according to examples disclosed herein is presented.

[0013] Figure 3 and 4 An example of an interface architecture supporting management command techniques for a stacked memory architecture according to examples disclosed herein is shown.

[0014] Figure 5An example of a process supporting management command techniques for a stacked memory architecture according to examples disclosed herein is presented.

[0015] Figure 6 A block diagram showing a memory interface supporting management command techniques for a stacked memory architecture according to examples disclosed herein.

[0016] Figure 7 A block diagram of a memory controller supporting management command techniques for a stacked memory architecture according to examples disclosed herein is shown.

[0017] Figure 8 and 9 A flow chart illustrating a method of supporting management command techniques for a stacked memory architecture according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0018] Some memory systems may include a stack of semiconductor dies, including one or more memory dies (e.g., array dies) stacked with a logic die, the logic die being operable to access a set of memory arrays distributed across the one or more memory dies. This stacked architecture may be implemented as part of a tightly coupled dynamic random access memory (TCDRAM) system, and may support solutions for memory-centric logic, such as a graphics processing unit (GPU) and other implementations. In some examples, the TCDRAM system may be tightly coupled (e.g., physically coupled, electrically coupled, directly coupled) to a processor (e.g., a GPU or other host) as part of a physical memory map accessible to the processor. This coupling may include one or more processors implemented in the same semiconductor die as at least a portion of the TCDRAM system (e.g., as part of the logic die) or one or more processors implemented in a die that is directly coupled (e.g., fused) to another die that includes at least a portion of the TCDRAM system or otherwise coupled to another die that includes at least a portion of the TCDRAM system (e.g., via a silicon interposer or other interposer component). Unlike cache-based memory, the TCDRAM system may not be supported by external memory levels with the same physical address. For example, the TCDRAM system may be associated with and located within a dedicated base address, wherein each portion of the TCDRAM system may not overlap within the address.

[0019] In some embodiments, a memory system (e.g., a TCDRAM system) may perform management operations (e.g., memory management operations) to support or maintain operational characteristics of the memory system (e.g., performance characteristics for operating one or more memory arrays of the memory system). For example, such management operations may include refresh operations, adverse access (e.g., row hammer) mitigation operations, scrubbing operations, repair operations, or other operations. In some examples, the logic of the memory system may be configured to determine when to perform management operations, which may involve coordination (e.g., timing, negotiation) of the management operations with a host system coupled to the memory system. For example, management operations of the memory system may be coordinated with access operations (e.g., write operations, read operations) commanded by the host system to support applications of the host system.

[0020] According to examples disclosed herein, a system may be configured to support management command signaling between a controller (e.g., of a host system) of a first semiconductor die and an interface circuit system (e.g., of a memory system, a memory interface block), the first semiconductor die being configured to access one or more memory arrays (e.g., of a memory system) of one or more second semiconductor dies. For example, the interface circuit system may be configured to schedule or otherwise determine that a management operation is to be performed, and may indicate (e.g., signal) an aspect requesting the controller to schedule the management operation. In response, the controller may indicate one or more commands to the interface circuit system to perform the management operation.

[0021] By supporting such management command signaling, the described techniques may support various improvements to the operation of a system including a host system and a memory system. For example, by providing such an indication as a request for aspects of scheduling a management operation (e.g., as a flexible request, as a request that may not be associated with an immediate response), the host system may be enabled to coordinate the management operation with other operations (e.g., operations that support functions or applications of the host system), such as access operations to one or more memory arrays of the memory system in support of an application of the host system. Such techniques may allow the host system to prioritize relatively higher priority access operations over the requested management operation. In some instances, such a request may include an indication of a duration within which the management operation will be performed, which may support management operation commands scheduled by the host system within a threshold duration that supports satisfying an operational characteristic of the memory system (e.g., reliability). In some instances, a management operation may be associated with a group (e.g., a sequence) of multiple operations (e.g., sub-operations, DRAM operations) such that a single request indication may be responded to with an indication of a group of multiple commands in a manner that reduces request or command signaling (e.g., from the interface circuitry to the controller). In some embodiments, such techniques may leverage existing command groups (e.g., a set of DRAM commands, a set of commands according to a standardized interface protocol), which may support relatively simplified specification definitions, relatively simplified scheduling at the host system, and relatively flexible design or modification of memory system interface circuitry, among other benefits.

[0022] Features of the present disclosure are illustrated and described in the context of systems and dies. Features of the present disclosure are further illustrated and described in the context of interface architectures, signaling diagrams, block diagrams, and flow charts.

[0023] Figure 1 An example of a system 100 that supports management command techniques for a stacked memory architecture according to examples disclosed herein is shown. The system 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, or other system. The system 100 includes a host system 105, a memory system 110, and one or more channels 115 (e.g., for providing a communicative coupling) coupling the host system 105 with the memory system 110. The system 100 may include one or more memory systems 110, but aspects of the one or more memory systems 110 may be described in the context of a single memory system 110.

[0024] The host system 105 may be an example of a processing system (e.g., circuitry, one or more processors, an application processing system, a processing circuitry, one or more processing components) that uses memory to perform processes (e.g., applications, functions, calculations), such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a wearable device, an Internet connection device, a vehicle controller, a system on a chip (SoC), or other fixed or portable electronic devices, among other examples. The host system 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., peripheral components, input / output controllers (not shown)). The components of the host system 105 may be coupled to each other using a bus 135.

[0025] The external memory controller 120 may be configured to enable communication of information (e.g., data, commands, control information, configuration information) between components of the system 100, such as between components of the host system 105 (e.g., the processor 125) and the memory system 110. For example, the external memory controller 120 may generate commands (e.g., in response to or otherwise in support of an application of the host system 105) to write data to or read data from the memory system 110 or otherwise communicate with the memory system 110. The external memory controller 120 may process (e.g., convert, translate) communications exchanged between the host system 105 and the memory system 110. In some examples, the external memory controller 120 or other components of the system 100 or associated functionality described herein may be implemented by or be part of the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software (e.g., instructions), or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host system 105. Although the external memory controller 120 is illustrated as being external to the memory system 110, in some examples, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory system 110 (e.g., the memory system controller 155, the local memory controller 165), or vice versa. In various examples, the host system 105 or the external memory controller 120 may be referred to as a host.

[0026] Processor 125 is operable to provide functionality (e.g., control functionality, processing functionality) for system 100 or host system 105. Processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof (e.g., as one or more processing components that are individually or collectively configured to support an application of host system 105). In some examples, processor 125 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples.

[0027] In some examples, system 100 or host system 105 may include input components, output components, or a combination thereof. Input components may include sensors, microphones, keyboards, another processor (e.g., on a printed circuit board), interfaces (e.g., user interfaces, interfaces between other devices), or peripheral devices that interface with system 100 via one or more peripheral components, as well as other examples. Output components may include displays, audio speakers, printing devices, another processor on a printed circuit board, or peripheral devices that interface with system 100 via one or more peripheral components, as well as other examples.

[0028] The memory system 110 may be a component of the system 100 that is operable to provide physical memory locations (e.g., addresses) that may be used or referenced by the system 100 (e.g., by the host system 105). The memory system 110 may include a memory system controller 155 and one or more memory dies 160 (e.g., memory dies) to support capacity for data storage. The memory system 110 may be configured to work with one or more different types of host systems 105, and may respond to and execute commands provided by the host system 105 (e.g., via the external memory controller 120). For example, the memory system 110 (e.g., the memory system controller 155) may receive a write command indicating that the memory system 110 will store data received from the host system 105, or receive a read command indicating that the memory system 110 will provide data stored in the memory die 160 to the host system 105, or receive a refresh command indicating that the memory system 110 will refresh data stored in the memory die 160, as well as other types of commands and operations.

[0029] The memory system controller 155 may include components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 155 may include hardware, firmware, or instructions that enable the memory system 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the operation of the memory system 110. The memory system controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the memory system controller 155 may cooperate with the local memory controller 165 of the memory die 160 to control the operation of the memory system 110.

[0030] Each memory die 160 may include one or more local memory controllers 165 and one or more memory arrays 170. A memory array 170 may be a collection of memory cells, each of which is operable to store one or more bits of data. A memory array 170 may include a two-dimensional (2D) array of memory cells or a three-dimensional (3D) array of memory cells. In some examples, a two-dimensional (2D) memory die 160 may include a single memory array 170. In some examples, a three-dimensional (3D) memory die 160 may include two or more memory arrays 170, which may be stacked on top of each other or positioned side-by-side (e.g., relative to a substrate).

[0031] The local memory controller 165 may include components (e.g., circuitry, logic, instructions) operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate (e.g., receive or transmit data or commands or both) with the memory system controller 155. In some examples, the memory system 110 may not include a memory system controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the memory system controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or any combination thereof. Examples of components that may be included in the memory system controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, a sensing component for sensing states of memory cells of the memory array 170, a writing component for writing states to memory cells of the memory array 170, or various other components operable to support the described operations of the memory system 110.

[0032] The host system 105 (e.g., external memory controller 120) and the memory system 110 (e.g., memory system controller 155) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission media, electrical conductors, conductive paths) between terminals associated with components of the system 100. For example, a channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at the host system 105 and a second terminal at the memory system 110. A terminal may be an example of a conductive input or output point of a device of the system 100, and a terminal may be operable to serve as part of a channel 115. In some implementations, at least the channel 115 between the host system 105 and the memory system 110 may include or be referred to as a host interface (e.g., a physical host interface). In some implementations, the host interface may include or be associated with interface circuitry (e.g., signal drivers, signal latches) at the host system 105 (e.g., at the external memory controller 120) or at the memory system 110 (e.g., at the memory system controller 155), or both.

[0033] In some examples, channels 115 (e.g., associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channels 115 may include one or more command and address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, signaling may be conveyed via channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on either a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols of a signal may be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0034] In some examples, at least a portion of the system 100 may implement a stacked die architecture in which multiple semiconductor dies are physically and communicatively coupled. In some such implementations, circuitry for accessing one or more memory arrays 170 (e.g., circuitry of the memory system 110) may be distributed among multiple semiconductor dies in a stack (e.g., a stack of multiple directly coupled semiconductor dies). For example, a first die may include a set of multiple first interface blocks (e.g., a memory interface block, an example of a first interface circuitry) and one or more second dies may include corresponding second interface blocks each coupled to the first interface block of the first die, each of which is configured to access one or more memory arrays of the second die. In some examples, the system may include a controller for each set of one or more first interface blocks (e.g., a memory controller, a host interface controller, at least a portion of the external memory controller 120) to support access operations (e.g., accessing one or more memory arrays 170) via the set of first interface blocks. In some examples, such controllers may be located in the same first die as the first interface blocks.

[0035] The memory system 110 may perform management operations (e.g., memory management operations) to support or maintain operational characteristics of the memory system 110 (e.g., performance characteristics for operating one or more memory arrays 170, performance characteristics for operating one or more memory dies 160). For example, such management operations may include refresh operations, adverse access (e.g., row hammer) mitigation operations, scrubbing operations, repair operations, or other operations. In some examples, logic of the memory system 110 (e.g., memory system controller 155, local memory controller 165) may be configured to determine when to perform management operations, which may involve coordination (e.g., scheduling, negotiation) of management operations with the host system 105. For example, management operations of the memory system 110 may be coordinated with access operations (e.g., write operations, read operations) commanded by the host system 105 to support applications of the host system 105.

[0036] According to examples disclosed herein, the system 100 may be configured to support management command signaling between a controller of a first semiconductor die (e.g., a controller of a host system 105, such as aspects of an external memory controller 120) and an interface circuit system (e.g., an interface circuit system of a memory system 110, a memory interface block), the first semiconductor die being configured to access one or more memory arrays of one or more second semiconductor dies (e.g., of the memory system 110). For example, the interface circuit system may be configured to schedule or otherwise determine that a management operation is to be performed, and may indicate (e.g., signal) aspects requesting the controller to schedule the management operation. In response, the controller may indicate one or more commands to the interface circuit system to perform the management operation.

[0037] By supporting such management command signaling, the described techniques may support various improvements to the operation of the system 100. For example, by providing such an indication as a request to schedule an aspect of a management operation (e.g., as a flexible request, as a request that may not be associated with an immediate response), the host system 105 (e.g., the external memory controller 120, a scheduling component of the host system 105) may be enabled to coordinate the management operation with other operations (e.g., operations supporting functions or applications of the host system 105), such as access operations to one or more memory arrays of the memory system 110 in support of applications of the host system 105. Such techniques may allow the host system 105 to prioritize relatively higher priority access operations over management operations requested by the memory system 110. In some examples, such a request may include an indication of a duration within which the management operation is to be performed, which may support scheduling of management operation commands by the host system 105 within a threshold duration that supports satisfying an operational characteristic of the memory system 110. In some examples, the management operation may be associated with a group (e.g., a sequence) of multiple operations (e.g., sub-operations, DRAM operations) such that a single request indication from the memory system 110 may be responded to by the host system 105 with an indication of a group of multiple commands in a manner that reduces command signaling (e.g., from the memory system 110 to the host system 105). In some implementations, such techniques may leverage an existing command group (e.g., a group of DRAM commands, a group of commands according to a standardized interface protocol), which may support relatively simplified specification definitions, relatively simplified scheduling at the host system 105, and relatively flexible design or modification of the interface circuitry of the memory system 110, among other benefits.

[0038] In addition to being applied in the systems described herein, the management command techniques for stacked memory architectures may generally be implemented to support artificial intelligence or machine learning applications and other types of computationally intensive applications. As the use of artificial intelligence increases to support machine learning, analysis, decision making, or other related applications, it may be desirable for electronic devices to support artificial intelligence applications and processes. For example, artificial intelligence applications may be associated with accessing relatively large amounts of data for analytical purposes and may benefit from memory systems that are capable of effectively and efficiently storing relatively large amounts of data or relatively quickly accessing stored data. Implementation of the techniques described herein may support artificial intelligence and machine learning techniques by improving the signaling of memory management operations and their scheduling, thereby enabling the memory interface circuitry to request memory management operations (e.g., to execute within the request duration) and enabling the host system to schedule response commands to perform memory management operations and schedule other operations, such as memory access operations. Such techniques may improve the optimization and allocation of resources between memory management and host applications, thereby supporting high-performance host applications while meeting the criteria for performance management of coupled memory arrays and other benefits.

[0039] Figure 2An example of a system 200 (e.g., a semiconductor system, a system coupling semiconductor dies, a TCDRAM system) supporting management command techniques for a stacked memory architecture according to examples disclosed herein is shown. System 200 illustrates an example of a die 205 (e.g., die 205-a, a semiconductor die, a logic die, a processor die, a host die) coupled with one or more dies 240 (e.g., dies 240-a-1 and 240-a-2, a semiconductor die, a memory die, an array die). Die 205 or die 240 may be formed using a respective semiconductor substrate (e.g., a substrate of a crystalline semiconductor material, such as silicon, germanium, silicon germanium, gallium arsenide, or gallium nitride) or a silicon-on-insulator (SOI) substrate (e.g., silicon on glass (SOG), silicon on sapphire (SOS)), or an epitaxial semiconductor material formed on another substrate, among other examples. Although the illustrated example of system 200 includes two dies 240, system 200 according to the described techniques may include any number of one or more dies 240 coupled to die 205, as well as other dies in stacked or other coupled arrangements. Furthermore, although the non-limiting examples of system 200 herein are generally described in terms of application to memory systems, memory subsystems, memory devices, or combinations thereof, examples of system 200 are not limited thereto. For example, aspects of the present disclosure may also be applied to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem for applications such as data collection, data processing, data storage, networking, communication, power, artificial intelligence, system on a chip, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

[0040] System 200 illustrates an example of interface circuitry between a host and memory (e.g., via a host interface, via a physical host interface) implemented in (e.g., divided between) multiple semiconductor dies (e.g., a stack of directly coupled dies). For example, die 205-a may include a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2, memory interface blocks), and each die 240 may include a set of one or more interface blocks 245 (e.g., access interface blocks) and one or more memory arrays 250 (e.g., die 240-a-1 includes interface block 245-a-1 coupled to a set of one or more memory arrays 250-a-1, die 240-a-2 includes interface block 245-a-2 coupled to a set of one or more memory arrays 250-a-2). Memory array 250 may be an example of memory array 170 and may include memory cells of various architectures, such as RAM, DRAM, SDRAM, SRAM, FeRAM, MRAM, RRAM, PCM, chalcogenide, NOR, or NAND memory cells, or any combination thereof.

[0041] Although the example of system 200 is illustrated as having one interface block 245 included in each die 240, a die 240 in accordance with the described techniques may include any number of one or more interface blocks 245, each coupled to a respective set of one or more memory arrays 250 and each coupled to a respective interface block 220 of die 205. Thus, the interface circuitry of system 200 may include one or more interface blocks 220 of die 205, wherein each interface block 220 is coupled (e.g., in communication) with a corresponding interface block 245 of die 240 (e.g., external to die 205). In some examples, the coupled combination of interface blocks 220 and interface blocks 245 (e.g., coupled via a bus associated with one or more channels, such as one or more data channels, one or more control channels, one or more clock channels, one or more pseudo channels, or a combination thereof) may include or be referred to as a data path associated with a respective set of one or more memory arrays 250.

[0042] In some implementations, the die 205 may include a host processor 210. The host processor 210 may be an instance of the host system 105 or a portion thereof (e.g., an aspect of the processor 125, an external memory controller 120, or both). The host processor 210 may be configured to perform operations that implement the storage of the memory array 250 (e.g., to support applications or other functions of the host system 105 that may request access to the memory array 250). For example, the host processor 210 may receive data read from the memory array 250 or may transmit data written to the memory array 250, or both (e.g., according to the application or other operation of the host processor 210). Additionally or alternatively, the host processor 210 may be external to the die 205, such as in another semiconductor die or other component that is coupled (e.g., communicatively coupled, directly coupled, bonded, coupled via another intervening component) to the die 205 via one or more contacts 212 (e.g., externally accessible terminals of the system 200).

[0043] The host processor 210 may be configured to communicate (eg, transmit, receive) signals with the interface block 220 via one or more host interfaces 216 (eg, physical host interfaces). The host interface 216 may implement a reference Figure 1In some examples, the host interface 216 can provide a communication coupling between the physical or functional boundaries of the host system 105 and the memory system 110. For example, the host processor 210 can be configured to transmit access signaling (e.g., control signaling, access command signaling, configuration signaling) via one or more host interfaces 216, and the access signaling can be received by the interface block 220 to support access operations (e.g., read operations, write operations) and other operations to the memory array 250. In some examples, the host interface 216 can include a corresponding set of one or more signal paths for each interface block 220, so that the host processor 210 can communicate with each interface block 220 via its corresponding set of signal paths (e.g., perform access operations via the interface block 220 selected by the host processor 210 according to the selection of the corresponding set). Additionally or alternatively, the host interface 216 may include one or more signal paths shared between multiple interface blocks 220 (not shown), and the interface blocks 220 or the host processor 210 or both may interpret, ignore, respond to, or suppress response to signaling via the shared signal paths of the host interface 216 based on logical indications (e.g., addressing indications associated with the interface blocks 220, interface enable signals, or interface select signals, which may be provided by the host processor 210 or the corresponding interface blocks 220, depending on the signaling direction).

[0044] In some examples, a corresponding host interface 216 may be coupled between a set of one or more interface blocks 220 and a corresponding controller 215 (e.g., host interface 216-a-1 coupled between interface block 220-a-1 and controller 215-a-1, host interface 216-a-2 coupled between interface block 220-a-2 and controller 215-a-2, host interface controller, host memory controller). Each controller 215 (e.g., controllers 215-a-1 and 215-a-2) may be an instance of a control circuit system (e.g., memory controller circuit system, host interface control circuit system) associated with the host system 105 and may be associated with a corresponding instance implementing one or more aspects of the external memory controller 120 or the memory system controller 155 or a combination thereof. The controller 215 and one or more corresponding interface blocks 220 may communicate (e.g., cooperate) to perform one or more operations associated with accessing a corresponding set of one or more memory arrays 250 (e.g., scheduling operations, access operations, operations initiated by the host processor 210). For example, each controller 215 (e.g., controllers 215-a-1 and 215-a-2) may be operable to respond to instructions (e.g., requests, commands) from the host processor 210 to access one or more memory arrays 250 to support functions or applications of the host processor 210, transmit associated commands to one or more interface blocks 220 to access one or more memory arrays 250 and communicate data with the host processor 210 (e.g., write data, read data), as well as other functions.

[0045] In some examples, one or more controllers 215 (e.g., controllers 215-a-1 and 215-a-2) may be implemented in die 205 (e.g., the same die that includes one or more interface blocks 220), whether host processor 210 is included in die 205 or external to die 205, and interface block 220 may communicate with host processor 210 via one or more controllers 215. In some other examples, controller 215 or associated circuitry or functionality may be implemented external to die 205 (e.g., in another die (not shown) coupled to respective interface blocks 220 via respective terminals of each of respective host interfaces 216), which may be in the same or different die as the die that includes host processor 210. In some other examples, aspects of one or more controllers 215 may be included in host processor 210 (e.g., as a memory interface of processor 210, as a memory interface of host system 105).

[0046] Although the example of system 200 is illustrated as including a controller 215 for each interface block 220 (e.g., controller 215-a-1 for interface block 220-a-1, controller 215-a-2 for interface block 220-a-2), in various examples, the controller 215 can be coupled with any number of one or more interface blocks 220. Additionally or alternatively, a given interface block 220 can operate based on a single controller 215 or can be operated by one or more of a group of multiple controllers 215 (e.g., according to a controller multiplexing scheme). In some examples, the controller 215 or the host interface 216 or both can be associated with a "channel group" corresponding to multiple memory arrays 250. For example, such a channel group may be associated with multiple memory arrays 250 accessed via a single interface block 245, multiple memory arrays 250 each accessed via a respective one of the interface blocks 245, or multiple memory arrays 250 each accessed via a respective one of the interface blocks 220, any of which may be associated with signaling via a single host interface 216 or a single controller 215. These and other configurations for implementing channel groups may support various techniques for parallel and high bandwidth data transfer, memory management operations, repair and replacement techniques, power and thermal distribution, and other techniques that exploit the described coupling of components and interfaces in multiple semiconductor dies (e.g., in accordance with a tightly coupled configuration of system 200).

[0047] In some examples, the host processor 210 may determine an access address (e.g., a logical address of the memory array 250, a physical address of the memory array 250, an address of the interface block 220, an address of the host interface 216, in response to an application of the host processor 210 or an application supported by the host processor 210) and determine to which controller 215 to transmit access signaling for accessing the address (e.g., a controller 215 or an interface block 220 corresponding to the address). In some examples, the address may be associated with a row of memory cells of the memory array 250, a column of memory cells of the memory array 250, or both. The host processor 210 may transmit access signaling (e.g., one or more access signals, one or more access commands) to the determination controller 215, and the determination controller 215 may in turn transmit the access signaling to the corresponding interface block 220. The corresponding interface block 220 may then transmit access signaling to the coupling interface block 245 to access the determination address (e.g., of the corresponding memory array 250).

[0048] The die 205 may also include a logic block 230 (e.g., a shared logic block, a central logic block, common logic circuitry, configuration circuitry, management circuitry, evaluation circuitry) that may be configured to communicate (e.g., transmit, receive) signaling with at least an interface block 220 of the die 205. In some cases, the logic block 230 may be configured to communicate information (e.g., commands, instructions, indications, data) with one or more interface blocks 220 to facilitate operation of the system 200. For example, the logic block 230 may be configured to transmit configuration signaling (e.g., initialization signaling, evaluation signaling, mapping signaling) that may be received by the interface block 220 to support configuration of the interface block 220 or to operate other aspects of the die 240 (e.g., via a corresponding interface block 245). The logic block 230 may be coupled to each interface block 220 via a respective bus 231 (e.g., bus 231-a-1 associated with interface block 220-a-1, bus 231-a-2 associated with interface block 220-a-2). In some examples, the respective buses 231 may each include a respective set of one or more signal paths, such that the logic block 230 may communicate with each interface block 220 via a respective set of signal paths. Additionally or alternatively, the respective bus 231 may include one or more signal paths (not shown) shared between multiple interface blocks 220.

[0049] In some implementations, logic block 230 may be configured to communicate (e.g., transmit, receive) signals with host processor 210 (e.g., via bus 232, via contacts 212 of host processor 210 external to die 205) such that logic block 230 may support an interface between interface block 220 and host processor 210. For example, host processor 210 may be configured to transmit initialization signaling (e.g., boot commands) or other configuration or operational signaling, which may be received by logic block 230 to support initialization, configuration, evaluation, or other operations of interface block 200. Additionally or alternatively, in some implementations, logic block 230 may be configured to communicate (e.g., transmit, receive) signals with components external to system 200 via bus 233 (e.g., and via contacts 234, which may be externally accessible terminals) such that logic block 230 may support an interface that bypasses host processor 210. Additionally or alternatively, logic block 230 may communicate with host processor 210 and may communicate with one or more memory arrays 250 of one or more dies 240 (e.g., for performing self-test operations to access memory arrays 250). In some examples, such implementations may support evaluation, configuration, or other operations of system 200 during manufacturing, assembly, verification, or other operations associated with system 200 (e.g., prior to coupling with host processor 210, without implementing host processor 210, for operations independent of the host processor) via one or more contacts 234 accessible at a physical interface of the system. Additionally or alternatively, logic block 230 may implement one or more aspects of controller 215. For example, logic block 130 may include or operate as one or more controllers 215 and may perform operations attributed to controller 215.

[0050] Each interface block 220 may be coupled with at least a respective bus 221 of die 205 and a respective bus 246 of die 240, which is configured to communicate signaling with the corresponding interface block 245 (e.g., via one or more associated signal paths). For example, interface block 220a-1 may be coupled with interface block 245-a-1 via bus 221-a-1 and bus 246-a-1, and interface block 220-a-2 may be coupled with interface block 245-a-2 via bus 221-a-2 and bus 246-a-2. In some examples, die 240 may include a bus, such as bus 255, that bypasses the operational circuitry of die 240 (e.g., bypasses the interface block 245 of a given die 240). For example, interface block 220-a-2 may be coupled to interface block 245-a-2 of die 240-a-2 via bus 255-a-1 of die 240-a-1, which may bypass interface block 245 of die 240-a-1. Such techniques may be extended for interconnection between more than two dies 240 (e.g., for interconnection via respective buses 255 of multiple dies 240).

[0051] The respective signal paths of the buses 221, 246, and 255 may be coupled to one another from one die to another via various arrangements of contacts at surfaces of the interfacing dies (e.g., exposed contacts, metal surfaces of the respective dies). For example, bus 221-a-1 may be coupled to bus 246-a-1 via contacts 222-a-1 of die 205-a (e.g., at a surface of die 205-a) and contacts 247-a-1 of die 240-a-1, bus 221-a-2 may be coupled to bus 255-a-1 via contacts 222-a-2 of die 205-a and contacts 256-a-1 of die 240-a-1, bus 255-a-1 may be coupled to bus 246-a-2 via contacts 257-a-1 of die 240-a-1 and contacts 247-a-2 of die 240-a-2, and so on. Although each respective bus is illustrated as having a single line coupled via a single contact, it should be appreciated that each signal path of a given bus may be associated with a respective contact to support separate communication coupling via each signal path of the given bus. In some examples, bus 255 may pass through a portion of die 240 (e.g., in an in-plane direction, along a direction different from the thickness direction, in a waterfall arrangement, in a staircase arrangement), which may support contacts 222 arranged along a surface of die 205 and other contacts coupled to an interface block 245 of a different die 240 in a stacking direction (e.g., via respective contacts 256 and 257 that do not overlap when viewed along the thickness direction).

[0052] The interconnection of the interfacing contacts may be supported by a variety of techniques. For example, in a hybrid bonding implementation, the interfacing contacts may be coupled by fusing the conductive material (e.g., electrically conductive material) of the interfacing contacts (e.g., without solder or other intervening material between the contacts). For example, in an assembled condition, the coupling of die 205-a to die 240-a-1 may include fusing the conductive material of contact 222-a-2 to the conductive material of contact 256-a-1, and the coupling of die 240-a-1 to die 240-a-2 may include fusing the conductive material of contact 257-a-1 to the conductive material of contact 247-a-2, and so on. In some examples, such coupling may include non-operational fusing of contacts (e.g., non-communication coupling, physical coupling), such as fusing of contact 260-a-1 to contact 256-a-2, neither of which is coupled to the operational circuitry of die 240-a-1 or 240-a-2. In some examples, such techniques may be implemented to improve coupling strength or uniformity (e.g., implementing contact 260 that may not be operatively coupled to interface block 245 or interface block 220), or such coupling may be a byproduct of duplication of components that may or may not be operable in various configurations (e.g., where for die 240 with co-arrangement of contacts 256 and 257, contacts 256-a-1 and 257-a-1 provide a communication path between interface block 245-a-2 and interface block 220-a-2, but contacts 256-a-2 and 257-a-2 do not provide a communication path between interface block 245 and interface block 220).

[0053] In some examples, the fusing of conductive materials between the dies (e.g., between contacts) may be accompanied by the fusing of other materials at one or more surfaces of the interfacing dies. For example, in an assembled condition, the coupling of die 205-a with die 240-a-1 may include the fusing of dielectric material 207 (e.g., non-conductive material) of die 205-a with dielectric material 242 of die 240-a-1, and the coupling of die 240-a-1 with die 240-a-2 may include the fusing of dielectric material 242 of die 240-a-1 with dielectric material 242 of die 240-a-2. In some examples, such dielectric materials may include oxides, nitrides, carbides, oxide-nitrides, oxide-carbides, or other transformations or doping of substrate materials (e.g., semiconductor substrate materials) of die 205 or die 240, as well as other materials that may support such fusing. However, the coupling between die 205 and die 240 may be implemented according to other techniques, which may implement solder, adhesives, thermal interface materials, and other intervening materials.

[0054] In some examples, the dies 240 may be coupled into a stack (e.g., to form a "cube" or other arrangement of the dies 240), and one or more of such stacks may subsequently be coupled to the die 205. In some examples, a respective group of one or more dies 240 may be coupled to each die 205 of the plurality of dies 205 formed as a wafer (e.g., in a chip-to-wafer bonding arrangement, before dicing the wafer of dies 205), and the dies 205 of the wafer each coupled to its respective group of dies 240 may be separated from each other (e.g., by dicing at least one wafer of dies 205). In some other examples, a respective group of one or more dies 240 may be coupled to a respective die 205 after the dies 205 are separated from the wafer of dies 205 (e.g., in a chip-to-chip bonding arrangement). In some other examples, a respective group of one or more wafers, each including a plurality of dies 240, may be coupled into a stack (e.g., in a wafer-to-wafer bonding arrangement). In various examples, the stack of die 240 may be separated from the coupled wafer after such techniques, or the stack of wafers with die 240 may be coupled to another wafer including multiple die 205 (e.g., in a second wafer-to-wafer bonding arrangement), after which the system 200 may be separated from the coupled die. In some other examples, the wafer-to-wafer coupling techniques may be implemented by stacking one or more wafers of die 240 (e.g., sequentially) on top of a wafer of die 205 before separation into the system 200, as well as other examples for forming the system 200.

[0055] The buses 221, 246, and 255 may be implemented to provide configuration signaling (e.g., coordination signaling, logic signaling, modulation signaling, digital signaling) between the interface block 220 and the corresponding interface block 245, which may involve various modulation or coding techniques performed by the transmission interface block (e.g., via a driver component of the transmission interface block). In some examples, this signaling may be supported (e.g., accompanied) by clock signaling communicated via the corresponding bus (e.g., coordinated with the signal transmission). For example, the bus may be configured to transmit one or more clock signals transmitted by the interface block 220 for reception by the interface block 245 (e.g., for triggering signal reception by a latch or other receiving component of the interface block 245, supporting the timing control operation of the interface block 245). Additionally or alternatively, the bus may be configured to transmit one or more clock signals transmitted by the interface block 245 for reception by the interface block 220 (e.g., for triggering signal reception by a latch or other receiving component of the interface block 220, supporting the timing control operation of the interface block 220). Such clock signals may be associated with the communication of various signaling (e.g., unidirectional communication, bidirectional communication, deterministic communication), such as control signaling, command signaling, data signaling, or any combination thereof. For example, a bus may include one or more signal paths for communicating a data bus (e.g., one or more data lanes, a DQ bus, a data interface via an interface block) according to one or more corresponding clock signals (e.g., a data clock signal) or one or more signal paths for communicating a control bus (e.g., a command / address (C / A) bus, a command interface via an interface block) according to one or more clock signals (e.g., a control clock signal), or any combination thereof.

[0056] Interface block 220, interface block 245, and logic block 230 may each include circuitry (signaling circuitry, multiplexing circuitry, processing circuitry, controller circuitry, logic circuitry, physical components, hardware) in various configurations (e.g., hardware configurations, logic configurations, software or instruction configurations) that support functionality assigned to the respective blocks for accessing or otherwise operating a corresponding set of memory arrays 250. For example, interface block 220 may include circuitry configured to perform a first subset of operations supporting access to memory arrays 250, and interface block 245 may include circuitry configured to perform a second subset of operations supporting access to memory arrays 250. In some examples, interface blocks 220 and 245 may support functional partitioning or distribution of functionality associated with memory system controller 155, local memory controller 165, or both across multiple dies (e.g., die 205 and at least one die 240). In some implementations, logic block 230 may be configured to coordinate or configure aspects of the operation of interface block 220, interface block 245, or both, and may support one or more aspects of implementing memory system controller 155. Such operations or subsets of operations may include operations performed in response to commands from host processor 210 or controller 215 or operations performed without commands from host processor 210 or controller 215 (e.g., operations determined or initiated by interface block 220, operations determined or initiated by interface block 245, operations determined or initiated by logic block 230), or various combinations thereof.

[0057] In some implementations, system 200 may include one or more instances of non-volatile storage devices (e.g., non-volatile storage device 235 of die 205, non-volatile storage device 270 of one or more dies 240, or a combination thereof). In some examples, logic block 230, interface block 220, interface block 245, or a combination thereof may be configured to communicate signaling with one or more instances of non-volatile storage devices. For example, logic block 230, interface block 220, or interface block 245 may be appropriately coupled to one or more instances of non-volatile storage devices via one or more buses (not shown) or corresponding contacts (not shown), which may each include one or more signal paths operable to communicate signaling (e.g., command signaling, data signaling). In some examples, logic block 230, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may configure one or more operations based on information (e.g., instructions, configurations, parameters) stored in one or more instances of non-volatile storage devices. Additionally or alternatively, in some examples, logic block 230, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may write information (e.g., configuration information, evaluation information) stored in one or more instances of non-volatile storage. In some examples, such non-volatile storage may include fuses, antifuses, or other types of one-time programmable storage elements, or any combination thereof.

[0058] In some embodiments, the system 200 may include one or more sensors (e.g., one or more sensors 237 of the die 205, one or more sensors 275 of the die 240, or a combination thereof). In some embodiments, the logic block 230, the interface block 220, the interface block 245, or a combination thereof may be configured to receive one or more indications based on measurements of one or more sensors of the system 200. For example, the logic block 230, the interface block 220, or the interface block 245 may be coupled to the one or more sensors via one or more buses (not shown) or corresponding contacts (not shown). Such sensors may include temperature sensors, current sensors, voltage sensors, counters, and other types of sensors. In some examples, the logic block 230, the one or more interface blocks 220, the one or more interface blocks 245, or a combination thereof may configure one or more operations based on the output of the one or more sensors. For example, the logic block 230 may configure one or more operations of the interface block 220 based on signaling (e.g., indications, data) received from the one or more sensors. Additionally or alternatively, the interface block 220 may generate access signaling for transmission to the corresponding interface block 245 based on one or more sensors.

[0059] In some examples, the circuitry of interface block 220, interface block 245, or logic block 230, or any combination thereof, may include components (e.g., transistors) formed at least in part from doped portions of a substrate of a respective die. In some examples, the substrate of die 205 may have characteristics (e.g., materials, material properties, physical shape, or size) that are different from characteristics of a substrate of die 240. Additionally or alternatively, in some examples, transistors formed from the substrate of die 205 may have characteristics (e.g., manufacturing characteristics, performance characteristics, physical shape, or size) that are different from transistors formed from the substrate of die 240 (e.g., according to a different transistor architecture, according to a different transistor design).

[0060] In some examples, the interface block 220 may support a layout of one or more components within 220. For example, the layout may include pairing components to share access ports (e.g., command ports, data ports). In addition, in some examples, the layout may support an interface for the controller 215 (e.g., host interface 216) that is different from an interface for the interface block 245 (e.g., via bus 221). For example, the host interface 216 may be synchronous and have separate channels for read and write operations, while the interface between the interface block 220 and one or more interface blocks 245 may be asynchronous and support both read and write operations using the same channel. In some examples, the signaling of the host interface 216 may be implemented with deterministic timing (e.g., deterministic between the controller 215 and one or more interface blocks 220), which may be associated with a configuration timing between a first signal and a response second signal. In some examples, signaling between interface block 220 and one or more interface blocks 245 may be implemented with different timing than that of host interface 216 (eg, according to a different clock frequency, according to a timing offset, such as a phase offset), which may be deterministic or non-deterministic.

[0061] The die 240 may include one or more cells 265 (e.g., modules) separated from a semiconductor wafer having a pattern of cells 265 (e.g., a two-dimensional pattern). Although each die 240 of the system 200 is illustrated as having a single cell 265 (e.g., cell 265-a-1 of die 240-a-1, cell 265-a-2 of die 240-a-2), a die 240 according to the described technology may include any number of cells 265, which may be arranged in various patterns (e.g., groups of one or more cells 265 along a row direction, groups of one or more cells 265 along a column direction, and other patterns). Each cell 265 may include at least the circuitry of a corresponding interface block 245 and a memory array 250, a bus 251, a bus 246, and one or more contacts 247 corresponding to the corresponding interface block 245. In some examples, each unit 265 may also include one or more buses 255, contacts 256, contacts 257, or contacts 260, as appropriate (e.g., associated with respective interface blocks 245 of units 265 of different dies 240), which may support various degrees of stackability or modularity between or via units 265 of other dies 240. Although examples of nonvolatile storage 270 and sensors 275 are illustrated as being external to the unit 265, in some other examples, nonvolatile storage 270, sensors 275, or both may additionally or alternatively be included in the unit 265.

[0062] In some examples, the interface block 220 may include circuitry configured to receive first access command signaling from the host processor 210 or controller 215 (e.g., via the host interface 216, via one or more contacts 212 from the host processor 210 or controller 215 external to the die 205, based on a request from a host application) and transmit second access command signaling to a respective (e.g., coupled) interface block 245 based on (e.g., in response to) the received first access command signaling. Thus, the interface block 245 may include circuitry configured to receive second access command signaling from the respective interface block 220 and, in some examples, access a respective set of one or more memory arrays 250 based on (e.g., in response to) the received second access command signaling. In various examples, the first access command signaling may include an access command associated with a type of operation (e.g., a read operation, a write operation, a refresh operation, a memory management operation), which may be associated with an indication of an address (e.g., a logical address, a physical address) of the one or more memory arrays 250. In some examples, the first access command signaling may include an indication of a logical address associated with the memory array 250, and the circuit system of the interface block 220 may be configured to generate a second access command signaling to indicate a physical address associated with the memory array 250 (e.g., a row address, a column address, using a logical-to-physical (L2P) table or other mapping or calculation functionality of the interface block 220).

[0063] In some examples, to support write operations of the system 200, the circuitry of the interface block 220 may be configured to receive first data signaling associated with the first access command signaling (e.g., from the host processor 210, from the controller 215, via the host interface 216, via one or more contacts 212 from the host processor 210 or the controller 215 external to the die 205) and transmit second data signaling (e.g., associated with the second access command signaling) based on the received first access command signaling and the first data signaling. Thus, the interface block 245 may be configured to receive the second data signal and write data to the one or more memory arrays 250 based on the received second access command signaling and the second data signaling (e.g., according to the indicated address associated with the first access command signaling). In some instances, interface block 220 may include error control functionality (e.g., error detection circuitry, error correction circuitry, error correction code (ECC) logic, ECC engine) that supports interface block 220 in generating second data signaling based on performing error control operations using received first data signaling (e.g., detecting or correcting errors in the first data signaling, determining one or more parity bits transmitted in the second data signaling and written with the data).

[0064] In some examples, to support read operations of the system 200, the circuitry of the interface block 245 may be configured to read data from the memory array 250 based on the received second access command signaling and transmit the first data signaling based on the read data. Thus, the interface block 220 may be configured to receive the first data signaling and transmit the second data signaling based on the received first data signaling (e.g., to the host processor 210, to the controller 215, via the host interface 216, to the host processor 210 or the controller 215 external to the die 205 via the one or more contacts 212). In some examples, the interface block 220 may include error control functionality that enables the interface block 220 to generate the second data signaling based on performing error control operations using the received first data signaling (e.g., detecting or correcting errors in the first data signaling, which may include calculations involving one or more parity bits received with the first data signaling).

[0065] In some examples, access command signaling transmitted by the interface block 220 to the interface block 245, as well as other signaling (e.g., based on access command signaling received from the host processor 210, based on start signaling received from the host processor 210, without receiving or otherwise independently of signaling from the host processor 210) may be generated according to various determination or generation techniques configured at the interface block 220 (e.g., based on a configuration modified at the interface block 220 for accessing the memory array 250). In some examples, such techniques may involve signaling or other coordination with the logic block 230, the host processor 210, one or more controllers 215, one or more instances of non-volatile storage devices, one or more sensors, or any combination thereof. Such techniques may support the interface block 220 in configuring aspects of access operations performed by the corresponding interface block 245 on the memory array 250, as well as other operations. For example, interface block 220 may include evaluation circuitry, access configuration circuitry, signaling circuitry, scheduling circuitry, repair circuitry, refresh circuitry, error control circuitry, adverse access (e.g., row hammer) mitigation circuitry, and other circuitry that is operable to configure operations associated with one or more dies (e.g., operations associated with accessing memory array 250 of die 240).

[0066] The system 200 may be configured to perform management operations to support or maintain operational characteristics, such as performance characteristics associated with operating one or more memory arrays 250. To support such techniques according to examples disclosed herein, the system 200 may be configured to support management command signaling between the controller 215 and the interface block 220. For example, the interface block 220 may be configured to schedule or otherwise determine that a management operation is to be performed, and may indicate (e.g., signal) an aspect requesting the controller 215 to schedule a management operation. In response, the controller 215 may indicate one or more commands to the interface block 220 to perform the management operation.

[0067] The described techniques for management operations may support various improvements to the operation of the system 200. For example, by providing such indications of management operations as requests to schedule aspects of the management operation (e.g., as flexible requests, as requests that may not be associated with an immediate response), the controller 215, the host processor 210, or a combination thereof may be enabled to coordinate the management operation with other operations (e.g., operations that support functions or applications of the host processor 210 or use the host processor 210), such as access operations to one or more memory arrays 250. Such techniques may allow the controller 215 or the host processor 210 to prioritize or parallelize relatively higher priority access operations over the requested management operation, which may include delaying the management operation, using a different controller 215 to support the access operation (e.g., selecting an available controller 215, an available host interface 216, or an available interface block 220, or a combination thereof, that is not associated with the requested management operation), and other scheduling or prioritization.

[0068] In some examples, such a request may include an indication of a duration within which the management operation is to be performed, such as a number of cycles (e.g., computing cycles, clock cycles, system cycles) between signaling of the management operation request and initiation or completion of the management operation. Such techniques may support management operation commands scheduled by the controller 215 within a threshold duration that supports the system 200 meeting desired operating characteristics (e.g., supporting performance requirements associated with accessing the memory array 250).

[0069] In some examples, a management operation may be associated with a group (e.g., a sequence) of multiple operations (e.g., sub-operations, DRAM operations) such that a single request indication through the interface block 220 may be responded to by the controller 215 with an indication of a group of commands (e.g., multiple indications, a sequence of indications, a compound command) in a manner that reduces request or command signaling (e.g., from the interface block 220 to the controller 215). In some embodiments, such techniques may utilize an existing command group (e.g., a set of commands according to a standardized interface protocol, a set of DRAM commands). For example, a first management operation may be associated with a first sequence of one or more DRAM commands or their timing, or both (e.g., according to a first request identifier), and a second management operation may be associated with a second sequence of one or more DRAM commands or their timing, or both (e.g., according to a second request identifier). In some embodiments, such associations between management operations and commands may be stored at the system (e.g., in the non-volatile storage device 235 or the non-volatile storage device 270 or a combination thereof) and may be signaled to the controller 215 (e.g., in a boot sequence, in an initialization sequence, in a configuration sequence, through the host interface 216). For example, such associations may be programmable (e.g., as instructions, as configuration parameters during manufacture or configuration of die 205 or die 240) or updated (e.g., via logic block 230, via contacts 234, by flashing instructions or parameters, before or after coupling the die stack), which may facilitate programming or updating such associations and does not involve other design coordination between interface block 220 and controller 215 (e.g., without having to update the specification of host interface 216).

[0070] Additionally or alternatively, criteria (e.g., selection criteria, determination criteria, scheduling criteria) for performing management operations may be stored at system 200 (e.g., in non-volatile storage 235 or non-volatile storage 270 or a combination thereof), which may be withheld from controller 215 and host processor 210. For example, scheduling details or initiation criteria for performing management operations may be programmed (e.g., as instructions, as configuration parameters, as parameters based on indications from one or more sensors 237 or sensors 275) or updated (e.g., via logic block 230, via contacts 234) and this information is not shared with a provider (e.g., designer, manufacturer) of host processor 210 or controller 215 and other aspects of system 200. In some instances, such techniques for storing criteria for performing management operations may hide such techniques from discovery.

[0071] Thus, according to these and other techniques, system 200 can be configured in a manner that supports a relatively simplified specification of host interface 216 to support management operations for maintaining performance of system 200, relatively simplified scheduling at controller 215 to support such management operations, and relatively flexible design or modification of memory system interface circuitry (e.g., interface block 220, logic block 230) for such support of management operations, and other benefits. Such techniques can be particularly beneficial in systems that couple semiconductor dies, including benefits of improved throughput, improved prioritization of operations, and reduced latency, among other benefits.

[0072] Figure 3 An example of an interface architecture 300 supporting management command techniques for a stacked memory architecture according to examples disclosed herein is shown. Interface architecture 300 illustrates an example of an interface block 245-b (e.g., of die 240) coupled to an interface block 220-b (e.g., of die 205). Interface block 245-b may be communicatively coupled to interface block 220-b via one or more of bus 301, bus 302, bus 303, and bus 304, each of which may be an example of bus 221 and bus 246 as well as one or more signal paths of bus 255, as appropriate.

[0073] The interface block 245-b includes a control interface 310 (e.g., a command interface) that can be configured to communicate with the interface block 220-b by signaling. For example, the control interface 310 can include a circuit system (e.g., a receiver, one or more latches) configured to receive control signaling (e.g., modulation control signaling, access command signaling, configuration signaling, address signaling, such as row address signaling or column address signaling) via the bus 301-a. The control interface 310 can also include a circuit system configured to receive clock signaling (e.g., clock signaling associated with the control interface 310, clock signaling with one or more phases, such as true and complement phases, dk_t / c signaling from the interface block 220-b) via the bus 302-a. The control interface 310 can use the bus 302-a to receive control signaling of the bus 301-a (e.g., for triggering one or more latches). The control interface 310 may transmit (eg, forward) control signaling and clock signaling (eg, timing for other operations of the interface block 245 - b ) to the interface controller 320 .

[0074] The interface block 245-b also includes two data interfaces 330 (e.g., data interfaces 330-a-1 and 330-a-2), which may also be configured to communicate signaling with the interface block 220-b. Each data interface 330 may include a corresponding bus and circuitry, the operation of which may be associated with (e.g., controlled by, coordinated with, operated based on) control signaling via the control interface 310. Although the example of the interface block 245-b includes two data interfaces 330 associated with the control interface 310 (e.g., in a "channel pair" arrangement, in a "pseudo-channel pair" arrangement), for a given control interface 310 of the interface block 245, the described techniques for the interface block 245 may include any number of one or more data interfaces 330 and associated buses and circuitry.

[0075] Each data interface 330 may be associated with a respective data path circuitry, which may include respective first-in, first-out (FIFO) and serialization / deserialization (SERDES) circuitry (e.g., FIFO / SERDES 340), respective write / sense circuitry 350, respective synchronization and sequencing circuitry (e.g., sync / seq logic 360), and respective timing circuitry 370, as well as interconnecting signal paths (e.g., one or more buses). However, in some other examples, the data path circuitry may be arranged differently or may include different circuitry components, which may include circuitry dedicated to the respective data path or circuitry shared between data paths, or various combinations thereof. Each data interface 330 may also be associated with a respective set of one or more memory arrays 250. In some examples, each memory array 250 may be understood to include respective addressing circuitry, such as bank logic or decoders (e.g., row decoders, column decoders) or memory cell sense amplifier circuitry, as well as other array circuitry. However, in some other examples, at least a portion of this circuitry may be included in the interface block 245.

[0076] Each data interface 330 may include circuitry (e.g., one or more latches, one or more drivers) configured to communicate (e.g., receive, transmit) data signaling (e.g., modulated data signaling, DQ signaling) via the corresponding bus 303. Each data interface 330 may also include circuitry for communicating clock signaling via the corresponding bus 304, which may support clock signal reception through the data interface 330 (e.g., first clock signaling associated with the data interface 330, clock signaling with one or more phases, such as true and complement phases, DQS_t / c signaling from the interface block 220-b, clock signaling associated with data reception or write operations) or clock signal transmission through the data interface 330 (e.g., second clock signaling associated with the data interface 330, RDQS_t / c signaling to the interface block 220-b, clock signaling associated with data transmission or read operations), or both. In some examples, data interface 330, bus 303, or a combination of bus 303 and bus 304 may be associated with a "pseudo-channel," and multiple pseudo-channels may be associated with the same control interface 310 or the same control bus (e.g., bus 301, a combination of bus 301 and bus 302). In some implementations, pseudo-channels of multiple interface blocks 245 may be grouped together (e.g., functionally, logically, electrically, such as by hard-wired signal paths or multiplexing circuitry) to support a channel group (e.g., associated with a corresponding host interface 216). Each data interface 330 may transmit clock signaling (e.g., received clock signaling, DQS_t / c signaling) to sync / seq logic 360 via a respective bus (e.g., for timing of other operations of interface block 245-b).

[0077] The interface controller 320 may support various functionalities (e.g., control functionality, configuration functionality) of the interface block 245-b for accessing or otherwise managing the operation of the coupled memory array 250. For example, the interface controller 320 may support access command coordination or configuration, delay or timing compensation, access command buffering (e.g., according to a FIFO or other organizational scheme), mode registers or logic for configuration settings or test functionality (e.g., evaluation functionality, BIST functionality), and other functions or combinations thereof. For each data path of the interface block 245 (e.g., associated with a corresponding data interface 330), the interface controller 320 may be configured to transmit signaling (e.g., address signaling, such as row address or row activation signaling) to the corresponding memory array 250 via a bus. For each data path of the interface block 245, the interface controller 320 may communicate signaling (e.g., timing signaling (which may be based on clock signaling received from the control interface 310), configuration signaling) with the corresponding timing circuit system 370 and sync / seq logic 360 via the corresponding bus.

[0078] For each data path, the respective timing circuitry 370 may support timing of various operations (e.g., activation, coupling operations, signal latching, signal driving) relative to timing signaling received from the interface controller 320. For example, the timing circuitry 370 may include a timing chain (e.g., a global column timing chain) configured to generate one or more clock signals or other activation signals for controlling the operation of the respective data paths, and such signaling may include transitions (e.g., rising edge transitions, falling edge transitions, on / off transitions) that are offset from, at a different rate than, or otherwise different from the transitions of the signaling from the interface controller 320 to support a given operation or combination of operations. For example, the timing circuitry 370 may be configured to transmit signaling (e.g., address signaling, such as column address or column activation signaling) to the respective memory array 250, transmit signaling (e.g., latch or driver timing signaling) to the respective write / sense circuitry 350, and transmit signaling (e.g., timing signaling) to the respective sync / seq logic.

[0079] For each data path, a corresponding FIFO / SERDES 340 may be configured to convert between data signaling of a first bus width (e.g., a relatively wide bus width, a data read / write (DRW) bus, a bus for communicating with a write / sense circuitry 350 having a relatively large number of signal paths) and a second bus width (e.g., a relatively narrow bus width, a bus for communicating with a data interface 330 having a smaller number of signal paths). In some examples, this transition may be accompanied by a change in the signaling rate between signaling from the data interface 330 and the write / sense circuitry 350 (e.g., for maintaining a given throughput). In various examples, the FIFO / SERDES 340 may receive data signaling from the data interface 330 and transmit data signaling to the write / sense circuitry 350 (e.g., for supporting write operations), or may receive data signaling from the sense circuitry 350 and transmit data signaling to the data interface 330 (e.g., for supporting read operations). In some examples (eg, to support read operations), the FIFO / SERDES 340 may be configured to transmit clock signaling (eg, RDQS_t / c signaling) to the data interface 330, which may be forwarded to the interface block 220-b.

[0080] The timing or other synchronization of operations performed by the FIFO / SERDES 340 may be supported by one or more clock signals and other signaling received from the corresponding sync / seq logic 360. For example, the sync / seq logic 360 may generate or otherwise coordinate clock signaling to support different signaling rates for different buses (e.g., based on received clock signaling). Additionally or alternatively, the FIFO / SERDES 340 may operate in one direction (e.g., for transmitting data to the data interface 330, for receiving data from the data interface 330) or other modes based on configuration signaling received from the sync / seq logic 360.

[0081] For each data path, a respective write / sense circuitry 350 may be configured to support access (e.g., data signaling, write signaling, read signaling) of a respective group of one or more memory arrays 250. For example, the write / sense circuitry 350 may be coupled to the memory arrays 250 via a bus (e.g., a global input / output (GIO) bus), which may include respective signal paths associated with each memory array 250 or may include signal paths shared by all memory arrays 250 of the group, in which case the memory array circuitry may include multiplexing circuitry operable to couple the bus with selected ones of the memory arrays 250. In some examples, the bus between the write / sense circuitry 350 and the group of one or more memory arrays 250 may include the same number of signal paths as the bus between the write / sense circuitry 350 and the FIFO / SERDES 340 (e.g., for signaling GIO[287:0]) or the same number of signal paths as the number of columns in each memory array 250. In some other examples, the memory array 250 may include a number of columns that is an integer multiple of the number of signal paths of the bus, in which case the memory array circuitry (e.g., each memory array 250) may include decoding circuitry operable to couple a subset of the memory cell columns or associated circuitry to the bus.

[0082] To support write operations, write / sense circuitry 350 may be configured to drive signaling operable to write one or more logic states to memory cells of memory array 250 (e.g., based on received data, based on received timing signaling, based on data signaling received via bus 303, and based on control signaling received via bus 301-a). In some examples, such signaling may be transmitted to support circuitry of memory array 250 or otherwise associated with memory array 250 (e.g., as an output of a signal corresponding to the logic state to be written), such as sense amplifier circuitry, voltage sources, current sources, or other driver circuitry operable to apply a bias across a storage element of a memory cell (e.g., across a capacitor, across a ferroelectric capacitor) or to apply a charge, current, or other signaling to a storage element of a memory cell (e.g., applying a current to a chalcogenide or other configurable memory material, applying a charge to the gate of a NAND memory cell), as well as other examples.

[0083] To support read operations, the write / sense circuitry 350 may be configured to receive signaling, which the write / sense circuitry 350 may further amplify for communication through the interface block 245-b. For example, the write / sense circuitry 350 may be configured to receive signaling corresponding to a logic state read from the memory array 250, but at a relatively low driver strength (e.g., relatively 'analog' signaling, which may be associated with a relatively low drive strength of a sense amplifier of the memory array 250). Thus, the write / sense circuitry 350 may include additional sense amplifiers (e.g., data sense amplifiers (DSAs) between a signal path between the write / sense circuitry and one or more memory arrays of the group and a corresponding signal path between the write / sense circuitry and the FIFO / SERDES), each of which may have a relatively high drive strength (e.g., for driving relatively 'digital' signaling).

[0084] Features of interface architecture 300 may be replicated in various numbers and arrangements to support semiconductor systems having multiple dies, such as various instances of system 200. In an example embodiment, each die 240 may be configured with 64 instances of interface block 245-b, which may support a data signaling width of 9,216 signal paths for each die 240 (e.g., where each bus 303 of a channel pair is associated with 72 signal paths). For system 200 having a stack of 8 dies 240 coupled to die 205, die 205 may thus be configured with 512 instances of interface block 220-b, thereby supporting a total data signaling width of 73,738 signal paths for system 200. However, in other embodiments, die 205 and die 240 may be configured with different numbers of interface blocks 220 and 245, respectively, and system 200 may be configured with different numbers of dies 240 per die 205.

[0085] Figure 4 An example of an interface architecture 400 supporting management command techniques for a stacked memory architecture according to examples disclosed herein is shown. The interface architecture 400 illustrates an example of an interface block 220-c (e.g., of a die 205) coupled to a controller 215-c (e.g., controller 215-c of a die 205, controller 215-c external to the die 205). In some examples, the controller 215-c may support operations of the host system 105, such as coordinating access operations in response to operations (e.g., instructions, requests, commands) of a host application. The interface block 220-c may include logic (e.g., management logic, media management logic) configured to determine management operations to perform memory system 110 (e.g., management operations to support operations associated with accessing memory array 250 (e.g., of one or more die 240)) and to transmit requests (e.g., by controller 215-c) scheduling such management operations. In some examples, interface block 220 - c may illustrate a single channel memory interface block, but the described techniques may be applicable to any number of channels or pseudo-channels of system 200 .

[0086] The controller 215-c may be communicatively coupled to the interface block 220-c via one or more of a bus 410, a bus 420, a bus 430, a bus 440, and a bus 450, each of which may be an example of one or more signal paths of the host interface 216-c. For example, the bus 410 may be associated with one or more signal paths for transmitting row command information from the controller 215-c to the interface block 220-c, such as corresponding or shared signal paths for transmitting ACT commands and PRE commands and accompanying address information (e.g., channel information, pseudo-channel information, bank information, row information). The bus 420 may be associated with one or more signal paths for transmitting column command information from the controller 215-c to the interface block 220-c, such as corresponding or shared signal paths for transmitting RD commands, RDA commands, WR commands, and WRA commands and accompanying address information (e.g., column information). Although bus 410 and bus 420 are illustrated separately, in some examples, bus 410 and bus 420 may be implemented as a common bus that supports the transmission of row command information and column command information via the same signal path. In some examples, the signal paths of bus 410, bus 420, or both may have corresponding signal paths included in bus 301 (e.g., between interface block 220-c and interface block 245). Bus 430 may be associated with one or more signal paths (e.g., 64 signal paths) for transmitting write data from controller 215-c to interface block 220-c, and bus 440 may be associated with one or more signal paths (e.g., 64 signal paths) for transmitting read data from interface block 220-c to controller 215-c. Although bus 430 and bus 440 are illustrated separately (e.g., as unidirectional buses), in some examples, bus 430 and bus 440 may be implemented as a common bus that supports the transmission of write data and read data via the same signal path (e.g., a bidirectional bus).

[0087] The host interface 216-c may support a command interface (e.g., a deterministic interface) for indications such as activate commands, precharge commands, read commands, and write commands, among others, which may be configured to operate according to configuration (e.g., predetermined, published, deterministic) timing and responses (e.g., response operations, response signaling). For example, the controller 215-c may be configured to handle command scheduling, which may include a combination of scheduling commands for supporting access operations of host applications and scheduling instructions for supporting management operations (e.g., requested by the interface block 220-c). In some implementations, such commands may be configured according to a memory protocol (e.g., a DRAM protocol). For example, a set of commands that may be configured between the controller 215-c and the interface block 220-c (e.g., a set of commands supported by the host interface 216-c) may include an activation command (e.g., an ACT command), a precharge command (e.g., a PRE command), a row no operation (e.g., an RNOP command), a read command (e.g., an RD command), an auto-precharge read command (e.g., an RDA command), a write command (e.g., a WR command), an auto-precharge write command (e.g., a WRA command), or a column no operation command (e.g., a CNOP command), as well as other commands or combinations thereof. In some examples, such commands may be accompanied by one or more delay commands that may be used to configure or request a delay (as a number of cycles) between other operations.

[0088] Table 1 illustrates examples of commands and associated identifiers that may be used in association with a given management operation:

[0089]

[0090] Table 1 - Example commands for managing operation associations

[0091] In some examples, such commands may be a configured set of possible commands known to the host system 105 (e.g., controller 215-c) and coupled memory system 110 (e.g., interface block 220-c) at system design time. In various examples, any one or more of such commands may be associated with a management operation (e.g., by a command ID) that may be requested by the interface block 220-c and scheduled by the controller 215-c (e.g., as a command for a compound operation).

[0092] In some embodiments, such commands may be subject to the same timing constraints (e.g., DRAM timing constraints) whether they are used to support host applications or management operations. For example, the controller 215-c, the interface block 220-c, or both may also be configured with command timings according to a memory protocol (e.g., a DRAM protocol), which may include configuration timings such as row-to-column delays for read operations (e.g., tRCDR), row-to-column delays for write operations (e.g., tRCDW), row precharge timings (e.g., tRP), row activation times (e.g., tRAS), row cycle times (e.g., tRC), row-to-row or RAS-to-RAS delay timings (e.g., tRRD), write recovery times (e.g., tWR), read-to-write delay timings (e.g., tRTW), write-to-read delay timings (e.g., tWTR), column-to-column delay timings (e.g., tCCD), and other timings or combinations thereof. Thus, in understanding configuration commands and associated timings, the controller 215-c may be configured to schedule commands (e.g., in response to application requests, in response to management operation requests) that meet configuration timing constraints in a manner that supports high performance for the associated host system 105, while also supporting management operations determined by the associated memory system 110. By mapping management operations to known commands and timings, such techniques may be performed using a transparent interface with relatively fewer commands than when management operations are defined in terms of new commands or timings.

[0093] The interface block 220-c may be configured to communicate a request to perform a management operation (e.g., a refresh operation, a row hammer mitigation operation, a scrub operation, a repair operation, a replacement operation) on one or more memory arrays 250, which may be transmitted as a request to the controller 215 to schedule the interface block 220-c to perform the management operation. In some embodiments, the host interface 216-c may be configured with a bus 450 (e.g., a bus dedicated to management operation requests, a unidirectional bus for signaling from the interface block 220-c to the controller 215-c), which may be associated with one or more signal paths dedicated to transmitting the management operation request from the interface block 220-c to the controller 215-c. In some other embodiments, such request signaling may be transmitted on a bus that is not dedicated to management operation requests but is otherwise different from the bus used for the interface block 220-c to receive commands from the controller 215-c (e.g., different from the bus 410 and the bus 420). In response to a management operation request, the controller 215-c operating as a centralized scheduler may schedule and transmit indications of one or more commands associated with the requested management operation, which may include a sequence of multiple commands indicated according to preconfigured timing constraints (e.g., a combination of any one or more of an ACT command, a PRE command, an RNOP command, an RD command, an RDA command, a WR command, a WRA command, or a CNOP command).

[0094] Figure 5An example of a process 500 that supports management command techniques for a stacked memory architecture according to examples disclosed herein is shown. Aspects of the process 500 may be performed by components of a system 200-d, such as a host processor 210-d, a controller 215-d, an interface block 220-d, and an interface block 245-d. The host processor 210-d and the controller 215-d may be components of a host system 105-a, and the interface block 220-d and the interface block 245-d may be components of a memory system 110-a. Although the example of the system 200-d includes a controller 215-d coupled to a single interface block 220-d and a single interface block 245-d, the described techniques may be supported by a controller 215-d coupled to any number of one or more interface blocks 220-d or any number of one or more interface blocks 245-d.

[0095] In some implementations, interface block 245-d can be a component of a first semiconductor die (e.g., die 240) and interface block 220-d can be a component of a second semiconductor die (e.g., die 205). In various implementations, controller 215-d can be a component of the second semiconductor die or another semiconductor die coupled to the second semiconductor die, and the host processor can be a component of the second semiconductor die or another semiconductor die (e.g., the same die as controller 215-d, a different die than controller 215-d), among other implementations.

[0096] The interface block 245-d may be coupled to the interface block via a bus 515, which may include one or more of the bus 301, the bus 302, the bus 303, or the bus 304. The interface block 220-d may be coupled to the controller 215-d via a bus 510, which may be an example of the host interface 216 (e.g., including one or more of the bus 410, the bus 420, the bus 430, the bus 440, or the bus 450). The controller 215-d may be coupled to the host processor 210-d via a bus 505.

[0097] In some examples, at 520, the controller 215-d and the interface block 220-d may perform initialization. For example, the controller 215-d and the interface block 220-d may exchange initialization signaling (e.g., via the bus 510) (e.g., boot signaling, configuration signaling, instruction signaling, or other signaling) and may perform various accompanying operations. In some examples, at the initialization portion of 520, the interface block 220-d may transmit information regarding timing, association of commands for various management operations, or a combination thereof (e.g., from the non-volatile storage device 235, from one or more instances of the non-volatile storage device 270, or a combination thereof). For example, the interface block 220-d may transmit an indication of a set of identifiers for a set of configuration management operations and a corresponding command sequence associated with each management operation in the set of management operations. Table 2 illustrates examples of such management operation identifiers that may be associated with corresponding management operations and corresponding operation sequences (e.g., including reference command IDs, such as the command IDs given in Table 1).

[0098] ID Management Operations sequence 1 Automatic refresh, hammer refresh ACT(2)+Delay(12)+PRE(3) 2 scrub ACT(2)+RDA(8) and ACT(2)+WRA(6) 3 Line Repair ACT(2)+PRE(3)+ACT(2)+PRE(3) and RNOP(1)

[0099] Table 2 - Instance management operation command association

[0100] Additionally or alternatively (e.g., omitting the initialization operation of 520), the timing, association of commands with management operations, or a combination thereof may be preconfigured at each of the controller 215-d and the interface block 220-d. For example, such information may be included in the design specifications (e.g., of the bus 510, the controller 215-d, the interface block 220-d) so that information regarding the timing, association of commands for various management operations, or a combination thereof may not be communicated from the interface block 220-d to the controller 215-d (e.g., during initialization of 520 or otherwise). In some other examples, the known association of management operations with command sequences may be omitted so that the management operation request itself may include an indication of the requested command sequence.

[0101] At 525, the interface block 220-d (e.g., a media management function) may determine a management operation to be performed. For example, the interface block 220-d may determine that criteria for performing a management operation have been met, which may be based on a duration since a previous management operation (e.g., according to a management operation schedule), an indication from sensor 237 or sensor 275, an indication of an adverse access operation, an indication of a component failure (e.g., an indication to perform a repair or replacement operation), and other criteria.

[0102] At 530 (e.g., in response to the determination of 525), the interface block 220-d may transmit a management operation (MO) request (e.g., via bus 510), which may be received by the controller 215-d. The request of 530 may request the controller 215-d to schedule the interface block 220-d to perform a management operation associated with the memory array 250 accessible via the interface block 220-d (e.g., via the interface block 245-d). In some examples, the request of 530 may be transmitted via a dedicated signal path of the bus 510 (e.g., bus 450). In various examples, the requested management operation may be a refresh operation on one or more rows of the memory array 250, a row hammer mitigation operation on one or more rows of the memory array 250, a scrub operation on one or more rows of the memory array 250, or a repair operation on one or more rows of the memory array 250.

[0103] The request of 530 may be associated with various information fields communicated to the controller 215-d. For example, the request of 530 may include an identifier (e.g., a tag) for associating a response command with the request 530, which may be used to map a command to the request of 530, to distinguish the management operation requested at 530 from other requested management operations, or both. In some instances, the request of 530 may include address information associated with the management operation (e.g., a pseudo channel indicator, a storage bank indicator). In some instances, the request of 530 may include an indication of the duration within which the controller 215-d will schedule the interface block 220-d to perform the management operation (e.g., a deadline, a delay, a scheduling window, a duration relative to the timing of the transmission or reception of the request of 530, a duration expressed as a number of system cycles). In some instances, this duration may be configured to be as long as possible while supporting management performance characteristics to support relatively higher scheduling flexibility of the controller 215-d.

[0104] The request of 530 may also include one or more indications of a set of one or more commands (e.g., a sequence of multiple commands, a compound command) associated with the management operation determined at 525. For example, the request of 530 may include an indication of an identifier associated with the requested management operation (e.g., an identifier corresponding to the management operation, such as an identifier communicated during initialization of 520 or otherwise configured or standardized between the controller 215-d and the interface block 220-d), where the identifier is known to the interface block 220-d and the controller 215-c to be associated with the set of one or more commands (e.g., a sequence of multiple commands). In some other examples, the request of 530 may include an indication of the command itself (e.g., rather than a preconfigured management operation identifier), which in some examples may include a set of multiple command identifiers (e.g., an indication including an ACT command, a delay command, and a PRE command for determining an "auto-refresh" management operation, which may be indicated as a sequence of identifiers, such as identifiers 2, 12, and 3, according to the commands of Table 1 and the management operation definition of the refresh operation of Table 2).

[0105] At 540 (e.g., based at least in part on the request of 530), the controller 215-d may schedule commands for transmission to the interface block 220-d (e.g., to at least perform the management operation requested at 530). In some examples, at least some of the commands scheduled at 540 may be commands to access one or more memory arrays 250 via the interface block 220-d (e.g., via the interface block 245-d). For example, the commands scheduled at 540 may include one or more row commands, one or more column commands, or a combination thereof. In some examples, the commands may be scheduled at 540 according to an association of the command with the requested management operation (e.g., an association communicated during initialization of 530 or otherwise configured between the controller 215-d and the interface block 220-d). In some examples, the commands of 540 may be scheduled according to a configured timing between respective ones of the command operations (e.g., according to a configured delay).

[0106] In some examples, the command scheduled at 540 for requesting a management operation may be coordinated with other commands (e.g., by the controller 215-d). For example, at 535, the host processor 210-d may transmit an application request (e.g., via the bus 505), which may be received by the controller 215-d. The application request at 535 may be a request for a write operation or a read operation, or a combination thereof, to support a function or application of the host system 105-a. In some examples, the application request at 535 may be received as one or more commands to access one or more memory arrays 250 (e.g., a memory array 250 corresponding to the management operation requested at 530, a memory array 250 different from the memory array corresponding to the management operation requested at 530, or a combination thereof). In various examples, the application request at 535 may be received before the management operation request at 530 or after the management operation request at 530.

[0107] As part of the scheduling at 540, the controller 215-d may evaluate the priority of the application request at 535 and the management operation request at 530. For example, if the application request at 535 has a relatively high priority and the duration indicated by the management operation request at 530 supports it, the controller 215-d may be configured to schedule at least some of the commands responsive to the application request at 535 for transmission before at least some of the commands responsive to the management operation request at 530. In some examples, such scheduling may take into account one or more other management operation requests (e.g., in addition to the management operation requested at 530), which may include prioritizing or interleaving commands for multiple requested management operations. Thus, the scheduling at 540 may support the controller 215-d in optimizing command transmissions among competing priorities of throughput, latency, reliability, stability, and other priorities.

[0108] At 550, the controller 215-d may transmit one or more commands (e.g., a sequence of multiple commands, via bus 510) for a management operation corresponding to the request of 530, which may be received by the interface block 220-d. In some examples, each of the commands of 540 may include an indication that the first command is associated with the request in 530 or is otherwise associated with the requesting management operation (e.g., a tag, which may be the same tag indicated in the request of 530).

[0109] In some examples (e.g., where appropriate), at 545, the controller 215-d may transmit one or more commands (e.g., via bus 510) in response to the application request (the request of 535), which may be received by the interface block 220-d. In some examples, each of the commands of 550 may include an indication (e.g., a tag) that the command is not associated with a requested management operation. Although the commands of 545 are illustrated as being transmitted prior to transmitting the commands of 550, in various examples, one or more of the commands of 545 may be transmitted by the controller 215-d between the transmission or receipt of the request of 530 and the transmission of the initial command of command 550, or by the controller 215-d between the commands of 550 (e.g., based on interleaving between the commands of 550 and the commands of 545), or by the controller 215-d after the commands of 550, or any combination thereof.

[0110] At 560, the interface block may transmit one or more commands that each correspond to the received command (e.g., command of 545, command of 550), which may be received by the interface block 245-d (e.g., for accessing one or more memory arrays 250). In some examples, the command of 560 may be transmitted according to a deterministic delay relative to receipt of a corresponding command by the interface block 220-d (e.g., from the controller 215-d).

[0111] In some examples, the interface block 220-d may support command substitution functionality that may reduce the amount of information provided to the controller 215-d to support memory management operations, such as reducing the amount of information signaled to the controller 215-d, hiding memory management techniques performed by the interface block 220-d. For example, at 555, the interface block 220-d may substitute one or more aspects of the command of 550 or the command of 550 itself with other aspects of the command (e.g., a command for transmitting 560).

[0112] In some examples, this replacement may be based on whether the command from the controller 215-d is associated with a management operation. For example, if the command (e.g., row command, column command) received at the interface block 220-d includes a tag indicating an association with a management operation request of 530 (e.g., of the command of 550), the interface block 220-d may replace the received command with a management command (e.g., a management row command, a management column command transmitted at 560). Alternatively, if the command (e.g., row command, column command) received at the interface block 220-d does not include a tag indicating an association with a management operation request of 530 (e.g., includes a tag that is not associated with a management operation as a command of 545), the interface block 220-d may not replace the received command with a management command, but may forward the command to the interface block 245-d (e.g., at 560).

[0113] In some examples, the replacement of 555 may include replacing one or more of the commands of 550 with corresponding commands of different types for transmission at 560. For example, to hide aspects of the refresh operation from the controller 215-d (e.g., to limit the controller 215-d's knowledge that a particular row is refreshed and other aspects of the refresh management operation determined by the interface block 220-d), the interface block 220-d may request management operations associated with the ACT command (e.g., in the command at 550), the delay, and the PRE command, and after the interface block 220-d receives the command, the interface block 220-d may replace the ACT command with a refresh command that performs a refresh on one or more rows (e.g., all rows) of the indicated memory bank (e.g., at the same address as the ACT command) and replace the PRE command with a RNOP command (e.g., for forwarding to the interface block 245-d in the corresponding command of 560). In some examples, such association of commands with management operations and corresponding replacements may be configured to satisfy timing constraints within the commands 550 and 560.

[0114] Additionally or alternatively, the replacement of 555 may include replacing address information included in one or more of the commands of 550 with new or updated address information of one or more commands for transmission at 560. For example, interface block 220-d may be configured to overwrite one or more fields associated with a management operation in the command of 550 (e.g., prior to forwarding to interface block 245-d) for implementing the management operation, which may hide aspects of addressing for the management operation from controller 215-d. Additionally or alternatively, interface block 220-d may be configured to confirm that audited commands (e.g., audited DRAM commands) comply with the same timing constraints as commands not associated with management operations. This configuration may minimize information related to configuring host interface 216 (e.g., configuration information, timing information), thereby simplifying aspects of scheduling of management operations.

[0115] Process 500 may illustrate a technical functional division between controller 215-d and interface block 220-d for supporting management operations of memory system 110-a. For example, with respect to command scheduling, controller 215-d may have full control over scheduling, while interface block 245-d may have no control over scheduling (e.g., outside of an indicated duration within which management operation commands are scheduled). With respect to configuration command groups, controller 215-d may be configured to generate commands, while interface block 220-d may be configured to generally pass such commands (e.g., except for the replacement technique of 555). With respect to the management operations themselves, interface block 220-d may be configured to determine management operations and transmit requests to controller 215-d, while controller 215-d may be configured to process such requests and issue response commands (e.g., commands of 550). Thus, the functional division illustrated by process 500 for system 200-d may support various improvements in scheduling flexibility, performance optimization, management operation definition and configuration, and memory management techniques in a tightly coupled implementation of hidden semiconductor dies, as well as other benefits.

[0116] Figure 6 A block diagram 600 is shown of a memory interface 620 (eg, an interface) that supports management command techniques for a stacked memory architecture according to examples disclosed herein. The memory interface 620 may be an example of aspects of an interface block 220 that may be included in a die 205, as described with reference to FIG. Figures 1 to 5 Description. The memory interface 620 or its various components may be examples of means for executing various aspects of the management command techniques for the stacked memory architecture described herein. For example, the memory interface 620 may include a management operation request component 625, a command receiving component 630, a command transmission component 635, a command replacement component 640, a management operation configuration component 645, or any combination thereof. Each of these components or components of its subcomponents (e.g., one or more processors, one or more memories) may communicate with each other directly or indirectly (e.g., via one or more buses).

[0117] The management operation request component 625 may be configured to or otherwise support means for transmitting a request from the memory interface 620 (e.g., the interface block 220 of the die 205) to the controller (e.g., the controller 215 of the die 205) to cause the controller to schedule the memory interface 620 to perform a management operation associated with the memory arrays (e.g., the one or more memory arrays 250) of the one or more first semiconductor dies (e.g., the die 240 coupled to the die 205). The command receiving component 630 may be configured to or otherwise support means for receiving a sequence of a plurality of first commands for the management operation from the controller at the memory interface 620 based on the request. The command transmitting component 635 may be configured to or otherwise support means for transmitting one or more second commands from the memory interface 620 to at least one of the one or more first semiconductor dies to perform the management operation on the memory array, the one or more second commands each corresponding to one of the first commands.

[0118] In some examples, the first command may be a command to access the memory array.In some examples, each first command may include an indication that the first command is associated with a management operation.

[0119] In some examples, the request may include a tag for associating the first command with the request. In some examples, the indication may include the tag to associate the first command with the management operation based on the request including the tag.

[0120] In some examples, command replacement component 640 may be configured to or otherwise support components for replacing first commands with one or more second commands based on requesting scheduled management operations based on a sequence of multiple first commands for management operations, and transmitting the one or more second commands may be based on the replacement.

[0121] In some examples, to support replacing first commands, command replacement component 640 may be configured or otherwise support means for replacing one or more of the first commands with corresponding second commands of different types.

[0122] In some examples, command replacement component 640 can be configured or otherwise support means for replacing first address information included in one or more of the first commands with second address information.

[0123] In some examples, the command receiving component 630 may be configured as or otherwise support means for receiving one or more third commands from the controller at the memory interface 620 to access a memory array of one or more first semiconductor dies or another memory array, and the one or more third commands may be received between the transmission of the request and the receipt of an initial first command of a sequence of multiple first commands, between first commands of a sequence of multiple first commands, or a combination thereof.

[0124] In some instances, the request may include a tag for associating a first command with the request, address information associated with the management operation, a first indication of a duration within which the controller is requested to schedule an interface to perform the management operation, a second indication of a sequence of multiple first commands, or a combination thereof.

[0125] In some examples, to support transfer requests, the management operation request component 625 may be configured or otherwise support means for transferring the request via a dedicated bus between the memory interface 620 and the controller that is distinct from the one or more buses over which the sequence of the plurality of first commands is received.

[0126] In some examples, the sequence of multiple first commands may include one or more row commands, one or more column commands, or a combination thereof.

[0127] In some examples, the management operation configuration component 645 can be configured to or otherwise support means for transmitting, from the memory interface 620 to the controller prior to transmitting the request (e.g., during an initialization operation), an indication of a set of identifiers of a set of management operations and a sequence of respective plurality of commands associated with each of the set of management operations. In some examples, the request can be for the management operation based on the request including an identifier corresponding to the management operation. In some examples, the sequence of the plurality of first commands can be received in accordance with the indication.

[0128] In some examples, the management operation may include a refresh operation on one or more rows of the memory array, a row hammer mitigation operation on one or more rows of the memory array, a scrub operation on one or more rows of the memory array, or a repair operation on one or more rows of the memory array.

[0129] In some examples, a sequence of multiple first commands and one or more second commands may be associated with the same execution duration.

[0130] In some examples, the described functionality of the memory interface 620 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of the memory interface 620 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0131] Figure 7A block diagram 700 is shown of a memory controller 720 that supports management command techniques for a stacked memory architecture according to examples disclosed herein. The memory controller 720 may be a reference Figures 1 to 5 7. The memory controller 720 or its various components may be examples of means for performing various aspects of the management command techniques for the stacked memory architecture described herein. For example, the memory controller 720 may include a management operation request receiving component 725, a command scheduling component 730, a command transmission component 735, an access command receiving component 740, a management operation configuration component 745, or any combination thereof. Each of these components or components of its subcomponents (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0132] The management operation request receiving component 725 may be configured to or otherwise support means for receiving a request at a memory controller 720 (e.g., a memory controller of die 205) from an interface (e.g., interface block 220 of die 205) to cause the memory controller 720 to schedule the interface to perform management operations associated with one or more memory arrays (e.g., memory array 250) of one or more first semiconductor dies (e.g., die 240 coupled to die 205). The command scheduling component 730 may be configured to or otherwise support means for determining, at the memory controller 720, a sequence of a plurality of commands for the management operation based on the request. The command transmitting component 735 may be configured to or otherwise support means for transmitting, from the memory controller 720 to the interface, a sequence of a plurality of commands for the management operation based on the determination.

[0133] In some instances, the request may include a tag for associating a command for the management operation with the request, address information associated with the management operation, a first indication of a duration within which the controller is requested to schedule an interface to perform the management operation, a second indication of a sequence of multiple commands, or a combination thereof.

[0134] In some examples, command scheduling component 730 can be configured or otherwise support means for scheduling an interface to perform a management operation within a duration from receipt of a request, the duration indicated by the request. In some examples, a sequence of multiple commands can be transmitted according to a schedule.

[0135] In some examples, the access command receiving component 740 may be configured or otherwise support means for receiving one or more second commands to access one or more memory arrays of the one or more first semiconductor dies at the memory controller 720. In some examples, the command transmitting component 735 may be configured or otherwise support means for transmitting one or more third commands to access the one or more memory arrays from the memory controller 720 to the interface based on the one or more second commands.

[0136] In some examples, the commands for the management operation may each include a first indication that the command is associated with the management operation. In some examples, the one or more third commands may each include a second indication that the third command is not associated with the management operation.

[0137] In some examples, the request may include a tag for associating a command for the management operation with the request. In some examples, the first indication includes the tag to associate the command with the management operation based on the request including the tag.

[0138] In some examples, the one or more third commands may be transmitted between receipt of the request and transmission of an initial command for a management operation of a sequence of multiple commands, between transmission of commands of a sequence of multiple commands, or a combination thereof.

[0139] In some examples, to support receiving requests, the management operation request receiving component 725 may be configured as or otherwise support means for receiving requests via a dedicated bus between the interface and the memory controller 720, the dedicated bus being different from the one or more buses via which the one or more third commands are transmitted.

[0140] In some examples, the sequence of multiple commands may include one or more row commands, one or more column commands, or a combination thereof.

[0141] In some examples, the management operation configuration component 745 can be configured to or otherwise support means for receiving an indication of a set of identifiers of a set of management operations and a corresponding sequence of a plurality of commands associated with each of the set of management operations from the interface at the memory controller 720 prior to receiving the request (e.g., during an initialization operation). In some examples, the request can be for the management operation based on the request including the identifier corresponding to the management operation. In some examples, the sequence of the plurality of commands can be transmitted according to the indication.

[0142] In some examples, the described functionality of the memory controller 720 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of the memory controller 720 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0143] Figure 8 A flowchart illustrating a method 800 for supporting management command techniques for a stacked memory architecture according to an example disclosed herein is shown. The operations of the method 800 may be implemented by the memory interface or components thereof described herein. For example, the operations of the method 800 may be implemented by reference to Figures 1 to 6 The memory interface described herein (e.g., interface block 220 of die 205, memory interface 620) performs. In some examples, the memory interface may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory interface may use dedicated hardware to perform aspects of the described functions.

[0144] At 805, the method may include transmitting a request from an interface of the second semiconductor die (e.g., interface block 220 of die 205) to a controller of the second semiconductor die (e.g., controller 215 of die 205) to cause the controller to schedule the interface to perform management operations associated with one or more memory arrays of the first semiconductor die coupled to the second semiconductor die (e.g., one or more memory arrays 250 of one or more die 240). In some examples, aspects of operation 805 may be described with reference to Figure 6 The described management operation requests component 625 to execute.

[0145] At 810, the method may include receiving a sequence of a plurality of first commands for managing operations from a controller at an interface based on the request. In some examples, aspects of operation 810 may be referred to as Figure 6 The command receiving component 630 described above is executed.

[0146] At 815, the method may include transmitting from the interface to at least one of the one or more first semiconductor dies one or more second commands to perform a management operation on the memory array, the one or more second commands each corresponding to one of the first commands. In some examples, aspects of operation 815 may be referred to as Figure 6 The command transmission component 635 described above performs the above operations.

[0147] In some examples, an apparatus described herein (e.g., a semiconductor die apparatus, a semiconductor system apparatus) may perform one or several methods such as method 800. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0148] Aspect 1: A method, apparatus, or non-transitory computer-readable medium includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: transmitting a request from an interface of a second semiconductor die to a controller of the second semiconductor die so that the controller schedules the interface to perform a management operation associated with a memory array of one or more first semiconductor die coupled to the second semiconductor die; receiving a sequence of multiple first commands for the management operation from the controller at the interface based on the request; and transmitting one or more second commands from the interface to at least one of the one or more first semiconductor die to perform the management operation on the memory array, the one or more second commands each corresponding to one of the first commands.

[0149] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, wherein the first commands are commands to access the memory array and each first command includes an indication that the first command is associated with the management operation.

[0150] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to Aspect 2, wherein the request includes a tag for associating the first command with the request and the indication includes the tag to associate the first command with the management operation based on the request including the tag.

[0151] Aspect 4: A method, apparatus or non-transitory computer-readable medium according to any one of Aspects 1 to 3, further comprising the following operations, features, circuit systems, logic, components or instructions or any combination thereof: based on the sequence of multiple first commands for the management operation, replacing the first command with the one or more second commands for the management operation based on the request scheduling, wherein transmitting the one or more second commands is based on the replacement.

[0152] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to Aspect 4, wherein replacing the first command includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for replacing one or more of the first commands with corresponding second commands of different types.

[0153] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 4 to 5, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for replacing first address information contained in one or more of the first commands with second address information.

[0154] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 6, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for receiving one or more third commands from the controller at the interface to access the memory array or another memory array of the one or more first semiconductor dies, wherein the one or more third commands are received between the transmission of the request and the receipt of an initial first command of the sequence of multiple first commands, between the first commands of the sequence of multiple first commands, or a combination thereof.

[0155] Aspect 8: A method, device, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, wherein the request includes a tag for associating the first command with the request, address information associated with the management operation, a first indication of the duration within which the controller is requested to schedule the interface to perform the management operation, a second indication of the sequence of multiple first commands, or a combination thereof.

[0156] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 8, wherein transmitting the request includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transmitting the request via a dedicated bus between the interface and the controller, the dedicated bus being different from one or more buses via which the sequence of multiple first commands is received.

[0157] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 9, wherein the sequence of a plurality of first commands comprises one or more row commands, one or more column commands, or a combination thereof.

[0158] Aspect 11: A method, apparatus or non-transitory computer-readable medium according to any one of Aspects 1 to 10, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for: before transmitting the request, transmitting from the interface to the controller an indication of a set of identifiers of a set of management operations including the management operation and a corresponding sequence of multiple commands associated with each management operation in the set of management operations, wherein the request is used for the management operation based on the identifier corresponding to the management operation included in the request; and wherein the sequence of multiple first commands is received according to the indication.

[0159] Aspect 12: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 11, wherein the management operation includes a refresh operation on one or more rows of the memory array, a row hammer mitigation operation on one or more rows of the memory array, a scrub operation on one or more rows of the memory array, or a repair operation on one or more rows of the memory array.

[0160] Aspect 13: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 12, wherein the sequence of multiple first commands and the one or more second commands are associated with the same execution duration.

[0161] Fig. 9 A flowchart illustrating a method 900 for supporting management command techniques for a stacked memory architecture according to examples disclosed herein is shown. The operations of the method 900 may be implemented by a memory controller or components thereof as described herein. For example, the operations of the method 900 may be implemented by reference to Figures 1 to 5 7 and 8 are performed by a memory controller (e.g., controller 215 of die 205 or another die coupled to die 205, memory controller 720). In some examples, the memory controller may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory controller may use dedicated hardware to perform aspects of the described functions.

[0162] At 905, the method may include receiving, at a controller of the second semiconductor die (e.g., controller 215 of die 205), a request from an interface of the second semiconductor die (e.g., interface block 220 of die 205) to cause the controller to schedule the interface to perform management operations associated with one or more memory arrays of one or more first semiconductor dies coupled to the second semiconductor die (e.g., one or more memory arrays 250 of one or more dies 240). In some examples, aspects of operation 905 may be described with reference to Figure 7 The described management operation request receiving component 725 is executed.

[0163] At 910, the method may include determining, at a controller, a sequence of a plurality of commands for managing operations based on the request. In some examples, aspects of operation 910 may be referred to as Figure 7 The command scheduling component 730 described above performs the above.

[0164] At 915, the method may include transmitting a plurality of commands for management operations from the controller to the interface based on determining a sequence. In some examples, aspects of operation 915 may be referred to as Figure 7 The command transmission component 735 described above is executed.

[0165] In some examples, an apparatus described herein (e.g., a semiconductor die apparatus, a semiconductor system apparatus) may perform one or several methods such as method 900. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0166] Aspect 14: A method, apparatus, or non-transitory computer-readable medium includes operations, features, circuit systems, logic, components, or instructions for the following, or any combination thereof: receiving a request at a controller of a second semiconductor die from an interface of the second semiconductor die so that the controller schedules the interface to perform management operations associated with one or more memory arrays of one or more first semiconductor die coupled to the second semiconductor die; determining a sequence of multiple commands for the management operations at the controller based on the request; and transmitting the sequence of multiple commands for the management operations from the controller to the interface based on the determination.

[0167] Aspect 15: A method, device or non-transitory computer-readable medium according to Aspect 14, wherein the request includes a tag for associating the command used for the management operation with the request, address information associated with the management operation, a first indication of the duration within which the controller is requested to schedule the interface to perform the management operation, a second indication of the sequence of multiple commands, or a combination thereof.

[0168] Aspect 16: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 14 to 15, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for scheduling the interface to perform the management operation within a duration from the receipt of the request, the duration being indicated by the request, and wherein the sequence of multiple commands is transmitted according to the schedule.

[0169] Aspect 17: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 14 to 16, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving one or more second commands at the controller of the second semiconductor die to access the one or more memory arrays of the one or more first semiconductor die; and transmitting one or more third commands from the controller to the interface to access the one or more memory arrays based on the one or more second commands.

[0170] Aspect 18: A method, apparatus, or non-transitory computer-readable medium according to Aspect 17, wherein the commands for the management operation each include a first indication that the command is associated with the management operation and the one or more third commands each include a second indication that the third command is not associated with the management operation.

[0171] Aspect 19: A method, apparatus, or non-transitory computer-readable medium according to Aspect 18, wherein the request includes a tag for associating the command for the management operation with the request and the first indication includes the tag to associate the command with the management operation based on the request including the tag.

[0172] Aspect 20: A method, device or non-transitory computer-readable medium according to any one of Aspects 17 to 19, wherein the one or more third commands are transmitted between the reception of the request and the transmission of an initial command for the management operation of the sequence of multiple commands, between the transmission of commands of the sequence of multiple commands, or a combination thereof.

[0173] Aspect 21: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 14 to 20, wherein receiving the request includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for receiving the request via a dedicated bus between the interface and the controller, the dedicated bus being different from one or more buses via which one or more third commands are transmitted.

[0174] Aspect 22: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 14-21, wherein the sequence of multiple commands includes one or more row commands, one or more column commands, or a combination thereof.

[0175] Aspect 23: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 14 to 22, further comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for: before receiving the request, receiving from the interface at the controller an indication of a set of identifiers of a set of management operations including the management operation and a corresponding sequence of multiple commands associated with each management operation in the set of management operations, wherein the request is used for the management operation based on the identifier corresponding to the management operation included in the request; and wherein the sequence of multiple commands is transmitted according to the indication.

[0176] It should be noted that the aspects described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0177] An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

[0178] Aspect 24: A device comprising: a second semiconductor die (e.g., die 205), comprising a controller (e.g., controller 215) and an interface (e.g., interface block 220) coupled to the controller, the interface comprising a circuit system, the circuit system being operable to: transmit a request to the controller so that the controller schedules the interface to perform management operations associated with one or more memory arrays of one or more first semiconductor dies coupled to the second semiconductor die; receive a sequence of multiple first commands for the management operations from the controller based on the request; and transmit one or more second commands to at least one of the one or more first semiconductor dies to perform the management operations on the memory array, the one or more second commands each corresponding to one of the first commands.

[0179] An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

[0180] Aspect 25: A device comprising: a second semiconductor die (e.g., die 205), comprising a controller (e.g., controller 215) and an interface (e.g., interface block 220) coupled to the controller, the controller comprising a circuit system, the circuit system being operable to: receive a request to cause the controller to schedule the interface to perform management operations associated with one or more memory arrays of one or more first semiconductor dies coupled to the second semiconductor die; determine a sequence of multiple commands for the management operations based on the request; and transmit the sequence of multiple commands for the management operations from the controller to the interface based on the determination.

[0181] A system is described. The following provides an overview of aspects of the apparatus described herein:

[0182] Aspect 26: A system (e.g., system 200) comprising: one or more first semiconductor dies (e.g., one or more dies 240) comprising: one or more memory arrays (e.g., memory array 250); and one or more first interfaces (e.g., interface block 245), each of which comprises a first circuit system operable to access at least one corresponding memory array of the one or more memory arrays; and a second semiconductor die (e.g., die 205) coupled to the one or more first semiconductor dies, the second semiconductor die comprising: one or more controllers (e.g., controller 215), each controller operable to: receive a command to access the one or more memory arrays; and based on receiving the access command, to schedule access to the one or more memory arrays; and one or more second interfaces (e.g., interface block 220) coupled to the one or more controllers, each second interface including a second circuit system, the second circuit system being operable to: transmit a request to a corresponding controller so that the corresponding controller schedules the second interface to perform a management operation associated with a memory array in the one or more memory arrays; receive a sequence of a plurality of first commands for the management operation from the corresponding controller based on the request; and transmit one or more second commands to the first interface corresponding to the memory array to perform the management operation on the memory array, the one or more second commands each corresponding to one of the first commands.

[0183] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0184] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (e.g., conductive contact, connection, coupling) with each other if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. The conductive path between components that are in electronic communication (e.g., conductive contact, connection, coupling) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or may be an indirect conductive path that includes an intermediate component (e.g., a switch, transistor, or other component). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0185] The term "isolation" may refer to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from one another. When a component isolates two components, the component may induce changes that prevent a signal from flowing between other components using a conductive path that previously permitted the signal to flow.

[0186] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open-circuit relationship between components, where signals cannot currently be communicated between the components (e.g., via conductive paths), to a closed-circuit relationship between the components, where signals can be communicated between the components (e.g., via conductive paths). When a component, such as a controller, couples other components together, the component may induce a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0187] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The "Detailed Description" includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0188] In the accompanying drawings, similar components or features may have the same reference label. Similar components may be distinguished by following the reference label with one or more dashes and an additional label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label, regardless of the additional reference labels.

[0189] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted over a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processing system, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may be physically located at various locations, including distributed such that portions of the functions are implemented at different physical locations.

[0190] The illustrative blocks and modules described herein may be implemented or executed with one or more processors (e.g., DSPs, ASICs, FPGAs), discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0191] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0192] As used herein (including in the claims), the article "a" before a noun is open-ended and should be understood to refer to "at least one" of those nouns or "one or more" of those nouns. Therefore, the terms "one", "at least one", "one or more", and "at least one of one or more" are interchangeable. For example, if a claim recites "a component" that performs one or more functions, each of the individual functions may be performed by a single component or any combination of multiple components. Therefore, the term "a component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. The subsequent use of the term "the / said" to refer to the component introduced with the article "a" may refer to any or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and then referring to "the component" in the claim may be understood to be equivalent to referring to "at least one of one or more components". Similarly, a component introduced as "one or more components" subsequently referenced using the term "the / said" may refer to any or all of the one or more components. For example, a subsequent reference to "one or more components" in a claim may be understood to be equivalent to referring to "at least one of the one or more components."

[0193] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media or a combination of multiple media that can be accessed by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a computer or processor.

[0194] The description and drawings are provided to enable one of ordinary skill in the art to make or use the present disclosure. One of ordinary skill in the art will appreciate the various modifications of the present disclosure, and the techniques disclosed herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a second semiconductor die comprising a controller and an interface coupled to the controller, the interface comprising circuitry operable to: transmitting a request to the controller to cause the controller to schedule the interface to perform management operations associated with memory arrays of one or more first semiconductor dies coupled to the second semiconductor die; receiving, from the controller, a sequence of a plurality of first commands for the management operation based on the request; and One or more second commands are transmitted to at least one of the one or more first semiconductor dies to perform the management operation on the memory array, the one or more second commands each corresponding to one of the first commands.

2. The apparatus according to claim 1, wherein: The first command is a command for accessing the memory array, and Each first command includes an indication that the first command is associated with the management operation.

3. The apparatus according to claim 2, wherein: The request includes a tag for associating the first command with the request, and The indication includes the tag to associate the first command with the management operation based on the request including the tag.

4. The apparatus of claim 1 , wherein the circuit system is further operable to: Based on the sequence of a plurality of first commands for the management operation, replacing the first commands with the one or more second commands based on the management operation scheduled for request, wherein transmitting the one or more second commands is based on the replacing.

5. The apparatus of claim 4, wherein to replace the first command, the circuit system is operable to: One or more of the first commands are replaced with a corresponding second command of a different type.

6. The apparatus of claim 4, wherein the circuit system is further operable to: First address information included in one or more of the first commands is replaced with second address information.

7. The apparatus of claim 1, wherein the circuit system is further operable to: One or more third commands are received to access the memory array or another memory array of the one or more first semiconductor dies, wherein the one or more third commands are received between the transmission of the request and receipt of an initial first command of the sequence of multiple first commands, between first commands of the sequence of multiple first commands, or a combination thereof.

8. The apparatus of claim 1 , wherein the request comprises a tag for associating the first command with the request, address information associated with the management operation, a first indication of a duration within which the controller is requested to schedule the interface to perform the management operation, a second indication of the sequence of multiple first commands, or a combination thereof.

9. The apparatus of claim 1 , wherein to transmit the request, the circuitry is operable to: The request is transmitted via a dedicated bus between the interface and the controller, the dedicated bus being distinct from one or more buses over which the sequence of multiple first commands is received.

10. The apparatus of claim 1, wherein the sequence of a plurality of first commands comprises one or more row commands, one or more column commands, or a combination thereof.

11. The apparatus of claim 1 , wherein the circuit system is further operable to: Prior to transmitting the request, transmitting to the controller an indication of a set of management operations including the management operation and a set of identifiers of a corresponding sequence of a plurality of commands associated with each management operation in the set of management operations, wherein: the request being for the management operation based on the request including an identifier corresponding to the management operation; and The sequence of a plurality of first commands is received in accordance with the indication.

12. The apparatus of claim 1, wherein the management operation comprises a refresh operation on one or more rows of the memory array, a row hammer mitigation operation on one or more rows of the memory array, a scrub operation on one or more rows of the memory array, or a repair operation on one or more rows of the memory array.

13. The apparatus of claim 1, wherein the sequence of multiple first commands and the one or more second commands are associated with a same execution duration.

14. A method comprising: transmitting a request from an interface of a second semiconductor die to a controller of the second semiconductor die to cause the controller to schedule the interface to perform a management operation associated with a memory array of one or more first semiconductor dies coupled to the second semiconductor die; receiving, at the interface from the controller, a sequence of a plurality of first commands for the management operation based on the request; and One or more second commands are transmitted from the interface to at least one of the one or more first semiconductor dies to perform the management operation on the memory array, the one or more second commands each corresponding to one of the first commands.

15. The method according to claim 14, wherein: The first command is a command for accessing the memory array, and Each first command includes an indication that the first command is associated with the management operation.

16. The method of claim 15, wherein: The request includes a tag for associating the first command with the request, and Each first command includes the tag to associate the first command with the management operation based on the request including the tag.

17. The method of claim 14, further comprising: Based on the sequence of a plurality of first commands for the management operation, replacing the first commands with the one or more second commands based on the management operation scheduled for request, wherein transmitting the one or more second commands is based on the replacing.

18. The method of claim 17, wherein replacing the first command comprises: One or more of the first commands are replaced with a corresponding second command of a different type.

19. The method of claim 17, further comprising: First address information included in one or more of the first commands is replaced with second address information.

20. The method of claim 17, further comprising: One or more third commands are received from the controller at the interface to access the memory array or another memory array of the one or more first semiconductor dies, wherein the one or more third commands are received between the transmission of the request and receipt of an initial first command of the sequence of multiple first commands, between first commands of the sequence of multiple first commands, or a combination thereof.

21. The method of claim 14, wherein the request comprises a tag for associating the first command with the request, address information associated with the management operation, a first indication of a duration within which the controller is requested to schedule the interface to perform the management operation, a second indication of the sequence of multiple first commands, or a combination thereof.

22. The method of claim 14, wherein transmitting the request comprises: The request is transmitted via a dedicated bus between the interface and the controller, the dedicated bus being distinct from one or more buses over which the sequence of multiple first commands is received.

23. The method of claim 14, wherein the sequence of a plurality of first commands comprises one or more row commands, one or more column commands, or a combination thereof.

24. The method of claim 14, further comprising: Prior to transmitting the request, transmitting from the interface to the controller an indication of a set of management operations including the management operation and a set of identifiers of a corresponding sequence of a plurality of commands associated with each management operation in the set of management operations, wherein: The request is for the management operation based on the request including an identifier corresponding to the management operation; and The sequence of a plurality of first commands is received in accordance with the indication.

25. The method of claim 14, wherein the management operation comprises a refresh operation on one or more rows of the memory array, a row hammer mitigation operation on one or more rows of the memory array, a scrub operation on one or more rows of the memory array, or a repair operation on one or more rows of the memory array.

26. The method of claim 14, wherein the sequence of multiple first commands and the one or more second commands are associated with a same execution duration.

27. A system comprising: One or more first semiconductor dies comprising: one or more memory arrays; and one or more first interfaces, each comprising first circuitry operable to access at least one corresponding memory array of the one or more memory arrays; and a second semiconductor die coupled to the one or more first semiconductor dies, the second semiconductor die comprising: One or more controllers, each controller being operable to: receiving a command to access the one or more memory arrays; and scheduling access of the one or more memory arrays based on receiving the access command; and one or more second interfaces coupled to the one or more controllers, each second interface comprising a second circuit system operable to: transmitting a request to a corresponding controller to cause the corresponding controller to schedule the second interface to perform a management operation associated with a memory array of the one or more memory arrays; receiving a sequence of a plurality of first commands for the management operation from the corresponding controller based on the request; and One or more second commands are transmitted to a first interface corresponding to the memory array to perform the management operation on the memory array, the one or more second commands each corresponding to one of the first commands.

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