Maintaining integrity of memory components

Abstract

The invention relates to maintaining integrity of memory components. A system and method for maintaining integrity of a memory component is provided. The system and method includes receiving, by a memory controller, a plurality of memory requests including at least one write request; assigning a block of data into a buffer cache to cache the at least one write request; detecting whether sufficient time exceeding a predetermined threshold has elapsed; in response to a sufficient time exceeding the predetermined threshold has elapsed, marking back-end memory as available; and in response to the flag, extracting the at least one write request to write data to the memory component.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 63 / 517.294, filed on August 2, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The following generally relates to one or more systems for memory. The present disclosure particularly relates to reliability, availability, and serviceability (RAS) features of memory. Background Art

[0004] Memory integrity is a hallmark of modern computing. Memory systems are often equipped with hardware and / or software / firmware protocols configured to check the integrity of one or more memory segments. These protocols may also determine whether the data located therein is accessible to higher-level subsystems or whether the data is error-free.

[0005] A typical RAS infrastructure for a memory system may be configured to detect and repair errors in the system. For example, RAS features may include an error correction system and a subsystem that executes error correction code. Such protocols are hardware features that can automatically correct memory errors once they are flagged by the RAS infrastructure. These errors may be due to noise, cosmic rays, hardware transients due to sudden changes in power supply lines, or physical errors in the media storing the data.

[0006] In addition, as computer memory subsystems scale in capacity, data errors become more common. Various error detection and correction methods may be used alone or in combination to ensure that data read from memory is identical to data previously stored or written. RAID (Redundant Array of Independent Disks) is one such error correction method. RAID was developed for, and historically used in, asynchronously accessed storage devices (e.g., disks).

[0007] In contrast, computer system main memory fault protection typically uses methods of operating multiple memory components in lockstep. Compared to such methods, RAID achieves relatively efficient and higher performance memory read access, and provides both memory device and more comprehensive channel fault tolerance and data protection compared to other data integrity methods. Fast and efficient read access is desirable because reads typically affect computing system performance and therefore power consumption. Write access typically has less impact on system performance.

[0008] RAID data and channel protection inherently causes significant memory access amplification when writing data. Typically, for each write (or store) to memory requested by the host computing system, RAID requires two separate memory read (or load) accesses followed by two write (or store) accesses. This write access memory operation or command amplification complicates the use of RAID to protect low-latency, typically synchronously accessed memory that services a mix of read and write requests.

[0009] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic DRAM (SDRAM), static RAM (SDRAM), flash memory, and others. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power source. SRAM memory cells can maintain their programmed state for the duration that the system is powered on. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time even in the absence of external power.

[0010] Many memory devices include multiple memory components. For example, a single read or write operation from a memory controller transfers data from or to multiple memory components in parallel. Therefore, a single access may include data stored across multiple memory devices. Compute Express Link (CXL) DRAM memory devices typically require high RAS. Summary of the invention

[0011] One aspect of the present disclosure relates to a method for maintaining the integrity of a memory component. The method includes: receiving, by a memory controller, a plurality of memory requests including at least one write request; allocating a data block to a buffer cache to cache the at least one write request; detecting whether a sufficient time exceeding a predetermined threshold has passed; in response to a sufficient time exceeding the predetermined threshold having passed, marking a backend memory as available; and in response to the marking, extracting the at least one write request to write data to the memory component.

[0012] In some embodiments, a moving average of the request rate is calculated over a variable time window.

[0013] In some embodiments, the method further comprises calculating a partial parity and storing it in a buffer cache.

[0014] In some embodiments, the method further includes writing both the original parity and the new data sectors to the backend memory.

[0015] In some embodiments, the method further includes reading unwritten data sectors from the backend memory and calculating new stripe parity.

[0016] In some embodiments, the method further includes writing both new parity and new data sectors to the backend memory.

[0017] Another aspect of the present disclosure is a system configured to maintain the integrity of a memory component. The system includes a memory controller configured to perform operations including: receiving a plurality of requests, the plurality of requests including at least one write request; allocating a data block to a buffer cache to cache the at least one write request; detecting whether a sufficient time exceeding a predetermined threshold has passed; in response to a sufficient time exceeding the predetermined threshold having passed, marking a backend memory as available; and in response to the marking, extracting the at least one write request to write data to the memory component.

[0018] In some embodiments, the operations further include determining whether the irrelevant request has passed.

[0019] In some embodiments, the operations further include determining whether sufficient time has passed to exceed the predetermined threshold based on one or more measurements of past requests.

[0020] In some embodiments, the one or more measurements include a moving average of the request rate.

[0021] In some embodiments, the moving average of the request rate is calculated over a variable time window.

[0022] In some embodiments, the operations further include reading old data when the backend memory is available. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The illustrative embodiments may take the form of various components and arrangements of components. The illustrative embodiments are shown in the accompanying drawings, and throughout the drawings, the same reference numerals may indicate corresponding or similar parts in the various drawings. The drawings are for the purpose of illustrating the embodiments only and should not be construed as limiting the present disclosure. Given the following enabling description of the drawings, the novel aspects of the present disclosure should be apparent to one of ordinary skill in the art.

[0024] Figure 1 A block diagram illustrating a system including a host and a memory module according to aspects of the present disclosure.

[0025] Figure 2 A table showing command amplification performance for several scenarios is illustrated in accordance with several aspects of the present disclosure.

[0026] Figure 3 Graphs illustrating several aspects according to the present disclosure.

[0027] Figure 4 Graphs illustrating several aspects according to the present disclosure.

[0028] Figure 5 Graphs illustrating several aspects according to the present disclosure.

[0029] Figure 6 Graphs illustrating several aspects according to the present disclosure.

[0030] Figure 7 Graphs illustrating several aspects according to the present disclosure.

[0031] Figure 8 Graphs illustrating several aspects according to the present disclosure.

[0032] Fig. 9 Methods according to several aspects of the present disclosure are described. DETAILED DESCRIPTION

[0033] Although illustrative embodiments are described herein for particular applications, the present disclosure is not limited thereto. A skilled artisan who has access to the teachings provided herein will recognize additional applications, modifications, and embodiments within the scope thereof, as well as additional areas in which the present disclosure will have significant utility.

[0034] By way of example only and not limitation, embodiments of the present disclosure include a platform of RAID protected memory devices. Embodiments feature the use and / or mechanization of buffer memory or cache memory, not to improve read performance, but to reduce the frequency of RAID write access memory command amplification in memory, and thus reduce its negative performance and power consumption impact.

[0035] Embodiments provide several advantages over conventional systems. For example, a write cache for caching either or both of data read from a memory or storage device back end and / or write data written by a host front end as provided by embodiments can both reduce the number of back end reads and writes and filter requests to the back end for accesses that are close to each other in both address space and cycle or access sequence order.

[0036] In addition, write caching as provided by the embodiments may also be combined with RAS schemes and pre-fetching to also reduce average read latency. For example, the following may be pre-fetched and cached to reduce latency and / or operations involved in completing subsequent host system requests.

[0037] Figure 1A functional block diagram of a system 100 according to an embodiment is illustrated. The system 100 includes a host system 102 coupled to a memory module 101 via a communication link 105. The host system 102 may be a system or subsystem configured to access the memory module 101 to write data therein or read data therefrom. For example, but not limited to, the host system may be a central processing unit (CPU), a graphics processing unit (GPU), or generally a computer system or subsystem equipped in hardware and software with components and protocols for performing write and read operations from the memory module 101.

[0038] Furthermore, one of ordinary skill in the art will readily appreciate that the arrangement of data in the memory module 101 may be arbitrary, and the methods and systems disclosed herein are not limited to a particular data arrangement when considering the memory module 101. Furthermore, the host system 102 may be communicatively coupled to the memory module 101 via a bus, a CXL bus, or may be co-located on the same chip or on the same board.

[0039] Memory module 101 may include a front end module 106 having circuitry for input and output functions. Such circuitry may include, for example, but not limited to, hardware for packaging commands received from host system 102 in a predetermined format, and similarly, circuitry for packaging data obtained from memory in a predetermined format before routing such data to host system 102 upon request.

[0040] The memory module 101 may include a buffer cache (or buffer memory) 108 that is configured to cache write data in order to limit the frequency of RAID access memory command amplification. This feature may be achieved by accessing the buffer cache 108 to retrieve data when performing an operation to maintain the integrity of a portion of the memory component 114. In general, the buffer cache 108 may be configured for write caching and pre-fetching write data stored therein.

[0041] The memory module 101 may further include a security and reliability, availability, and serviceability (SRAS) module 110 that may be configured to perform one or more tasks associated with maintaining the integrity of data located in the memory component 114. For example, but not limited to, one such task may be a RAID protocol configured to ensure the integrity of the data in the memory component 114. When executing such a RAID protocol, the SRAS module 110 may be configured to cache write data in the buffer cache 108 and / or it may be configured to pre-fetch write data from the buffer cache 108 to reduce RAID access command amplification.

[0042] The memory module 101 may further include a back-end module 112 that interfaces the SRAS module 110 with a memory component 114. The module 104 may generally include interface circuitry that allows read / write operations to be performed on one or more sectors of the memory component 114.

[0043] The memory module 101 may include a plurality of memory components 114. The memory components 114 may include memory cells of any architecture without departing from the teachings of the present disclosure. For example, the memory components 114 may include a DRAM array, an SRAM array, etc. In general, the memory components 114 may be any storage technology in which an array of memory segments is used to store data.

[0044] Figure 2 Several performance examples 200 according to an embodiment are described. Figure 2 middle, Figure 1 The host system 102 of the embodiment exchanges commands and / or data with the memory module 101 at a bandwidth corresponding to, for example, but not limited to, an 8-lane CXL3 host interface. Therefore, the performance results of the embodiments are subject to these constraints. Without loss of generality, one of ordinary skill in the art will recognize that the performance results may vary depending on bandwidth and other factors while providing the reduction in command amplification provided by the embodiments.

[0045] Specifically, table 202 illustrates typical read / write hybrid commands sent from host system 102 to memory module 101. These commands may appear in several non-limiting sample cases in column 202a of table 202. For example, sample case -1 Figure 2 (1F2) represents 100% write commands; sample case -2F2 represents 30% read commands and 70% write commands; sample case -3F2 represents an even split: 50% read and 50% write commands; and sample case -4F2 represents 100% read commands. The read commands 202b and write commands 202c of table 202 illustrate general bandwidth consumption. Here, bandwidth consumption is a function of the architecture of the communication link 105 coupling the host system 102 and the memory module 101.

[0046] Table 204 depicts a scenario where the RAID protocol is executed naively, i.e., as typically done with the RAID protocol in state-of-the-art systems. In this sample approach, in an embodiment, the write command 204c is amplified by a factor of 2 compared to the right command 202c. Table 204 also illustrates the read command overhead 204b. This results in additional bandwidth usage and memory access. As can be seen in column 204d of table 204, when considering sample cases 1-3, the write command is amplified by at least 2.5 times (e.g., 2.5X, 3.11X, 4X, etc.). The only sample case without command amplification is sample case-4, where all requests of the host system 102 are read requests.

[0047] Table 206 illustrates the performance of an embodiment employing write caching and prefetching commands with buffer cache 108. Command amplification is 1.25X for case-1F2 (reduced from 4X in table 204), 2X for case-2F2 (reduced from 3.11X), and 1.12X for case-3F2 (reduced from 2.5X). As demonstrated herein, system 100 can use an exemplary write caching and prefetching approach to reduce memory access command amplification and save bandwidth and power.

[0048] Figure 3 Graph 300 illustrates memory access patterns for a naive RAID case when read cache hits and misses occur in the absence of RAS errors. Specifically, graph 300 shows three sample cases: Sample case 1 when there is a cache read hit 302 Figure 3 (1F3); sample case -2F3 when there is a cache read miss 304 without cache allocation; and sample case -3F3 when there is a cache read miss 306 with allocation. In sample case -3F3, over time, cache allocations require additional cache transactions, such as cache requests 308 and discard victims 310, which require and consume additional cache bandwidth. For example, if the cache is kept clean, i.e., all writes are written to the memory component 114, then discard victims 310 are not needed.

[0049] Figure 4 Describe the sample situation (for example, sample situation-1 Figure 4 400 of memory access patterns for sample cases (1F4) and (2F4) characterized by read / write collection cache hits and misses without RAS errors. In such cases, cache misses with allocations occur (e.g., 402 and 404), and cache misses with collection of RAS stripe discards occur before allocations. Cache allocations then require additional cache transactions, increasing the required cache bandwidth. If the cache remains clean, i.e., all writes are written to the memory component 114, then discards of victim segments 406 are not required.

[0050] Figure 5 Description for example sample case-1 Figure 5Graph 500 of memory access patterns for the case of (1F5) and sample case -2F5, characterized by write cache hits without and with gather and cache allocation. In such cases, parity is not allocated in cache, and stripe parity reads are updated by the RAS manager (e.g., within the SRAS module 110) in the buffer cache 108. In this embodiment, both the write cache new data 502 and parity are implemented to achieve stripe gather. Parity is updated using updates to the miss table array. In addition, the write request initiates both data and parity cache requests, and the tag must know the RAS mapping from the SRAS module 110.

[0051] Figure 6 Description for example sample case-1 Figure 6 An exemplary graph 600 of memory access patterns for the case of (1F6) and sample case - 2F6, characterized by a write cache miss with gather and parity cache allocation. In these cases, the write is not allocated in cache, and the stripe parity read and update are affected by the RAS manager in the SRAS module 110. In addition, the write allocated in cache is dirty (i.e., there is no write-through), and the victim stripe parity is updated by the RAS manager of the SRAS module 110.

[0052] Figure 7 Description for example sample case-1 Figure 7 An exemplary graph 700 of memory access patterns for cases (1F7) and sample case - 2F7, characterized by write cache misses with gather and parity cache allocation. In these cases, writes are not allocated in cache and stripe parity reads are updated by the RAS manager of the SRAS module 110. In addition, writes allocate new data in cache and miss table updates parity to achieve gather.

[0053] Figure 8 Description for example sample case-1 Figure 8An exemplary graph 800 of memory access patterns for the case of (1F8) and sample case - 2F8, characterized by the collection of write cache misses on the cached RAS stripes. In sample cases - 1F8 and 2F8, write requests (e.g., 802 and 804) cache new data 806 and stripe parity 808, which enables collection, and the miss table 810 updates the stripe parity 808. In these cases, if parity is always the last stripe sector to be discarded, then write data cache hits and RAS stripe parity cache misses are not possible. If the cache is maintained as clean, then the victim cache line does not need to be discarded and written back to memory. However, the write request initiates both data and parity cache requests, and the cache tags are aware of the RAS mapping.

[0054] As will be readily appreciated by those skilled in the art, the write cache features contemplated in the present disclosure may be implemented in several ways. By way of example only, four non-limiting examples of write cache implementations for channel fault tolerance within an overall RAS scheme for implementing a 64B host system user data cache line length in a RAID5 (4+1) subsystem are listed below. Write cache lines may be managed as 64B sectors to match the host system cache line size and facilitate write cache management.

[0055] In a first embodiment, the write cache memory has a row or block size of 320B (i.e., 256B user data + 64B RAID XOR or 5x 64B sectors per write cache line, sized to fit exactly in a RAID stripe). In a second embodiment, a write cache memory with a row or block size greater than 320B (e.g., 512B) may contain an entire RAID stripe including both 4 user data 64B sectors and one associated RAID stripe exclusive-OR (XOR) 64B sector, constituting a 320B portion of a cache line.

[0056] In a third embodiment, separate cache memories may be used, one cache with a 256B cache line / block size (containing 4 adjacent 64B user data sectors) and a second cache with a 64B cache line / block size for RAS XOR. In a fourth embodiment, the write cache memory has a 64B line or block size, where each line can store a 64B host system user data cache line or a 64B RAID XOR without cache index conflicts between all user data cache lines in the RAID stripe and the RAID stripe XOR.

[0057] Fig. 9A flow chart illustrating an exemplary method 900 of practicing an embodiment of the present invention, beginning at block 902. The method 900 includes allocating host write request data to a write buffer cache (e.g., buffer cache 108) at block 904. At decision block 906, the method 900 detects whether enough time has passed and / or unrelated requests, or infers that the backend memory (e.g., memory 114) is occasionally available based on one or more measurements of past requests. Such requests may include, for example, a moving average request rate over a variable time window.

[0058] If the backend memory is available, the method 900 includes reading the old data and calculating partial parity for storage in the buffer cache at block 908. The method 900 further includes repeating blocks 904 through 908 for write requests to the same RAID stripe. Additionally, at block 910, the method 900 further includes waiting until a data or parity cache entry is victimized, or if it includes initiating the victimization, if the entire RAID stripe has been written and the backend memory is available.

[0059] If the write is already cached for the entire RAID stripe of data, then method 900 includes calculating parity (ie, discarding the cached partial parity) and writing both the data and the calculated parity to the back end.

[0060] Otherwise, the method 900 proceeds to block 912 to read the original parity from the back-end memory and calculate the new stripe parity. Block 912 also includes writing both the parity and the new data sectors to the back-end memory. Alternatively, the method 900 will proceed to block 914 to read the unwritten data sectors from the back-end, calculate the new stripe parity, and write both the new parity and the new data sectors to the back-end. The exemplary method 900 ends at block 916.

[0061] Having described several specific embodiments, a general embodiment consistent with the teachings of the present disclosure is now described. For example, but not limited to, such embodiments may be a system or method. An example system may include a RAID subsystem configured to maintain the integrity of a segment of memory. The system may further include a buffer memory communicatively coupled to the RAID subsystem. And the RAID subsystem may be configured to limit the frequency of RAID access memory command amplification by accessing the buffer memory, the subsystem is performing an operation configured to maintain the integrity of a segment of memory.

[0062] Without loss of generality, the buffer memory may be a cache memory, or it may be a memory module of a computer system, or it may be a memory module of a storage device. The RAID subsystem is further configured to limit the frequency of amplification of RAID write access memory commands. In addition, the system may be configured to cache data in the buffer memory, and the cached data may be user data and / or RAID XOR parity data. In such cases, the parity does not need to be read more than once for any subsequent write request.

[0063] In addition, the RAID subsystem may be further configured to reduce RAID parity reads when more than one data write request is collected into the buffer memory. Also, the RAID subsystem may be further configured to perform two or three back-end reads and / or three back-end writes when two user data writes are collected for a given RAID stripe.

[0064] An example method may be configured for reducing RAID command amplification when accessing memory. The method may include performing certain operations by a RAID subsystem configured to maintain the integrity of a segment of memory. The operations may include caching data in a buffer memory and limiting the frequency of RAID access memory command amplification. The latter may be achieved by accessing the buffer memory to retrieve data while performing operations to maintain the integrity of the segment of memory.

[0065] In the above method, the buffer memory may be one of the cache memories. In addition, the memory (i.e., not the buffer memory) may be a computer system memory or a storage memory. In the above method, the frequency of RAID access memory command amplification may be the frequency of write access memory command amplification, and the cached data may include write user data and / or RAID XOR parity data. And for any subsequent write request, the parity data does not need to be read more than once.

[0066] The operations may further include reducing RAID parity reads when more than one data write request is collected into the buffer memory. Also, the operations may further include performing two or three back-end reads when two user data writes are collected for a given RAID stripe. Furthermore, the operations may further include performing three back-end writes.

[0067] In general, embodiments confer several advantages, some of which are discussed below. For example, a write cache for caching either or both of data read from a memory or storage device back end and / or write data written by a host front end as provided by embodiments can both reduce the number of back end reads and writes and filter requests to the back end for accesses that are close to each other in both address space and cycle or access sequence order.

[0068] Additionally, write caching as provided by embodiments may also be combined with RAS schemes and prefetching to also reduce average read latency. For example, the following may be prefetched and cached to reduce latency and / or operations involved in completing subsequent host system requests: On a read where a RAID detects a failure, channel fault tolerance requires reading all other user data and parity in the associated RAID stripe, which may then be cached to satisfy future host read requests.

[0069] Those skilled in the relevant art will appreciate that various adaptations and modifications of the embodiments described above may be configured without departing from the scope and spirit of the present disclosure. Therefore, it should be understood that within the scope of the appended claims, the present disclosure may be practiced in a manner other than that specifically described herein.

Claims

1. A method for maintaining the integrity of a memory component, the method comprising: receiving, by a memory controller, a plurality of memory requests including at least one write request; allocating data blocks into a buffer cache to cache the at least one write request; detecting whether sufficient time has passed to exceed a predetermined threshold, In response to a sufficient time having passed to exceed the predetermined threshold, Mark the backend storage as available; and In response to the marking, the at least one write request is extracted to write data to the memory component.

2. The method of claim 1, further comprising determining whether an irrelevant request has passed. 3 . The method of claim 1 , further comprising determining whether sufficient time has passed to exceed the predetermined threshold based on one or more measurements of past requests. The method of claim 3 , wherein the one or more measurements comprise a moving average of a request rate.

5. The method of claim 1, further comprising reading old data when the backend memory is available. The method of claim 1 , wherein the storage component is a RAID stripe.

7. The method of claim 6, further comprising waiting until a data or parity cache entry is victimized.

8. The method of claim 6, further comprising initiating victimization when the RAID stripe has been written and the backend storage is available.

9. The method of claim 6, further comprising reading original parity from the backend memory and calculating new stripe parity.

10. A system configured to maintain the integrity of a memory component, the system comprising: A memory controller configured to perform operations including: receiving a plurality of requests, the plurality of requests including at least one write request; allocating data blocks into a buffer cache to cache the at least one write request; detecting whether sufficient time has passed to exceed a predetermined threshold, In response to a sufficient time having passed to exceed the predetermined threshold, Mark the backend storage as available; and In response to the marking, the at least one write request is extracted to write data to the memory component.

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