Method and apparatus to differentially update programmable circuitry

Abstract

The invention relates to a method and apparatus to differentially update programmable circuitry. An example apparatus includes interface circuitry; a machine readable instruction; and programmable circuitry configured to instantiate and / or execute the machine-readable instructions to: determine a number of memory sectors (210-230) to shift an original image (105) based on a length of additional data (330) in an updated image (110) in differential image data; shifting the original image (105) by the number of memory sectors to create a swap area (476), the swap area including the number of memory sectors; and constructing the updated image (110) based on the differential image data (155) and the original image (105).

Description

Technical Field

[0001] The present description relates generally to updating programmable circuitry and, more particularly, to methods and apparatus to differentially update programmable circuitry. Background Art

[0002] Microprocessor circuitry is programmable circuitry that can be configured to execute machine-readable instructions. Microprocessor circuitry can be configured by an image stored in flash memory. The image contains a plurality of instructions that, when executed, cause the microprocessor circuitry to instantiate the circuitry to perform an operation. Summary of the invention

[0003] For methods and devices for differentially updating programmable circuit systems, an example device includes: an interface circuit system; machine-readable instructions; and a programmable circuit system configured to instantiate and / or execute the machine-readable instructions to perform the following operations: determine a certain number of memory sectors by which the original image is to be shifted based on the length of additional data in an updated image in differential image data; shift the original image by the number of memory sectors to create a swap area, the swap area including the number of memory sectors; and construct the update image based on the differential image data and the original image. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an example update environment in which example microprocessor circuitry is to update an original image in an example flash memory using example update circuitry in response to differential image data.

[0005] Figure 2 is Figure 1 An example of an original image of the microprocessor circuit system is updated during operation Figure 1 Timing diagram of the Flash memory.

[0006] Figure 3 yes Figure 1 A block diagram of an example implementation of update circuitry of FIG. 1 , wherein example differential update controller circuitry constructs an update image using differential image data.

[0007] Figure 4 It is used to build Figure 3 The updated image and replace it when building the updated image part Figure 1 The original image Figure 3 A block diagram of an example implementation of a differential update controller circuit.

[0008] Figure 5 is used to build Figure 3-4 The updated image and replace it when building the updated image part Figure 1 and 4 During the instance operation of the original image Figure 1 and 2 Timing diagram of the Flash memory.

[0009] Figure 6 Yes means you can use Figure 3 Example programmable circuitry implementations of update circuitry to implement, instantiate and / or perform example machine-readable instructions and / or flow diagrams of example operations.

[0010] Figures 7A-7C Form means that you can use Figure 3-5 The differential update controller circuit system and / or more generally use Figure 3 Example programmable circuitry implementations of update circuitry to implement, instantiate and / or perform example machine-readable instructions and / or flow diagrams of example operations.

[0011] Figure 8 is a program comprising machine-readable instructions structured to implement, instantiate and / or execute an example Figure 6 , 7A , 7B and / or 7C to implement the example operation Figure 3 A block diagram of an example processing platform of a programmable circuit system for updating circuit system.

[0012] Fig. 9 yes Figure 8 A block diagram of an example implementation of a programmable circuit system.

[0013] Fig.10 yes Figure 8 A block diagram of another example implementation of a programmable circuit system.

[0014] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0015] The drawings are not necessarily drawn to scale. In general, the same reference numerals in the drawings and the specification refer to the same or similar parts. Although the drawings show regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, boundaries and / or lines may be unobservable, mixed, and / or irregular.

[0016] Microprocessor circuitry is programmable circuitry that can be configured to execute machine-readable instructions. Microprocessor circuitry can be configured by an image stored in flash memory. The image contains a plurality of instructions that, when executed, cause the microprocessor circuitry to instantiate the circuitry to perform operations. As microprocessor circuitry becomes more common, the motivation for designers to efficiently update images of microprocessor circuitry continues to increase.

[0017] Designers can update executable files, such as images for programmable circuit systems, to improve operation, add additional functionality, fix problems, etc. An updated version of a previous executable file containing the desired improvements and / or additions is created external to the device that is used to execute the instructions. For example, a manufacturer or supplier can generate the updated version as a software update. Once created, the updated image is supplied to the device that will execute the instructions.

[0018] Some devices store the update image in a flash memory of the programmable circuit system. Using the flash memory to store the update image allows the programmable circuit system to continue to store the update image when the programmable circuit system is powered off. The process to replace the existing / original image with the update image begins in response to a power cycle (e.g., turning off and on) of the programmable circuit system. Such a process of replacing the existing / original image with the update image may be referred to as an update process. Once power is restored, the programmable circuit system executes the machine-readable instructions from the flash memory to instantiate the circuit system, thereby replacing the original image with the update image.

[0019] Some circuit systems instantiated to update programmable circuit systems require that a complete version of both the original image and the update image be stored in flash memory in order to replace the original image with the update image. However, as programmable circuit systems become more complex, the size of the images continues to increase. In some devices, the available portion of the flash memory used to store the update image may not be large enough to store the update image. In such devices, designers need to add external flash memory to store the update image. Alternatively, some designers have begun to look for alternative methods of storing the update image. One alternative method includes reducing the size of the update image.

[0020] The Bsdiff process can be used to reduce the executable file to generate differential image data representing the difference between the original image and the updated image. Bsdiff is described in Colin Percival's " Simple diff of executable code ( Differences of Executable Code " (which is incorporated by reference in its entirety). SimpleLink TM A similar process is described in the CC13x2 / CC26x2SDK TI 15.4-Stck User Guide (which is incorporated by reference in its entirety) which can be found at

[0021] https: / / software-dl.ti.com / simplelink / esd / simplelink_cc13x2_26x2_sdk / 4.40.04.04 / exports / do cs / ti154stack / html / ti154stack / oad-turbo-oad.html#turbo- oad-image-tool The Bsdiff process uses the original image and the update image to generate differential image data. The differential image data can be stored in a reduced memory portion compared to storing the update image. However, in a resource-constrained system such as a microprocessor circuit system, replacing the update image with differential image data for use in a programmable circuit system requires building the update image during the update process. Therefore, it is necessary to modify the existing process for updating the programmable circuit system to include building the update image using the differential image data.

[0022] Examples described herein include methods and apparatus for differentially updating a programmable circuit system using differential image data. In some described examples, the update circuit system constructs an update image using the differential image data and an original image of the programmable circuit system. In such examples, the update circuit system includes a differential update controller circuit system that constructs a portion of the update image in a random access memory (RAM). The differential update controller circuit system prepares for an update process by shifting the original image in a flash memory to create a swap area. The swap area is a plurality of memory sectors. A memory sector is a portion of the flash memory corresponding to the plurality of bits that are cleared when any one of the plurality of bits is written. The differential update controller circuit system determines a plurality of memory sectors to be used for the swap area based on the differential image data.

[0023] The differential update controller circuitry monitors the portion of the update image in the RAM to determine when to transfer a portion of the constructed update image. The differential update controller circuitry transfers memory sectors equivalent to the constructed update image to the swap area when the update image is constructed. When the update image is transferred to the swap area, the differential update controller circuitry shifts the swap area by clearing the memory sectors storing the portion of the original image, which no longer requires the remaining portion of the update image to be constructed. Advantageously, the update circuitry described herein uses the differential image data to update the programmable circuitry.

[0024] Figure 1 is a block diagram of an example update environment 100. Figure 1 In the example of , update environment 100 includes example original image 105, example update image 110, example differential circuitry 115, example update media 120, and example microprocessor circuitry 125. Update environment 100 differentially updates microprocessor circuitry 125 by replacing original image 105 with update image 110. Alternatively, environment 100 can be modified according to the teachings described herein to replace and / or modify microprocessor circuitry 125 with an alternative programmable circuitry.

[0025] Images 105 and 110 are executable files that, when executed, cause microprocessor circuit system 125 to instantiate circuit system to perform operations. Images 105 and 110 contain multiple machine-readable instructions. The machine-readable instructions of images 105 and 110 define the operations to be performed by microprocessor circuit 125. In some instances, images 105 and 110 are binary files containing machine-readable instructions specific to the type, construction, version and / or style of programmable circuit system. For example, original image 105 may contain multiple sixteen-bit instructions specific to programmable circuit system configured to execute sixteen-bit instructions. In some instances, designers use programming languages ​​such as assembler C, C++, C# to create relatively high-level abstractions of operations generated by the execution of images 105 and 110. In such instances, designers can use converters, compilers and / or synthesis tools to obtain images 105 and / or 110 from relatively high-level abstractions.

[0026] exist Figure 1 In the example of , the original image 105 represents an executable file stored in the microprocessor circuit system 125 before the update process described herein. The original image 105 includes a plurality of machine-readable instructions that are executable by the microprocessor circuit system 125.

[0027] Update image 110 represents an executable file to be stored in microprocessor circuit system 125. In some examples, update image 110 is a modified version of original image 105. For example, a designer deletes, adds, and / or modifies machine-readable instructions of original image 105 to generate update image 110. In response to the update process, update image 110 replaces original image 105 in microprocessor circuit system 125. During the update process, microprocessor circuit system 125 replaces original image 105 with update image 110. After the update process, update image 110 may be referred to as the original image. Figure 2-7C Describe such an update process.

[0028] Differential circuit system 115 receives images 105 and 110. In some examples, differential circuit system 115 receives images 105 and 110 from external circuit systems such as converters, compilers, synthesis tools, etc. In other examples, differential circuit system 115 accesses images 105 and 110 based on file paths corresponding to each of images 105 and 110 (e.g., locations on a network, personal computer, workstation, etc.). Differential circuit system 115 generates differential image data based on images 105 and 110. Differential circuit system 115 generates differential image data using the Bsdiff process described above. Differential circuit system 115 supplies the differential image data to microprocessor circuit system 125 using update media 120. In some examples, differential circuit system 115 writes the differential image data to a memory location in microprocessor circuit system 125. Advantageously, microprocessor circuit system 125 can use the differential image data and original image 105 to construct updated image 110.

[0029] In some examples, differential circuitry 115 includes circuitry to compress differential image data. For example, differential circuitry 115 compresses a number of bits by creating a representation of a number of similar bits and / or a sequence of bits using fewer bits. In such an example, when one hundred twenty-eight bits have the same logic level (e.g., logic one or logic zero), differential circuitry 115 may compress one hundred twenty-eight sequential bits to eight bits. Advantageously, the length of the differential image data is less than the length of update image 110. Advantageously, differential circuitry 115 reduces the amount of non-volatile memory space required to update microprocessor circuitry 125.

[0030] Update medium 120 communicatively couples differential circuitry 115 to microprocessor circuitry 125. Update medium 120 allows differential circuitry 115 to communicate with microprocessor circuitry 125 using a communication protocol (e.g., Inter-Integrated Circuit (I2C), Serial Peripheral Interface (SPI), etc.). In some examples, update medium 120 is a physical medium (e.g., a connector). For example, update medium 120 may be a connector that directly connects differential circuitry 115 to microprocessor circuitry 125. In other examples, update medium 120 is a wireless medium (e.g., air). For example, when differential circuitry 115 and microprocessor circuitry 125 include circuitry for over-the-air communication, update medium 120 may be air. Update medium 120 supplies differential image data from differential circuitry 115 to microprocessor circuitry 125.

[0031] Microprocessor circuitry 125 is communicatively coupled to differential circuitry 115 via update media 120. Figure 1In the example of , microprocessor circuit system 125 includes example update circuit system 130, example RAM 135 and example flash memory 140. Microprocessor circuit system 125 is a programmable circuit system configured to execute machine-readable instructions. In some examples, microprocessor circuit system 125 includes additional and / or alternative components, such as one or more processing cores, alternative memory, etc.

[0032] Update circuitry 130 is coupled to RAM 135 and flash memory 140. In some examples, update circuitry 130 is communicatively coupled to RAM 135 and flash memory 140 via an internal bus. In such examples, the internal bus allows update circuitry 130 to read from and / or write to RAM 135 and / or flash memory 140. Update circuitry 130 is adapted to be coupled to differential circuitry 115 via update media 120. Update circuitry 130 reads differential image data and original image 105 from flash memory 140.

[0033] Update circuitry 130 creates a swap area in flash memory 140 by shifting original image 105 (hereinafter referred to as Figure 4 105 and the differential image data to store update image 110. Update circuitry 130 constructs a portion of update image 110 in RAM 135 using original image 105 and the differential image data. Update circuitry 130 writes the constructed portion of update image 110 to a swap area in flash memory 140. Update circuitry 130 shifts the swap area by clearing the portion of original image 105. Update circuitry 130 clears the portion of original image 105 because it is no longer necessary to reference the portion of original image 105 to construct update image 110. Figure 2 An example implementation of update circuitry 130 is described in further detail in . Advantageously, update circuitry 130 constructs update image 110 using differential image data and original image 105. Advantageously, update circuitry 130 replaces original image 105 when constructing update image 110.

[0034] RAM 135 is coupled to update circuit system 130 and flash memory 140. RAM 135 is an addressable volatile memory that is readable and writable. RAM 135 stores data in response to a write command. Advantageously, the write command to RAM 135 is not limited to a specific number of bits. Update circuit system 130 constructs a portion of update image 110 by writing bits to RAM 135. RAM 135 supplies data values ​​to the circuit system in response to a read command. In some instances, update circuit system 130 transmits the constructed portion of update image 110 by reading data from RAM 135. In such instances, update circuit system 130 writes the constructed portion of update image 110 to flash memory 140 to complete the transmission. Advantageously, update circuit system 130 utilizes RAM 135 to construct a portion of update image 110.

[0035] Flash memory 140 is coupled to update circuit system 130 and RAM 135. Flash memory 140 is adapted to be coupled to differential circuit system 115 via update medium 120. Flash memory 140 is a readable and writable non-volatile memory. Flash memory 140 is divided into a plurality of memory sectors. A memory sector is a plurality of addressable bits. When one or more of the plurality of bits of a memory sector are written, all of the plurality of bits are cleared before writing to one or more of the plurality of bits. Flash memory 140 stores data responses to write commands. However, flash memory 140 clears all bits of the memory sector written to in response to a write command. Therefore, flash memory 140 may be referred to as a read-only memory (ROM). In some instances, the flash memory may limit write commands to instances in which the data being written substantially includes a memory sector equivalent to the data. In such instances, flash memory 140 stores data in response to a write command including data having a length substantially equal to the length of a memory sector to prevent data loss.

[0036] Sectors of flash memory 140 may be divided to store operation-specific machine-readable instructions and / or microprocessor-specific data. Figure 1 In the example of , flash memory 140 is divided into a first example plurality of sectors 145, a second example plurality of sectors 150, a third example plurality of sectors 155, and a fourth example plurality of sectors 160. Each of the plurality of sectors 145-160 includes a plurality of memory sectors that can be individually read and / or written.

[0037] exist Figure 1In the example of , the first plurality of sectors 145 stores machine-readable instructions specific to initializing the microprocessor circuit system 125. After power is supplied to (e.g., turned on) the microprocessor circuit 125, the programmable circuit system executes the machine-readable instructions of the first plurality of sectors 145. This time may be referred to as startup or bootstrapping. Therefore, the first plurality of sectors 145 may be referred to as MCUBoot sectors.

[0038] First plurality of sectors 145 includes machine readable instructions that, when executed, instantiate update circuitry 130 using programmable circuitry. For example, update circuitry 130 may be programmable circuitry that executes the machine readable instructions of first plurality of sectors 145. The machine readable instructions of first plurality of sectors 145 instantiate update circuitry 130 in response to determining that an update process is to begin. In some examples, the machine readable instructions of first plurality of sectors 145 instantiate update circuitry 130 in response to determining that differential image data is received and / or stored in flash memory 140.

[0039] In example operations where updating will not occur during startup of microprocessor circuitry 125, first plurality of sectors 145 cause programmable circuitry to execute machine-readable instructions corresponding to raw image 105. In example operations where updating will occur, such as after differential circuitry 115 writes differential image data to flash memory 140, the instructions of first plurality of sectors 145 cause programmable circuitry to instantiate update circuitry 130. In such example operations, execution of the instructions of first plurality of sectors 145 causes update circuitry 130 to update microprocessor circuitry 125 using raw image 105 and differential image data. Figure 2-7C Example operation of update circuitry 130 during an update process is described.

[0040] exist Figure 1 In some examples, second plurality of sectors 150 stores data specific to the operation of microprocessor circuit system 125. Second plurality of sectors 150 functions as non-volatile storage (NVS). Advantageously, when power is no longer supplied to (e.g., turned off) microprocessor circuit system 125, the data stored in second plurality of sectors 150 remains in flash memory 140. Thus, second plurality of sectors 150 may be referred to as an NVS area. In some examples, second plurality of sectors 150 stores security information, total uptime of microprocessor circuit system 125, network information, etc. In other examples, second plurality of sectors 150 stores data to provide continuity to original image 105. For example, second plurality of sectors 150 stores data specific to original image 105.

[0041] The third plurality of sectors 155 corresponds to the available memory sectors. Figure 1In an example of the third plurality of sectors 155, the third plurality of sectors 155 provides a location for the differential circuitry 115 to write differential image data. For example, the differential circuitry 115 supplies the differential image data to the microprocessor circuitry 125 by writing the differential image data to the third plurality of sectors 155. In such an example, the microprocessor circuitry 125 may determine to update the original image 105 in response to detecting the differential image data in the third plurality of sectors 155. In addition, the third plurality of sectors 155 provides additional sectors of the flash memory 140 to utilize during the update process. For example, before building a portion of the update image 110, the update circuitry 130 may expand the fourth plurality of sectors 160 by adding memory sectors from the third plurality of sectors 155. In such an example, the update circuitry 130 shifts the memory sectors storing the original image 105 using sectors from the third plurality of sectors 155 to add additional memory sectors for instructions added from the original image 105 to the update image 110.

[0042] exist Figure 1 In the example of , fourth plurality of sectors 160 stores original image 105. In some examples, fourth plurality of sectors 160 may include one or more empty memory sectors. After initialization of microprocessor circuitry 125, programmable circuitry executes machine-readable instructions of fourth plurality of sectors 160. Update circuitry 130 updates the data stored in fourth plurality of sectors 160 during an update process. After the update process described below, fourth plurality of sectors 160 stores update image 110 (as described below in Figure 2 and 5 ).

[0043] Figure 2 is Figure 1 The microprocessor circuit system 125 Figure 1 During the update operation 200 of the original image 105 Figure 1 A timing diagram of the flash memory 140 is shown in FIG. Figure 2 In the example of Figure 1 a first plurality of sectors 145, Figure 1 a second plurality of sectors 150, Figure 1 The third plurality of sectors 155, Figure 1 1 , a fourth plurality of sectors 160 of flash memory 140, a first instance memory sector 210, a second instance memory sector 220, a third instance memory sector 230, a fourth instance memory sector 240, and a fifth instance memory sector 250. Memory sectors 210-250 are writable sections of flash memory 140.

[0044] At a first time (T0) 260, the flash memory 140 is configured for a normal operating mode. At the first time 260, the microprocessor circuitry 125 is turned on (e.g., powered on, bootstrapped). After the first time 260, the microprocessor circuitry 125 executes the instructions of the first plurality of sectors 145 to initialize the microprocessor circuitry 125. After failing to detect differential image data in the third plurality of sectors 155, the microprocessor circuitry 125 continues to execute the instructions of the fourth plurality of sectors 160. At this time after the first time 260, the microprocessor circuitry 125 performs the normal operation of the microprocessor circuitry 125 by executing the instructions stored in the fourth plurality of sectors 160. Figure 1 The original image 105 instructions are used to continue normal operations.

[0045] Between the first time 260 and the second time (T1) 270, Figure 1 The differential circuit system 115 writes the differential image data to the third plurality of sectors 155. After the second time 270, execution of the instructions of the first plurality of sectors 145 causes detection of the differential image data. At this time, the instructions of the first plurality of sectors 145 are instantiated Figure 1 The update circuit system 130 is used to update the fourth plurality of sectors 160. After the second time 270 and the instantiation of the update circuit system 130, the update circuit system 130 uses Figure 1 The constructed sectors of the update image 110 shift, read and / or clear the memory sectors 210-250.

[0046] At the second time 270 and the third time (T N ) 280, the microprocessor circuitry 125 instantiates the update circuitry 130 in response to a restart (e.g., power off and on) of the microprocessor circuitry 125. Between the second time 270 and the third time 280, the update circuitry 130 constructs the update image 110 based on the original image 105 of the fourth plurality of sectors 160 and the differential image data of the third plurality of sectors 155. At the third time 280, the update circuitry 130 has overwritten each of the memory sectors 210-250 with the constructed sectors of the update image 110. After the third time 280, the update circuitry 130 may erase the third plurality of sectors 155 and begin normal operation by executing instructions of the update image 110 in the fourth plurality of sectors 160.

[0047] Figure 3 yes Figure 1 In response to the execution of the instructions of the first plurality of sectors 145, the programmable circuit system in Figure 2 The second time 270 with Figure 2 The third time 280 is instantiated Figure 3The update circuit system 130. Figure 3 In the example of , the update circuit system 130 includes an example differential data controller circuit system 310, an example decompression circuit system 320, an example additional data 330, an example control data 340, an example differential data 350, and an example differential update controller circuit system 360. The update circuit system 130 reads Figure 1 and 2 The third plurality of sectors 155 are used to receive differential image data. The updating circuit system 130 reads Figure 1 and 2 The fourth plurality of sectors 160 are used to receive Figure 1 The original image 105. The updating circuit system 130 updates Figure 1 Microprocessor circuit system 125.

[0048] Figure 3 The update circuit system 130 of can be instantiated (e.g., create an instance, generate, realize, implement, etc. for any length of time) by a programmable circuit system such as a central processing unit (CPU) that executes the first instruction. Additionally or alternatively, Figure 3 The update circuit system 130 may be instantiated (e.g., created as an example, produced for any length of time, realized, implemented, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA) structured and / or configured to perform operations corresponding to the first instruction in response to executing the second instruction. It should be understood that, therefore, Figure 3 Some or all of the circuitry may be instantiated at the same or different times. Figure 3 Some or all of the circuitry of may be instantiated, for example, in one or more threads that execute simultaneously on hardware and / or execute serially on hardware. Furthermore, in some instances, Figure 3 Some or all of the circuitry of may be implemented by a microprocessor circuitry executing instructions and / or an FPGA circuitry performing operations to implement one or more virtual machines and / or containers.

[0049] The differential data controller circuitry 310 is coupled to Figure 1 and 2 The differential data controller circuitry 310 reads the third plurality of sectors 155 to receive the differential image data. In some examples, the differential data controller circuitry 310 supplies a read command to the flash memory 140. In such examples, the flash memory 140 supplies the differential image data to the differential data controller circuitry 310 in response to the read command.

[0050] Differential data controller circuitry 310 parses the differential image data into additional data 330, control data 340, and differential data 350. In some examples, differential data controller circuitry 310 determines starting memory addresses for additional data 330, control data 340, and differential data 350. In such examples, differential data controller circuitry 310 provides the starting memory address locations of data 330-350 to differential update controller circuitry 360.

[0051] Differential data controller circuitry 310 determines whether any of data 330-350 is compressed. Differential data controller circuitry 310 provides any compressed data in data 330-350 to decompression circuitry 320. Figure 3 In the example of , differential data controller circuitry 310 provides compressed versions of control data 340 and differential data 350 to decompression circuitry 320 .

[0052] Decompression circuitry 320 is coupled to differential data controller circuitry 310, control data 340, and differential data 350. Decompression circuitry 320 decompresses the differential image data. Figure 3 In some examples, decompression circuitry 320 decompresses control data 340 and differential data 350. In some examples, decompression circuitry 320 utilizes run-length decoding to decompress compressed versions of control data 340 and differential data 350. Advantageously, decompression circuitry 320 allows differential image data to include compressed data. Advantageously, Figure 1 The differencing circuitry 115 may utilize run-length encoding to compress the differential image data prior to storing the differential image data in the flash memory 140. Advantageously, the differencing circuitry 115 may utilize compression circuitry to further reduce the size of the differential image data.

[0053] exist Figure 3 In the example of FIG. 1 , the differential data includes additional data 330, control data 340, and differential data 350. Additional data 330 represents data to be added to original image 105 to construct updated image 110. For example, additional data 330 may be one or more instructions that need to be added to original image 105 to generate updated image 110. Additional data 330 represents data that may not be differentially combined with data of original image 105.

[0054] The control data 340 specifies a process for constructing the update image 110 using the original image 105, the additional data 330, and the differential data 350. The control data 340 is a plurality of control blocks each containing first data, second data, and third data. The first data of the control block of the control data 340 specifies a first number of bytes to be copied from the original image 105 and XORed with corresponding bytes of the differential data 350. The second data of the control block of the control data 340 specifies a second number of bytes to be copied from the additional data 330. The third data of the control block of the control data 340 specifies a third number of bytes of the original image 105 to be discarded. The differential update controller circuit system 360 performs operations corresponding to the control blocks of the control data 340.

[0055] The differential data 350 represents the difference between the bytes of the original image 105 and the updated image 110. The differential circuit system 115 generates the differential data 350 by XORing the bytes of the original image 105 with the corresponding bytes of the updated image 110. In some example operations, the differential circuit system 115 XORs the instructions present in the original image 105. Advantageously, XORing the bytes of the original image 105 and the differential data 350 allows the differential update controller circuit system 360 to construct the updated image 110 by modifying portions of the original image 105. Advantageously, the differential data 350 allows consecutive portions of the original image 105 that are unchanged in the updated image 110 to be represented by the same logic level (e.g., logic one, logic zero). Advantageously, consecutive portions of the differential data 350 that share the same logic level are compressible.

[0056] The differential update controller circuitry 360 accesses the original image 105 in the fourth plurality of sectors 160, Figure 1 135, the additional data 330, the control data 340, and the differential data 350. The differential update controller circuitry 360 constructs the update image 110 in the RAM 135 using the original image 105 and the data 330-350. The differential update controller circuitry 360 transfers the constructed sectors of the update image 110 to the fourth plurality of sectors 160. In some examples, when constructing the memory sectors of the update image in the RAM 135, the differential update controller circuitry 360 transfers the constructed portions of the update image 110 to the fourth plurality of sectors 160. For example, the differential update controller circuitry 360 may transfer one hundred bytes from the RAM 135 in response to determining that the memory sector is approximately equal to one hundred bytes.

[0057] Combined with the following Figure 4 and 5 An example implementation of differential update controller circuitry 360 is described. Figure 6Flowcharts of 7A-7C and / or 7A-7C describe example operations performed by differential update controller circuitry 360 .

[0058] Figure 4 yes Figure 3 A block diagram of an example implementation of a differential update controller circuit system 360 is shown. Figure 4 In the example of , differential update controller circuitry 360 includes example tracking circuitry 400, example differential pointer 404, example additional pointer 408, example control pointer 412, example raw pointer 416, example RAM pointer 420, example sector shift circuitry 424, example controller circuitry 428, example XOR circuitry 432, example RAM transfer circuitry 436, example sector write circuitry 440, example RAM pointer tracker circuitry 444, example sector size 448, example flash transfer circuitry 452, example RAM update circuitry 456, example sector clear circuitry 460, example raw pointer tracker circuitry 464, example length determination circuitry 468, and example memory clear circuitry 472. Differential update controller circuitry 360 is coupled to Figure 1 and 3 RAM 135 and Figure 1-3 The flash memory 140. Figure 4 In the example of , for purposes of illustration, the original image 105 is a string of bytes. Alternatively, the differential update controller circuitry 360 may be modified according to the description herein to replace and / or modify the original image 105 into a replacement executable file.

[0059] Tracking circuitry 400 is coupled to controller circuitry 428, XOR circuitry 432, RAM transfer circuitry 436, sector write circuitry 440, and sector clear circuitry 460. Figure 4 In the example of , tracking circuitry 400 includes circuitry to store pointers 404 - 420 . In some examples, tracking circuitry 400 can be implemented using a memory such as a plurality of registers, a portion of RAM 135 , or the like.

[0060] The differential pointer 404 is the flash memory 140 and Figure 3The differential pointer 404 initially stores the starting address of the differential data 350. For example, the differential pointer 404 initially stores the memory address corresponding to the first bit of the first byte (e.g., 0x20) of the differential data 350. The differential pointer 404 is coupled to the XOR circuitry 432. The XOR circuitry 432 increments the memory address of the differential pointer 404. For example, the XOR circuitry 432 may increment the differential pointer 404 by two bytes so that the memory address of the differential pointer 404 corresponds to the third byte (e.g., 0x00) of the differential data 350.

[0061] The additional pointer 408 is the same as the flash memory 140. Figure 3 408. The RAM transfer circuitry 436 may be configured to receive the memory address of the additional pointer ...

[0062] The control pointer 412 is the flash memory 140 and Figure 3 4. The control pointer 412 initially stores a memory address corresponding to the location of the control data 340. The control pointer 412 initially stores a starting address of the control data 340. For example, the control pointer 412 initially stores a memory address corresponding to the first bit of the first control block of the control data 340 (e.g., (2,5,3)). The control pointer 412 is coupled to the controller circuitry 428. The controller circuitry 428 increments the memory address of the control pointer 412. For example, the controller circuitry 428 may increment the control pointer 412 by one control block so that the memory address of the control pointer 412 corresponds to the second control block of the control data 340 (e.g., (6,0,0)).

[0063] The original pointer 416 is the pointer to the flash memory 140 corresponding to the original image 105 in Figure 1-34. The raw pointer 416 may be coupled to the sector shift circuitry 424, the controller circuitry 428, the XOR circuitry 432, and the sector clear circuitry 460. The sector shift circuitry 424, the controller circuitry 428, and / or the XOR circuitry 432 may increment the memory address of the raw pointer 416. For example, the controller circuitry 428 may increment the raw pointer 416 by three bytes so that the memory address of the raw pointer 416 corresponds to the fourth byte of the raw image 105 (e.g., 0x6C).

[0064] RAM pointer 420 is a memory address of RAM 135 corresponding to the location where the portion of update image 110 is to be constructed. RAM pointer 420 initially stores the starting address of the location in RAM 135 where the portion of update image 110 is to be constructed. RAM pointer 420 is coupled to XOR circuitry 432, RAM transfer circuitry 436, and sector write circuitry 440. XOR circuitry 432 and RAM transfer circuitry 436 increment the memory address of RAM pointer 420. Sector write circuitry 440 may decrement RAM pointer 420 to the previous memory address.

[0065] Sector shift circuitry 424 is coupled to flash memory 140 and tracking circuitry 400. Sector shift circuitry 424 receives additional pointer 408 and original pointer 416. Sector shift circuitry 424 uses additional pointer 408 to determine the length of additional data 330. Sector shift circuitry 424 determines a certain number of memory sectors required to store additional data 330. For example, sector shift circuitry 424 divides the length of additional data 330 by the length of a memory sector to determine the certain number of memory sectors required for additional data 330. Alternative methods of determining the length of additional data 330 may be used in accordance with the teachings described herein.

[0066] The sector shift circuitry 424 creates an example swap region 476 in the fourth plurality of sectors 160 by shifting the original image 105. The sector shift circuitry 424 shifts the original image 105 by the number of memory sectors required to store the additional data 330 plus one additional memory sector. Thus, the swap region 476 is a number of empty memory sectors corresponding to the number of memory sectors by which the sector shift circuitry 424 shifted the original image 105. The sector shift circuitry 424 sets the raw pointer 416 to correspond to the shifted position of the original image 105 in the fourth plurality of sectors 160. For example, when the sector shift circuitry 424 creates the swap region 476 using twenty-one bytes, the sector shift circuitry 424 increments the raw pointer 416 by twenty-one bytes.

[0067] Controller circuitry 428 is coupled to flash memory 140, tracking circuitry 400, XOR circuitry 432, RAM transfer circuitry 436, and sector write circuitry 440. Controller circuitry 428 receives control pointer 412 from tracking circuitry 400. Controller circuitry 428 reads a control block from control data 340 of flash memory 140 based on control pointer 412. Controller circuitry 428 determines first data, second data, and third data based on the control block from control data 340. Controller circuitry 428 supplies the first data to XOR circuitry 432. Controller circuitry 428 supplies the second data to RAM transfer circuitry 436. Controller circuitry 428 increments original pointer 416 based on the third data. Controller circuitry 428 increments control pointer 412 to a memory address corresponding to a subsequent control block in control data 340.

[0068] XOR circuitry 432 is coupled to RAM 135, flash memory 140, tracking circuitry 400, and controller circuitry 428. XOR circuitry 432 receives differential pointer 404, raw pointer 416, and RAM pointer 420 from tracking circuitry 400. XOR circuitry 432 receives first data from controller circuitry 428. The first data specifies a certain number of bytes that XOR circuitry 432 will XOR. XOR circuitry 432 reads a certain number of bytes of original image 105 based on the first data and raw pointer 416. XOR circuitry 432 reads a certain number of bytes of differential data 350 based on the first data and differential pointer 404. The first data specifies a certain number of bytes that XOR circuitry 432 reads from original image 105 and differential data 350. For example, when the first data specifies two bytes, XOR circuitry 432 reads two bytes of original image 105 and differential data 350.

[0069] XOR circuitry 432 generates a portion of update image 110 by XORing a number of bytes of original image 105 with a number of bytes of differential data 350. XOR circuitry 432 writes the portion of update image 110 to RAM 135 at the memory address specified by RAM pointer 420. XOR circuitry 432 increments differential pointer 404, original pointer 416, and RAM pointer 420 by the number of bytes specified by the first data.

[0070] RAM transfer circuitry 436 is coupled to RAM 135, flash memory 140, tracking circuitry 400, and controller circuitry 428. RAM transfer circuitry 436 receives additional pointer 408 and RAM pointer 420 from tracking circuitry 400. RAM transfer circuitry 436 receives second data from controller circuitry 428. The second data specifies a number of bytes that RAM transfer circuitry 436 is to transfer from flash memory 140 to RAM 135. RAM transfer circuitry 436 transfers a number of bytes of additional data 330 to RAM 135 based on additional pointer 408 and RAM pointer 420. Additional pointer 408 specifies a memory address to begin transferring from additional data 330. RAM pointer 420 specifies a memory address to transfer a portion of additional data 330 to RAM 135. RAM transfer circuitry 436 increments additional pointer 408 and RAM pointer 420 by the number of bytes specified by the second data. Advantageously, RAM transfer circuitry 436 adds the one or more bytes of additional data 330 to RAM 135 .

[0071] Sector write circuitry 440 is coupled to RAM 135, flash memory 140, tracking circuitry 400, and controller circuitry 428. Figure 4 , sector write circuitry 440 includes RAM pointer tracker circuitry 444, sector size 448, flash transfer circuitry 452, and RAM update circuitry 456. Sector write circuitry 440 monitors the construction of update image 110 in RAM 135. Sector write circuitry 440 writes the constructed sectors of update image 110 to swap area 476.

[0072] The RAM pointer tracker circuitry 444 is coupled to the tracking circuitry 400, the controller circuitry 428, the sector size 448, and the flash transfer circuitry 452. The RAM pointer tracker circuitry 444 receives the RAM pointer 420 from the tracking circuitry 400. The sector size 448 represents the size of a memory sector of the flash memory 140. The RAM pointer tracker circuitry 444 monitors the increments of the RAM pointer 420. The RAM pointer tracker circuitry 444 determines the difference between the RAM pointer 420 and the initial value of the RAM pointer 420. The RAM pointer tracker circuitry 444 compares the difference between the values ​​of the RAM pointer 420 to the sector size 448.

[0073] In response to determining that the difference between the values ​​of RAM pointer 420 is greater than sector size 448, RAM pointer tracker circuitry 444 prevents controller circuitry 428 from reading subsequent control blocks. In response to determining that the difference between the values ​​of RAM pointer 420 is greater than sector size 448, RAM pointer tracker circuitry 444 supplies the initial address of RAM pointer 420 to flash transfer circuitry 452. After determining that the difference between the values ​​of RAM pointer 420 is less than sector size 448, RAM pointer tracker circuitry 444 allows controller circuitry 428 to continue reading subsequent control blocks. Advantageously, RAM pointer tracker circuitry 444 detects when differential update controller circuitry 360 has constructed a memory sector in RAM 135 that is equivalent to update image 110.

[0074] The flash transfer circuitry 452 is coupled to the RAM 135, the flash memory 140, the RAM pointer tracker circuitry 444, the sector size 448, and the RAM update circuitry 456. The flash transfer circuitry 452 receives the initial address of the RAM pointer 420 from the RAM pointer tracker circuitry 444. The flash transfer circuitry 452 reads the sector size 448 of the data from the RAM 135 based on the initial address of the RAM pointer 420. The sector size 448 of the data from the RAM 135 is the constructed sector of the update image 110. The flash transfer circuitry 452 writes the sector size 448 of the data from the RAM 135 to the swap area 476 of the flash memory 140. The flash transfer circuitry 452 indicates to the RAM update circuitry 456 that the sector of the update image 110 has been transferred to the flash memory 140.

[0075] The flash transfer circuitry 452 determines a sector in the fourth plurality of sectors 160 based on an example sector record 480. The sector record 480 is a plurality of bytes configured to track the progress of the differential update controller circuitry 360. The sector record 480 includes a record corresponding to each sector in the fourth plurality of sectors 160. For example, when the fourth plurality of sectors 160 includes one hundred records, the sector record 480 includes one hundred records. The sector record 480 is initialized to a first value (e.g., 0xFF). In response to writing the constructed sector of the update image 110 to the memory sector, the flash transfer circuitry 452 sets the record corresponding to the memory sector in the fourth plurality of sectors 160 to a second value (e.g., 0x51). Advantageously, the sector record 480 tracks the progress of the differential update circuitry 360 in the non-volatile memory. Advantageously, the sector record 480 allows the microprocessor circuitry 125 to monitor the progress of the differential update circuitry 360 in the non-volatile memory. Figure 2 Power was lost during update operation 200.

[0076] RAM update circuitry 456 is coupled to RAM 135, tracking circuitry 400, and flash transfer circuitry 452. RAM update circuitry 456 receives RAM pointer 420 from tracking circuitry 400. RAM update circuitry 456 receives an indication from flash transfer circuitry 452 in response to a sector of update image 110 being transferred from RAM 135 to flash memory 140. RAM update circuitry 456 shifts the constructed portion of update image 110 that remains in RAM 135 following the indication from flash transfer circuitry 452 to the initial value of RAM pointer 420. RAM update circuitry 456 decrements RAM pointer 420 by sector size 448. Advantageously, RAM pointer tracker circuitry 444 determines that RAM update circuitry 456 has decremented RAM pointer 420 and allows controller circuitry 428 to continue reading subsequent instructions.

[0077] Sector clear circuitry 460 is coupled to flash memory 140 and tracking circuitry 400. Figure 4 In the example of FIG. 4 , sector clearing circuitry 460 includes raw pointer tracker circuitry 464, length determination circuitry 468, and memory clearing circuitry 472. Sector clearing circuitry 460 determines when a memory sector of raw image 105 is no longer needed. Sector clearing circuitry 460 erases sectors of raw image 105 that are no longer needed by differential update controller circuitry 360.

[0078] The raw pointer tracker circuitry 464 is coupled to the tracking circuitry 400, the length determination circuitry 468, and the memory clearing circuitry 472. The raw pointer tracker circuitry 464 receives the raw pointer 416 from the raw pointer tracker circuitry 464. The raw pointer tracker circuitry 464 determines whether the raw pointer 416 has been incremented beyond a memory sector boundary. A memory sector boundary is a memory address corresponding to the start of a subsequent memory sector. The raw pointer tracker circuitry 464 determines the memory address that the raw pointer 416 has incremented beyond in a previous memory sector. The raw pointer tracker circuitry 464 supplies the memory address to the memory clearing circuitry 472.

[0079] The memory clearing circuitry 472 is coupled to the flash memory 140 and the raw pointer tracker circuitry 464. The memory clearing circuitry 472 receives the memory address from the raw pointer tracker circuitry 464. The memory clearing circuitry 472 supplies a write command to the flash memory 140 to clear the memory sector containing the memory address from the raw pointer tracker circuitry 464. After the write command from the memory clearing circuitry 472, the cleared memory sector may be considered as part of the swap area 476.

[0080] exist Figure 4 In some examples, the differential image data of the third plurality of sectors 155 is considered to be uncompressed. In some examples, the data 330, 340, and / or 350 may be obtained by Figure 3 135 . In such examples, the data 330, 340, and / or 350 may be accessed in an alternative memory location (e.g., in the RAM 135). Accordingly, the differential update controller circuit 360 may be modified as described herein to access the data 330, 340, and / or 350 in the alternative memory location. For example, one or more of the pointers 404-416 may be modified to correspond to a memory address in the RAM 135 or an alternative memory location and / or memory type.

[0081] In the example operation, Figure 2During startup of the microprocessor circuitry 125 after the second time 270, execution of the instructions of the first plurality of sectors 145 instantiates the differential update controller circuitry 360 and sets the sector record 480 to the first value. In such example operation, the tracking circuitry 400 initializes the pointers 404-420 memory addresses corresponding to each of the pointers 404-420. For example, the tracking circuitry 400 initializes the differential pointer 404 to a memory address corresponding to the first byte (e.g., 0x20) of the differential data 350. After initialization of the tracking circuitry 400, the sector shift circuitry 424 creates the swap area 476 by shifting the original image 105 based on the length of the additional data 330. The sector shift circuitry 424 increments the original pointer 416 to correspond to the shifted position of the original image 105.

[0082] In an example operation, the controller circuit system 428 reads a first control block of the control data 340 based on the control pointer 412. The first control block of the control data 340 includes first data, second data, and third data. The controller circuit system 428 supplies the first data to the XOR circuit system 432 and supplies the second data to the RAM transfer circuit system 436. The XOR circuit system 432 generates a first portion of the update image 110 by XORing a certain number of bytes of the original image 105 with a certain number of bytes of the differential data 350 in response to the first data. The XOR circuit system 432 writes the first portion of the update image 110 to the RAM 135 starting from the memory address specified by the RAM pointer 420. Advantageously, the first data allows the XOR circuit system 432 to update a portion of the original image 105 to construct a portion of the update image 110 using the differential data 350. The XOR circuit system 432 increments the pointers 404, 416, and 420 by a certain number of bytes specified in the first data.

[0083] After XOR circuitry 432 increments pointers 404, 416, and / or 420, RAM transfer circuitry 436 generates a second portion of update image 110 by reading a certain number of bytes specified by the second data of additional data 330. RAM transfer circuitry 436 writes the second portion of update image 110 starting from the memory address specified by RAM pointer 420. Advantageously, the second data allows RAM transfer circuitry 436 to construct update image 110 by adding portions of additional data 330 to RAM 135. RAM transfer circuitry 436 increments pointers 408 and 420 by the certain number of bytes specified in the second data.

[0084] After the RAM transfer circuitry 436 increments the pointers 408 and / or 420, the controller circuitry 428 increments the raw pointer 416 by a number of bytes specified by the third data. Advantageously, the controller circuitry 428 ignores portions of the original image 105 by incrementing the raw pointer 416. Advantageously, the third data allows the controller circuitry 428 to construct the updated image 110 by ignoring portions of the original image 105. The controller circuitry 428 increments the control pointer 412 to correspond to subsequent instructions.

[0085] After controller circuitry 428 increments control pointer 412, sector write circuitry 440 determines whether differential update controller circuitry 360 has constructed the memory sector of update image 110. In response to determining that RAM pointer 420 indicates that the memory sector of update image 110 is in RAM 135, RAM pointer tracker circuitry 444 prevents controller circuitry 428 from proceeding to a subsequent control block. For example, the difference between the initial value of RAM pointer 420 and the current value of RAM pointer 420 is greater than or equal to sector size 448.

[0086] After RAM pointer tracker circuitry 444 determines that a portion of update image 110 is ready to be transferred from RAM 135, flash transfer circuitry 452 uses sector record 480 to determine a location in flash memory 140 to transfer the sector of update image 110. In some examples, flash transfer circuitry 452 writes the sector of update image 110 to a memory sector corresponding to a first one of sector record 480 having a first value. Flash transfer circuitry 452 sets the record in sector record 480 corresponding to the write location to a second value. Advantageously, changing the value of sector record 480 allows the update process to continue even if microprocessor circuitry 125 is powered off and on.

[0087] The RAM update circuitry 456 shifts the remaining portion of the update image 110 in the RAM 135 to the initial value of the RAM pointer 420. The RAM update circuitry 456 decrements the RAM pointer 420 by the sector size 448. In some example operations, the RAM pointer tracker circuitry 444 allows the controller circuitry 428 to proceed to a subsequent control block when the remaining data in the RAM 135 has a length less than the sector size 448. In other example operations, the RAM pointer tracker circuitry 444 may initiate another transfer from the RAM 135 in response to the remaining data having a length greater than the sector size 448.

[0088] During such example operation, the sector clearing circuitry 460 monitors the raw pointer 416. The raw pointer tracker circuitry 464 detects when the raw pointer 416 crosses a memory sector boundary. When the raw pointer 416 increments to an address in a different memory sector, the raw pointer tracker circuitry 464 determines that the raw pointer 416 has crossed a memory sector boundary. The memory clearing circuitry 472 clears memory sectors that are no longer needed by the differential update controller circuitry 360. Advantageously, the memory clearing circuitry 472 clears memory sectors of the raw image 105 when they are no longer needed.

[0089] Controller circuitry 428 continues to read and parse control blocks of control data 340 until update image 110 has been completely constructed. Sector write circuitry 440 transfers the constructed portion of update image 110 from RAM 135 after the final control block from control data 340. Sector clear circuitry 460 may clear third plurality of sectors 155 after completing the update process using the final control block from control data 340. In some examples, sector clear circuitry 460 clears third plurality of sectors 155 after verifying update image 110. Once update image 110 is stored in fourth plurality of sectors 160, microprocessor circuitry 125 may continue normal operations using the update image.

[0090] Figure 5 is Figure 1 During the example update operation 500 of the microprocessor circuit system 125 Figure 1-4 A timing diagram of the flash memory 140 is shown in FIG. Figure 5 In the example of Figure 1-4 The third plurality of sectors 155, Figure 2 The first memory sector 210, Figure 2 The second memory sector 220, Figure 2 The third memory sector 230, Figure 2 The fourth memory sector 240, Figure 2 The fifth memory sector 250, the sixth example memory sector 510 and the seventh example memory sector 520 of the flash memory 140. The memory sectors 210-250, 510 and 520 are Figure 1-4 The writable portion of the fourth plurality of sectors 160. Figure 5 In the example of Figure 2 The second time 270 with Figure 2 The third time is between 280.

[0091] Between the second time 270 and the first time (T2) 530, the sector shift circuitry 424 will Figure 1-4The original image 105 is shifted, thereby creating Figure 4 The swap area 476 of FIG. 530 includes the memory sectors 210 - 230 . At the first time 530 , the start of the original image 105 corresponds to the sixth memory sector 510 .

[0092] Between the first time 530 and the second time (T3) 540, Figure 3 The differential update controller circuit system 360 is constructed based on the differential image data of the third plurality of sectors 155. Figure 1-4 Prior to the second time 540, the sector write circuitry 440 writes the first sector of the update image 110 to the first memory sector 210. At the second time 540, the swap area 476 includes the memory sectors 220 and 230.

[0093] Between the second time 540 and the third time (T4) 550, the differential update controller circuitry 360 continues to construct portions of the update image 110 based on the differential image data of the third plurality of sectors 155. Prior to the third time 550, the sector write circuitry 440 writes the second sector of the update image 110 to the second memory sector 220. Between the second time 540 and the third time 550, Figure 4 The sector clearing circuitry 460 determines that the portion of the original image 105 stored in the sixth memory sector 510 is no longer needed to construct the updated image 110. Prior to the third time 550, the sector clearing circuitry 460 clears the sixth memory sector 510 to shift the swap area 476. At the third time 550, the swap area 476 includes the memory sectors 230 and 510.

[0094] Between times 550 and 280, the differential update controller circuitry 360 continues to construct and transmit the update image 110 while clearing the memory sectors of the original image 105. At a third time 280, the differential update controller circuitry 360 has completed the update process of operation 500.

[0095] Figure 6 is a flow chart representing example machine readable instructions and / or example operations 600 that may be used Figure 1 , 3 and 4 differential update controller circuitry 360 and / or more generally using Figure 1 and 2 The example programmable circuit system implementation of the update circuit system 130 is implemented, instantiated and / or executed to update Figure 1 Microprocessor circuit system 125. Figure 6The example machine readable instructions and / or example operations 600 begin at block 605 where the microprocessor circuit system 125 stores the differential image data in a flash memory. In some examples, Figure 1 The differential circuit system 115 uses Figure 1 The update medium 120 writes the differential image data to Figure 1-5 In such an example, the differential circuit system 115 uses the Bsdiff, Figure 1-5 The original image 105 and Figure 1-5 The updated image 110 is used to generate differential image data.

[0096] Figure 4 The sector shifting circuitry 424 determines a number of memory sectors by which to shift the original image based on the differential image data. (Block 610). In some examples, the sector shifting circuitry 424 determines a number of memory sectors by which to shift the original image based on the differential image data. Figure 3 and 4 The length of the additional data 330 determines the number of memory sectors by which the original image 105 is to be shifted. In such an example, the sector shifting circuitry 424 determines the number of memory sectors required to represent the additional data 330 plus the additional memory sectors. Thus, the sector shifting circuitry 424 may be configured to shift the original image 105 based on the length of the additional data 330 and further based on the additional length of the memory sectors (e.g., Figure 5 An additional memory sector in the example of ) is used to determine a certain number of memory sectors by which the original image is to be shifted.

[0097] Sector shift circuitry 424 shifts the original image by the determined number of memory sectors to create a swap region. (Block 615). In some examples, sector shift circuitry 424 shifts the original image by the determined number of memory sectors to create a swap region. Figure 1-5 The fourth plurality of sectors 160 in the original image 105 are shifted to create Figure 4 The swap area 476 of FIG. 470 includes the determined number of memory sectors, ie, the number of memory sectors determined in block 610. In such an example, the swap area 476 includes the determined number of memory sectors.

[0098] Figure 4 Controller circuit system 428, Figure 4 The XOR circuitry 432 and / or Figure 4 The RAM transfer circuit system 436 of the controller circuit system 428 constructs a portion of the updated image based on the differential image data and the original image. (Block 620). In some examples, the controller circuit system 428, the XOR circuit system 432 and / or the RAM transfer circuit system 436 constructs a portion of the updated image based on the original image 105, Figure 3 and 4 Additional data 330, Figure 3 and4 The control data 340 and Figure 3 and 4 The difference data of 350 Figure 1 , 3 and 4 to construct a portion of the update image 110 in the RAM 135 of the controller circuit system 426. In such an example, the XOR circuit system 432 and / or the RAM transfer circuit system 436 construct a portion of the update image 110 in the RAM 135 based on the first data and the second data from the controller circuit system 426.

[0099] Figure 4 The sector write circuitry 440 determines whether the length of the portion of the updated image is greater than or equal to the length of the memory sector. (Block 625). In some examples, the sector write circuitry 440 determines whether the length of the portion of the updated image is greater than or equal to the length of the memory sector. Figure 4 The sector write circuitry 440 compares the length of the portion of the update image 110 in the RAM 135 with the initial value of the RAM pointer 420 to determine the length of the portion of the update image 110 in the RAM 135. In such an example, the sector write circuitry 440 compares the length of the portion of the update image 110 in the RAM 135 with the initial value of the RAM pointer 420. Figure 4 The sector size 448 is compared to determine whether the portion of the update image 110 has a length greater than the sector size 448.

[0100] If sector write circuitry 440 determines that the length of the portion of the update image is not greater than or equal to the length of the memory sector (e.g., block 625 returns a “no” result), controller circuitry 426, XOR circuitry 432, and / or RAM transfer circuitry 436 construct a subsequent portion of the update image based on the differential image data and the original image. (Block 630). In some examples, XOR circuitry 432 and / or RAM transfer circuitry 436 construct a subsequent portion of update image 110 in response to controller circuitry 428 providing the first data and the second data of a subsequent control block of control data 340. Control proceeds to return to block 625.

[0101] If the sector write circuitry 440 determines that the length of the portion of the update image is greater than or equal to the length of the memory sector (e.g., block 625 returns a "yes" result), the sector write circuitry 440 writes the memory sector of the portion of the update image to the swap area. (Block 635). In some examples, the sector write circuitry 440 writes the memory sector of the portion of the update image to the swap area based on Figure 4 The sector record 480 of 480 determines the location of the sectors to be written to the update image 110. In such an example, the sector write circuit system 440 writes the sectors of the update image 110 to the flash memory 140, updates the sector record 480, and updates the remaining data in the RAM 135.

[0102] Figure 4The sector clearing circuitry 460 of the original image clears the memory sectors that do not have active pointers. (Block 640). In some examples, the sector clearing circuitry 460 detects Figure 4 When the original pointer 416 of the updated image 105 crosses into a subsequent memory sector of the original image 105. In such an example, the sector clearing circuitry 460 clears the previous memory sector of the original image 105. Advantageously, clearing the previous memory sector of the original image 105 shifts the swap area 476 by adding the cleared sectors to the swap area 476 and deleting the sectors storing portions of the updated image from the swap area 476.

[0103] Controller circuitry 428 determines whether update image 110 has been completely constructed. (Block 645). In some examples, controller circuitry 428 determines whether update image 110 has been completely constructed based on control data 340. In such examples, controller circuitry 428 determines that update image 110 has been completely constructed based on determining that all control blocks of control data 340 have been implemented. In other examples, controller circuitry determines that update image 110 has been completely constructed based on determining that control pointer 412 identifies a memory address outside of control data 340.

[0104] If the controller circuitry 428 determines that the update image has not been fully constructed (e.g., block 645 returns a “no” result), control proceeds back to block 630. If the controller circuitry 428 determines that the update image has been fully constructed (e.g., block 645 returns a “yes” result), control proceeds to the end.

[0105] Although reference Figure 6 The flowchart illustrated in the foregoing describes an example process, but many other methods of updating the microprocessor circuit system using differential image data may be used instead according to the teachings of the present disclosure. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated example.

[0106] Figures 7A-7C Form means that you can use Figure 3-5 Example programmable circuitry implementations of differential update controller circuitry are provided to implement, instantiate and / or perform example machine readable instructions and / or example operation flowcharts.

[0107] Figures 7A-7C is a flowchart representing example machine readable instructions and / or example operations 700 that may be used Figure 1 , 3and 4 differential update controller circuitry 360 and / or more generally using Figure 1 and 2 The example programmable circuit system implementation of the update circuit system 130 is implemented, instantiated and / or executed to update Figure 1 Microprocessor circuit system 125. Figures 7A-7C Example machine readable instructions and / or example operations 700 begin at block 702 where, Figure 1 The microprocessor circuit system 125 stores the differential image data. In some examples, Figure 1 The differential circuit system 115 uses Figure 1 The update medium 120 writes the differential image data to Figure 1-5 In such an example, the differential circuit system 115 uses the Bsdiff, Figure 1-5 The original image 105 and Figure 1-5 The updated image 110 is used to generate differential image data.

[0108] Flash memory 140 initializes sector records for memory sectors allocated to the original image. (Block 704). In some examples, in response to programmable circuitry executing instructions to instantiate update circuitry 130, flash memory 140 initializes Figure 4 In such an example, in response to determining that microprocessor circuitry 125 is to be updated, flash memory 140 sets sector record 480 equal to the first value.

[0109] Figure 3 The differential data controller circuit system 310 determines the location of the differential data, the additional data, and the control in the differential image data. (Block 706). In some examples, the differential data controller circuit system 310 determines Figure 3 and 4 Additional data 330, Figure 3 and 4 The control data 340 and Figure 3 and 4 In some such examples, the differential data controller circuitry 310 provides the differential image data to the memory address of the differential data 350. Figure 3 The decompression circuit system 320 is used to decompress the additional data 330, the control data 340 and / or the differential data 350.

[0110] Figure 4 The tracking circuit system 400 creates a first pointer corresponding to the starting byte of the differential data. (Block 708). In some examples, the tracking circuit system 400 Figure 4The differential pointer 404 is initialized to a memory address corresponding to the starting byte of the differential data 350 .

[0111] The tracking circuit system 400 creates a second pointer corresponding to the starting byte of the additional data. (Block 710). In some examples, the tracking circuit system 400 will Figure 4 The additional pointer 408 is initialized to a memory address corresponding to the starting byte of the additional data 330 .

[0112] The tracking circuit system 400 creates a third pointer corresponding to the starting byte of the control data. (Block 712). In some examples, the tracking circuit system 400 Figure 4 The control pointer 412 is initialized to a memory address corresponding to the starting byte of the control data 340 .

[0113] Figure 4 The sector shift circuitry 424 determines the length of the additional data 330. (Block 714). In some examples, the sector shift circuitry 424 determines the length of the additional data 330 using the additional pointer 408.

[0114] Sector shift circuitry 424 determines a number of memory sectors required to add the additional data based on the length of the additional data. (Block 716) In some examples, sector shift circuitry 424 divides the length of additional data 330 by the size of the memory sector to determine the number of memory sectors required to add the additional data 330.

[0115] The sector shifting circuitry 424 shifts the original image by the determined number of memory sectors plus the additional memory sector. (Block 718). Although described as shifting one additional memory sector, the sector shifting circuitry 424 may be configured to shift the original image by the determined number plus two or more additional memory sectors. In some examples, the sector shifting circuitry 424 Figure 1-5 The original image 105 in the fourth plurality of sectors 160 is shifted. In such an example, the sector shifting circuit system 424 creates Figure 4 Advantageously, creating the swap area 476 allows the differential update controller circuitry 360 to transfer portions of the update image 110 without writing over the original image 105.

[0116] The tracking circuit system 400 creates a fourth pointer corresponding to the starting byte of the original image. (Block 720). In some examples, the tracking circuit system 400 Figure 4 The raw pointer 416 is initialized to a memory address corresponding to the starting byte of the raw image 105 in the flash memory 140 .

[0117] The tracking circuit system 400 creates a fifth pointer corresponding to the starting byte of the location in the RAM to construct a portion of the update image. (Block 722). In some examples, the tracking circuit system 400 will Figure 4 The RAM pointer 420 is initialized to Figure 1 , 3 and 4 RAM 135 will build with Figure 1-5 The location of the updated image 110 corresponds to the memory address.

[0118] Now turn to Figure 7B , Figure 4 The controller circuit system 428 determines the first data, the second data, and the third data from the control block of control data identified by the third pointer. (Block 724). In some examples, the controller circuit system 428 reads the control block from the control data 340 based on the control pointer 412. In such examples, the controller circuit system 428 parses the control block into the first data, the second data, and the third data.

[0119] Figure 4 The XOR circuitry 432 generates a first portion of the updated image by XORing a first number of bytes from the original image with a first number of bytes from the differential data, the first number of bytes being based on the first data. (Block 726). In some examples, the XOR circuitry 432 determines the first number of bytes to XOR based on the first data from the controller circuitry 426. In such examples, the XOR circuitry 432 reads the first number of bytes from the original image 105 based on the original pointer 416 and reads the first number of bytes from the differential data 350 based on the differential pointer 404.

[0120] XOR circuitry 432 writes the first portion of the update image to RAM based on the fifth pointer. (Block 728) In some examples, XOR circuitry 432 writes the first portion of update image 110 resulting from the XOR operation to RAM 135 based on the location specified by RAM pointer 420.

[0121] XOR circuitry 432 adds the first number of bytes to the first pointer, the second pointer, and the fifth pointer. (Block 730) In some examples, XOR circuitry 432 increments differential pointer 404, raw pointer 416, and RAM pointer 420 by a number of bytes specified by the first data.

[0122] Figure 4The RAM transfer circuitry 436 generates a second portion of the updated image by adding a second number of bytes from the additional data, the second number of bytes being based on the second data. (Block 732). In some examples, the RAM transfer circuitry 436 determines the second number of bytes based on the second data from the controller circuitry 426. In such examples, the RAM transfer circuitry 436 reads the second number of bytes from the additional data 330 based on the additional pointer 408.

[0123] RAM transfer circuitry 436 writes the second portion of the update image to RAM based on the fifth pointer. (Block 734 ) In some examples, RAM transfer circuitry 436 writes the second portion of update image 110 to RAM 135 based on the location specified by RAM pointer 420 .

[0124] RAM transfer circuitry 436 adds the second number of bytes to the second pointer and the fifth pointer. (Block 736) In some examples, RAM transfer circuitry 436 increments additional pointer 408 and RAM pointer 420 by a number of bytes specified by the second data.

[0125] The controller circuitry 428 adds a third number of bytes to the fourth pointer, the third number of bytes being based on the third pointer. (Block 738) In such an example, the controller circuitry 428 ignores bytes of the original image 105 by incrementing the original pointer 416 by a number of bytes specified by the third data.

[0126] Now turn to Figure 7C , Figure 4 The RAM pointer tracker circuitry 444 determines whether the difference between the starting byte of the location in RAM for constructing the portion of the update image and the fifth pointer is greater than or equal to the size of the memory sector. (Block 740). In some examples, the RAM pointer tracker circuitry 444 determines whether the portion of the update image 110 constructed in RAM 135 represents a memory sector of the update image 110. In such examples, the RAM pointer tracker circuitry 444 may determine the length of the portion of the update image 110 in RAM 135.

[0127] if Figure 4 If the RAM pointer tracker circuitry 444 determines that the difference between the starting byte of the location in RAM for constructing the portion of the update image and the fifth pointer is greater than or equal to the size of the memory sector (e.g., block 740 returns a "yes" result), then Figure 4The flash transfer circuitry 452 of the memory 452 writes the sectors of the update image to the swap area. (Block 742). In some examples, the flash transfer circuitry 452 reads the memory sectors equivalent to the constructed portion of the update image 110 from the RAM 135 and writes the memory sectors equivalent to the update image 110 to the swap area 476. In such examples, the flash transfer circuitry 452 determines the memory sectors of the swap area 476 to write based on the sector record 480.

[0128] Flash transfer circuitry 452 updates the sector record. (Block 744) In some examples, flash transfer circuitry 452 writes a second value to a record in sector record 480 that corresponds to the memory sector written to during block 742. In such examples, the second value indicates that the memory sector includes a portion of update image 110.

[0129] Figure 4 The RAM update circuitry 456 shifts the remaining data in the RAM to the starting byte of the location in the RAM used to construct the update image. (Block 746). In some examples, the RAM update circuitry 456 shifts the data remaining in the RAM 135 after writing the portion of the update image 110 by a number of bytes that is equal to the memory sector (e.g., Figure 2 and 5 The size of the memory sectors 210-250).

[0130] The RAM update circuitry 456 subtracts a number of bytes in the memory sector from the fifth pointer. (Block 748). In some examples, the RAM update circuitry 456 subtracts a number of bytes equal to the size of the memory sector from the RAM pointer 420. Control proceeds back to block 740.

[0131] if Figure 4 If the RAM pointer tracker circuitry 444 determines that the difference between the starting byte of the location in RAM for constructing the portion of the update image and the fifth pointer is not greater than or equal to the size of the memory sector (e.g., block 740 returns a "no" result), then Figure 4 The raw pointer tracker circuitry 464 determines whether the fourth pointer has crossed a memory sector boundary. (Block 750) In some examples, the raw pointer tracker circuitry 464 monitors the raw pointer 416 to determine when the memory address of the raw pointer 416 is incremented to a different memory sector.

[0132] If the raw pointer tracker circuitry 464 determines that the fourth pointer has crossed a memory sector boundary (eg, block 750 returns a "yes" result), then Figure 4The memory clearing circuitry 472 of the fourth pointer clears the memory sectors before the memory sectors of the fourth pointer. (Block 752). In some examples, the memory clearing circuitry 472 clears the memory sectors between the swap area 476 and the memory sector identified by the original pointer 416.

[0133] If the raw pointer tracker circuitry 464 determines that the fourth pointer has not crossed a memory sector boundary (e.g., block 750 returns a “no” result) or the operation of block 752 occurs, the controller circuitry 428 determines whether there are more control blocks in the control data. (Block 754). In some examples, the controller circuitry 428 determines whether there are additional control blocks based on the control pointer 412 and / or in response to receiving the final control block.

[0134] If the controller circuit system 428 determines that there are more control blocks in the control data (e.g., block 754 returns a "yes" result), the controller circuit system 428 increments the third pointer to advance to the subsequent control block. (Block 756). In some examples, the controller circuit system 428 increments the control pointer 412 to the subsequent control block of the control data 340. The control proceeds back to block 724.

[0135] If the controller circuitry 428 determines that there are no more control blocks in the control data (eg, block 754 returns a "no" result), then Figure 4 Sector write circuitry 440 writes the remainder of the update image to the swap area and updates the sector record. (Block 758). In some examples, flash transfer circuitry 452 writes the remaining constructed portion of update image 110 in RAM 135 to swap area 476. In such examples, RAM update circuitry 456 updates sector record 480 to complete the update process. Control passes to end.

[0136] Although reference Figures 7A-7C The flowchart illustrated in the foregoing describes an example process, but many other methods of updating the microprocessor circuit system using differential image data may be used instead according to the teachings of the present disclosure. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated example.

[0137] Although in Figure 3 Description Implementation Figure 1 The example method of updating the circuit system 130, but Figure 3 One or more of the elements, processes and / or devices described in the may be combined, divided, rearranged, omitted, eliminated and / or implemented in any other manner. In addition, Figure 3The differential data controller circuit system 310, Figure 3 decompression circuitry 320, differential update controller circuitry 360, and / or more generally Figure 3 The example update circuit system 130 may be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, Figure 3 The differential data controller circuit system 310, Figure 3 Any of the decompression circuitry 320, the differential update controller circuitry 360, and / or more generally the example update circuitry 130 may be implemented by programmable circuitry in combination with machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a programmable logic device (PLD), and / or a field programmable logic device (FPLD) such as an FPGA. Further, Figure 3 Examples of update circuitry 130 may include in addition to or in lieu of Figure 3 The invention may include one or more elements, processes and / or devices other than those described in the specification, and / or may include more than one of any or all of the described elements, processes and devices.

[0138] Figure 6 , 7A , 7B and / or 7C show that the programmable circuit system can be executed to implement and / or instantiate Figure 3 The example machine-readable instructions and / or representations of the update circuit system 130 may be executed by the programmable circuit system to implement and / or instantiate Figure 3 The machine-readable instructions may be a flowchart of an example operation of the update circuit system 130. Figure 8 The programmable circuit system 812 shown in the example processor platform 800 described above may be executed by one or more executable programs or portions of one or more executable programs, and / or may be described below in conjunction with Fig. 9 The example programmable circuit system (e.g., FPGA) described in the present invention and / or 10 may be used to perform one or more functions or functional portions thereof. In some examples, machine-readable instructions enable operations, tasks, etc. to be performed and / or executed in an automated manner in the real world. As used herein, "automatically" means without human intervention.

[0139] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical disks (e.g., Blu-ray disks, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAIDs), registers, ROMs, solid-state drives (SSDs), SSD memories, non-volatile memories (e.g., electrically erasable programmable read-only memories (EEPROMs), flash memories, etc.), volatile memories (e.g., any type of random access memories (RAMs), etc.), and / or any other storage devices or storage disks. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed and / or executed by programmable circuit systems located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or instantiated and / or embodied in dedicated hardware by one or more hardware devices other than programmable circuit systems. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, a client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between a server and an endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. Furthermore, although reference is made to Figure 6 , 7A, 7B and / or 7C describe example procedures, but many other methods of implementing example update circuit systems may be used instead. For example, the execution order of the blocks of the flowchart may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are structured to perform corresponding operations without running software or firmware. The programmable circuit system may be distributed in different network locations and / or locally in one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)). For example, the programmable circuit system can be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination thereof.

[0140] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bit stream (e.g., a computer-readable bit stream, a machine-readable bit stream, etc.), etc.) or a data structure (e.g., a portion of an instruction, a code, a representation of a code, etc.), which may be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located in the same or different locations of a network or collection of networks (e.g., in the cloud, an edge device, etc.). The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, decapsulation, distribution, redistribution, compilation, etc., in order to make them directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, machine-readable instructions may be stored in multiple portions that are individually compressed, encrypted, and / or stored on separate computing devices, wherein the portions, when decrypted, decompressed, and / or combined, form a set of machine-executable and / or machine-executable instructions that implement one or more functions and / or operations that may together form, for example, the programs described herein.

[0141] In another example, the machine-readable instructions may be stored in a state where they can be read by programmable circuitry, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or another device. In another example, the machine-readable instructions and / or corresponding programs may need to be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before they can be executed in whole or in part. Therefore, as used herein, machine-readable, computer-readable, and / or machine-readable media may contain instructions and / or programs regardless of the specific format or state of the machine-readable instructions and / or programs.

[0142] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0143] Computer readable Figure 6 , 7A, 7B, and / or 7C can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media are explicitly defined to include any type of computer-readable storage device and / or storage disk, and exclude propagation signals and exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage devices or storage disks, where information is stored for any duration (e.g., for an extended period of time, permanently, temporarily, temporarily buffered, and / or cached information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware to retain information over a period of time, but exclude propagating signals and transmission media. Examples of non-transitory computer-readable storage devices and non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuit system, which may or may not be configured by computer-readable instructions, machine-readable instructions, etc., and / or is manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0144] "Include" and "comprising" (and all forms and tenses thereof) are used herein as open terms. Thus, whenever a claim uses any form of "include" or "comprising" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or in any type of claim recitation, it should be understood that additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term, such as in the preamble of a claim, it is open-ended in the same manner as the terms "include" and "comprising." The term "and / or" when used in the form of, for example, A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A or B” is intended to refer to embodiments that include any of the following: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A or B” is intended to refer to embodiments that include any of the following: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B. As used herein in the context of describing the execution or performance of processes, instructions, actions, activities, and / or steps, the phrase “at least one of A and B” is intended to refer to embodiments that include any of the following: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of a process, instruction, action, activity, and / or step, the phrase "at least one of A or B" is intended to refer to an implementation that includes any of the following: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B.

[0145] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of the objects described. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed individually, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different instances or claims, these features may be combined, and the inclusion in different instances or claims does not imply that a combination of features is not feasible and / or advantageous.

[0146] Figure 8 is structured to execute and / or instantiate Figure 6 , 7A , 7B and / or 7C example machine readable instructions and / or example operations to implement Figure 3 The programmable circuit system platform 800 is a block diagram of an example programmable circuit system platform 800 of the update circuit system 130. The programmable circuit system platform 800 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smart phone, such as an iPad TM tablet computer), personal digital assistant (PDA), Internet appliance, DVD player, CD player, digital video recorder, Blu-ray player, game console, personal video recorder, set-top box, headsets (e.g., augmented reality (AR) headsets, virtual reality (VR) headsets, etc.) or other wearable devices, or any other type of computing and / or electronic device.

[0147] The programmable circuit system platform 800 of the illustrated example includes a programmable circuit system 812. The programmable circuit system 812 of the illustrated example is hardware. For example, the programmable circuit system 812 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit system 812 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 812 implements Figure 3 The differential data controller circuit system 310, Figure 3 decompression circuitry 320, differential update controller circuitry 360, and / or more generally Figure 1 and 3 The update circuit system 130 is provided.

[0148] The programmable circuit system 812 of the illustrated example includes a local memory 813 (e.g., cache, registers, etc.). The programmable circuit system 812 of the illustrated example communicates with a main memory 814, 816 via a bus 818, the main memory including a volatile memory 814 and a non-volatile memory 816. The volatile memory 814 may be comprised of a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 816 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memories 814, 816 of the illustrated example is controlled by a memory controller 817. In some examples, the memory controller 817 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data to and from the main memories 814, 816.

[0149] The programmable circuit system platform 800 of the illustrated example also includes an interface circuit system 820. The interface circuit system 820 can be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0150] In the illustrated example, one or more input devices 822 are connected to the interface circuitry 820. The input devices 822 permit a user (e.g., a human user, a machine user, etc.) to enter data and / or commands into the programmable circuitry 812. The input devices 822 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a track pad, a trackball, an isochronous device, and / or a speech recognition system.

[0151] One or more output devices 824 are also connected to the interface circuit system 820 of the illustrated example. The output device 824 may be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuit system 820 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit system such as a GPU.

[0152] The interface circuitry 820 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces, to facilitate the exchange of data with external machines (e.g., any type of computing device) over the network 826. Communications may occur over, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, and the like.

[0153] The programmable circuit system platform 800 of the illustrated example also includes one or more mass storage disks or devices 828 to store firmware, software and / or data. Examples of such mass storage disks or devices 828 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0154] can be Figure 6 , 7A The machine-readable instructions 832 implemented by the machine-readable instructions of 7B and / or 7C may be stored in the mass storage device 828, in the volatile memory 814, in the non-volatile memory 816 and / or on at least one non-transitory computer-readable storage medium such as a CD or DVD that may be removable.

[0155] Fig. 9 yes Figure 8 812 of the programmable circuit system 812. In this example, Figure 8 The programmable circuit system 812 is implemented by the microprocessor 900. For example, the microprocessor 900 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit system). The microprocessor 900 executes Figure 6 , 7A , 7B and / or 7C to effectively Figure 2 The circuit system is instantiated as a logic circuit to perform operations corresponding to those machine-readable instructions. In some such instances, Figure 3 The circuit system is instantiated by the hardware circuits of the microprocessor 900 in combination with machine-readable instructions. For example, the microprocessor 900 may be implemented by a multi-core hardware circuit system such as a CPU, DSP, GPU, XPU, etc. Although the microprocessor may include any number of instance cores 902 (for example, 1 core), the microprocessor 900 of this example is a multi-core semiconductor device including N cores. The cores 902 of the microprocessor 900 may operate independently or may cooperate to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 902, or may be executed by multiple of the cores 902 at the same or different times. In some instances, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more of the cores 902. The software program may correspond to a thread executed by Figure 6 , 7A , 7B and / or 7C represent part or all of the machine-readable instructions and / or operations.

[0156] The cores 902 can communicate via a first example bus 904. In some examples, the first bus 904 can be implemented by a communication bus to enable communications associated with one or more of the cores 902. For example, the first bus 904 can be implemented by at least one of an interconnect integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 904 can be implemented by any other type of computing or electrical bus. The cores 902 can obtain data, instructions, and / or signals from one or more external devices via an example interface circuit system 906. The cores 902 can output data, instructions, and / or signals to one or more external devices via the interface circuit system 906. Although the core 902 of this example includes an example local memory 920 (e.g., a level 1 (L1) cache that can be split into an L1 data cache and an L1 instruction cache), the microprocessor 900 also includes an example shared memory 910 (e.g., a level 2 (L2 cache)) that can be shared by the cores for high-speed access to data and / or instructions. Data and / or instructions can be transferred (e.g., shared) by writing to and / or reading from the shared memory 910. The local memory 920 and shared memory 910 of each core 902 can be a plurality of levels of cache memory and main memory (e.g., Figure 8 The cache memory is part of a storage device hierarchy of main memory 814, 816 of the main memory 814, 816. Generally, higher level memory in the hierarchy exhibits shorter access times and has smaller storage capacity than lower level memory. Changes to various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0157] Each core 902 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit system. Each core 902 includes a control unit circuit system 914, an arithmetic and logic (AL) circuit system (sometimes referred to as an ALU) 916, a plurality of registers 918, a local memory 920, and a second instance bus 922. Other structures may exist. For example, each core 902 may include a vector unit circuit system, a single instruction multiple data (SIMD) unit circuit system, a load / store unit (LSU) circuit system, a branch / jump unit circuit system, a floating point unit (FPU) circuit system, etc. The control unit circuit 914 includes a semiconductor-based circuit structured to control (e.g., coordinate) data movement within the corresponding core 902. The AL circuit system 916 includes a semiconductor-based circuit structured to perform one or more mathematical and / or logical operations on data within the corresponding core 902. The AL circuit system 916 of some instances performs integer-based operations. In other instances, the AL circuit system 916 also performs floating-point operations. In still other examples, AL circuitry 916 may include a first AL circuitry that performs integer-based operations and a second AL circuitry that performs floating-point operations. In some examples, AL circuitry 916 may be referred to as an arithmetic logic unit (ALU).

[0158] Registers 918 are semiconductor-based structures for storing data and / or instructions, such as the results of one or more operations performed by the AL circuit system 916 of the corresponding core 902. For example, registers 918 may include vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Registers 918 may be arranged in groups, such as Fig. 9 Alternatively, registers 918 may be organized in any other arrangement, format, or structure, such as being distributed in core 902 to reduce access time. Second bus 922 may be implemented by at least one of an I2C bus, an API bus, a PCI bus, or a PCIe bus.

[0159] Each core 902 and / or more generally the microprocessor 900 may include additional and / or alternative structures to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common grid stoppers (CMSs), one or more shifters (e.g., barrel shifters), and / or other circuitry. The microprocessor 900 is a semiconductor device fabricated to include many transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) included in one or more packages.

[0160] The microprocessor 900 may include and / or collaborate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some instances, the accelerator is implemented by a logic circuitry to perform certain tasks more quickly and / or efficiently than a general-purpose processor can perform. Examples of accelerators include ASICs and FPGAs, such as those described herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be onboard the microprocessor 900, in the same chip package as the microprocessor 900, and / or in one or more separate packages with the microprocessor 900.

[0161] Fig.10 yes Figure 8 1000. In this example, programmable circuit system 812 is implemented by FPGA circuit system 1000. For example, FPGA circuit system 1000 can be implemented by an FPGA. For example, FPGA circuit system 1000 can be used to execute a programmable circuit system 812 that can be executed by a corresponding machine-readable instruction. Fig. 9 However, once configured, FPGA circuit system 1000 instantiates operations and / or functions corresponding to machine-readable instructions in hardware, and thus can generally perform operations / functions faster than the operations / functions could be performed by a general-purpose microprocessor executing corresponding software.

[0162] More specifically, as described above Fig. 9 The microprocessor 900 (which can be programmed to execute Figure 6 , 7A , 7B and / or 7C, but whose interconnections and logic circuitry are fixed once manufactured. Fig.10 The FPGA circuit system 1000 of the example includes interconnects and logic circuit systems, which can be configured, structured, programmed and / or interconnected in different ways after manufacturing to instantiate, for example, Figure 6 , 7A , 7B, and / or 7C. In particular, FPGA circuit system 1000 can be considered as an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected through the interconnects, effectively forming one or more dedicated logic circuit systems (unless and until FPGA circuit system 1000 is reprogrammed). The logic circuits are configured so that the logic gates can cooperate in different ways to perform different operations on data received by the input circuit system. Those operations may correspond to the operations performed by the input circuit system. Figure 6 , 7A, 7B, and / or 7C. Thus, FPGA circuit system 1000 may be configured and / or structured to effectively communicate with Figure 6 , 7A , 7B and / or 7C are instantiated as dedicated logic circuits to perform the operations / functions corresponding to those software instructions in a dedicated manner similar to an ASIC. Therefore, the FPGA circuit system 1000 can be executed with a general-purpose microprocessor. Figure 6 , 7A , 7B and / or 7C perform the operations / functions faster than some or all of the operations / functions corresponding to the machine-readable instructions.

[0163] exist Fig.10 In an example, the FPGA circuit system 1000 is configured and / or structured in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file may be compiled and / or generated based on instructions in a hardware description language (HDL) such as Lucid, a very high speed integrated circuit (VHSIC) hardware description language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) may write code or a program corresponding to one or more operations / functions in the HDL; the code / program may be converted to a low-level language as needed; and the code / program (e.g., code / program in a low-level language) may be converted (e.g., by a compiler, a software application, etc.) into a binary file. In some examples, Fig.10 The FPGA circuit system 1000 can access and / or load binary files to enable Fig.10 The FPGA circuit system 1000 is configured and / or structured to perform one or more operations / functions. For example, a binary file may be generated by Fig.10 The FPGA circuit system 1000 can be implemented by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions accessible to cause Fig.10 Configuration and / or structuring of FPGA circuit system 1000 or a portion thereof.

[0164] In some instances, the binary file is compiled, generated, converted, and / or otherwise output from a unified software platform for programming the FPGA. For example, the unified software platform may convert a first instruction (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into a second instruction corresponding to one or more operations / functions in an HDL. In some such instances, the binary file is compiled, generated, and / or otherwise output from the unified software platform based on the second instruction. In some instances, Fig.10 The FPGA circuit system 1000 can access and / or load binary files to enable Fig.10 The FPGA circuit system 1000 is configured and / or structured to perform one or more operations / functions. For example, a binary file may be generated by Fig.10 The FPGA circuit system 1000 can be implemented by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions accessible to cause Fig.10 Configuration and / or structuring of FPGA circuit system 1000 or a portion thereof.

[0165] Fig.10 The FPGA circuit 1000 includes an example input / output (I / O) circuit system 1002 to obtain data from and / or output data to an example configuration circuit system 1004 and / or external hardware 1006. For example, the configuration circuit system 1004 may be implemented by an interface circuit system that can obtain a binary file, which may be implemented by a bitstream, data, and / or machine-readable instructions to configure the FPGA circuit system 1000 or a portion thereof. In some such examples, the configuration circuit system 1004 may obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), etc. and / or any combination thereof. In some examples, the external hardware 1006 may be implemented by an external hardware circuit system. For example, the external hardware 1006 may be implemented by Fig. 9 The microprocessor 900 is implemented.

[0166] FPGA circuitry 1000 also includes an array of example logic gate circuitry 1008, a plurality of example configurable interconnects 1010, and example storage circuitry 1012. Logic gate circuitry 1008 and configurable interconnects 1010 may be configured to instantiate a plurality of configurable interconnects 1010 and configurable storage circuitry 1012. Figure 6 , 7A , 7B and / or 7C machine-readable instructions corresponding to one or more operations / functions, and / or other desired operations. Fig.10The logic gate circuit system 1008 shown in is manufactured in blocks or groups. Each block includes a semiconductor-based electrical structure that can be configured into a logic circuit. In some examples, the electrical structure includes a logic gate (e.g., And gate, Or gate, Nor gate, etc.) that provides a basic building block for the logic circuit. An electrically controlled switch (e.g., transistor) is present in each logic gate circuit system 1008 to enable the configuration of the electrical structure and / or logic gate to form a circuit to perform the desired operation / function. The logic gate circuit system 1008 may include other electrical structures, such as a lookup table (LUT), a register (e.g., a flip-flop or latch), a multiplexer, etc.

[0167] The configurable interconnect 1010 of the illustrated example is a conductive path, trace, via, etc. that may include electrically controlled switches (e.g., transistors), the state of which can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuit systems 1008 to program the desired logic circuit.

[0168] The storage circuitry 1012 of the illustrated example is structured to store the results of one or more operations performed by corresponding logic gates. The storage circuitry 1012 may be implemented by registers, etc. In the illustrated example, the storage circuitry 1012 is distributed among the logic gate circuitry 1008 to facilitate access and increase execution speed.

[0169] Fig.10 The example FPGA circuit system 1000 also includes an example dedicated operation circuit system 1014. In this example, the dedicated operation circuit system 1014 includes a dedicated circuit system 1016, which can be called to implement common functions, thereby eliminating the need to program those functions on site. Examples of such dedicated circuit systems 1016 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory, and multiplier-accumulator circuit systems. There may be other types of dedicated circuit systems. In some examples, the FPGA circuit system 1000 may also include an example general programmable circuit system 1018, such as an example CPU 1020 and / or an example DSP 1022. There may be other general programmable circuit systems 1018 that can be programmed to perform other operations, such as GPUs, XPUs, etc., in addition or alternatively.

[0170] although Fig. 9 and 10 illustrate Figure 8 These are two example implementations of programmable circuitry 812, but many other approaches are contemplated. For example, the FPGA circuitry may include an onboard CPU, such as one or more Fig.10The instance CPU is 1020. Therefore, Figure 8 The programmable circuit system 812 may additionally be configured by combining at least Fig. 9 The example microprocessor 900 is Fig.10 In some such hybrid examples, Fig. 9 The one or more cores 902 may execute Figure 6 , 7A , 7B and / or 7C to perform a first operation / function, Fig.10 The FPGA circuit system 1000 may be configured and / or structured to perform the same as that Figure 6 , 7A , 7B and / or 7C, and / or the ASIC may be configured and / or structured to perform the same operations / functions as those described above. Figure 6 , 7A , 7B and / or 7C corresponds to a third operation / function of the third portion of the machine-readable instructions represented by the flowcharts.

[0171] It should be understood, therefore, Figure 3 Some or all of the circuitry of may be instantiated at the same or different times. For example, Fig. 9 The same and / or different portions of microprocessor 900 may be programmed to execute portions of machine-readable instructions at the same and / or different times. In some examples, Fig.10 The same and / or different portions of FPGA circuit system 1000 may be configured and / or structured to perform operations / functions corresponding to portions of the machine-readable instructions at the same and / or different times.

[0172] In some instances, Figure 3 Some or all of the circuitry of may be instantiated, for example, in one or more threads that execute simultaneously and / or serially. Fig. 9 The microprocessor 900 may execute machine-readable instructions in one or more threads of execution simultaneously and / or serially. In some examples, Fig.10 The FPGA circuit system 1000 can be configured and / or structured to perform operations / functions simultaneously and / or serially. In addition, in some examples, Figure 3 Some or all of the circuitry in the Fig. 9 The system is implemented in one or more virtual machines and / or containers executed on the microprocessor 900.

[0173] In some instances, Figure 8 The programmable circuit system 812 may be in one or more packages. For example, Fig. 9 The microprocessor 900 and / or Fig.10The FPGA circuit system 1000 may be in one or more packages. In some examples, the XPU may be composed of Figure 8 The XPU may be implemented by a programmable circuit system 812, which may be in one or more packages. For example, the XPU may be included in a CPU in a package (e.g., Fig. 9 Microprocessor 900, Fig.10 CPU 1020, etc.), a DSP in another package (e.g., Fig.10 DSP 1022 in another package), a GPU in yet another package, and an FPGA in yet another package (e.g., Fig.10 FPGA circuit system 1000).

[0174] In this specification, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, C, such as: (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments that include any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0175] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0176] Numerical identifiers such as "first", "second", "third", etc. are only used to distinguish elements of substantially the same type in terms of structure and / or function. These identifiers as used in the detailed description are not necessarily consistent with the identifiers used in the claims.

[0177] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or through a combination thereof.

[0178] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnects or their ends between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components.

[0179] Circuits or devices described herein as including certain components may alternatively be adapted to be coupled to those components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0180] The circuits described herein can be reconfigured to include replaced components to provide functionality that is at least partially similar to the functionality available before component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements that are coupled in series and / or in parallel to provide the impedance amount represented by the resistor shown. For example, a resistor or capacitor shown and described as a single component in this article may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described as a single component in this article may alternatively be a plurality of resistors or capacitors coupled in series between two nodes that are the same as a single resistor or capacitor, respectively. Although some elements of the described examples are included in the integrated circuit and other elements are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being outside the integrated circuit may be included in the integrated circuit, and / or some features described as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0181] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise stated, "about," "substantially," or "substantially" preceding a value means + / - 10% of the value, or if the value is zero, means a reasonable range of values ​​around zero.

[0182] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

[0183] From the foregoing, it should be appreciated that example systems, apparatus, articles, and methods have been described that enable microprocessor circuitry to be updated using differential image data. The described systems, apparatus, articles, and methods improve the efficiency of using a computing device by allowing microprocessor circuitry to be updated using differential image data using Bsdiff. The described systems, apparatus, articles, and methods are accordingly directed to one or more improvements in the operation of a machine, such as a computer or other electronic and / or mechanical device.

Claims

1. A device comprising: Interface circuit system; machine-readable instructions; as well as A programmable circuit system configured to instantiate and / or execute the machine-readable instructions to: determining a number of memory sectors by which to shift the original image based on a length of additional data in an updated image in the differential image data; shifting the original image by the number of memory sectors to create a swap area, the swap area comprising the number of memory sectors; as well as The updated image is constructed based on the differential image data and the original image.

2. The apparatus of claim 1, further comprising a first memory configured to store the original image and differential image data and a second memory configured to store one or more portions of the updated image.

3. The apparatus of claim 1 , wherein the differential image data comprises additional data, differential data, and control data, the control data comprises a plurality of control blocks, each control block of the plurality of control blocks having first data, second data, and third data, wherein the programmable circuit system is configured to: determining the first data and the second data of the control block of the control data; generating a first portion of the updated image by XORing a first number of bytes from the differential data with the first number of bytes from the original image, the first number of bytes being based on the first data; and A second portion of the updated image is generated from a second number of bytes from the additional data, the second number of bytes being based on the second data.

4. The apparatus of claim 3, wherein the programmable circuitry is configured to: determining a length of the first portion of the update image and a length of the second portion of the update image; determining whether the length is greater than or equal to a sector size, the sector size being the number of bytes in a memory sector; and In response to determining that the length is greater than or equal to a length of a memory sector, the number of bytes is written to the memory sectors of the first portion of the update image and the second portion of the update image.

5. The apparatus of claim 1, wherein the programmable circuitry is configured to shift the swap region by clearing a memory sector of the original image in response to determining that the pointer to the memory sector is no longer needed.

6. The apparatus of claim 1 , wherein the programmable circuit system is configured to track the construction of the update image using a plurality of records, the plurality of records comprising a record for each memory sector of the swap area and the original image, the record being used to identify one of a first value or a second value.

7. The apparatus of claim 1, wherein the programmable circuitry is configured to swap portions of the original image with the update image based on the construction of portions of the update image.

8. The device according to claim 1, wherein The differential image data comprises additional data to be added to the original image to construct the updated image; and The differential image data contains differential data representing a difference between bits of the original image and the update image.

9. At least one non-transitory computer-readable storage medium comprising instructions that, when executed, cause a programmable circuit system to perform at least the following operations: determining a number of memory sectors by which to shift the original image based on a length of additional data in an updated image in the differential image data; shifting the original image by the number of memory sectors to create a swap area, the swap area comprising the number of memory sectors; as well as The updated image is constructed based on the differential image data and the original image.

10. The at least one non-transitory computer-readable storage medium of claim 9, further comprising a first memory configured to store the original image and differential image data and a second memory configured to store one or more portions of the updated image.

11. The at least one non-transitory computer-readable storage medium of claim 9, wherein the differential image data comprises additional data, differential data, and control data, the control data comprises a plurality of control blocks, each control block of the plurality of control blocks having first data, second data, and third data, wherein the instructions are used to cause the programmable circuit system to: determining the first data and the second data of the control block of the control data; generating a first portion of the updated image by XORing a first number of bytes from the differential data with the first number of bytes from the original image, the first number of bytes being based on the first data; and A second portion of the updated image is generated from a second number of bytes from the additional data, the second number of bytes being based on the second data.

12. The at least one non-transitory computer-readable storage medium of claim 11, wherein the instructions are to cause the programmable circuit system to: determining a length of the first portion of the update image and a length of the second portion of the update image; determining whether the length is greater than or equal to a sector size, the sector size being the number of bytes in a memory sector; and In response to determining that the length is greater than or equal to a length of a memory sector, the number of bytes is written to the memory sectors of the first portion of the update image and the second portion of the update image.

13. The at least one non-transitory computer-readable storage medium of claim 9, wherein the instructions are to cause the programmable circuitry to shift the swap region by clearing a memory sector of the original image in response to determining that the pointer to the memory sector is no longer needed.

14. The at least one non-transitory computer-readable storage medium of claim 9, wherein the instructions are to cause the programmable circuit system to track the construction of the update image using a plurality of records, the plurality of records comprising a record for each memory sector of the swap area and the original image, the record identifying one of a first value or a second value.

15. The at least one non-transitory computer-readable storage medium of claim 9, wherein the instructions are to cause the programmable circuitry to swap the original image with the update image based on the construction of a portion of the update image.

16. The at least one non-transitory computer-readable storage medium of claim 9, wherein: The differential image data comprises additional data to be added to the original image to construct the updated image; and The differential image data contains differential data representing a difference between bits of the original image and the update image.

17. A method comprising: determining a number of memory sectors by which to shift the original image based on a length of additional data in an updated image in the differential image data; shifting the original image by the number of memory sectors to create a swap area, the swap area comprising the number of memory sectors; as well as The updated image is constructed based on the differential image data and the original image.

18. The method according to claim 17, wherein the differential image data comprises additional data, differential data and control data, the control data comprises a plurality of control blocks, each of the plurality of control blocks has first data, second data and third data, the method further comprising: determining the first data and the second data of the control block of the control data; generating a first portion of the updated image by XORing a first number of bytes from the differential data with the first number of bytes from the original image, the first number of bytes being based on the first data; as well as A second portion of the updated image is generated from a second number of bytes from the additional data, the second number of bytes being based on the second data.

19. The method according to claim 18, further comprising: determining a length of the first portion of the update image and a length of the second portion of the update image; determining whether the length is greater than or equal to a sector size, the sector size being the number of bytes in a memory sector; as well as In response to determining that the length is greater than or equal to a length of a memory sector, the number of bytes is written to the memory sectors of the first portion of the update image and the second portion of the update image.

20. The method of claim 17, further comprising shifting the swap area by clearing a pointer to a memory sector of the original image in response to determining that the pointer is no longer needed.

Images