A SIMD instruction conversion optimization method based on instruction pipeline

Abstract

The invention discloses a SIMD instruction conversion optimization method based on instruction pipeline. When executing an executable file in a dynamic instruction conversion mode, for instructions to be converted without operands, the existing instruction conversion mode is adopted to complete the conversion. For instructions to be converted with operands, the segmentation mode of the operands of the instructions to be converted is determined according to the ratio of the word length of the instruction to be converted and the word length of the ARM instruction. Then, according to the segmentation mode and whether the instructions to be converted are located in a loop body, the ARM instruction combination to be converted into is determined, and the ARM instruction combination obtained by the conversion is executed in an instruction pipeline mode to complete the conversion of the instructions to be converted, thereby effectively reducing the performance loss caused by the data segmentation process.

Description

Technical Field

[0001] The invention belongs to the technical field of computer software development, and in particular relates to a SIMD instruction conversion optimization method based on instruction pipeline. Background Art

[0002] The SIMD extended instruction set under the existing x86 architecture supports a variety of word lengths. For example, in 256-bit mode, the vector register can store 256-bit data. Common operations include arithmetic operations and logical operations on 256-bit vectors. NEON is a SIMD extended instruction set in the ARM architecture, and its data vector length is usually 128 bits. Therefore, when using NEON instructions to process longer data vectors related to the SIMD instructions of the x86 architecture, it is necessary to first split the long vector of the x86 architecture into multiple shorter data vectors that can be processed by the NEON instructions, and then process them separately, and finally merge the processing results. However, since additional splitting and merging operations need to be performed, the execution performance of executable files may be reduced when simulating the execution of the SIMD instructions of the x86 architecture in the ARM architecture based on the data vector splitting method. Summary of the invention

[0003] In view of this, the present invention provides a SIMD instruction conversion optimization method based on instruction pipeline, which determines the ARM instruction combination that the instruction needs to be converted into according to the segmentation method of the instruction operands and whether the instruction is located in a loop body, and then executes the converted ARM instruction combination in an instruction pipeline manner to realize instruction conversion.

[0004] The present invention provides a SIMD instruction conversion optimization method based on instruction pipeline, which specifically includes the following steps:

[0005] Step 1, load and execute the executable file through dynamic instruction conversion, if the current instruction to be converted is an instruction with operands in the x86 architecture, execute step 2, otherwise convert the current instruction to be converted into an ARM instruction and then execute step 10;

[0006] Step 2, record the ratio of the word length of the current instruction to be converted to the word length of the ARM instruction as N, obtain M operands of the current instruction to be converted and the first calculation method, and divide the M operands into M1 group and M2 group, and divide each operand into N sub-operands; if the current instruction to be converted is in a loop body, record the loop body as the first loop body and execute step 3, otherwise execute step 6;

[0007] Step 3: Take the instructions in the first loop body as the first instruction set. If there is data dependency between the current instruction to be converted and other instructions and the data dependency is register dependency, then execute step 4; otherwise, execute step 9.

[0008] Step 4: Select multiple ARM architecture registers to replace the registers in the first instruction set, and form a second instruction set by converting the ARM instructions. If there is no data dependency between the instructions in the second instruction set, execute step 5; otherwise, execute step 9;

[0009] Step 5, add a second loop body in the first loop body, the total number of loops of the second loop body is N, set the initial value of the loop number n to 1 and the value of n is not greater than N, load the first sub-operand of the M operands; in the nth loop of the second loop body, when n+1 is not greater than N, load the n+1th sub-operand of the M1 group operand, then use the first calculation method to complete the calculation of the nth sub-operand of the M1 group operand, and finally load the n+1th sub-operand of the M2 group operand when n+1 is not greater than N, if n is not greater than N, let n be incremented by 1 and then execute the second loop body, otherwise end the loop; use the instruction pipeline method to execute the second loop body to complete the conversion of the current instruction to be converted, and execute step 10;

[0010] Step 6: Take a set number of instructions before and after the current instruction to be converted in the executable file as a third instruction set. If there is data dependency between the current instruction to be converted and other instructions and the dependency is register, then execute step 7; otherwise, execute step 9;

[0011] Step 7: convert the instructions in the third instruction set into ARM instructions, select multiple ARM architecture registers to replace the registers in the third instruction set, and form a fourth instruction set by the ARM instructions obtained by the conversion. If there is no data dependency between the instructions in the fourth instruction set, execute step 8, otherwise execute step 9;

[0012] Step 8, construct a third loop body, the total number of loops of the third loop body is N, let the initial value of the loop number n be 1 and the value of n be not greater than N; in the nth loop of the third loop body, load the nth sub-operand of the M operands and use the first calculation method to complete the calculation of the nth sub-operand of the M operands, when n+1 is not greater than N, load the n+1th sub-operand of the M operands and use the first calculation method to complete the calculation of the n+1th sub-operand of the M operands, if n is not greater than N, let n be incremented by 1 and then execute the third loop body, otherwise end the loop; use the instruction pipeline method to execute the third loop body to complete the conversion of the current instruction to be converted, and execute step 10;

[0013] Step 9: Complete the conversion of the instruction according to the data dependency of the current instruction to be converted;

[0014] Step 10. If the executable file has not completed execution, select the next instruction as the current instruction to be converted. When the current instruction to be converted is an instruction with an operand, execute step 2. When the current instruction to be converted is an instruction without an operand, convert the current instruction to be converted into an ARM instruction and then execute step 10. Otherwise, complete the execution of the executable file and end this process.

[0015] Furthermore, in step 3, the method for determining whether there is data dependency between the current instruction to be converted and other instructions and the dependency is register dependency is: using a register tracking method to analyze the first instruction set to determine the dependency relationship between the current instruction to be converted and other instructions.

[0016] Furthermore, the implementation method of selecting multiple ARM architecture registers to replace the registers in the first instruction set in step 4 is: implementing it by register renaming.

[0017] Furthermore, in step 6, the method for determining whether there is data dependency between the current instruction to be converted and other instructions and the dependency is register dependency is: using a register tracking method to analyze the third instruction set to determine the dependency relationship between the current instruction to be converted and other instructions.

[0018] Furthermore, the implementation method of selecting multiple ARM architecture registers to replace the registers in the third instruction set in step 7 is: implementing it by register renaming.

[0019] Furthermore, the instruction with operands is a single-operand instruction, a double-operand instruction or a multi-operand instruction. Beneficial Effects

[0020] When the present invention executes an executable file in a dynamic instruction conversion mode, for instructions to be converted without operands, the existing instruction conversion mode is used to complete the conversion. For instructions to be converted with operands, the segmentation mode of the operands of the instructions to be converted is determined according to the ratio of the word length of the instruction to be converted and the word length of the ARM instruction. Then, according to the segmentation mode and whether the instruction to be converted is located in a loop body, the ARM instruction combination to be converted into is determined, and the ARM instruction combination obtained by the conversion is executed in an instruction pipeline mode to complete the conversion of the instruction to be converted, thereby effectively reducing the performance loss caused by the data segmentation process. DETAILED DESCRIPTION

[0021] The present invention is described in detail with reference to the following embodiments.

[0022] Instruction pipelining is a technology used to improve CPU performance. It improves processor efficiency and throughput by breaking down the instruction execution process into multiple stages and allowing these stages to process different instructions in parallel at different time points.

[0023] The invention provides a SIMD instruction conversion optimization method based on instruction pipeline, the core idea of ​​which is: when executing an executable file in a dynamic instruction conversion mode, for instructions to be converted without operands, the existing instruction conversion mode is used to complete the conversion; for instructions to be converted with operands, the division mode of the operands of the instructions to be converted is determined according to the ratio of the word length of the instruction to be converted and the word length of the ARM instruction; then, according to the division mode and whether the instruction to be converted is located in a loop body, the ARM instruction combination to be converted into is determined; and the ARM instruction combination obtained by the conversion is executed in an instruction pipeline mode to complete the conversion of the instruction to be converted.

[0024] The present invention provides a SIMD instruction conversion optimization method based on instruction pipeline, which specifically includes the following steps:

[0025] Step 1: Load and execute the executable file through dynamic instruction conversion. If the current instruction to be converted is an instruction with operands in the x86 architecture, execute step 2; otherwise, convert the current instruction to be converted into an ARM instruction and then execute step 10.

[0026] The existing x86 architecture generally provides a variety of instructions such as no operand instructions, single operand instructions, double operand instructions and multi-operand instructions. With the development of the x86 instruction set, an extended instruction set supporting 256-bit word length operations has been constructed, and on this basis, 512-bit word length operations have been introduced. The present invention mainly focuses on extended instruction sets with word lengths greater than 128 bits.

[0027] The x86 instruction set contains multiple instruction types, including data transfer instructions, calculation instructions, control instructions, transfer instructions, input and output instructions, etc.

[0028] Step 2, record the ratio of the word length of the current instruction to be converted to the word length of the ARM instruction as N, obtain M operands of the current instruction to be converted and the first calculation method, and divide the M operands into M1 group and M2 group, and divide each operand into N sub-operands; analyze the relevant code of the current instruction to be converted to determine whether the current instruction to be converted is located in the loop body, if the current instruction to be converted is located in the loop body, record the loop body as the first loop body and execute step 3, otherwise execute step 6.

[0029] Step 3: Take the instructions in the first loop body as the first instruction set, and use the register tracking method to analyze the first instruction set to determine the dependency between the current instruction to be converted and other instructions. If there is data dependency and it is register dependency, execute step 4, otherwise execute step 9.

[0030] Step 4: Convert the instructions in the first instruction set into ARM instructions, and use register renaming to select multiple ARM architecture registers to replace the registers related to the instructions in the first instruction set. The ARM instructions obtained by the conversion form a second instruction set. If there is no data dependency between the instructions in the second instruction set, execute step 5; otherwise, execute step 9.

[0031] Step 5. Select a register in the ARM architecture, add a second loop body in the first loop body, the total number of loops of the second loop body is N, set the initial value of the loop number n to 1 and n is not greater than N, load the first sub-operand of the M operands; in the nth loop of the second loop body, first load the n+1th sub-operand of the M1 group operand when n+1 is not greater than N, then use the first calculation method to complete the calculation of the nth sub-operand of the M1 group operand, and finally load the n+1th sub-operand of the M2 group operand when n+1 is not greater than N, if n is not greater than N, let n be incremented by 1 and continue to execute the second loop body, otherwise end the loop; use the instruction pipeline method to execute the second loop body to complete the conversion of the current instruction to be converted, and execute step 10.

[0032] Step 6: Take a set number of instructions before and after the current instruction to be converted in the executable file as the third instruction set, and use the register tracking method to analyze the third instruction set to determine the dependency relationship between the current instruction to be converted and other instructions. If there is data dependency and it is register dependency, execute step 7; otherwise, execute step 9.

[0033] Step 7: Convert the instructions in the third instruction set into ARM instructions, and use register renaming to select multiple ARM architecture registers to replace the registers related to the instructions in the third instruction set. The ARM instructions obtained by the conversion form a fourth instruction set. If there is no data dependency between the instructions in the fourth instruction set, execute step 8; otherwise, execute step 9.

[0034] Step 8. Select a register in the ARM architecture and construct a third loop body. The total number of loops of the third loop body is N. The initial value of the number of loops n is 1 and n is not greater than N. In the nth loop of the third loop body, load the nth sub-operand of the M operands and use the first calculation method to complete the calculation of the nth sub-operand of the M operands. When n+1 is not greater than N, load the n+1th sub-operand of the M operands and use the first calculation method to complete the calculation of the n+1th sub-operand of the M operands. If n is not greater than N, let n be incremented by 1 and continue to execute the third loop body, otherwise end the loop; use the instruction pipeline method to execute the third loop body to complete the conversion of the current instruction to be converted, and execute step 10.

[0035] Step 9: Complete the instruction conversion according to the data dependency of the current instruction to be converted.

[0036] Step 10. If the executable file has not been executed, the next instruction is selected as the current instruction to be converted. When the current instruction to be converted is an instruction with operands in the x86 architecture, step 2 is executed. When the current instruction to be converted is an instruction without operands in the x86 architecture, the current instruction to be converted is converted into an ARM instruction and then step 10 is executed; otherwise, the execution of the executable file is completed and this process ends. Example

[0037] In this embodiment, a SIMD instruction conversion optimization method based on instruction pipeline provided by the present invention is used to realize dynamic conversion of basic arithmetic operation instructions in AVX instructions to NEON instructions by modifying the AVX instruction conversion module of the dynamic instruction conversion engine. The basic arithmetic operation instructions include addition instructions (VADDPS, VADDPD, VADDSS or VADDPI), subtraction instructions (VSUBPS, VSUBPD or VSUBSS), multiplication instructions (VMULPS or VMULPD), fused multiplication instructions (VFMADDPS or VFMADDPD), etc., and specifically includes the following steps:

[0038] S1. When converting AVX basic arithmetic operation instructions into NEON instructions, it is necessary to split the operands of two 256-bit vectors into two 128-bit vectors and then execute the corresponding NEON arithmetic operation instructions, and then perform subsequent conversion operations.

[0039] For example, the AVX addition instruction: vaddps ymm0, ymm0, ymm1, adds the single-precision floating-point numbers in two 256-bit vector registers ymm0 and ymm1, and then stores the result back to register ymm0. When converting it to a NEON instruction, it is necessary to split the operands of the two 256-bit vectors into two 128-bit vectors and then execute the corresponding NEON arithmetic operation instructions, and then perform subsequent conversion operations. The specific steps are as follows:

[0040] S2. Determine whether there is data dependency in the converted instruction stream, and try to eliminate the dependency. Analyze the data dependency of AVX instructions based on the existing memory access analysis or register tracking method. If there is data dependency and it is register dependency, use the register renaming method to resolve the register dependency. If there is no data dependency, execute S4, otherwise execute S3.

[0041] S3. Execute loading, calculation and storage in the order of AVX instructions, that is, execute instructions sequentially, first complete the loading and calculation of the first 128-bit part, then load and calculate the second 128-bit part, and finally store the result. Specifically, split ymm0 into two 128-bit NEON registers q0 and q2, split ymm1 into two 128-bit NEON registers q1 and q3, and the converted NEON code is as follows:

[0042] / / Load and add the first 128-bit portion

[0043] ldr q0, [r0] / / load the first 128-bit vector from memory address r0 to q0

[0044] ldr q1, [r0, #16] / / Load the first 128-bit vector from memory address r0 + 16 into q1

[0045] qadd q0, q0, q1 / / Add the 128-bit vectors in q1 and q0 and store the result back in q0

[0046] / / Load and add the second 128-bit portion

[0047] ldr q2, [r0, #32] / / load the second 128-bit vector from memory address r0 + 32 into q2

[0048] ldr q3, [r0, #48] / / load the second 128-bit vector from memory address r0 + 48 into q3

[0049] qadd q2, q2, q3 / / Add the 128-bit vectors in q3 and q2, and store the result back in q2

[0050] / / Store the result back into memory

[0051] str q0, [r1] / / Store the 128-bit result in q0 to memory address r1

[0052] str q2, [r1, #16] / / Store the 128-bit result in q2 to memory address r1 + 16

[0053] S4. Use the instruction pipeline to optimize the NEON instruction, that is, load the data in advance to make it parallel with the calculation operation. When the first 128-bit vector is added, the second 128-bit vector is loaded. The optimized instruction code is as follows:

[0054] / / Load and add the first 128-bit portion

[0055] ldr q0, [r0] / / load the first 128-bit vector from memory address r0 to q0

[0056] ldr q1, [r0, #16] / / Load the first 128-bit vector from memory address r0 + 16 into q1

[0057] qadd q0, q0, q1 / / Add the 128-bit vectors in q1 and q0 and store the result back in q0

[0058] / / Load the second vector of the second 128-bit part in advance and parallelize the calculation of the first part

[0059] ldr q3, [r0, #48]

[0060] qadd q2, q2, q3 / / Add the 128-bit vectors in q3 and q2, and store the result back in q2

[0061] / / Store the result back into memory

[0062] str q0, [r1] / / Store the 128-bit result in q0 to memory address r1

[0063] str q2, [r1, #16] / / Store the 128-bit result in q2 to memory address r1 + 16

[0064] In the unoptimized case, the load operations are executed sequentially, which will generate waiting time. For example, the loading of the second 128-bit vector is started only after the loading of the first 128-bit vector is completed. In the optimized pipeline code, the first load operation ldr q2, [r0, #32] of the second 128-bit vector is performed in advance, and while the addition calculation qadd q0, q0, q1 of the first 128-bit vector is being performed, the second load operation ldr q3, [r0, #48] of the second 128-bit vector is also being performed. This reduces the waiting time and improves the parallelism and overall performance of instruction execution.

[0065] S5. If it is detected whether AVX is in a loop (for example, processing multiple vectors in an array), determine whether there is data dependency in the converted instruction stream within a single loop, and try to eliminate the dependency. If there is still data dependency, perform standard data segmentation and AVX to NEON instruction conversion, otherwise execute S6.

[0066] The specific sample code to perform standard data segmentation and AVX to NEON instruction conversion is as follows:

[0067] / / Assume that n 256-bit vector pairs are to be processed, r0 points to the input data, r1 points to the output result storage location, and r2 stores the number of vector pairs n

[0068] MOV r3, #0 / / loop counter

[0069] LOOP_START:

[0070] / / Load and add the first 128-bit portion

[0071] ldr q0, [r0] / / load the first 128-bit vector from memory address r0 to q0

[0072] ldr q1, [r0, #16] / / Load the first 128-bit vector from memory address r0 + 16 into q1

[0073] qadd q0, q0, q1 / / Add the 128-bit vectors in q1 and q0 and store the result back in q0

[0074] / / Load and add the second 128-bit portion

[0075] ldr q2, [r0, #32] / / load the second 128-bit vector from memory address r0 + 32 into q2

[0076] ldr q3, [r0, #48] / / load the second 128-bit vector from memory address r0 + 48 into q3

[0077] qadd q2, q2, q3 / / Add the 128-bit vectors in q3 and q2, and store the result back in q2

[0078] / / Store the result back to memory (assuming it is stored to result_ptr and result_ptr + 16)

[0079] str q0, [r1] / / Store the 128-bit result in q0 to memory address r1

[0080] str q2, [r1, #16] / / Store the 128-bit result in q2 to memory address r1 + 16

[0081] add r0, r0, #64 / / point to the next pair of 256-bit vectors

[0082] add r1, r1, #32 / / point to the next set of result storage locations

[0083] add r3, r3, #1

[0084] CMP r3, r2

[0085] BNE LOOP_START

[0086] S6. By loading the data of the next pair of vectors in advance, the data loading and calculation operations can be partially overlapped in each loop iteration. That is, while the first 128-bit vector of the current vector pair is added, the partial data of the second 128-bit vector of the next pair of vectors is loaded to reduce the waiting time between each loop iteration and improve the overall execution efficiency. Based on the above unpipelined code, the pipelined sample code is as follows:

[0087] / / Assume that n 256-bit vector pairs are to be processed, r0 points to the input data (vector pair), r1 points to the output result storage location, and r2 stores the number of vector pairs n

[0088] MOV r3, #0 / / loop counter

[0089] LOOP_START_PIPELINED:

[0090] / / Pre-load the first vector of the second 128-bit portion of the next pair of vectors

[0091] ldr q2, [r0, #32]

[0092] / / Load and add the first 128-bit portion

[0093] ldr q0, [r0] / / load the first 128-bit vector from memory address r0 to q0

[0094] ldr q1, [r0, #16] / / Load the first 128-bit vector from memory address r0 + 16 into q1

[0095] qadd q0, q0, q1 / / Add the 128-bit vectors in q1 and q0 and store the result back in q0

[0096] / / Load the second vector of the second 128-bit part of the next pair of vectors in advance and parallelize the calculation of the first part

[0097] ldr q3, [r0, #48]

[0098] qadd q2, q2, q3 ; add the 128-bit vectors in q3 and q2 and store the result back in q2

[0099] / / Store the result back to memory (assuming it is stored to result_ptr and result_ptr + 16)

[0100] str q0, [r1] / / Store the 128-bit result in q0 to memory address r1

[0101] str q2, [r1, #16] / / Store the 128-bit result in q2 to memory address r1 + 16

[0102] add r0, r0, #64 / / point to the next pair of 256-bit vectors

[0103] add r1, r1, #32 / / point to the next set of result storage locations

[0104] add r3, r3, #1

[0105] CMP r3, r2

[0106] BNE LOOP_START_PIPELINED

[0107] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A SIMD instruction conversion optimization method based on instruction pipeline, characterized in that: The specific steps include: Step 1, load and execute the executable file through dynamic instruction conversion, if the current instruction to be converted is an instruction with operands in the x86 architecture, execute step 2, otherwise convert the current instruction to be converted into an ARM instruction and then execute step 10; Step 2, record the ratio of the word length of the current instruction to be converted to the word length of the ARM instruction as N, obtain M operands of the current instruction to be converted and the first calculation method, and divide the M operands into M1 group and M2 group, and divide each operand into N sub-operands; if the current instruction to be converted is in a loop body, record the loop body as the first loop body and execute step 3, otherwise execute step 6; Step 3: Take the instructions in the first loop body as the first instruction set. If there is data dependency between the current instruction to be converted and other instructions and the data dependency is register dependency, then execute step 4; otherwise, execute step 9. Step 4: Select multiple ARM architecture registers to replace the registers in the first instruction set, and form a second instruction set by converting the ARM instructions. If there is no data dependency between the instructions in the second instruction set, execute step 5; otherwise, execute step 9; Step 5, add a second loop body in the first loop body, the total number of loops of the second loop body is N, set the initial value of the number of loops n to 1 and the value of n is not greater than N, and load the first sub-operand of the M operands; In the nth loop of the second loop body, when n+1 is not greater than N, the n+1th sub-operand of the M1 group operand is loaded, and then the calculation of the nth sub-operand of the M1 group operand is completed by using the first calculation method, and finally when n+1 is not greater than N, the n+1th sub-operand of the M2 group operand is loaded, and if n is not greater than N, n is incremented by 1 and the second loop body is executed, otherwise the loop ends; the second loop body is executed in an instruction pipeline manner to complete the conversion of the current instruction to be converted, and step 10 is executed; Step 6: Take a set number of instructions before and after the current instruction to be converted in the executable file as a third instruction set. If there is data dependency between the current instruction to be converted and other instructions and the dependency is register, then execute step 7; otherwise, execute step 9; Step 7: convert the instructions in the third instruction set into ARM instructions, select multiple ARM architecture registers to replace the registers in the third instruction set, and form a fourth instruction set by the ARM instructions obtained by the conversion. If there is no data dependency between the instructions in the fourth instruction set, execute step 8, otherwise execute step 9; Step 8, construct the third loop body, the total number of loops of the third loop body is N, and the initial value of the number of loops n is set to 1 and the value of n is not greater than N; In the nth loop of the third loop body, the nth sub-operand of the M operands is loaded and the calculation of the nth sub-operand of the M operands is completed by using the first calculation method. When n+1 is not greater than N, the n+1th sub-operand of the M operands is loaded and the calculation of the n+1th sub-operand of the M operands is completed by using the first calculation method. If n is not greater than N, n is incremented by 1 and the third loop body is executed. Otherwise, the loop ends. The third loop body is executed in an instruction pipeline manner to complete the conversion of the current instruction to be converted, and step 10 is executed; Step 9: Complete the conversion of the instruction according to the data dependency of the current instruction to be converted; Step 10. If the executable file has not completed execution, select the next instruction as the current instruction to be converted. When the current instruction to be converted is an instruction with an operand, execute step 2. When the current instruction to be converted is an instruction without an operand, convert the current instruction to be converted into an ARM instruction and then execute step 10. Otherwise, complete the execution of the executable file and end this process.

2. The SIMD instruction conversion optimization method according to claim 1, characterized in that: In step 3, the judgment method of whether there is data dependency between the current instruction to be converted and other instructions and the dependency is register dependency is: using the register tracking method to analyze the first instruction set to determine the dependency relationship between the current instruction to be converted and other instructions.

3. The SIMD instruction conversion optimization method according to claim 1, characterized in that: The implementation method of selecting multiple ARM architecture registers to replace the registers in the first instruction set in step 4 is: implementing it by register renaming.

4. The SIMD instruction conversion optimization method according to claim 1, characterized in that: In step 6, the judgment method of whether there is data dependency between the current instruction to be converted and other instructions and the dependency is register dependency is: using the register tracking method to analyze the third instruction set to determine the dependency relationship between the current instruction to be converted and other instructions.

5. The SIMD instruction conversion optimization method according to claim 1, characterized in that: The implementation method of selecting multiple ARM architecture registers to replace the registers in the third instruction set in step 7 is: implementing it by register renaming.

6. The SIMD instruction conversion optimization method according to claim 1, characterized in that: The instruction with operands is a single-operand instruction, a double-operand instruction or a multi-operand instruction.