Handling memory access transactions

Abstract

A memory access transaction is processed. The memory attribute structure includes one or more memory address entries. Each memory address entry includes a respective range of memory addresses mapped to a respective priority level. A memory attribute table is used when processing a memory access transaction through an execution path of a processing system. During the processing, a memory address of a memory access transaction is determined. The memory attribute structure is to determine a priority level mapped to the determined memory address, and process a memory access transaction based on the determined priority level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to UK patent application GB2311971.2 filed on August 4, 2023 and UK patent application GB2311973.8 filed on August 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to processing of memory access transactions (eg, load and store transactions) by a processing system. Background Art

[0004] In a computing (or processing) system, a central processing unit (CPU) is responsible for executing the instructions of a computer program. The CPU typically includes an arithmetic logic unit (ALU) that performs arithmetic and logical operations, processor registers that supply operands to the ALU and store the results of the ALU operations, a control unit responsible for fetching, decoding, and executing instructions as part of an instruction cycle, and one or more buses that allow data to flow between other components. The components of the CPU are arranged in an execution path (or data path). During a given instruction cycle, instructions are fetched from a program memory, then decoded to determine what the CPU needs to do, and ultimately executed. During the execution of an instruction, data is transferred along one of the execution paths of the CPU.

[0005] A processing system may have a load-store architecture whereby the instruction set architecture (i.e., the instruction set implemented by the system) falls into one of several categories, including: memory access instructions (where data is transferred between memory and registers), ALU operations (where data is transferred only between registers), instructions that modify system registers without using the ALU, branches, system calls, barriers, and no operations (NOPs).

[0006] A memory system (or memory access) instruction refers to a load or store instruction. For example, a memory access instruction may be "read the value from memory address 1234 into value A" or "write value B to memory address 5678". A given memory access instruction may generate one or more memory access transactions, i.e., one or more requests to read data from or write data to memory. When the CPU executes memory instructions, some memory system transactions (i.e., load or store requests) go through the same execution path, e.g., from a control unit through a memory system unit to a slave unit (e.g., a DRAM controller), and may return results along the same path. Whether transactions go through the same execution path depends on the design of the CPU.

[0007] Transactions typically require data and control information to be stored in buffers internal and external to the CPU. In other words, a transaction may need to be written to certain buffers in the memory system in order to proceed through the memory system.

[0008] When processing multiple transactions that use the same execution path, a portion of the execution path or a buffer may be used by a previous transaction (e.g., a transaction of a previously executed instruction, or a different transaction resulting from the same instruction), which means that the processing of the current transaction is delayed until that portion of the execution path or that buffer is available for the current transaction. That is, the processing of one transaction depends on the processing of another transaction.

[0009] The dependency of the processing of one transaction on another transaction is problematic. For example, it is problematic if the transaction needs to be executed quickly (i.e., within a certain time frame) and the execution of the transaction requires components or buffers of the execution path currently used by a different transaction. For example, a transaction may involve safety-critical operations that should not be delayed by other non-safety-related operations. A specific example is in the context of an anti-lock braking system (ABS). In this context, transactions related to instructions to apply the brakes should not be affected by other transactions. Therefore, there is a need for the CPU to be able to prioritize a subset of a set of transactions that do use the same execution path. Summary of the invention

[0010] This summary is provided only to illustrate some of the concepts disclosed herein and their possible implementations. Not all of what is described in the summary is intended to limit the scope of the present disclosure. Instead, the scope of the present disclosure is limited only by the claims.

[0011] Some CPUs require that certain memory access instructions have higher determinism or quality of service (QoS) guarantees than other memory access instructions. In other words, the CPU may require that a particular memory access instruction be executed within a time threshold or without any delay. Previous attempts to deal with this problem involved having separate ports (a port is a collection of signals used to send data between two segments of a system) for each memory region (i.e., address range) that required deterministic guarantees, with the locations of these ports being in a fixed address space, and the ports being driven by separate, non-shared logic.

[0012] Some embodiments of the present disclosure address this problem by designating certain memory regions as high priority using a memory attribute structure (eg, a lookup table), and prioritize the processing of transactions requiring the high priority memory regions.

[0013] Some embodiments of the present disclosure address this problem by using a memory attribute structure to designate certain memory regions as high priority, and to reserve buffer space (e.g., a collection of registers (or other memory types, such as RAM) used to store data or control for a transaction) for transactions that require the high priority memory regions.

[0014] According to embodiments of the present disclosure, marking a transaction as high priority means that it can be prioritized at some or all stages of the execution path. This has the effect that it reaches the slave unit (e.g., DRAM controller) as quickly as possible without having to wait for the execution path to process other transactions. Similarly, the results of the transaction can be prioritized when being returned to the CPU.

[0015] Similarly, reserving buffer space for high priority transactions has the effect that there are free buffers available for reading and writing (load or store) data required by the transaction, which means that processing of the high priority transaction is not delayed until buffer space becomes available.

[0016] According to one aspect disclosed herein, a method for processing a memory access transaction through an execution path of a processing system is provided. A memory attribute structure includes one or more memory address entries, each memory address entry including a corresponding memory address range mapped to a corresponding priority level in a set of priority levels. The method includes determining a memory address of the memory access transaction; using the memory attribute structure to determine a priority level mapped to the determined memory address; and processing the memory access transaction based on the determined priority level.

[0017] Each memory address entry specifies a corresponding priority level of a corresponding memory address range. That is, the corresponding priority level of the memory address range is defined in (and specified by) the memory attribute table.

[0018] Using the memory attribute structure to determine the priority level may include identifying (eg, looking up) a memory address of a memory access transaction in a memory attribute table and identifying a priority level assigned to the memory address region as part of an associated memory address entry.

[0019] In an embodiment, processing the memory access transaction includes associating the memory access transaction with the determined priority level; and prioritizing the memory access transaction over one or more corresponding memory access transactions associated with corresponding priority levels having lower priorities than the determined priority level.

[0020] For example, memory access transactions may be prioritized for one or more of: transmission through one or more interfaces of the processing system, receipt into a buffer space, and processing by one or more components of the execution path.

[0021] In an embodiment, the memory access transaction may be associated with a flag indicating the priority level.

[0022] In an embodiment, the processing system may include one or more buffer spaces reserved for use by memory access transactions associated with a predetermined priority level. A memory access transaction may be allocated to one of the reserved buffer spaces.

[0023] In an embodiment, the memory attribute structure may be configurable by a user of the processing system. For example, one or more of the following may be configurable: a respective priority level mapped to a respective memory address range, one or more reserved buffer spaces reserved for use by memory access transactions associated with the respective priority level, a configurable number of priority levels in the set of priority levels, and a respective number of reserved buffer spaces for each respective priority level.

[0024] According to another aspect disclosed herein, a processing system is provided for processing a memory access transaction through an execution path of the processing system. The processing system has stored in a memory a memory attribute structure including one or more memory address entries, each memory address entry including a corresponding memory address range mapped to a corresponding priority level in a set of priority levels. The processing system is configured to: determine a memory address of the memory access transaction; use the memory attribute structure to determine a priority level mapped to the determined memory address; and process the memory access transaction based on the determined priority level.

[0025] According to another aspect disclosed herein, a method for configuring a memory attribute structure for use in processing a memory access transaction through an execution path of a processing system is provided. The method includes configuring one or more memory address entries, each memory address entry including a corresponding memory address range mapped to a corresponding priority level in a set of priority levels. A central processing unit of the processing system is configured to use the memory attribute structure to determine a corresponding priority level of a corresponding memory address mapped to a corresponding memory access transaction, and to process the corresponding memory access transaction based on the corresponding priority level.

[0026] According to another aspect disclosed herein, a processing system is provided, the processing system being used to process memory access transactions through an execution path of the processing system. The processing system has stored in a memory a memory attribute structure including one or more memory address entries, each memory address entry including a corresponding memory address range mapped to a corresponding priority level in a set of priority levels. The processing system is configured to: configure the one or more memory address entries, each memory address entry including a corresponding memory address range mapped to a corresponding priority level in a set of priority levels; use the memory attribute structure to determine a corresponding priority level of a corresponding memory address mapped to a corresponding memory access transaction; and process the corresponding memory access transaction based on the corresponding priority level.

[0027] According to another aspect disclosed herein, a memory attribute structure is provided for use by a central processing unit when processing memory access transactions through an execution path of a processing system, wherein the memory attribute structure includes one or more memory address entries, each memory address entry including a corresponding memory address range mapped to a corresponding priority level in a set of priority levels.

[0028] The processing system may be included in hardware on an integrated circuit. A method of manufacturing a processing system at an integrated circuit manufacturing system may be provided. An integrated circuit definition data set may be provided, the integrated circuit definition data set, when processed in the integrated circuit manufacturing system, configures the system to manufacture the processing system. A non-transitory computer-readable storage medium may be provided, having stored thereon a computer-readable description of the processing system, the computer-readable description, when processed in the integrated circuit manufacturing system, causing the integrated circuit manufacturing system to manufacture an integrated circuit including the processing system.

[0029] An integrated circuit manufacturing system may be provided, the integrated circuit manufacturing system comprising: a non-transitory computer-readable storage medium having stored thereon a computer-readable description of a processing system; a layout processing system configured to process the computer-readable description to generate a circuit layout description of an integrated circuit including the processing system; and an integrated circuit generation system configured to manufacture the processing system based on the circuit layout description.

[0030] A computer program code for performing any of the methods described herein may be provided.A non-transitory computer readable storage medium may be provided on which computer readable instructions are stored which, when executed in a computer system, cause the computer system to perform any of the methods described herein.

[0031] As will be apparent to the skilled person, the above features may be combined as appropriate and may be combined with any aspect of the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Examples will now be described in detail with reference to the accompanying drawings, in which:

[0033] Figure 1 A computer system in which a graphics processing system is implemented is shown;

[0034] Figure 2 An integrated circuit manufacturing system for producing an integrated circuit including a graphics processing system is shown;

[0035] Figure 3 An exemplary processing system configured to prioritize certain memory access instructions is shown; and

[0036] Figure 4 A flow chart for prioritizing certain memory access instructions is shown.

[0037] The accompanying drawings show various examples. It will be appreciated by the skilled person that the element boundaries (e.g., boxes, groups of boxes, or other shapes) shown in the accompanying drawings represent an example of boundaries. In some examples, it may be the case that an element can be designed as multiple elements, or multiple elements can be designed as one element. Where appropriate, common reference numerals are used throughout the accompanying drawings to indicate similar features. DETAILED DESCRIPTION

[0038] The following description is presented by way of example to enable one skilled in the art to make and use the invention.The present invention is not limited to the embodiments described herein, and various modifications to the disclosed embodiments will be apparent to those skilled in the art.

[0039] Embodiments will now be described by way of example only.

[0040] Figure 3A simplified version of a processing system is schematically shown. The processing system includes a CPU (i.e., a main processing unit) 302, an interconnect 304, and a memory system 310. The memory system 310 is external to the CPU 302. The CPU 302 is connected to the memory system 310 via the interconnect 304 (i.e., a communication bus) and is configured to communicate with the memory system. The CPU 302 is connected to the interconnect 304 via an interface 308. Similarly, the interconnect 304 is connected to the memory system 310 via an interface 306. The processing system also includes a memory attribute structure 312. The memory attribute structure can take the form of a table, or more generally any type of code. The memory attribute table 312 can be stored within the CPU 302 or separate from the CPU. In either case, the CPU is configured to access the memory attribute table. The memory system 310 can take any suitable form, such as one or more caches, one or more registers, and a main memory. The system can include each type of memory. Although the memory system 310 is shown as being connected to the interconnect 304 via a single interface 306, it should be appreciated that the memory system 310 may be composed of several subsystems, each with its own connection to the interconnect.

[0041] The memory attribute table includes, in particular, a plurality of memory address entries. Each memory address entry specifies a region (or range) of memory. A memory region may be specified by an upper address and a lower address. Alternatively, a memory region may be specified by a lower address and a size. Each memory range is mapped to a priority level (i.e., associated with a priority level). For example, each memory address entry may be a key-value pair, wherein the key is a memory range, and the value is a priority level. In some examples, there are only two priority levels, such as a high priority level and a low priority level, or prioritized and not prioritized. In these examples, a memory region mapped to a low priority level or not prioritized does not need to include an indication of a low (or lacking) priority level. That is, it is sufficient that there is no indication of a high priority level. In some examples, there may be more than two priority levels, such as high, medium, and low, or very high, high, and low. As long as a hierarchy with a highest priority level and a lowest priority level is followed, any number of priority levels may exist. Priority levels may be indicated in the memory attribute table in any suitable manner, such as by an integer (1 or 0), a string (e.g., "high" or "low"), or otherwise. In some examples, only some of the available memory ranges are included as part of a corresponding entry in the memory attribute table. In other examples, each available memory range is included as part of a corresponding entry in the memory attribute table. In the previous example, not including a memory range can be interpreted as that the memory range has the lowest priority.

[0042] One reason to mark an address range as high priority is that some peripherals (e.g., external devices) are particularly important to the high priority code and will be within the given address range. Another reason is that the system needs to reserve small, fast memory blocks for high priority code, leaving large, slow memory blocks for normal code.

[0043] The memory attribute table may include other information discussed further below.

[0044] The processing system is configured to process memory access instructions, i.e., load and store instructions. A given memory access instruction may be decoded into one or more memory access transactions. A memory access transaction is a request to read or write data. For simplicity, the examples will be described primarily in the context of a one-to-one mapping of instructions to transactions, but it will be appreciated that the examples may be more generally applicable to a one-to-many mapping of instructions to transactions. These examples may also be applied to a many-to-one mapping of transactions to instructions, where multiple instructions target the same region of memory and may be combined into one transaction.

[0045] Each memory access transaction is associated with a memory address. If the memory access transaction is a request to load (i.e., read) data, the memory address may be an address in memory 310 where the requested data is stored. If the memory access transaction is a request to store (i.e., write) data, the address may be an address in memory 310 where the data is to be stored.

[0046] The processing system is configured to process memory access transactions based on an associated memory address and a priority level of the memory address. When processing a memory access transaction, the CPU 302 determines (e.g., when decoding a corresponding memory access instruction) a memory address required for the transaction. The CPU 302 looks up the memory address in a memory attribute table. That is, the CPU 302 determines which memory address entry includes a memory range that includes the memory address required for the transaction. The CPU 302 then identifies a priority level that is mapped to the memory range that includes the required memory address. Thereafter, the processing of the memory access transaction is based at least in part on the priority level.

[0047] The CPU 302 may associate a memory access transaction with a priority level. This may be done in any suitable manner. For example, the CPU 302 may attach (e.g., pre-set or append) a flag (e.g., one or more bits) indicating the priority level to the transaction. The flag may remain attached to the memory access transaction as it is passed to each component of the processing system so that the component is aware of its priority level.

[0048] Memory access transactions can be prioritized to process memory access transactions with lower priorities. That is, CPU 302 can determine the corresponding memory addresses required for one or more other memory access transactions, and then determine the corresponding priority levels of those memory addresses. If a memory transaction is associated with a priority level that is higher (i.e., larger, more important, etc.) than the priority level of one or more memory access transactions in those other memory access transactions, the memory transaction is prioritized over lower priority transactions. For example, in the case of only two priority levels, if the transaction is a high priority transaction, it is prioritized over low priority transactions. On the contrary, the transaction may not be prioritized over a transaction with a higher priority than the target priority level. Similarly, in some examples, the transaction is not prioritized over a previous transaction with the same priority level (i.e., a transaction that CPU 302 has already started processing).

[0049] A memory access transaction may be prioritized for transmission to one or more components of the processing system compared to a lower priority memory access transaction. That is, the memory access transaction may be prioritized when selecting which memory access transaction to send through one or more interfaces between components of the processing system. For example, the memory access transaction may be prioritized for transmission between the CPU 302 and the interconnect 304 and / or between the interconnect 304 and the memory system 310. Similarly, the result of the (one or more) operation(s) triggered to be performed by the memory access transaction may be prioritized when being returned to the CPU 302 from the memory system 310 via the interconnect 304. In some examples, the selection of memory access transactions is prioritized at each interface of the processing system.

[0050] Compared to lower priority memory access transactions, memory access transactions can be prioritized to be processed by one or more components of the processing system. For example, CPU 302 can process memory access transactions before one or more lower priority transactions, for example, a memory access transaction can be selected to be executed before a lower priority transaction. Interconnect 304 can process memory access transactions before one or more lower priority transactions, for example, a memory access transaction can be sent to memory system 310 before a lower priority transaction. Similarly, memory access transactions can be prioritized to be accepted into buffer space before lower priority transactions. That is, if buffer space is available to accept transactions, memory access transactions can be sent to the buffer instead of lower priority transactions.

[0051] As mentioned, the processing system may include multiple buffers. One or more buffers are included in the logic inside the CPU 302. One or more buffers may be included in the logic inside the interconnect 304. Among these buffers, some buffers may be reserved for the processing of high priority transactions. That is, some buffers may be marked as "reserved buffers". When the CPU 302 determines that a memory access transaction has a certain priority level (e.g., any level higher than the lowest priority level), one of the buffers in the reserved buffers may remain free to accept the memory access transaction. In other words, the CPU 302 assigns the memory access transaction to the reserved buffer so that the memory access transaction is sent to the buffer and stored in the buffer without delay.

[0052] Each memory region may be mapped to one or more reserved buffers. Additionally or alternatively, each priority level may be mapped to one or more reserved buffers. The mapping may be stored in the memory attribute table 312. For example, a memory address entry mapping includes a memory region mapped to one or more reserved buffers. An entry may include an indication or reference to a reserved buffer used by the CPU 302 to direct a memory access transaction to one of the buffers.

[0053] The memory address entries in the memory attribute table may be fixed or configurable by a user of the device comprising the processing system. In the latter case, one or more entries may be preloaded. New entries may be created. Entries may be edited. For example, a user may configure the memory attribute table by mapping priority levels to memory address ranges. The number of priority levels may be selected by the user. A user may configure the memory attribute table by marking one or more buffers as reserved buffers. A user may select the number of reserved buffers to be allocated to each memory range and / or priority level. A user may select the total number of reserved buffers. The memory attribute table may be configured at build time of the processing system.

[0054] Figure 4An exemplary process of a memory access transaction according to the embodiments described herein is shown. Some steps may be omitted and / or performed in a different order. The process may involve additional steps not shown. In step S01, CPU 302 executes a memory access instruction that generates one or more memory access transactions. For a given memory access transaction, in step S02, CPU 302 determines the memory address associated with the transaction. In step S03, CPU 302 searches the memory address in the memory attribute table 312 and determines whether the memory address is marked as a high priority. If the memory address is marked as a high priority, then in step S04, the transaction (e.g., with a flag) is marked as a high priority. If the memory address is marked as a high priority, then in step S05, buffer space is reserved for the transaction. In step S06, the high priority transaction is prioritized over the low priority transaction, including: prioritizing the selection of transactions to be sent through the CPU-interconnect interface 308 and any interconnect-slave unit interface (for example, if any) between the interconnect and a slave or auxiliary processing unit), prioritizing the acceptance of the transaction into the reserved buffer space, and prioritizing the sending of the results of the transaction executed to be sent through the slave unit-interconnect interface and / or the interconnect-CPU interface 308.

[0055] The processing system may have a RISC-V architecture. The memory attribute table may be a physical memory attribute (PMA) table. The RISC-V PMA table may be extended so that it specifies determinism / QoS requirements for each address range. Each group of memory areas with sharing requirements may have an internal buffer and logic reserved for memory access packets, and may have its own external interface. The number of packets, the amount of reserved logic for each packet, and the area of ​​each packet may be configurable at build time. Existing solutions are not configurable or flexible, are more complex, and have a higher area cost. For example, if the system has different ports for different memory ranges to provide deterministic guarantees, this will require additional areas to provide dedicated logic for driving different ports, and once the hardware has been manufactured, the memory range cannot be changed. In contrast, the present solution allows the same hardware logic to be configured in different ways depending on usage requirements.

[0056] Figure 1A computer system in which the processing system described herein may be implemented is shown. The computer system includes a CPU 902, a GPU 904, a memory 906, a neural network accelerator (NNA) 908, and other devices 914 (e.g., a display 916, a speaker 918, and a camera 922). A processing block 910 is implemented on the CPU 902. The processing block may be configured to perform the methods described herein. In other examples, one or more of the depicted components may be omitted from the system, and / or the processing block 910 may be implemented on the GPU 904 or within the NNA 908. The components of the computer system may communicate with each other via a communication bus 920. A storage area 912 is implemented as part of the memory 906.

[0057] Although shown with different reference numerals, Figure 3 The CPU 302, interconnect 304 and memory 310 may be Figure 1 The processing block 910 may be configured to perform the operations described above as being performed by the CPU 302, the bus 920, and the memory 906.

[0058] Figures 1 to 3 The processing system of FIG. 1 is shown as including a plurality of functional blocks. This is merely illustrative and is not intended to define a strict division between different logical elements of such an entity. Each functional block may be provided in any suitable manner. It should be understood that intermediate values ​​described herein as being formed by the processing system need not be physically generated by the processing system at any point in time, and may represent only logical values ​​that are convenient for describing the processing performed by the processing system between its input and output.

[0059] The processing system described herein may be included in hardware on an integrated circuit. The processing system described herein may be configured to perform any of the methods described herein. In general, any of the functions, methods, techniques, or components described above may be implemented in software, firmware, hardware (e.g., fixed logic circuits), or any combination thereof. The terms "module," "function," "component," "element," "unit," "block," and "logic" may be used herein to generally represent software, firmware, hardware, or any combination thereof. In the case of software implementation, a module, function, component, element, unit, block, or logic represents a program code that, when executed on a processor, performs a specified task. The algorithms and methods described herein may be performed by one or more processors that execute code, which causes (one or more) processors to perform the algorithm / method. Examples of computer-readable storage media include random access memory (RAM), read-only memory (ROM), optical disks, flash memory, hard disk storage, and other memory devices that may use magnetic, optical, and other technologies to store instructions or other data and may be accessed by a machine.

[0060] As used herein, the terms computer program code and computer readable instructions refer to any kind of executable code for a processor, including code expressed in machine language, interpreted language, or scripting language. Executable code includes binary code, machine code, byte code, code that defines an integrated circuit (e.g., hardware description language or netlist), and code expressed in programming language code such as C, Java, or OpenCL. Executable code can be, for example, any kind of software, firmware, script, module, or library that, when properly executed, processed, interpreted, compiled, run in a virtual machine or other software environment, causes a processor of a computer system supporting the executable code to perform the tasks specified by the code.

[0061] A processor, computer or computer system may be any kind of device, machine or special purpose circuit, or a collection or part thereof, which has processing capabilities so that it can execute instructions. A processor may be or include any kind of general or special purpose processor, such as a CPU, GPU, NNA, system on chip, state machine, media processor, application specific integrated circuit (ASIC), programmable logic array, field programmable gate array (FPGA), etc. A computer or computer system may include one or more processors.

[0062] The present invention is also intended to cover software (e.g., HDL (Hardware Description Language) software) that defines the configuration of hardware as described herein, which is used to design integrated circuits or to configure programmable chips to perform desired functions. That is, a computer-readable storage medium may be provided on which is encoded a computer-readable program code in the form of an integrated circuit definition data set, which, when processed (i.e., run) in an integrated circuit manufacturing system, configures the system to manufacture a processing system configured to perform any of the methods described herein, or to manufacture a processing system that includes any of the devices described herein. The integrated circuit definition data set may be, for example, an integrated circuit description.

[0063] Thus, a method of manufacturing a processing system as described herein at an integrated circuit manufacturing system may be provided. Furthermore, an integrated circuit definition data set may be provided which, when processed in an integrated circuit manufacturing system, causes the method of manufacturing a processing system to be performed.

[0064] The integrated circuit definition data set may be in the form of computer code, for example as a netlist, code for configuring a programmable chip, as a hardware description language that defines hardware suitable for fabrication at any level in an integrated circuit, including as register transfer level (RTL) code, as a high-level circuit representation such as Verilog or VHDL, and as a low-level circuit representation such as OASIS (RTM) and GDSII. The higher-level representation that logically defines hardware suitable for fabrication in an integrated circuit (e.g., RTL) may be processed at a computer system configured to generate a manufacturing definition of the integrated circuit in the context of a software environment that includes definitions of circuit elements and rules for combining those elements to generate a manufacturing definition of the integrated circuit so defined by the representation. As is typically the case with software executed at a computer system to define a machine, one or more intermediate user steps (e.g., providing commands, variables, etc.) may be required to configure the computer system to generate a manufacturing definition of the integrated circuit to execute code that defines the integrated circuit to generate the manufacturing definition of the integrated circuit.

[0065] Now refer to Figure 2 An example of processing an integrated circuit definition data set at an integrated circuit manufacturing system to configure the system into a manufacturing processing system is described.

[0066] Figure 2 An example of an integrated circuit (IC) manufacturing system 1002 is shown, which is configured to manufacture a processing system as described in any example herein. In particular, the IC manufacturing system 1002 includes a layout processing system 1004 and an integrated circuit generation system 1006. The IC manufacturing system 1002 is configured to receive an IC definition data set (e.g., defining a processing system as described in any example herein), process the IC definition data set, and generate an IC (e.g., which includes a processing system as described in any example herein) based on the IC definition data set. Processing of the IC definition data set configures the IC manufacturing system 1002 to manufacture an integrated circuit including a processing system as described in any example herein.

[0067] The layout processing system 1004 is configured to receive and process an IC definition data set to determine a circuit layout. Methods for determining a circuit layout based on an IC definition data set are known in the art and may, for example, involve synthesizing RTL code to determine a gate-level representation of a circuit to be generated, for example, in terms of logic components (e.g., NAND, NOR, AND, OR, MUX, and FLIP-FLOP components). By determining location information for the logic components, the circuit layout may be determined by the gate-level representation of the circuit. This may be done automatically or with user involvement in order to optimize the circuit layout. When the layout processing system 1004 has determined the circuit layout, it may output the circuit layout definition to the IC generation system 1006. The circuit layout definition may be, for example, a circuit layout description.

[0068] As is known in the art, the IC generation system 1006 generates the IC according to the circuit layout definition. For example, the IC generation system 1006 may implement a semiconductor device manufacturing process to generate the IC, which may involve a multi-step sequence of photolithography and chemical processing steps during which electronic circuits are gradually formed on a wafer made of semiconductor material. The circuit layout definition may be in the form of a mask that can be used in a photolithography process to generate the IC according to the circuit definition. Alternatively, the circuit layout definition provided to the IC generation system 1006 may be in the form of a computer readable code that the IC generation system 1006 may use to form a suitable mask for generating the IC.

[0069] The different processes performed by the IC manufacturing system 1002 may all be implemented at one location, such as by one party. Alternatively, the IC manufacturing system 1002 may be a distributed system such that some processes may be performed at different locations and may be performed by different parties. For example, some of the following stages may be performed at different locations and / or by different parties: (i) synthesizing RTL code representing an IC definition data set to form a gate-level representation of a circuit to be generated; (ii) generating a circuit layout based on the gate-level representation; (iii) forming a mask based on the circuit layout; and (iv) using the mask to manufacture the integrated circuit.

[0070] In other examples, processing of an integrated circuit definition data set at an integrated circuit manufacturing system may configure the system to manufacture a processing system without processing the IC definition data set to determine a circuit layout. For example, the integrated circuit definition data set may define a configuration of a reconfigurable processor such as an FPGA, and processing of the data set may configure the IC manufacturing system to generate a reconfigurable processor having the defined configuration (e.g., by loading the configuration data into the FPGA).

[0071] In some embodiments, when processed in an integrated circuit manufacturing system, the integrated circuit manufacturing definition data set can cause the integrated circuit manufacturing system to generate an apparatus as described herein. Figure 2 Configuring an integrated circuit manufacturing system in the manner described may enable manufacturing of the apparatus described herein.

[0072] In some examples, the integrated circuit definition data set may include software that runs on, or in combination with, hardware defined at the data set. Figure 2 In the example shown, the IC generation system can be further configured by the integrated circuit definition dataset to load firmware onto the integrated circuit according to the program code defined at the integrated circuit definition dataset when manufacturing the integrated circuit, or otherwise provide the integrated circuit with program code for use with the integrated circuit.

[0073] Compared to known implementations, the implementation of the concepts set forth in this application in devices, equipment, modules and / or systems (and in the methods implemented herein) can cause performance improvements. Performance improvements can include one or more of improved computing performance, reduced latency, increased throughput and / or reduced power consumption. During the manufacture of such devices, devices, modules and systems (e.g., in integrated circuits), a trade-off can be made between performance improvements and physical implementations to improve manufacturing methods. For example, a trade-off can be made between performance improvements and layout area to match the performance of known implementations, but using less silicon. For example, this can be accomplished by reusing functional blocks in a serial manner or sharing functional blocks between elements of devices, devices, modules and / or systems. In contrast, the concepts set forth in this application that cause improvements in the physical implementations of devices, devices, modules and systems (e.g., reduced silicon area) can be weighed against performance improvements. This can be accomplished, for example, by manufacturing multiple instances of a module within a predefined area budget.

[0074] Applicants hereby independently disclose each individual feature described herein and any combination of two or more such features, to the extent that such feature or combination can be implemented based on the specification as a whole in view of the common general knowledge of a person skilled in the art, regardless of whether such feature or combination of features solves any problem disclosed herein. In view of the foregoing description, it will be clear to a person skilled in the art that various modifications can be made within the scope of the invention.

Claims

1. A method of processing memory access transactions through an execution path of a processing system, wherein a memory attribute structure comprises one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level in a set of priority levels, and wherein the method comprises: determining a memory address of the memory access transaction; using the memory attribute structure to determine a priority level mapped to the determined memory address; as well as The memory access transaction is processed based on the determined priority level.

2. The method of claim 1 , wherein processing the memory access transaction comprises: associating the memory access transaction with the determined priority level; as well as The memory access transaction is prioritized over one or more corresponding memory access transactions associated with corresponding priority levels having lower priorities than the determined priority level. 3 . The method of claim 2 , wherein the prioritizing comprises prioritizing selection of the memory access transaction for transmission over one or more interfaces of the processing system. 4 . The method of claim 3 , wherein the one or more interfaces include a CPU-interconnect interface and / or an interconnect-slave interface.

5. The method of claim 2, wherein the prioritizing comprises prioritizing acceptance of memory transactions into a buffer space. 6 . The method of claim 2 , wherein the prioritizing comprises prioritizing processing of the memory access transaction by one or more components of the execution path.

7. The method of claim 2, wherein the associating comprises associating a flag with the memory access transaction, wherein the flag indicates the priority level.

8. The method of claim 2, wherein the memory access transaction is deprioritized over one or more corresponding memory access transactions associated with corresponding priority levels having a higher priority than the determined priority level.

9. The method of claim 1 , wherein the processing system includes one or more buffer spaces reserved for use by memory access transactions associated with a predetermined priority level, and wherein processing the memory access transaction includes assigning the memory access transaction to one of the reserved buffer spaces.

10. The method of claim 9, wherein a plurality of reserved buffer spaces are reserved for memory access transactions associated with the determined priority level.

11. The method of claim 9, wherein the processing system comprises a plurality of buffer spaces, and wherein the method comprises marking one or more buffer spaces of the plurality of buffer spaces as the one or more reserved buffer spaces.

12. The method of claim 9, wherein the memory attribute structure includes, for each respective priority level in the set of priority levels, a respective indication of one or more respective reserved buffer spaces.

13. The method of claim 1, wherein the memory attribute structure is configurable by a user of the processing system. The method of claim 13 , wherein the respective priority levels mapped to the respective memory address ranges are configurable.

15. The method of claim 9, wherein the memory attribute structure is configurable by a user of the processing system, and wherein one or more reserved buffer spaces reserved for use by memory access transactions associated with respective priority levels are configurable. The method of claim 13 , wherein the number of priority levels in the set of priority levels is configurable.

17. The method of claim 13, wherein the memory attribute structure is configurable by a user of the processing system, and wherein the respective amount of reserved buffer space for each respective priority level is configurable.

18. The method of claim 13, wherein the memory attribute structure is configurable at build time of the processing system.

19. A computer program embodied on a non-transitory computer readable storage medium and configured such that when executed on a processing system, the processing system performs a method of processing a memory access transaction through an execution path of the processing system, wherein a memory attribute structure comprises one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level in a set of priority levels, and wherein the method comprises: determining a memory address of the memory access transaction; using the memory attribute structure to determine a priority level mapped to the determined memory address; as well as The memory access transaction is processed based on the determined priority level.

20. A processing system for processing memory access transactions through an execution path of the processing system, wherein the processing system has stored in a memory a memory attribute structure comprising one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level in a set of priority levels, and wherein the processing system is configured to: determining a memory address of the memory access transaction; using the memory attribute structure to determine a priority level mapped to the determined memory address; and The memory access transaction is processed based on the determined priority level.

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