Heterogeneous multi-core device and scheduling method

Abstract

The invention provides a heterogeneous multi-core device and a scheduling method, the heterogeneous multi-core device comprises a plurality of cores, the plurality of cores comprise at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any one of the at least one high-performance core is greater than the maximum power consumption of any one of the at least one energy-efficiency core, and the maximum power consumption of any one of the at least one energy-efficiency core is greater than the maximum power consumption of any one of the at least one energy-efficiency core. The maximum computing power of any one of the at least one high-performance core is higher than that of any one of the at least one energy efficiency core; wherein a first core in the plurality of cores can allocate a first computing resource for the first thread and allocate a second computing resource for the second thread, the first computing resource and the second computing resource belong to a second core in the plurality of cores, and the second core is the first core or another core different from the first core; the second core may execute the first thread and the second thread in parallel. The cores in the heterogeneous multi-core device can execute a plurality of threads by using any type of cores in parallel, so that the utilization rate of computing resources in the heterogeneous multi-core device can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a heterogeneous multi-core device and a scheduling method. Background Art

[0002] With the development of electronic technology and the growth of user needs, electronic devices can realize more and more functions. When electronic devices realize different functions, they have different requirements for the computing power of the processor. In order to meet the diverse functional requirements of electronic devices, various types of processor cores (referred to as cores) are set in electronic devices, that is, a heterogeneous multi-core architecture is adopted. In a heterogeneous multi-core architecture, a variety of cores with different processing capabilities can be set, for example, energy-efficient cores (i.e., cores with lower power consumption) and high-performance cores (i.e., cores with higher performance) are set. When the computing power required for the thread corresponding to the function to be realized by the electronic device is small, the electronic device uses the energy-efficient core to execute the thread, which can reduce the energy consumption of the system; when the computing power required for the thread corresponding to the function to be realized by the electronic device is large, the electronic device uses the high-performance core to execute the thread, which can better meet the performance requirements of the thread.

[0003] However, the types of processor cores in electronic devices are limited, and it is difficult to meet the diverse computing power requirements of various threads, which still leads to performance or power consumption waste in the processor cores of electronic devices. Summary of the invention

[0004] The embodiments of the present application provide a heterogeneous multi-core device and a scheduling method to improve the utilization rate of computing resources of the heterogeneous multi-core device.

[0005] In a first aspect, an embodiment of the present application provides a heterogeneous multi-core device, which includes multiple cores, the multiple cores including at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core of the at least one high-performance core is greater than the maximum power consumption of any core of the at least one energy-efficiency core, and the maximum computing capability of any core of the at least one high-performance core is higher than the maximum computing capability of any core of the at least one energy-efficiency core; wherein a first core among the multiple cores is used to allocate a first computing resource to a first thread and a second computing resource to a second thread, the first computing resource and the second computing resource belong to a second core among the multiple cores, and the second core is the first core or another core different from the first core; and the second core is used to execute the first thread and the second thread in parallel, wherein the first computing resource is used to execute the first thread and the second computing resource is used to execute the second thread.

[0006] Among them, the heterogeneous multi-core device can be a chip or a chip module.

[0007] In the embodiment of the present application, the cores in the heterogeneous multi-core device can use any type of core to execute multiple threads in parallel, which can effectively improve the utilization rate of computing resources in the heterogeneous multi-core device and further effectively improve the peak computing power of the heterogeneous multi-core device.

[0008] In one possible design, the multiple cores further include at least one medium-performance core, the maximum power consumption of any one of the at least one high-performance cores is greater than the maximum power consumption of any one of the at least one medium-performance cores, and the maximum computing capability of any one of the at least one high-performance cores is higher than the maximum computing capability of any one of the at least one medium-performance cores; the maximum power consumption of any one of the at least one medium-performance cores is greater than the maximum power consumption of any one of the at least one energy-efficiency cores, and the maximum computing capability of any one of the at least one medium-performance cores is higher than the maximum computing capability of any one of the at least one energy-efficiency cores. In this design, by setting medium-performance cores in a heterogeneous multi-core device, resource allocation to threads is made more flexible, and the diverse performance requirements of different threads can be adapted.

[0009] In one possible design, the first core is specifically used to: allocate a first computing resource to the first thread on the second core according to the performance requirements of the first thread; and allocate a second computing resource to the second thread on the second core according to the performance requirements of the second thread. In this design, computing resources are flexibly allocated to each thread in combination with the performance requirements of each thread, rather than configuring fixed resources for each thread, so as to adapt to the diverse needs of different threads. Specifically, the first core can determine the second core from multiple cores, for example, select the second core according to the performance requirements of the first thread and the performance requirements of the second thread, and the performance of the second core can match the performance requirements of the first thread and the performance requirements of the second thread. For another example, first computing resources and second computing resources are respectively allocated to the first thread and the second thread on the second core according to the performance requirements of the first thread and the performance requirements of the second thread, so as to meet the specific performance requirements of the two threads.

[0010] Optionally, the performance requirement of the first thread is characterized by at least one of the delay sensitivity, business scenario, or user experience of the first thread, and the performance requirement of the second thread is characterized by at least one of the delay sensitivity, business scenario, or user experience of the second thread.

[0011] In one possible design, the first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource different from the first dedicated computing resource; the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the second core. In this design, different dedicated computing resources are allocated to the first thread and the second thread, so that the first thread and the second thread do not interfere with each other when they are executed.

[0012] In one possible design, the first computing resource and the second computing resource include shared computing resources; the second core is further used to: execute the first thread and the second thread in parallel by time-sharing multiplexing the shared computing resources; wherein the priority of the first thread is higher than the priority of the second thread; in time-sharing multiplexing, the time when the first thread uses the shared computing resources takes precedence over the time when the second thread uses the shared computing resources. In this design, the computing resources shared by the first thread and the second thread can be time-sharing multiplexed in combination with the priorities of the first thread and the second thread, effectively improving the utilization rate of computing resources in a heterogeneous multi-core device.

[0013] In a possible design, the shared computing resource includes at least one of the following: an instruction translation bypass cache ITLB, an instruction cache memory ICache, a branch target buffer BTB, a register renaming table RRT, a physical register file RPF, a data translation bypass cache DTLB, or a cache memory DCache. In this design, the first thread and the second thread can share one or more hardware resources, effectively improving resource utilization in a heterogeneous multi-core device.

[0014] In a possible design, the second core supports simultaneous multi-threaded SMT mode and single-threaded ST mode; the second core can also control the second core to switch between SMT mode and ST mode according to the number of threads currently running in the operating system. In this design, the second core can be controlled to switch between SMT mode and ST mode in combination with the number of threads currently running in the operating system in the heterogeneous multi-core device, which can effectively reduce unnecessary power consumption of the second core.

[0015] In one possible design, the second core is further used to: when the first thread causes a blockage in the front end of the pipeline of the second core, and the third thread causes a blockage in the back end of the pipeline of the third core among the multiple cores, schedule the third thread to be executed on the second core, or schedule the first thread to be executed on the third core. The third core is a core different from the second core in the heterogeneous multi-core device. In this design, in combination with the thread execution status of the second core and the third core, the multiple threads to be executed are scheduled to be executed on the appropriate core, so that the computing resources of the core can be better utilized.

[0016] In a possible design, the first thread and the second thread have the same security level. In this design, by setting the same security level for the first thread and the second thread, the first thread and the second thread can be run in an environment with the same security level, thereby avoiding the potential security risks caused by the first thread and the second thread being executed in environments with different security levels.

[0017] In one possible design, the security level is a trusted execution environment (TEE) mode. In this design, by setting the security features of the first thread and the second thread to TEE mode, it is possible to avoid the security risks caused by the first thread being executed in REE and the second thread being executed in REE when the second core executes the first thread and the second thread in parallel.

[0018] In a second aspect, an embodiment of the present application also provides a scheduling method, the method comprising: allocating a first computing resource to a first thread, and allocating a second computing resource to a second thread; wherein the first computing resource and the second computing resource belong to a first core or a second core among a plurality of cores included in a heterogeneous multi-core device; the plurality of cores include at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core in the at least one high-performance core is greater than the maximum power consumption of any core in the at least one energy-efficiency core, and the maximum computing capability of any core in the at least one high-performance core is higher than the maximum computing capability of any core in the at least one energy-efficiency core; executing the first thread and the second thread in parallel, wherein the first computing resource is used to execute the first thread, and the second computing resource is used to execute the second thread.

[0019] In one possible design, the multiple cores also include at least one medium-performance core, the maximum power consumption of any of the at least one high-performance core is greater than the maximum power consumption of any of the at least one medium-performance core, and the maximum computing capability of any of the at least one high-performance core is higher than the maximum computing capability of any of the at least one medium-performance core; the maximum power consumption of any of the at least one medium-performance core is greater than the maximum power consumption of any of the at least one energy-efficiency core, and the maximum computing capability of any of the at least one medium-performance core is higher than the maximum computing capability of any of the at least one energy-efficiency core.

[0020] In one possible design, allocating a first computing resource to a first thread includes: allocating the first computing resource to the first thread on the second core according to the performance requirements of the first thread; allocating a second computing resource to a second thread includes: allocating the second computing resource to the second thread on the second core according to the performance requirements of the second thread. Specifically, the second core is selected according to the performance requirements of the first thread and the performance requirements of the second thread, and the performance of the second core can match the performance requirements of the first thread and the performance requirements of the second thread. For another example, the first computing resource and the second computing resource are respectively allocated to the first thread and the second thread on the second core according to the performance requirements of the first thread and the performance requirements of the second thread, so as to meet the specific performance requirements of the two threads.

[0021] In one possible design, the first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource different from the first dedicated computing resource; the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the first core or the second core.

[0022] In one possible design, the first computing resource and the second computing resource include shared computing resources; the method also includes: executing the first thread and the second thread in parallel by time-sharing multiplexing the shared computing resources; wherein the priority of the first thread is higher than the priority of the second thread; in time-sharing multiplexing, the time when the first thread uses the shared computing resources takes precedence over the time when the second thread uses the shared computing resources.

[0023] In one possible design, the shared computing resources include at least one of the following: an instruction translation bypass buffer ITLB, an instruction cache memory ICache, a branch target buffer BTB, a register renaming table RRT, a physical register file RPF, a data translation bypass buffer DTLB, or a cache memory DCache.

[0024] In one possible design, the second core supports simultaneous multi-threaded SMT mode and single-threaded ST mode; the method also includes: controlling the second core to switch between the SMT mode and the ST mode according to the number of threads currently running in the operating system.

[0025] In one possible design, the method further includes: when the first thread causes a blockage in the pipeline front end of the second core and the third thread causes a blockage in the pipeline back end of a third core among the multiple cores, scheduling the third thread to execute on the second core, or scheduling the first thread to execute on the third core, wherein the third core is different from the second core.

[0026] In a possible design, the first thread and the second thread have the same security level.

[0027] In one possible design, this security level is Trusted Execution Environment (TEE) mode.

[0028] In a third aspect, an embodiment of the present application also provides a scheduling device, which includes a scheduling unit and an execution unit; wherein: the scheduling unit is used to allocate a first computing resource to a first thread, and allocate a second computing resource to a second thread; wherein the first computing resource and the second computing resource belong to a first core or a second core among a plurality of cores included in a heterogeneous multi-core device; the plurality of cores include at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core in at least one high-performance core is greater than the maximum power consumption of any core in at least one energy-efficiency core, and the maximum computing capability of any core in at least one high-performance core is higher than the maximum computing capability of any core in at least one energy-efficiency core; the execution unit is used to execute the first thread and the second thread in parallel, wherein the first computing resource is used to execute the first thread, and the second computing resource is used to execute the second thread.

[0029] In one possible design, the multiple cores also include at least one medium-performance core, the maximum power consumption of any of the at least one high-performance core is greater than the maximum power consumption of any of the at least one medium-performance core, and the maximum computing capability of any of the at least one high-performance core is higher than the maximum computing capability of any of the at least one medium-performance core; the maximum power consumption of any of the at least one medium-performance core is greater than the maximum power consumption of any of the at least one energy-efficiency core, and the maximum computing capability of any of the at least one medium-performance core is higher than the maximum computing capability of any of the at least one energy-efficiency core.

[0030] In one possible design, the scheduling unit is specifically used to: allocate a first computing resource to the first thread on the second core according to the performance requirement of the first thread; allocate a second computing resource to the second thread on the second core according to the performance requirement of the second thread. Specifically, the second core is selected according to the performance requirement of the first thread and the performance requirement of the second thread, and the performance of the second core can match the performance requirement of the first thread and the performance requirement of the second thread. For another example, the first computing resource and the second computing resource are allocated to the first thread and the second thread on the second core respectively according to the performance requirement of the first thread and the performance requirement of the second thread, so as to meet the specific performance requirements of the two threads.

[0031] In one possible design, the first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource different from the first dedicated computing resource; the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the first core or the second core.

[0032] In one possible design, the first computing resource and the second computing resource include shared computing resources; the execution unit is further used to: execute the first thread and the second thread in parallel by time-sharing multiplexing the shared computing resources; wherein the priority of the first thread is higher than the priority of the second thread; in time-sharing multiplexing, the time the first thread uses the shared computing resources takes precedence over the time the second thread uses the shared computing resources.

[0033] In one possible design, the shared computing resources include at least one of the following: an instruction translation bypass buffer ITLB, an instruction cache memory ICache, a branch target buffer BTB, a register renaming table RRT, a physical register file RPF, a data translation bypass buffer DTLB, or a cache memory DCache.

[0034] In one possible design, the scheduling unit is also used to: when the first thread causes a blockage in the front end of the pipeline of the second core, and the third thread causes a blockage in the back end of the pipeline of the third core among the multiple cores, schedule the third thread to be executed on the second core, or schedule the first thread to be executed on the third core; wherein the third core is different from the second core.

[0035] In a possible design, the first thread and the second thread have the same security level.

[0036] In one possible design, this security level is Trusted Execution Environment (TEE) mode.

[0037] In a fourth aspect, an embodiment of the present application further provides a computing device, which includes a heterogeneous multi-core device as described in the first aspect and any optional design of the first aspect, or includes a scheduling device as described in the third aspect and any optional design of the third aspect.

[0038] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium, which includes instructions, and when the computer-readable storage medium is run on a computer, enables the computer to execute the operating steps of the method described in the second aspect and any optional design of the second aspect.

[0039] The beneficial effects of each possible design in the second to fifth aspects of the present application can be referred to the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic diagram of a system architecture applicable to the embodiments of the present application;

[0041] Figure 2 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0042] Figure 3 is a structural diagram of a processor provided in an embodiment of the present application;

[0043] Figure 4A This is one of the structural schematic diagrams of a heterogeneous multi-core device provided in an embodiment of the present application;

[0044] Figure 4B This is the second structural schematic diagram of a heterogeneous multi-core device provided in an embodiment of the present application;

[0045] Figure 4C It is a structural schematic diagram of a scheduling device provided in an embodiment of the present application;

[0046] Figure 5 It is a flowchart of a scheduling method provided in an embodiment of the present application; Figure 6 It is a schematic diagram of a configuration of computing resources provided in an embodiment of the present application;

[0047] Figure 7 is a schematic diagram of a pipeline micro-architecture of a processor core provided in an embodiment of the present application;

[0048] Figure 8 is a schematic diagram of thread scheduling of a multi-core processor provided in an embodiment of the present application;

[0049] Fig. 9 It is a schematic diagram of a scenario in which two computing resources in the processor core provided by the present application are both running in the TEE;

[0050] Fig.10 This is a schematic diagram of a scenario where REE mode and TEE mode are running on a processor core at the same time;

[0051] Fig.11 This is a schematic diagram of a scenario in which two REE modes are simultaneously run on a processor core provided by the present application. DETAILED DESCRIPTION

[0052] Some terms used in the embodiments of the present application are explained below to facilitate understanding by those skilled in the art.

[0053] 1) Processor, which can be located in a complete system on chip (SoC) or in multiple independent chips, realizes data calculation, processing or control functions, and includes processor core and / or memory.

[0054] 2) Processor core, referred to as core, refers to the core part of the processor. A processor can contain one or more processor cores, each of which has its own execution logic, register files, and computing resources. Each processor core can execute one or more threads or instructions.

[0055] 3) Simultaneous multiple threading (SMT), also known as hyperthreading, can be understood as multiple threads executed in parallel by a processor core. A processor core can be configured to execute one thread at a time or multiple threads simultaneously. A processor core configured to execute one thread at a time is said to be in single threaded (ST) mode. A processor core configured to execute multiple threads simultaneously is said to be in SMT mode.

[0056] 4) Thread level parallelism (TLP) is a parallel technology based on the resource management and scheduling of the processor core. Its purpose is to achieve thread-level parallelism, allowing one core to execute multiple threads simultaneously to fully utilize all the resources of the processor core.

[0057] 5) Trusted execution environment (TEE) is a secure computing environment designed to provide a highly protected and isolated execution environment to ensure the security of sensitive data and critical applications. TEE protects sensitive data and critical operations through hardware and software mechanisms, and can prevent malware, attackers and physical attacks from invading and tampering with data and computing. The TEE mode exists in the secure area of ​​the processor core and memory of the electronic device to ensure that sensitive data is stored, processed and protected in a trusted environment. In TEE mode, it is capable of securely executing authorized security software (trusted application (TA)), so it can provide end-to-end security by implementing protection, confidentiality, integrity and data access rights. Specifically, TEE provides a secure world based on hardware isolation to protect the security of sensitive data and the correct execution of programs. To implement TEE, all hardware and software resources of the computing device need to be divided into a secure world and a non-secure world. The two worlds have independent system resources (such as registers, physical memory and peripherals), and the secure world and the non-secure world cannot exchange data at will. The code and resources in the secure world are protected by strict access control policies. Processes in the non-secure world are prohibited from accessing the secure world to ensure that sensitive resources stored in the secure world are not illegally accessed or stolen, which can effectively reduce the disclosure of security system vulnerabilities, external attacks, and virus intrusions. For example, TEE stores sensitive information such as user identity, keys, and certificates in a secure area. This sensitive information can only be accessed or modified by the TA authorized by TEE, and TEE provides encryption and integrity protection mechanisms for the operation and processing of this sensitive information. In addition, TEE can also provide security services for operating systems in normal execution environments (such as Android). For example, the keys stored in TEE can be used to encrypt user information in normal execution environments (such as sensitive information such as address books and text messages) to ensure the security of sensitive information stored in normal execution environments.

[0058] 6) Rich execution environment (REE) refers to a general execution environment in a computing device that provides general computing and application running. Compared with the trusted execution environment (TEE), the rich execution environment is more general and open, and does not have the same strict security protection and isolation mechanism as TEE. REE provides a general operating system and runtime environment, such as Windows, Linux, Android, etc., allowing users to install and run various third-party applications. REE is usually the default execution environment for computing devices, which provides a wide range of applications and functions to meet the general computing needs of users. However, compared with TEE, REE has lower security and lacks specialized hardware and software protection mechanisms, so additional security measures are required when processing sensitive data and critical operations. Therefore, the TEE environment has a higher security level than REE, and the software and hardware resources that TEE can access are separated from the software and hardware resources that REE can access. Client applications (CA) in REE (such as fingerprint collection, payment applications, etc.) can interact with TA in TEE by calling interfaces. Each TA has one or more corresponding CAs in the REE. In the REE environment, the CA's interface can be called to transmit information to the TEE environment to execute the TA, complete the corresponding functions, and then return the calculation results.

[0059] 7) In the embodiments of the present application, "at least one" refers to one or more, and "at least two" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, and c can represent: a, b, c, a and b, a and c, b and c, or a, b and c, where a, b, c can be single or multiple.

[0060] 8) The modifiers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish between multiple modified contents, and are not used to limit the size, shape, content, order, timing, priority, quantity or importance of the multiple modified contents. For example, the first core and the second core are only used to distinguish between cores that perform different operations, and do not represent the difference in priority or importance of the cores without combining other limiting features. In addition, in the embodiments of the present application, the word "exemplary" is used to indicate an example, illustration or explanation. Any embodiment or design described as "example" in this application should not be interpreted as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word example is intended to present concepts in a concrete way.

[0061] The technical solutions in the embodiments of the present application are described below in conjunction with the accompanying drawings.

[0062] Figure 1 A schematic diagram of a system architecture applicable to an embodiment of the present application is shown, and the architecture includes a computing device 100, a third-party server 200, and a cloud server 300. Among them, the computing device 100 refers to various computers, mobile devices and IoT devices, such as desktops, laptops, smart phones, tablets, sensors, etc. The computing device 100 can run various applications to meet the needs of users. The third-party server 200 is a physical server managed and maintained by an independent service provider, and the third-party server 200 is used to maintain applications developed by application developers. For example, the third-party server 200 can be a server for maintaining WeChat applications or game applications. The cloud server 300 is a virtual server based on cloud computing technology, and the cloud server 300 can perform security detection, security auditing, security marking, grouping and other operations on the applications maintained by the third-party server 200. Among them, the cloud server 300 can perform security marking and grouping operations on the application according to the frequency of use of the application, daily activity, attack records, and special permissions. For example, the cloud server 300 may mark the security level of an application with an attack record as low, and set the application with a low security level to a group; the cloud server 300 may mark the security level of an application without an attack record as high, and set the application with a low security level to a group. For another example, the cloud server 300 may set multiple applications with a high frequency of use to a group, and multiple applications with a low frequency of use to another group. In a possible implementation, the computing device 100 may run multiple applications in the same group at the same time to meet various needs of users.

[0063] like Figure 2As shown, the computing device 100 may include a processor 101 and a memory 102. The processor 101 may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD) or other integrated chips, or may include any one or more of the above devices, and the embodiments of the present application are not specifically limited.

[0064] Among them, the memory 102 is used to store program instructions and data, etc. Specifically, the program instructions may include a program code, and the program code includes a computer operation instruction. The processor 101 can execute the program instructions stored in the memory 102, and use the data stored in the memory 102 to implement the functions of the computing device 100. The memory 102 may be a volatile memory or a non-volatile memory, or the memory 102 may include a volatile and a non-volatile memory. Optionally, the computing device also includes a communication interface, and the memory 102 is coupled to the processor 101 through the communication interface, so that the processor 101 reads the program instructions stored in the memory 102 through the communication interface.

[0065] It should be understood that the connection medium between the processor 101, the memory 102 and the communication interface is not limited in the embodiments of the present application. Figure 2 The memory 102, the processor 101 and the communication interface are connected via a communication bus. Figure 2 The connections between other components are shown in bold lines, which are only schematic and not limiting. The bus may include an address bus, a data bus, a control bus, etc. For ease of representation, Figure 2 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0066] In the embodiment of the present application, the processor 101 may include one chip or multiple chips, and the processor 101 may be implemented using a heterogeneous multi-core architecture. Figure 3A possible structural diagram of the processor 101 is shown in FIG. Figure 3 In the figure, processor 101 includes chip 14 and chip 15, and chip 14 and chip 15 are connected by a bus, which can be any one or more of a data bus, a power bus, a control bus, and a status signal bus. The bus can also be other types of buses that realize connections between devices in processor 101, such as Intel quick path interconnect (QPI).

[0067] Each chip in the processor 101 adopts a heterogeneous multi-core architecture. The components and connection methods inside each chip are described below using chip 14 and chip 15 as examples. Among them, chip 14 includes a heterogeneous multi-core device 140, a memory 144, and a memory manager 143. The heterogeneous multi-core device 140, the memory 144, and the memory manager 143 are interconnected through an on-chip bus. Among them, the heterogeneous multi-core device 140 includes multiple processor cores (such as processor core 141 and processor core 142). When each processor core is configured in SMT mode, each processor core can execute multiple threads in parallel. The hardware resources in each hardware unit used to process each thread in a processor core are logically a logical CPU, which can also be called computing resources, and the computing resources used by the same processor core when executing different threads can be the same or different. For example, the logical CPU in the processor core 141 includes computing resources 1411 and computing resources 1412. The processor core 141 can use computing resources 1411 to execute thread 1, and the processor core 141 can use computing resources 1412 to execute thread 2. The logical CPU in the processor core 142 includes computing resource 1421 and computing resource 1422. The processor core 142 can use computing resource 1421 to execute thread 3, and the processor core 142 can use computing resource 1422 to execute thread 4. The memory 144 refers to an internal memory that directly exchanges data with the computing resources in the heterogeneous multi-core device 140. It can read and write data at any time and at a very high speed. It serves as a temporary data storage for the operating system or other running programs. The memory 144 can be, for example, a static random access memory (SRAM). The memory manager 143 is used to manage and plan data transmission from the memory 144 to any of the computing resources 1411, computing resource 1412, computing resource 1421, and computing resource 1422. The memory manager 143 can be a separate chip outside the chip 14, or a separate chip such as Figure 3 The module shown may be integrated in chip 14 .

[0068] The chip 15 includes a heterogeneous multi-core device 150, a memory 154 and a memory manager 153, and the heterogeneous multi-core device 150, the memory 154 and the memory manager 153 are interconnected through an on-chip bus. Among them, the heterogeneous multi-core device 150 includes multiple processor cores (such as processor core 151 and processor core 152), and each processor core can execute multiple threads in parallel when configured in SMT mode. The hardware resources in each hardware unit used to process each thread in a processor core are logically a logical CPU, which can also be called computing resources, and the computing resources used when executing different threads in the same processor core can be the same or different. For example, the logical CPU in the processor core 151 includes computing resources 1511 and computing resources 1512, and the processor core 151 can use computing resources 1511 to execute thread 5, and the processor core 151 can use computing resources 1512 to execute thread 6. The logical CPU in processor core 152 includes computing resource 1521 and computing resource 1522. Processor core 152 can use computing resource 1521 to execute thread 7, and processor core 152 can use computing resource 1522 to execute thread 8. Memory 154 refers to an internal memory that directly exchanges data with computing resources in heterogeneous multi-core device 150. It can read and write data at any time and at a high speed, and serves as a temporary data storage for an operating system or other running programs. Memory 154 can be, for example, SRAM. Memory manager 153 is used to manage and plan data transmission from memory 154 to any of computing resources 1511, computing resource 1512, computing resource 1521, and computing resource 1522. Memory manager 153 can be a separate chip outside chip 15, or a separate chip such as CPU 151. Figure 3 The module shown may be a module integrated in the chip 15 .

[0069] In some possible embodiments, the heterogeneous multi-core device 140 or the heterogeneous multi-core device 150 may be a separate chip or chip module outside the chips 14 and 15. That is, the heterogeneous multi-core device and the memory and the memory manager may not be in the same chip, so that the memory and the memory manager may be located on an additional chip. It should be understood that the number of chips in the processor 101 may be more or less, and the number of processor cores in the heterogeneous multi-core device 140 or the heterogeneous multi-core device 150 may be more or less, and the embodiments of the present application do not impose specific limitations.

[0070] The processor core in the processor 101 may run an operating system to implement various software functions of the processor 101. The operating system may run various applications and convert tasks generated by various applications into threads to be executed and assign them to the processor core for execution. The processor core running the operating system may be one or more processor cores in the processor 101. For example, the operating system may be run by any one of the processor cores 141, 142, 151, or 152. For another example, the operating system may run on the processor core 141 and the processor core 142 at the same time.

[0071] It should be understood that, with respect to the energy consumption and performance of the multiple processor cores in the heterogeneous multi-core device 140 or the heterogeneous multi-core device 150, the multiple processor cores in the heterogeneous multi-core device 140 or the heterogeneous multi-core device 150 may be divided into at least one of a high-performance core, an energy-efficient core, and a medium-performance core. Exemplarily, the structure of the heterogeneous multi-core device 140 may also be as follows: Figure 4A As shown, in Figure 4A In the embodiment, the heterogeneous multi-core device 140 includes a high-performance core 201 and an energy-efficiency core 202, thereby forming a large-core-large-core architecture. The high-performance core 201 includes at least one high-performance core, such as a high-performance core 2011 and a high-performance core 2012; the energy-efficiency core 202 includes at least one energy-efficiency core, such as an energy-efficiency core 2021 and an energy-efficiency core 2022. The maximum power consumption of any one of the at least one high-performance core is greater than the maximum power consumption of any one of the at least one energy-efficiency core, and the maximum computing power of any one of the at least one high-performance core is greater than the maximum computing power of any one of the at least one energy-efficiency core. In other words, the high-performance core has higher performance, while the energy-efficiency core has lower performance than the high-performance core but has higher energy efficiency. In this way, the characteristics of the high-performance core and the energy-efficiency core can be combined to allocate appropriate computing resources to the threads to be executed, so that the resource allocation of the threads to be executed is more flexible and the performance of the large-core-large-core is fully utilized.

[0072] Optionally, the heterogeneous multi-core device 140 may further include a medium-performance core 203, and the medium-performance core 203 includes at least one medium-performance core, for example, a medium-performance core 2031 and a medium-performance core 2032. The maximum power consumption of any one of the at least one high-performance cores is greater than the maximum power consumption of any one of the at least one medium-performance cores, and the maximum computing power of any one of the at least one high-performance cores is higher than the maximum computing power of any one of the at least one medium-performance cores; the maximum power consumption of any one of the at least one medium-performance cores is greater than the maximum power consumption of any one of the at least one energy-efficiency cores, and the maximum computing power of any one of the at least one medium-performance cores is higher than the maximum computing power of any one of the at least one energy-efficiency cores. In this way, by setting high-performance cores, energy-efficiency cores, and medium-performance cores in the heterogeneous multi-core device, resource allocation to threads is made more flexible, and the high-performance cores, energy-efficiency cores, and medium-performance cores can form a three-cluster architecture, which can better adapt to the diverse performance requirements of different threads.

[0073] In some embodiments, the high-performance core 201 may also be referred to as a large core, the medium-performance core 203 may also be referred to as a medium core, and the energy-efficiency core 202 may also be referred to as a small core. Figure 4B FIG. 1 shows a schematic diagram of a structure in which a heterogeneous multi-core device 140 includes a large core, a medium core, and a small core. Figure 4B In (a), the large core and the medium core in the heterogeneous multi-core device 140 support SMT, but the small core does not support SMT; Figure 4B In (b), the small cores in the heterogeneous multi-core device 140 support SMT, while the large cores and the medium cores do not support SMT; Figure 4B In (c), the small core, the large core, and the medium core in the heterogeneous multi-core device 140 all support SMT. It can be seen that there are multiple implementations of the heterogeneous multi-core device 140 when it is used to implement the SMT mode.

[0074] like Figure 4C As shown, one or more cores in the heterogeneous multi-core device 140 may also include Figure 4C The scheduling device 220 shown in the figure includes a scheduling unit 221 and an execution unit 222. The scheduling unit 221 and the execution unit 222 can be implemented by software or by a combination of hardware and software. The relevant software can include software computer instructions running on one or more cores of the heterogeneous multi-core device. The two methods are introduced below.

[0075] 1. Software method

[0076] Specifically, the scheduling unit 221 may be implemented by a scheduling algorithm executed by the first core in the heterogeneous multi-core device 140, and may include software computer instructions corresponding to the first core. The execution unit 222 may be implemented by pipeline micro-architecture software executed by the second core in the heterogeneous multi-core device 140, and the pipeline micro-architecture software may include software computer instructions corresponding to the second core.

[0077] 2. Combination of hardware and software

[0078] Specifically, the scheduling unit 221 can be implemented by running the corresponding software through the first core in the heterogeneous multi-core device 140, that is, it includes a combination of the first core and the corresponding software. The execution unit 222 can be implemented by running the corresponding software through the second core in the heterogeneous multi-core device 140, that is, it includes a combination of the second core and the corresponding software.

[0079] In combination with the computing device 100 and the heterogeneous multi-core device 140, the present application embodiment provides a scheduling method to improve the utilization of computing resources in the heterogeneous multi-core device, thereby improving the peak computing power of the heterogeneous multi-core device. Figure 5 The scheduling method provided in the embodiment of the present application is described.

[0080] Figure 5 is one of the flowcharts of a scheduling method provided in an embodiment of the present application. The method can be implemented by an operating system or other types of driver software or application software and by a processor core (e.g. Figure 3 The processor core 141 in the processor core 141 is executed. Figure 5 In the embodiment of the present application, the first core and the second core in the heterogeneous multi-core device 140 are taken as examples to introduce the scheduling scheme provided by the embodiment of the present application. The first core can be any one of the high-performance cores, medium-performance cores, or energy-efficient cores in the heterogeneous multi-core device 140, and the second core can be the first core or another core different from the first core in the heterogeneous multi-core device 140, and the other core can also be any one of the high-performance cores, medium-performance cores, or energy-efficient cores. The scheduling method includes:

[0081] S501: A first core allocates a first computing resource to a first thread, wherein the first thread may include one or more threads.

[0082] S502: The first core allocates a second computing resource to a second thread, wherein the second thread may include one or more threads.

[0083] In the embodiment of the present application, when the first core runs an operating system, the first thread and the second thread may be multiple threads created by the operating system. The first thread and the second thread may be threads corresponding to the same task of the same application, or the first thread and the second thread may be threads corresponding to different tasks of the same application, or the first thread and the second thread may be threads corresponding to different applications.

[0084] In a possible implementation, the first core may allocate a first computing resource to the first thread on the second core according to the performance requirements of the first thread, and allocate a second computing resource to the second thread on the second core according to the performance requirements of the second thread. In this way, by combining the performance requirements of each thread, computing resources are flexibly allocated to each thread, rather than configuring fixed resources for each thread, so as to adapt to the diverse needs of different threads. Optionally, the performance requirements of the first thread are characterized by at least one of the delay sensitivity, business scenario, or user experience of the first thread, and the performance requirements of the second thread are characterized by at least one of the delay sensitivity, business scenario, or user experience of the second thread. In general, when the performance requirements of multiple threads are higher, such as low latency, high computing speed or high computing power, it is necessary to select a core with higher performance from the multiple cores and allocate computing resources to the multiple threads on the core. The performance of the selected core matches the performance requirements of the multiple threads, that is, it can meet the performance requirements of the multiple threads and there will be no performance waste caused by excess performance. For example, when multiple threads need to be executed, the first core selects a suitable core, namely the second core, from the multiple cores, and uses the computing resources of the selected core to serve the multiple threads to implement the SMT mode. The selected core may be the first core itself or another core, which is not limited in this embodiment. When the first core determines that the performance requirements of the multiple threads are relatively low, the selected core is an energy-efficient core with lower performance to reduce power consumption; when the first core determines that the performance requirements of the multiple threads are medium, the selected core is a medium-performance core with medium performance to achieve a compromise between performance and power consumption; when the first core determines that the performance requirements of the multiple threads are high, the selected core is a high-performance core to give priority to meeting the performance requirements. After determining the selected second core, the first core further allocates first computing resources and second computing resources to the first thread and the second thread on the second core according to the performance requirements of the first thread and the performance requirements of the second thread, respectively, to meet the specific requirements of each thread itself.

[0085] As can be seen from the foregoing description, there are certain differences in the computing power and power consumption of the high-performance cores, medium-performance cores, and energy-efficiency cores in the heterogeneous multi-core device 140. Among them, the maximum computing power of the high-performance core is higher than the maximum computing power of the medium-performance core, and the maximum computing power of the medium-performance core is higher than the maximum computing power of the energy-efficiency core; the maximum power consumption of the high-performance core is less than the maximum power consumption of the medium-performance core, and the maximum power consumption of the medium-performance core is less than the maximum power consumption of the energy-efficiency core. Therefore, the first core can allocate computing resources to the first thread in combination with the performance requirements of the first thread and the characteristics of the high-performance cores, medium-performance cores, and energy-efficiency cores in the heterogeneous multi-core device 140; similarly, the first core can allocate computing resources to the second thread in combination with the performance requirements of the second thread and the characteristics of the high-performance cores, medium-performance cores, and energy-efficiency cores in the heterogeneous multi-core device 140. In this way, the performance requirements of the first thread and the performance requirements of the second thread are adapted to the resources of various types of cores in the heterogeneous multi-core device 140, which can effectively improve the resource utilization of the heterogeneous multi-core device 140.

[0086] For example, if the delay sensitivity of the first thread is high, the first core can allocate the computing resources of the high-performance core (i.e., large core) to the first thread, so that the first thread can be executed quickly, effectively reducing the execution time of the first thread, and thus effectively meeting the delay sensitivity of the first thread. Correspondingly, if the delay sensitivity of the second thread is low, the first core can allocate the computing resources of the medium-performance core (i.e., medium core) or the energy-efficiency core (i.e., small core) to the second thread. Since the power consumption of the medium-performance core (i.e., medium core) or the energy-efficiency core (i.e., small core) is low, using the computing resources of the medium-performance core (i.e., medium core) or the energy-efficiency core (i.e., small core) to execute the second thread can effectively reduce the power consumption generated when the second thread is executed.

[0087] For another example, if the business scenario of the first thread is a call scenario, and the business scenario of the second thread is an application update scenario, and the real-time requirement of the business scenario of the first thread is higher than that of the business scenario of the second thread, then the first core can allocate the computing resources of the high-performance core (i.e., large core) to the first thread, and allocate the computing resources of the medium-performance core (i.e., medium core) or the energy-efficient core (i.e., small core) to the second thread. In this way, the first thread can be executed quickly, effectively meeting the real-time requirement of the business scenario of the first thread; and the power consumption generated when the second thread is executed can be effectively reduced while meeting the real-time requirement of the business scenario of the second thread.

[0088] For another example, if the first thread is a thread for a game application and the second thread is a thread for a system update, and the user experience requirement of the first thread is higher than that of the second thread, the first core can allocate computing resources of a high-performance core (i.e., a large core) to the first thread, and allocate computing resources of a medium-performance core (i.e., a medium core) or an energy-efficient core (i.e., a small core) to the second thread. In this way, the first thread can be executed quickly, effectively meeting the user experience requirement of the first thread; and the power consumption generated when the second thread is executed can be effectively reduced while meeting the user experience requirement of the second thread.

[0089] like Figure 6 As shown in FIG. 1 , in some possible implementations, the computing resources of the high-performance core (i.e., the big core (b-core)), the medium-performance core (i.e., the medium core (m-core)), and the energy-efficient core (i.e., the small core (s-core)) can be represented by the dimensionless value of the central processing unit capacity (CPUcapacity). The CPU capacity of the big core is 12, the CPU capacity of the medium core is 8, and the CPUcapacity of the small core is 4. Furthermore, the first core can flexibly allocate the computing resources of the big core, the medium core, and the small core to form Figure 6 The CPU capacity shown in the figure is a computing resource of 1-12, so that the heterogeneous multi-core device can provide a variety of computing power supply capabilities, thereby meeting the computing power requirements of various threads.

[0090] Accordingly, the first core can be based on Figure 6 The table shown allocates computing resources to the first thread or the second thread.

[0091] For example, if the CPU capacity corresponding to the performance requirement of the first thread is 12, then the first computing resource allocated by the first core to the first thread is all the computing resources of a large core.

[0092] For another example, the CPU capacity corresponding to the performance requirement of the first thread is 11, the CPU capacity corresponding to the performance requirement of the second thread is 1, the first computing resource allocated by the first core to the first thread is 11 / 12 of the computing resources of a large core, and the first computing resource allocated by the first core to the second thread is 1 / 12 of the computing resources of a large core.

[0093] For another example, the CPU capacity corresponding to the performance requirement of the first thread is 10, the CPU capacity corresponding to the performance requirement of the second thread is 2, the first computing resource allocated by the first core to the first thread is the computing resource of 10 / 12 of a large core, and the first computing resource allocated by the first core to the second thread is the computing resource of 2 / 12 of a large core.

[0094] For another example, the CPU capacity corresponding to the performance requirement of the first thread is 9, the CPU capacity corresponding to the performance requirement of the second thread is 3, the first computing resource allocated by the first core to the first thread is the computing resource of 9 / 12 of a large core, and the first computing resource allocated by the first core to the second thread is the computing resource of 3 / 12 of a large core.

[0095] For another example, the CPU capacity corresponding to the performance requirement of the first thread is 8, and the CPU capacity corresponding to the performance requirement of the second thread is 4. The first computing resources allocated by the first core to the first thread are all the computing resources of a medium core, and the second computing resources allocated by the first core to the second thread are all the computing resources of a small core. Alternatively, the first computing resources allocated by the first core to the first thread are the computing resources of 8 / 12 of a large core, and the second computing resources allocated by the first core to the second thread are the computing resources of 4 / 12 of a large core.

[0096] For another example, the CPU capacity corresponding to the performance requirement of the first thread is 7, and the CPU capacity corresponding to the performance requirement of the second thread is 5. The first computing resource allocated by the first core to the first thread is the computing resource of a large core 7 / 12, and the second computing resource allocated by the first core to the second thread is the computing resource of a large core 5 / 12. Alternatively, the first computing resource allocated by the first core to the first thread is the computing resource of a medium core 7 / 8, and the second computing resource allocated by the first core to the second thread is the computing resource of a medium core 5 / 8.

[0097] For another example, the CPU capacity corresponding to the performance requirement of the first thread is 6, and the CPU capacity corresponding to the performance requirement of the second thread is 6. The first computing resource allocated by the first core to the first thread is a computing resource of 6 / 12 of a large core, and the second computing resource allocated by the first core to the second thread is a computing resource of 6 / 12 of a large core. Alternatively, the first computing resource allocated by the first core to the first thread is a computing resource of 6 / 8 of a medium core, and the second computing resource allocated by the first core to the second thread is a computing resource of 6 / 8 of a medium core.

[0098] For another example, the CPU capacity corresponding to the performance requirement of the first thread is 5, and the CPU capacity corresponding to the performance requirement of the second thread is 7. The first computing resource allocated by the first core to the first thread is the computing resource of 5 / 12 of a large core, and the second computing resource allocated by the first core to the second thread is the computing resource of 7 / 12 of a large core. Alternatively, the first computing resource allocated by the first core to the first thread is the computing resource of 5 / 8 of a medium core, and the second computing resource allocated by the first core to the second thread is the computing resource of 7 / 8 of a medium core.

[0099] For another example, the CPU capacity corresponding to the performance requirement of the first thread is 4, and the CPU capacity corresponding to the performance requirement of the second thread is 8. The first computing resource allocated by the first core to the first thread is the computing resource of a small core, and the second computing resource allocated by the first core to the second thread is the computing resource of a medium core. Alternatively, the first computing resource allocated by the first core to the first thread is the computing resource of 4 / 12 of a large core, and the second computing resource allocated by the first core to the second thread is the computing resource of 8 / 12 of a large core.

[0100] For another example, the CPU capacity corresponding to the performance requirement of the first thread is 3, and the CPU capacity corresponding to the performance requirement of the second thread is 9. The first computing resource allocated by the first core to the first thread is any one of 3 / 12 computing resources of a large core, 3 / 8 computing resources of a medium core, and 3 / 4 computing resources of a small core, and the second computing resource allocated by the first core to the second thread is 9 / 12 computing resources of a large core.

[0101] For another example, the CPU capacity corresponding to the performance requirement of the first thread is 2, and the CPU capacity corresponding to the performance requirement of the second thread is 10. The first computing resource allocated by the first core to the first thread can be any one of 2 / 12 computing resources of a large core, 2 / 8 computing resources of a medium core, and 2 / 4 computing resources of a small core, and the second computing resource allocated by the first core to the second thread is 10 / 12 computing resources of a large core.

[0102] For another example, the CPU capacity corresponding to the performance requirement of the first thread is 1, and the CPU capacity corresponding to the performance requirement of the second thread is 11. The first computing resource allocated by the first core to the first thread can be any one of 1 / 12 of the computing resources of a large core, 1 / 8 of the computing resources of a medium core, and 1 / 4 of the computing resources of a small core, and the second computing resource allocated by the first core to the second thread is 11 / 12 of the computing resources of a large core.

[0103] It should be understood that Figure 6The specific values ​​of the CPU capacities of the medium-large core, the medium core, and the small core are merely examples, and are not limitations on the CPU capacities of the medium-large core, the medium core, and the small core.

[0104] In an embodiment of the present application, the first computing resource includes a first dedicated computing resource, the second computing resource includes a second dedicated computing resource, and the first dedicated computing resource is different from the second dedicated computing resource. In this way, different dedicated computing resources are allocated to the first thread and the second thread, so that the first thread and the second thread do not interfere with each other when they are executed by the second core. Among them, the first dedicated computing resource and the second dedicated computing resource are both hardware resources of the second core, but the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the second core.

[0105] The hardware resources of the second core include various hardware units in the pipeline architecture of the second core executing multiple threads in parallel. Figure 7 A pipeline architecture for executing multiple threads in parallel on a second core, the architecture comprising an instruction translation lookaside buffer (ITLB), a data translation lookaside buffer (DTLB), an instruction cache (ICache), a data cache (DCache), a branch target buffer (BTB), a register rename table (RRT), a reorder buffer (ROB), and a physical register file (PRF). Among them, ITLB is used to cache the conversion relationship between the virtual address and the physical address of the instruction, DTLB is used to cache the conversion relationship between the virtual address and the physical address of the data, ICache is used to cache instructions, DCache is used to cache recently used data, BTB is used to save the address of the branch instruction that successfully branches and its branch target address in a buffer, and the buffer uses the address of the branch instruction as an identifier; RRT is used to implement register renaming, which is used to rename the source register and target register (i.e., virtual register) in the instruction to the corresponding physical register; ROB is used to store the results of instructions and the execution order information of instructions to implement out-of-order execution of instructions and ensure the correctness of instructions. PRF is used for register allocation, register renaming, and operand tracking. Therefore, Figure 7Taking the hardware unit corresponding to the pipeline architecture in as an example, the hardware resources of the second core include ITLB, ICache, BTB, RRT, PRF, DTLB, and DCache; accordingly, the first dedicated computing resources or the second dedicated computing resources may include at least one of the following: ITLB, ICache, BTB, RRT, PRF, DTLB, or DCache.

[0106] Optionally, the first core may allocate computing resources to the first thread and the second thread in combination with the priorities of the first thread and the second thread. For example, when the priority of the first thread is higher than the priority of the second thread, the proportion of the first dedicated computing resources in the hardware resources of the second core is higher than the proportion of the second dedicated computing resources in the hardware resources of the second core. The priority of the first thread or the priority of the second thread may be characterized by at least one of delay sensitivity, business scenario, or user experience.

[0107] For example, the first thread is a thread for a calling application, the second thread is a thread for a reading application, and the delay sensitivity of the first thread is higher than that of the second thread, then the priority of the first thread is higher than that of the second thread; accordingly, the first dedicated computing resources are 70% of the resources in the ITLB and 70% of the resources in the DTLB, and the second dedicated computing resources are 30% of the resources in the ITLB and 30% of the resources in the DTLB.

[0108] For another example, the business scenario of the first thread is a call scenario, and the business scenario of the second thread is an application update scenario. The real-time requirement of the business scenario of the first thread is higher than the real-time requirement of the business scenario of the second thread, then the priority of the first thread is higher than the priority of the second thread; accordingly, the first dedicated computing resources include 60% of the resources in ITLB, 60% of the resources in DTLB, 60% of the resources in ICache, and 60% of the resources in DCache, and the second dedicated computing resources include 40% of the resources in ITLB, 40% of the resources in DTLB, 40% of the resources in ICache, and 40% of the resources in DCache.

[0109] For another example, the first thread is a thread for a gaming application, the second thread is a thread for a system update, and the user experience requirement of the first thread is higher than that of the second thread, then the priority of the first thread is higher than that of the second thread; accordingly, the first dedicated computing resources include 80% of the resources in the ITLB, 80% of the resources in the DTLB, 80% of the resources in the ICache, and 80% of the resources in the DCache, and the second dedicated computing resources include 20% of the resources in the ITLB, 20% of the resources in the DTLB, 20% of the resources in the ICache, and 20% of the resources in the DCache.

[0110] S503: The second core executes the first thread and the second thread in parallel. In S503, the second core uses the first computing resource to execute the first thread, and uses the second computing resource to execute the second thread.

[0111] In S503, the second core executes the first thread and the second thread in parallel, which can effectively improve the utilization rate of computing resources in the heterogeneous multi-core device, thereby effectively improving the peak computing power of the heterogeneous multi-core device.

[0112] As can be seen from the foregoing description, the first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource. Accordingly, the second core uses the first dedicated computing resource and executes the first thread, and the second core uses the second dedicated computing resource to execute the second thread.

[0113] Furthermore, the first computing resource and the second computing resource may also include a shared computing resource, which is a hardware resource of the second core. Accordingly, the second core uses the first dedicated computing resource and the shared computing resource to execute the first thread, and the second core uses the second dedicated computing resource and the shared computing resource to execute the second thread. The second core may time-share the shared computing resource when executing the first thread and the second thread in parallel.

[0114] Optionally, when the priority of the first thread is higher than the priority of the second thread, the time when the first thread uses the shared computing resources takes precedence over the time when the second thread uses the shared computing resources, that is, the time when the second core uses the shared computing resources to execute the first thread takes precedence over the time when the second core uses the shared computing resources to execute the second thread. Also, when the priority of the first thread and the priority of the second thread are the same, the embodiment of the present application does not restrict the time when the second core uses the shared computing resources to execute the first thread and the time when the second core uses the shared computing resources to execute the second thread.

[0115] Please continue to see Figure 7 , when the hardware resources of the second core include ITLB, ICache, BTB, RRT, PRF, DTLB, and DCache, the shared computing resources may include at least one of ITLB, ICache, BTB, RRT, PRF, DTLB, or DCache.

[0116] For example, if the shared computing resources include ICache, BTB, RRT, PRF, and DCache, the second core can execute the first thread and the second thread in parallel by time-sharing multiplexing ICache, BTB, RRT, PRF, and DCache; and when the priority of the first thread is higher than the priority of the second thread, the time when the second core uses ICache to execute the first thread takes precedence over the time when the second core uses ICache to execute the second thread, the time when the second core uses BTB to execute the first thread takes precedence over the time when the second core uses BTB to execute the second thread, the time when the second core uses RRT to execute the first thread takes precedence over the time when the second core uses RRT to execute the second thread, the time when the second core uses PRF to execute the first thread takes precedence over the time when the second core uses PRF to execute the second thread, and the time when the second core uses DCache to execute the first thread takes precedence over the time when the second core uses DCache to execute the second thread.

[0117] For another example, if the shared computing resources include BTB, RRT, and PRF, the second core can execute the first thread and the second thread in parallel by time-sharing multiplexing BTB, RRT, and PRF; and when the priority of the first thread is higher than the priority of the second thread, the time when the second core uses BTB to execute the first thread takes precedence over the time when the second core uses BTB to execute the second thread, the time when the second core uses RRT to execute the first thread takes precedence over the time when the second core uses RRT to execute the second thread, and the time when the second core uses PRF to execute the first thread takes precedence over the time when the second core uses PRF to execute the second thread.

[0118] For another example, the shared computing resources include RRT and PRF, and the second core executes the first thread and the second thread in parallel by time-sharing multiplexing RRT and PRF; the priority of the first thread is the same as the priority of the second thread, and the time when the second core uses RRT to execute the first thread can be earlier or later than the time when the second core uses RRT to execute the second thread, and the time when the second core uses PRF to execute the first thread is earlier or later than the time when the second core uses PRF to execute the second thread.

[0119] In the embodiment of the present application, the basic unit of the second core execution program is a thread, and a thread can be regarded as an independent execution sequence, which contains a series of instructions that need to be executed on the second core. As the basic unit of the operation to be performed on the processor, the instruction is a machine code represented by binary, which is used to indicate the specific operation to be performed by the second core, such as addition, multiplication, memory reading and writing, etc. The instruction usually includes an opcode (used to specify the type of operation) and an operand (used to specify the source and target of the operation). Accordingly, when the second core executes multiple threads in parallel, the second core can execute multiple instructions of multiple threads in parallel. In the second core, a series of instructions can be generated for each thread to be executed, and a series of instructions of the thread are sent to the instruction pipeline of the second core for execution. The instruction pipeline includes multiple processing stages, and each stage executes a specific operation of the instruction (such as fetching, decoding, execution, memory access and write back, etc.). In the second core that supports multi-threading, the thread scheduler can select instructions of multiple threads to alternately execute the processing stages of different threads, that is, execute instructions of different threads in different clock cycles.

[0120] Please continue to see Figure 7 ,exist Figure 7 The first thread is thread 1, and the second thread is thread 2. Figure 7 , from the perspective of instruction execution of thread 1 and thread 2, the specific process of how the second core can execute the first thread and the second thread in parallel is introduced, and the process includes:

[0121] (1) Instruction fetch:

[0122] In the instruction fetching stage, the second core is responsible for obtaining the instructions of thread 1 and thread 2, and caching the instructions of thread 1 and thread 2 in the ITLB. Also, in the instruction fetching stage, the second core can predict the target addresses of the branch instructions of thread 1 and thread 2 through the branch predictor, and save the address of the branch instruction that successfully branches and its branch target address in a buffer through the BTB. The buffer uses the address of the branch instruction as an identifier to retrieve the instructions of the correct branch path.

[0123] Among them, the second core can combine the priorities of thread 1 and thread 2 to implement the instruction fetching stage of thread 1 and thread 2. For example, if the priority of thread 1 is higher than that of thread 2, the second core will first obtain the instructions of thread 1 from the memory, and then obtain the instructions of thread 2 from the memory after the instructions of thread 1 are obtained; or, the second core will first obtain the instructions of thread 1 from the memory, and only when the instructions of thread 1 cannot be fetched from the memory, will the second core obtain the instructions of thread 2 from the memory. For another example, if the priority of thread 1 is the same as that of thread 2, the second core will take turns to obtain the instructions of thread 1 and thread 2 from the memory.

[0124] (2)Decoding and renaming (instruction decode and register renaming):

[0125] In the decoding stage, the second core can decode the instructions of thread 1 and thread 2 and convert them into internal control signals and operands. In addition, the decoding stage also includes a register renaming stage. In the register renaming stage, RRT can avoid the data dependency between the instructions of thread 1 and thread 2 by renaming the source registers and target registers (i.e., virtual registers) in the instructions of thread 1 and thread 2 into corresponding physical registers, thereby improving instruction-level parallelism.

[0126] In the decoding stage and the renaming stage, in the case of out-of-order execution, the instructions of thread 1 and the instructions of thread 2 may enter the ROB in any order, and the results are submitted in the order of the original instruction sequence after completion of execution.

[0127] (3) dispatch:

[0128] In the dispatch phase, the second core is responsible for dispatching the instructions obtained after decoding the instructions of thread 1 and thread 2 to the execution unit (EU) for execution. EU contains various functional units, such as arithmetic logic unit (ALU), floating point unit (FPU), etc. Correspondingly, EU can perform arithmetic operations, logical operations, displacement operations, etc. corresponding to various instructions. When the second core executes multiple threads in parallel, each thread can use EU independently to achieve instruction-level parallel processing. For example, the instructions of thread 1 are executed through EU0, and the instructions of thread 2 are executed through EU1.

[0129] Also, in the dispatch phase, the second core will process the memory access instructions (i.e., load instructions and store instructions) of thread 1 and thread 2 through the load-store unit (LSU), implement the read and write operations between the second core and the memory, and be responsible for processing the transmission and caching of the data related to thread 1 and thread 2. Among them, when the load instruction executed by the LSU needs to access the memory, it will use DTLB to perform address translation, convert the virtual address into the corresponding physical address, and then access it in the physical address space. Since Dcache stores the most recently used data, when the load instruction executed by the LSU needs to read data, it will first look for the required data in Dcache. If the data is in Dcache, LSU can directly obtain the data from Dcache, thereby avoiding the delay of accessing the main memory. If the data is not in Dcache, LSU will obtain the data from the main memory and load the data into Dcache for subsequent access. In addition, LSU maintains the store queue (SQ) and load queue (LQ), which can effectively manage the execution order of store instructions and load instructions, effectively improve instruction-level parallelism and memory access efficiency, and thus improve processor performance. Among them, the role of SQ is to process store instructions. SQ will track the target address and data to be written for each store instruction, and maintain the execution order of store instructions. SQ will also check the data dependency between store instructions to ensure that the previous load instruction is completed before the store instruction to avoid data competition and memory consistency problems; the role of LQ is to process load instructions. LQ will track the target address of each load instruction, maintain the execution order of load instructions, and check the data dependency between load instructions and store instructions to ensure that load instructions are executed only after the corresponding store instructions are completed to ensure that the correct data is read. When the second core executes multiple threads in parallel, each thread can use LSU independently to achieve independent access to memory. For example, the instructions of thread 1 are executed through LSU0, and the instructions of thread 2 are executed through LSU2.

[0130] Among them, the second core can combine the priorities of thread 1 and thread 2 to implement the dispatch stage of the priorities of thread 1 and thread 2. For example, if the priority of thread 1 is higher than that of thread 2, the second core will preferentially dispatch the instructions of thread 1 to LSU0, and after the instructions of thread 1 are dispatched, the instructions of thread 2 will be dispatched to LSU1; or, the second core will preferentially dispatch the instructions of thread 1 to LSU0, and when the waiting time of the access instruction of thread 1 in SQ is greater than the preset threshold, the second core will dispatch the instructions of thread 2 to LSU1. For another example, if the priority of thread 1 is the same as that of thread 2, the second core will dispatch the instructions of thread 1 to LSU0 and the instructions of thread 2 to LSU1 in turn.

[0131] Also, in the dispatch stage, each instruction of thread 1 and thread 2 needs to be assigned a set of physical registers to store operands and results. At this time, PRF will maintain a pool of available physical registers and assign these physical registers to instructions. Also, PRF can use register renaming technology to rename logical registers to physical registers, which can avoid data dependencies between the instructions of thread 1 and thread 2, so that the instructions of thread 1 and thread 2 can be executed in parallel. In addition, PRF can track the physical registers used by the instructions of thread 1 and thread 2 as operands, so as to ensure that the operands of the instructions of thread 1 and thread 2 are accurate and consistent with the previous instruction execution results.

[0132] (4) Retire:

[0133] In the retirement phase, the instructions executed by thread 1 and thread 2 are marked as committed and written to the status register or update the relevant data in the memory. If an exception or interrupt occurs during the execution, the retirement phase is responsible for handling these exceptions. It ensures that the exception handler is executed correctly and aborts or restarts the pipeline when necessary. And, even if out-of-order execution occurs in the pipeline, the retirement phase ensures that the results of the instructions are correctly committed according to the original order of the program.

[0134] The "memory" involved in the above process can be understood as the memory in the chip integrated in the heterogeneous multi-core device where the second core is located, for example, Figure 3 In some possible embodiments, the heterogeneous multi-core device 140 further includes a third core, which is another core not used for the second core. The other core may be any one of a high-performance core, a medium-performance core, or an energy-efficient core in the heterogeneous multi-core device 140. The third core also supports the SMT mode. Figure 8 As shown in (a), when the second core is executing thread 1, the third core is executing thread 3; Figure 8As shown in (b), if thread 1 causes a blockage in the front end of the pipeline of the second core, and thread 3 causes a blockage in the back end of the pipeline of the third core, the second core can schedule thread 3 to execute on the second core, that is, the second core executes thread 1 and thread 3 in parallel; or, the second core can schedule thread 1 to execute on the third core, that is, the third core executes thread 1 and thread 3 in parallel. Wherein, thread 1 causes a blockage in the front end of the pipeline of the second core, including but not limited to the following situations: in the value acquisition stage, the instruction of thread 1 cannot be taken out from the memory, or the instructions cached in the ITLB have reached the upper limit, and the instruction of thread 1 cannot be put into the ITLB; in the decoding stage, an error occurs in decoding the instruction of thread 1. And, thread 3 causes a blockage in the back end of the pipeline of the third core, including but not limited to the following situations: the waiting time of the access instruction of thread 3 in the SQ is greater than the first preset value, or the waiting time of the load instruction of thread 3 in the LQ is greater than the second preset value, or the third core cannot access the data related to thread 3 from the DCache. In this way, by combining the execution status of thread 1 and thread 3, thread 1 and thread 3 are scheduled to be executed on the same core, which can further improve the resource utilization and system performance of the heterogeneous multi-core device 140.

[0135] In some possible embodiments, the second core supports SMT mode and ST mode, and the second core can control the second core to switch between SMT mode and ST mode according to the number of threads currently running in the operating system. For example, the second core takes the large core and the medium core as examples, and the threads currently running in the operating system include thread 1, thread 2, thread 3, and thread 4, then the large core runs in SMT mode, so that the large core can execute thread 1 and thread 2 in parallel; and the medium core runs in SMT mode, so that the medium core can execute thread 3 and thread 4 in parallel. For another example, the second core takes the large core as an example, and the threads currently running in the operating system include thread 1 and thread 2, then the large core runs in SMT mode, so that the large core can execute thread 1 and thread 2 in parallel. For another example, the second core takes the large core and the medium core as examples, and the threads currently running in the operating system include thread 1 and thread 2, then the large core runs in ST mode, so that the large core executes thread 1; and the medium core runs in ST mode, so that the medium core executes thread 2. For another example, the second core is a large core, and the threads currently running in the operating system include thread 1, then the large core runs in ST mode, so that the large core executes thread 1. In this way, when the number of threads currently running in the operating system is small, the second core can be controlled to run in ST mode, which can effectively reduce the power consumption of the second core.

[0136] As can be seen from the previous description, REE refers to the ordinary execution environment, including the operating system and user space applications. In the ARM architecture, exception levels (EL) 0, EL1, EL2 and EL3 are defined. Each exception level has different permissions and functions to support different operations and tasks. Among them, EL0 is called the unprivileged exception level, corresponding to ordinary user space applications. EL1 is the privilege level of the operating system kernel. At the EL1 level, the operating system kernel can directly access hardware resources and manage and schedule EL0 level applications. EL2 is the virtualization privilege level. At the EL2 level, a virtualization hypervisor can be run to support virtualization technology, such as running virtual machines on the ARM architecture. EL3 is the highest privilege level, also known as the secure monitor mode, and is the only exception level that has the ability to switch between secure execution state and non-secure execution state.

[0137] And, as can be seen from the above description, TEE refers to the trusted execution environment corresponding to REE, which is used to process security-sensitive tasks and data. TEE and REE can run in two different security domains, that is, TEE corresponds to the secure world and REE corresponds to the non-secure world. Correspondingly, in the ARM architecture, the secure exception level 0 (secure EL0, S-EL0), S-EL1, S-EL2, and S-EL3 in the secure world are defined for TEE. Among them, S-EL0 is the lowest privilege level of TEE. At the SEL0 level, TEE can execute ordinary user space tasks in the secure domain and has certain privileges to process security-sensitive operations and data. S-EL1 is the TEE privilege level. At the S-EL1 level, TEE can execute kernel-level tasks in the secure domain and has a higher privilege level for managing and protecting operations and resources inside the TEE. S-EL2 is the virtualization privilege level of TEE. At the S-EL2 level, a virtualization supervisor can be run to support virtualization technology, such as running virtual machines in the secure domain. S-EL3 is the highest privilege level of TEE, which can run also known as the security supervisor. It is the only exception level that has the ability to switch between secure execution state and non-secure execution state.

[0138] Fig. 9 This is a schematic diagram of a scenario in which the second core runs two computing resources in an embodiment of the present application. Fig. 9In the example, the second core includes computing resources 1 and computing resources 2, which can also be called hardware threads (also called logical threads). The second core uses computing resources 1 to execute the first thread, and the second core uses computing resources 2 to execute the second thread. Both computing resources 1 and computing resources 2 have REE mode and TEE mode.

[0139] exist Fig. 9 In the REE mode, EL1 and EL2 are included. EL1 is used to run the REE operating system (OS) (such as Linux), and EL2 is used to run a virtualization supervisor. The TEE mode includes S-EL1, S-EL2, and S-EL3. The TEE OS and secure partition (SP) run in S-EL1, S-EL2 is used to run a virtualization supervisor, and the security monitor runs in S-EL3. Among them, SP is used to provide hardware-level security isolation and protection. The security monitor is used to realize the switching between REE mode and TEE mode.

[0140] If the first thread and the second thread are both threads corresponding to tasks in REE mode, when the second core executes the first thread and the second thread in parallel, one of the threads triggers the CA / TA process, and the computing resource corresponding to the thread enters TEE mode. At this time, the second core will execute TEE mode and REE mode at the same time. For example, when the first thread triggers the CA / TA process, computing resource 1 will enter TEE mode, and computing resource 2 corresponding to the second thread will still remain in REE mode. At this time, the second core will run both REE mode and TEE mode (such as Fig.10 As shown), the data in TEE mode is at risk of illegal access such as side-channel detection. Among them, the CA / TA process includes: CA registers the corresponding TA in TEE. A secure communication channel is established between CA and TEE to interact securely with TA. CA sends a request to TEE to start the corresponding TA. The request includes the identifier of the TA to be started and the required parameters. TEE verifies the identifier of the TA in the request and ensures the integrity and authenticity of the TA. If the verification is successful, TEE loads the TA and transfers control to the execution environment of the TA. The TEE performs its specific security functions and operations. The TA can use the security API provided by the TEE to perform security operations such as key generation, encryption and decryption, and digital signatures. The TA returns the results to the CA for subsequent processing by the CA. After the TA completes a specific operation, the CA can request to terminate and uninstall the TA.

[0141] As can be seen from the above, there is a security risk when the first thread and the second thread are executed in environments with different security levels. Therefore, in the embodiment of the present application, the same security level can be set for the first thread and the second thread, so that the first thread and the second thread can run in an environment with the same security level, thereby preventing the security risks caused by the first thread and the second thread being executed in environments with different security levels. For example, the security levels of the first thread and the second thread can be set to TEE mode.

[0142] Since the second core uses computing resource 1 to execute the first thread, and the second core uses computing resource 2 to execute the second thread, the security levels of computing resource 1 and computing resource 2 can be adjusted so that the security levels of the first thread and the second thread are both in TEE mode. Fig. 9 , the process of adjusting the security level of computing resource 1 and computing resource 2 includes:

[0143] Step ①, computing resource 1 switches from REE mode to TEE mode.

[0144] Specifically, computing resource 1 is switched from EL1 in REE mode to S-EL2 in TEE mode, that is, computing resource 1 is moved from the non-secure world to the secure world. In this way, computing resource 1 can run in TEE.

[0145] Step ②, computing resource 1 triggers the process interruption of computing resource 2.

[0146] Specifically, the second core can trigger an inter-processor interrupt (IPI) of the scheduler in the second core before computing resource 1 enters TEE mode according to the topological structure of the multi processor identity register (MPIDR), trigger computing resource 2 to schedule out the second thread being executed thereon, and power off computing resource 2. When computing resource 1 enters TEEOS through S-EL2, the status of computing resource 2 is checked. If computing resource 2 is still not powered off, a fast interrupt request (FIQ) is configured for computing resource 2 to interrupt computing resource 2 from EL1 in REE mode.

[0147] Among them, MPIDR usually contains information such as processor number, cluster number and layer number, which can help operating systems and software effectively manage and schedule tasks of multi-core processors.

[0148] Step ③, computing resource 2 switches from REE mode to TEE mode.

[0149] Specifically, computing resource 2 is switched from EL1 in REE mode to S-EL2 in TEE mode, that is, computing resource 2 is moved from the non-secure world to the secure world. In this way, computing resource 2 can run in TEE.

[0150] Step ④: Computing resource 1 and computing resource 2 run in TEE OS.

[0151] Specifically, after computing resource 1 enters S-EL2 in TEE mode from EL1 in REE mode, it enters TEE OS from S-EL2 in TEE mode and runs computing resource 1 in TEE OS. At this time, the second core uses computing resource 1 to execute the first thread, and the security level of the first thread is TEE mode. Similarly, computing resource 2 has either been powered off or has been forced to wait in TEE state after entering S-EL2 in TEE mode from EL1 in REE mode. If the power-on process of computing resource 2 is triggered in the middle, it will also trigger computing resource 2 to be forced to wait in TEE state when the process passes through S-EL2. At this time, the second core uses computing resource 2 to execute the second thread, and the security level of the second thread is TEE mode.

[0152] Step ⑤, computing resource 1 and computing resource 2 switch from TEE mode to REE mode.

[0153] Specifically, after the second core uses computing resource 1 to execute the first thread, and uses computing resource 2 to execute the second thread, computing resource 1 and computing resource 2 synchronously exit from TEE mode to EL1 in REE mode.

[0154] In the above process, the second core can run computing resource 1 and computing resource 2 in TEE mode at the same time (such as Fig.11 As shown), the first thread executed by computing resource 1 and the second thread executed by computing resource 2 have the same security level (i.e., TEE mode), which can eliminate the security risks caused by the different security levels of the first thread and the second thread when the second core executes the first thread and the second thread in parallel.

[0155] According to the method provided in the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores a program code. When the program code runs on a computer, the computer executes the method of any one of the above method embodiments.

[0156] An embodiment of the present application also provides an electronic device, which is used to execute a method in any one of the above method embodiments.

[0157] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0158] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0159] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0160] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0161] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0162] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0163] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0164] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A heterogeneous multi-core device, characterized in that: The method comprises a plurality of cores, wherein the plurality of cores comprises at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core in the at least one high-performance core is greater than the maximum power consumption of any core in the at least one energy-efficiency core, and the maximum computing capability of any core in the at least one high-performance core is greater than the maximum computing capability of any core in the at least one energy-efficiency core; wherein: A first core among the multiple cores is used to allocate a first computing resource to a first thread and a second computing resource to a second thread, wherein the first computing resource and the second computing resource belong to a second core among the multiple cores, and the second core is the first core or another core different from the first core; The second core is used to execute the first thread and the second thread in parallel, wherein the first computing resource is used to execute the first thread, and the second computing resource is used to execute the second thread.

2. The device according to claim 1, characterized in that The multiple cores also include at least one medium-performance core, the maximum power consumption of any of the at least one high-performance core is greater than the maximum power consumption of any of the at least one medium-performance core, and the maximum computing capability of any of the at least one high-performance core is higher than the maximum computing capability of any of the at least one medium-performance core; the maximum power consumption of any of the at least one medium-performance core is greater than the maximum power consumption of any of the at least one energy-efficiency core, and the maximum computing capability of any of the at least one medium-performance core is higher than the maximum computing capability of any of the at least one energy-efficiency core.

3. The device according to claim 1 or 2, characterized in that The first core is specifically used for: Allocating the first computing resource to the first thread on the second core according to the performance requirement of the first thread; The second computing resource is allocated to the second thread on the second core according to the performance requirement of the second thread.

4. The device according to any one of claims 1 to 3, characterized in that: The first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource different from the first dedicated computing resource; the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the second core.

5. The device according to any one of claims 1 to 4, characterized in that: The first computing resource and the second computing resource include shared computing resources; the second core is further used to: execute the first thread and the second thread in parallel by time-sharing the shared computing resources; wherein the priority of the first thread is higher than the priority of the second thread; in the time-sharing, the time when the first thread uses the shared computing resources takes precedence over the time when the second thread uses the shared computing resources.

6. The device according to claim 5, characterized in that The shared computing resources include at least one of the following: Instruction translation bypass buffer ITLB, instruction cache memory ICache, branch target buffer BTB, register renaming table RRT, physical register file RPF, data translation bypass buffer DTLB, or cache memory DCache.

7. The device according to any one of claims 1 to 6, characterized in that: The second core is further used for: When the first thread causes a blockage in the pipeline front end of the second core and the third thread causes a blockage in the pipeline back end of the third core among the multiple cores, the third thread is scheduled to be executed on the second core, or the first thread is scheduled to be executed on the third core, wherein the third core is different from the second core.

8. The device according to any one of claims 1 to 7, characterized in that: The first thread and the second thread have the same security level.

9. The device according to claim 8, characterized in that The security level is Trusted Execution Environment (TEE) mode.

10. A scheduling method, characterized in that: The method comprises: Allocating a first computing resource to a first thread, and allocating a second computing resource to a second thread; wherein the first computing resource and the second computing resource belong to a first core or a second core among a plurality of cores included in a heterogeneous multi-core device; the plurality of cores include at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core in the at least one high-performance core is greater than the maximum power consumption of any core in the at least one energy-efficiency core, and the maximum computing capability of any core in the at least one high-performance core is greater than the maximum computing capability of any core in the at least one energy-efficiency core; The first thread and the second thread are executed in parallel, wherein the first computing resource is used to execute the first thread and the second computing resource is used to execute the second thread.

11. The method according to claim 10, characterized in that The multiple cores also include at least one medium-performance core, the maximum power consumption of any of the at least one high-performance core is greater than the maximum power consumption of any of the at least one medium-performance core, and the maximum computing capability of any of the at least one high-performance core is higher than the maximum computing capability of any of the at least one medium-performance core; the maximum power consumption of any of the at least one medium-performance core is greater than the maximum power consumption of any of the at least one energy-efficiency core, and the maximum computing capability of any of the at least one medium-performance core is higher than the maximum computing capability of any of the at least one energy-efficiency core.

12. The method according to claim 10 or 11, characterized in that Allocating the first computing resource to the first thread includes: allocating the first computing resource to the first thread on the second core according to the performance requirement of the first thread; The allocating the second computing resource to the second thread includes: allocating the second computing resource to the second thread on the second core according to the performance requirement of the second thread.

13. The method according to any one of claims 10 to 12, characterized in that: The first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource different from the first dedicated computing resource; the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the first core or the second core.

14. The method according to any one of claims 10 to 13, characterized in that: The first computing resource and the second computing resource include shared computing resources; the method further comprising: The first thread and the second thread are executed in parallel by time-sharing the shared computing resources; wherein the priority of the first thread is higher than the priority of the second thread; in the time-sharing, the time when the first thread uses the shared computing resources takes precedence over the time when the second thread uses the shared computing resources.

15. The method according to claim 14, characterized in that The shared computing resources include at least one of the following: Instruction translation bypass buffer ITLB, instruction cache memory ICache, branch target buffer BTB, register renaming table RRT, physical register file RPF, data translation bypass buffer DTLB, or cache memory DCache.

16. The method according to any one of claims 10 to 15, characterized in that: The method further comprises: When the first thread causes a blockage in the pipeline front end of the second core and the third thread causes a blockage in the pipeline back end of a third core among the multiple cores, the third thread is scheduled to be executed on the second core, or the first thread is scheduled to be executed on the third core, wherein the third core is different from the second core.

17. The method according to any one of claims 10 to 16, characterized in that: The first thread and the second thread have the same security level.

18. The method according to claim 17, characterized in that The security level is Trusted Execution Environment (TEE) mode.

19. A scheduling device, characterized in that: include: A scheduling unit, configured to allocate a first computing resource to a first thread, and allocate a second computing resource to a second thread; wherein the first computing resource and the second computing resource belong to a first core or a second core among a plurality of cores included in a heterogeneous multi-core device; the plurality of cores include at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core in the at least one high-performance core is greater than the maximum power consumption of any core in the at least one energy-efficiency core, and the maximum computing capability of any core in the at least one high-performance core is greater than the maximum computing capability of any core in the at least one energy-efficiency core; An execution unit is used to execute the first thread and the second thread in parallel, wherein the first computing resource is used to execute the first thread and the second computing resource is used to execute the second thread.

20. The device according to claim 19, characterized in that The multiple cores also include at least one medium-performance core, the maximum power consumption of any of the at least one high-performance core is greater than the maximum power consumption of any of the at least one medium-performance core, and the maximum computing capability of any of the at least one high-performance core is higher than the maximum computing capability of any of the at least one medium-performance core; the maximum power consumption of any of the at least one medium-performance core is greater than the maximum power consumption of any of the at least one energy-efficiency core, and the maximum computing capability of any of the at least one medium-performance core is higher than the maximum computing capability of any of the at least one energy-efficiency core.

21. The device according to claim 19 or 20, characterized in that The scheduling unit is specifically used for: Allocating the first computing resource to the first thread on the second core according to the performance requirement of the first thread; The second computing resource is allocated to the second thread on the second core according to the performance requirement of the second thread.

22. The device according to any one of claims 19 to 21, characterized in that The first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource different from the first dedicated computing resource; the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the first core or the second core.

23. The device according to any one of claims 19 to 22, characterized in that The first computing resource and the second computing resource include shared computing resources; the execution unit is further used for: The first thread and the second thread are executed in parallel by time-sharing the shared computing resources; wherein the priority of the first thread is higher than the priority of the second thread; in the time-sharing, the time when the first thread uses the shared computing resources takes precedence over the time when the second thread uses the shared computing resources.

24. The device according to claim 23, characterized in that The shared computing resources include at least one of the following: Instruction translation bypass buffer ITLB, instruction cache memory ICache, branch target buffer BTB, register renaming table RRT, physical register file RPF, data translation bypass buffer DTLB, or cache memory DCache.

25. The device according to any one of claims 19 to 24, characterized in that The scheduling unit is also used for: When the first thread causes a blockage in the pipeline front end of the second core and the third thread causes a blockage in the pipeline back end of the third core among the multiple cores, the third thread is scheduled to be executed on the second core, or the first thread is scheduled to be executed on the third core, wherein the third core is different from the second core.

26. The device according to any one of claims 19 to 25, characterized in that The first thread and the second thread have the same security level.

27. The device according to claim 26, characterized in that The security level is Trusted Execution Environment (TEE) mode.

28. A computing device, characterized in that The computing device comprises a heterogeneous multi-core device as described in any one of claims 1-9 or any one of claims 19-27.

29. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes instructions, which, when executed on a computer, enable the computer to execute the operating steps of any one of the methods of claims 10 to 18.

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