Ras to trigger L2P table movement in CXL devices with compression

Abstract

The invention relates to a RAS triggering L2P table movement in a CXL device with compression. A system and method are provided in a central controller system for identifying and mitigating errors on a die containing task-critical logical-to-physical addressing information. The logical-to-physical L2P addressing information is crucial to translate a logical memory address of uncompressed data to a physical address of compressed data. When it is detected that a die containing L2P data is corrupted, the corrupted data is corrected, and all of the data is moved to uncorrupted dies having a specified offset relative to the original address of the die.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 517,333, filed on August 2, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The following generally relates to one or more systems for memory. In particular, it relates to error detection, correction, and maintaining critical logical-to-physical (L2P) addressing stored on dynamic random access memory (DRAM). Background Art

[0004] Memory devices (also referred to as storage media devices) are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to a logical 1 or a logical 0. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] Over time, memory cells may degrade, resulting in data corruption when data is read to or read back from the memory. To compensate for this degradation, memories such as DRAM may have reserved memory locations. When the DRAM is first shipped (when the DRAM is initially packaged), these reserved memory locations may be intentionally not utilized. Instead, these memory cells are reserved for so-called post-packaging repair. This means that during the life of the DRAM, when the original memory cells show signs of failure over time, the original memory cells can be replaced with reserved memory cells.

[0006] Application-specific integrated circuits (ASICs) can be designed and used for many different purposes in computers, mobile phones, and other digital systems and control systems. For example, an ASIC can regulate access to DRAM by a computer's central processing unit (CPU) or a cell phone's microprocessor. As another example, a Computer Express Link (CXL) ASIC can be used as a controller to regulate dynamic memory and integrate different digital memory circuits according to recently emerging hardware standards.

[0007] Data from the host system may also be compressed when stored in memory. When data is compressed, the logical memory addresses provided by the host system are translated into different physical memory addresses. The address mapping of logical addresses to physical addresses may be stored in an L2P table, which itself is stored in DRAM. If the die on which the L2P table is stored is damaged or corrupted, the correct memory mapping may still be restored by various error correction methods. However, it is preferred to store an uncorrupted version of the L2P table, which may require moving the corrected mapping data to a new die. Summary of the invention

[0008] One aspect of the present disclosure relates to a tangible, non-transitory computer-readable storage medium comprising instructions that, when executed by a processor of a memory system, cause the processor to perform a method comprising the steps of: reading a data value from a logical-to-physical (L2P) table, wherein the L2P table comprises a mapping from a logical memory address associated with a host system to a physical address in a compressed segment of the memory system; detecting an error in the read operation, the error indicating a failure of a memory die stored in the L2P table; when the error is detected, determining a correction for the error; and copying the L2P table from a current L2P table location to a new L2P table location.

[0009] In some embodiments, the computer-readable storage medium further comprises setting the offset to a value such that when the copy operation is complete, the current L2P table location plus the offset indicates the new L2P table location in the memory.

[0010] Another aspect of the disclosure relates to a memory system comprising: a central controller; a dynamic random access memory (DRAM) communicatively coupled to the central controller, the DRAM comprising a plurality of dies configured to store compressed data; and a logical to physical (L2P) table stored in the plurality of dies configured to store compressed data and comprising a mapping from a logical memory address associated with a host system to a physical address in a compressed section of the memory system. The controller is configured to: read a data value from the L2P table; detect an error in the read operation, the error indicating a failure of a memory die used to store the L2P table; when the error is detected, determine a correction for the error; and copy the L2P table from a current L2P table location to a new L2P table location.

[0011] In some embodiments, the central controller is further configured to set the offset to a value such that when the copy operation is complete, the current memory address plus the offset indicates the new L2P table location in memory.

[0012] In some embodiments, the central controller includes an error manager configured to replicate the L2P table.

[0013] In some embodiments, the error manager is further configured to set the offset to the value such that when the copy operation is complete, the current memory address plus the offset indicates the new L2P table location in memory.

[0014] Another aspect of the present disclosure relates to a method of copying a logical-to-physical (L2P) table to a new L2P table location, comprising: reading a data value from an L2P table, wherein the L2P table comprises a mapping from a logical memory address associated with a host system to a physical address in a compressed segment of the memory system; detecting an error in the read operation, the error indicating a failure of a memory die stored in the L2P table; and when the error is detected, determining a correction for the error; and copying the L2P table from a current L2P table location to a new L2P table location.

[0015] In some embodiments, the method further comprises determining the address of the L2P table by adding a current physical memory address and an offset memory address.

[0016] In some embodiments, the method further includes setting an initial value of the offset memory address to zero.

[0017] In some embodiments, the method further comprises determining whether copying the L2P table from the current L2P table location to the new L2P table location is complete.

[0018] In some embodiments, the method further comprises setting the offset to a value such that when the copy operation is complete, the current L2P table location plus the offset indicates the new L2P table location in the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Advantageous designs of the embodiments of the present disclosure are derived from the independent and dependent claims, the description and the drawings. In the following, preferred examples of the embodiments of the present disclosure are explained in detail with the aid of the drawings. The drawings, which are incorporated herein and form part of the specification, illustrate the present disclosure. The drawings, together with the description, further serve to explain the principles of the present disclosure and enable a person skilled in the relevant art to use the present disclosure.

[0020] Figure 1 A schematic modular depiction of an exemplary legacy host computer system is illustrated.

[0021] Figure 2 A schematic modular depiction of an exemplary host computer system incorporating CXL technology is illustrated.

[0022] Figure 3 A schematic modular depiction of a logical to physical memory table is illustrated.

[0023] Figure 4 An exemplary time sequence of memory events in an exemplary DRAM is presented.

[0024] Figure 5 An exemplary memory addressing scheme including location equations for a logical to physical memory table is described.

[0025] Figure 6 A flow chart illustrating an exemplary method of implementing copying a logical-to-physical memory table to a new location. DETAILED DESCRIPTION

[0026] Although illustrative embodiments are described herein for specific applications, it should be understood that the present disclosure is not limited thereto. Those skilled in the art and those who are able to obtain the teachings provided herein will recognize additional applications, modifications and embodiments within the scope thereof, as well as additional areas in which the present disclosure will have significant practical value.

[0027] Figure 1 A schematic modular depiction illustrating an exemplary legacy host computer system 100. Computer system 100 includes an exemplary motherboard 105, which includes a host CPU 107 and various ASICs 106 known in the art. Motherboard 105 may also include various data buses (including DRAM channels 120), physical ports, and expansion slots (not shown).

[0028] For example, motherboard 105 may include Figure 1 105. Among the ASICs on the motherboard 105 may be a double data rate (DDR) controller and physical layer 110. The DDR controller and physical layer 110 provide direct data communication between the host CPU 107 and provide direct read / write (R / W) commands 102 of the DRAM 115 by the host CPU 107. The direct data communication and R / W commands 102 may occur via a DRAM channel 120.

[0029] Figure 2 A schematic modular depiction of an exemplary host computer system 200 incorporating CXL technology is illustrated. As background, CXL is an open standard, cache coherent interconnect for processors, memory, and memory expansion. CXL is defined by a series of commands and required memory command responses defined in a specification created by the Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association and the CXL Consortium.

[0030] CXL technology maintains coherency between the memory space of the host CPU 107 and the DRAM 115 on the attached device. The combination of the motherboard 105 and the CPU 107 may be simply referred to in the art as a host device, and may have memory in addition to the CXL ASIC. The host device 205 is the source of data write commands (W) and data read requests (R) comprising the CXL transaction 202.

[0031] A service host bus (SMBus) not shown in the figure can communicate control commands and CXL ASIC status from the CXL driver 210 to the host CPU 107 / from the host CPU 107 to the CXL driver 210. The CXL driver 210 can be composed of multiple ASICs mounted on a shared board, or can be a single ASIC with multiple submodules. In general, the CXL driver 210 responds to data requests from the host CPU 107 to read / write data from / to the DRAM memory 115 or other types of suitable data storage devices.

[0032] The host device 205 may include an exemplary motherboard and various ASICs known in the art. The motherboard 105 may again include various data buses, including DRAM channels 120. The DRAM channels 120 may be a Peripheral Connection Interface Express bus (PCIe bus), which may also be referred to as a CXL link. The host device 205 may also have physical ports and expansion slots (not shown).

[0033] The motherboard 105 may be mounted on a board, or include a slot (not shown) for insertion of a CXL driver 210. As discussed throughout this document, the CXL driver 210 serves as a mediator and controller between the CPU 107 and the DRAM 115. The DRAM channel 120 is used to digitally ferry CXL transaction commands 202 between the host CPU 107 and the CXL driver 210. The motherboard 105 may also include a slot (not shown) for insertion and communicatively coupling of the DRAM 115 shown elsewhere in the drawings. The CXL driver 210 and the DRAM 115 are in turn typically coupled via a DDR channel 290, which itself may be integrated into the motherboard 105.

[0034] The CXL driver 210 itself may include an exemplary CXL operation ASIC 230. The CXL operation ASIC 230 itself may include a CXL transaction layer 235 configured to provide data interface to / from the host CPU 107 for the CXL transactions 202 and thereby for the data R / W commands 102. Unlike conventional main memory where the CPU 107 makes transactions to the DRAM 115 through the DRAM channel 120, the CXL driver 210 may have one or more ASICs to intercept the CXL transactions 202 passing through the CXL driver 210 and convert them into DRAM transactions. One function of the CXL operation ASIC 230 in the CXL driver 210 is to convert the R / W commands 102 passing through the CXL transactions 202 into DRAM requests.

[0035] The CXL operation ASIC 230 may also include a CXL central controller (CXL CC) 240 and a DDR controller and physical layer 245. The motherboard 105 may be directly connected to the CXL operation ASIC 230 via the DRAM channel 120. The DDR controller and physical layer 245 may operate similarly to the DDR controller and physical layer 245 of the computer system 100 that interfaces with the DRAM 115, as discussed above. Similarly, the CXL operation ASIC 230 may be directly connected to the DRAM 115 via the DDR channel 290. Specifically, the CXL CC 240 is communicatively coupled to the DRAM 115.

[0036] The CXL operations ASIC 230 may have logic blocks (shown as CXL CC 240) to perform additional tasks, such as error correction, thermal management, media management, etc. In particular, the CXL CC 240 may include a data compressor module 242, a reliability and serviceability module (RAS) 243, and an error manager 244. In some embodiments, the CXL CC may also include an offset register 241 (which may be part of the error manager 244) and may be used to store a memory address offset 420 (see Figure 4 ). In alternative embodiments, offset register 241 may not be present, and memory address offset 420 may be stored in a suitable memory location in uncompressed die 250 or compressed die 255. The operation of CXL CC 240 is discussed further below.

[0037] The CXL driver 210 may additionally include various peripheral components 215 (the details of which are beyond the scope of this document) and a power management integrated circuit (IC) 225 .

[0038] In an embodiment, the CXL driver 210 has an onboard DRAM 115 with multiple dies 250, 255 for data storage. Some dies may be designated as uncompressed dies 250 that store uncompressed data, while other dies may be designated as compression dies 255 that store data that has been compressed by the data compressor module 242. To reiterate, there are uncompressed sections of memory dies 250 and compressed sections of memory dies 250. The dies 250, 255 may also be used to store a logical to physical table 220 that maps logical addresses Ln provided by the CPU 107 and / or DDR controller and physical layer 245 to physical memory addresses Pn on the compression dies 255.

[0039] Figure 3 Another schematic diagram of DRAM 115 and L2P table 220 is presented. As indicated in the figure, one, two, or more selected dies 305 (which may be referred to as L2P dies 305 ) may initially be designated for storing L2P table 220 .

[0040] CXL with compression features is used to increase the capacity of CXL devices. Data compressor module 242 may use any of a variety of lossless compression schemes, such as LZ4, to compress data received from DRAM channel 120. This makes the effective storage capacity in DRAM 115 larger.

[0041] Because data compression is employed selectively (i.e., not for all data), DRAM 115 is typically mapped to two regions, one designated as uncompressed die 250, and one with compressed die 255. (Note that the die are typically physically the same die, but designated for different types of storage.) The two different regions are visible to CXL operating ASIC 230, but not to host CPU 107. Due to data compressor module 242, CXL driver 210 can store data in a smaller physical area (using less DRAM 115) than the amount of data received from host CPU 107.

[0042] The L2P table 220 provides a linear page mapping based on the data as requested by the host CPU 107 and the data as stored in the DRAM 115. There is a page mapping that maps a logical address Ln to a physical address Pn. The L2P table 220 is implemented in the media subsystem, that is, it is stored in the DRAM 115, so that some dies 305 of the DRAM are occupied by the L2P table 220.

[0043] L2P table 220 may be housed in one or even more L2P dies 305. As with any DRAM, dies may fail in CXL driver 210.

[0044] The CXL operation ASIC 230 has a RAS 243, which provides error detection and can correct data with errors. TM Can be used for error detection and correction. Chip hunting has the RAS feature that can correct erroneous data on the chip data. In the case of whole die damage, chip hunting is an exemplary mechanism for correcting errors from whole die failure.

[0045] Thus, the RAS 243 decode module (not illustrated) provides 64 bytes of cleaned and corrected data even from chips with errors. The CXL driver 210 can then collect the target data from the appropriate location in the compressed physical memory. The RAS 243 can correct up to one die based on redundancy in the stored data. Another exemplary error correction mechanism is Reed-Solomon code. Chip hunting, Reed-Solomon and other error correction codes are consistent with the present systems and methods.

[0046] If an error occurs in L2P table 220, the error may be corrected each time it is detected via the error correction method described above. However, this requires consuming both clock cycles and energy, both of which are preferably minimized. Furthermore, if additional errors occur on the same L2P die (305), beyond a certain point the errors are uncorrectable. Thus, the entire L2P table 220 is permanently corrupted, and CXL driver 210 then becomes useless.

[0047] In an embodiment, the present systems and methods first identify corrected mapping data for the L2P table 220. However, in addition, when a fault affects the L2P table, this triggers a move (ie, copy) of the entire contents of the L2P die (305) to another area of ​​the compression die 255.

[0048] To reiterate: Chip hunting, Reed-Solomon, and other error correction methods can work to correct errors in the L2P table 220. But the L2P table 220 should be preserved throughout the life of the system, so it is preferred that there are no errors in the L2P table 220 at all. If the L2P table 220 has failed, then it is preferred to correct the errors and then move the corrected table to a new location with a new L2P die 305 that has not failed. Therefore, when a failure affects the L2P table 220, the present system and method triggers a table move. In one embodiment, the entire table is copied to the new die. In an alternative embodiment, only the portion of the table on the failed die is copied to the new location.

[0049] Figure 4 An exemplary time sequence 402 of memory events in an exemplary DRAM 115 is presented. Figure 4In FIG. 1 , two DRAM dies 255 are used to store L2P table 117, but this is exemplary only. In alternative embodiments, only one die is used, or more than two dies may be used.

[0050] At the first time T1, the L2P table 117 (see Figure 5 ) are stored in two L2P dies 305 at a particular home location (memory location 405) in DRAM 115. The home location means that the selected die 305 is the initial die for storing L2P table 117. The selection may be based on factory settings, settings established during initial startup of CXL driver 210, settings established during initialization of host device 205, etc.

[0051] The L2P table 117 in the L2P die 305 is used during normal computer operation throughout the time interval from T=1 until time T=2. When accessing data in the compressed memory (writing data to the compressed memory or reading data from the compressed memory), the L2P table 117 is used to map the physical memory address indicated by the host CPU 107 to the logical memory address. During normal operation, the RAS 243 monitors the memory access to the L2P die 305 to check for any read errors.

[0052] Routine processing operations require CXL CC 240 (via DDR controller and physical layer 245) to read and write data values ​​to L2P table 117. The data values ​​written to / read from L2P table 117 may be, for example, logical addresses, physical addresses, or paired logical / physical addresses combined in a single data structure (e.g., a series of bytes).

[0053] At time T=2, a read is performed on the L2P table 117, and the RAS 243 detects a read error in the erroneous die 410, which is one of the L2P dies 305. The RAS 243 initiates two actions: Using a suitable error correction method as discussed above, the RAS 243 is able to correct the read error. The RAS 243 also triggers the error manager 244 to initiate a data copy process.

[0054] In one embodiment, the data copy process may copy the entire L2P table 117 to the other die at a new location, memory location 425. The new location is identified in part by a memory address offset 420 indicating the translation from the original memory location 405 to the new location 425. In an alternative embodiment, the data copy process may copy only the data contents of the erroneous die 410 to the new memory location 425, which is again identified via the appropriate offset 420.

[0055] At time T=3, the fault manager 244 has completely copied the L2P table 117 to the new memory location 425. All further memory accesses to the L2P table 117 are made to the die at the new memory location 425.

[0056] Figure 5 1 to 5. The CXL CC 240 (including the data compressor module 242 and the RAS 243) can address the L2P table 117 via the L2P location equation 500 to illustrate an exemplary addressing scheme employing the L2P location equation 500. The CXL CC 240 stores the original memory location 405 of the L2P table 117 and stores an offset 420, which is assigned a value (n) in the figure. By default (e.g., during the time interval from T=1 to T=2), n=0. To access the L2P table, the CXL CC 240 adds the original memory location 405 and the offset 420 to obtain a resulting physical address 520.

[0057] In some embodiments, offset 420 is recorded in the compression area. In alternative embodiments, offset 420 may be stored in offset register 241. In some embodiments, the address of L2P table 117 is stored as a logical address translated into a physical location. Add offset 420 to get the actual physical location: L+translation+offset=new physical address.

[0058] Therefore, the address calculation of the L2P table 117 is simple, and because the newly placed table incorporates the corrected L2P map data, no nanoseconds are lost in data correction.

[0059] Figure 6 A flow chart of an exemplary method 600 for L2P table movement in a CXL device employing data compression is presented. Method 600 assumes that L2P table 117 has been established in the CXL driver at initial memory location 405 on initial die 305. Method 600 also assumes that initial offset 420 has been previously stored in memory with a value of 0.

[0060] Method 600 begins at block 604 where the host CPU requests data from a compressed region of memory, providing a logical memory address Ln. In block 608, CXL CC 240, and in some embodiments specifically data compressor module 242, reads L2P table 117 to obtain a mapping from logical address Ln to compressed physical address Pn.

[0061] In frame 612, RAS243 checks whether the retrieved data has errors. If no errors are found in frame 612, method 600 proceeds to frame 618, wherein program operation is carried out according to normal standard processing. This requires retrieving the data requested by host CPU 107 from the appropriate physical address in memory Pn. Method 600 returns to frame 604.

[0062] If an error is found in block 612, the method 600 proceeds to block 622. In block 622, the RAS 243 and / or the error manager 244 corrects the error. The method 600 continues with two blocks: blocks 626 and 660, which occur substantially in parallel.

[0063] In block 626, memory and program operations proceed according to normal standard processing. This processing entails retrieving the data requested by the host CPU 107 from the appropriate physical address in memory Pn based on the corrected L2P memory data as determined in block 626. In block 660, the RAS triggers the error manager 244 to start the copy operation, and the method 600 continues with block 664.

[0064] Box 664 is a copy operation and contains two sub-boxes: 664A and 664B. In box 664A, a new memory location 425 of the L2P table 117 is determined by the error manager 244. The new memory location 425 is selected from among the unused compression dies 255. The new memory location is identified by an offset 420 from the original memory location 405 of the L2P table 117.

[0065] In block 664B, the L2P table 117 with the corrected data is copied to the die at the new memory location 425. This creates an L2P table 117 that is not corrupted.

[0066] The data movement during the copy operation is a progressive copy in the background from the original memory location 405 to the new memory location 425. While the data is being copied, CXL CC 240 will continue to utilize L2P table 117 for the data at the original location 405, using error correction performed by RAS 243.

[0067] In block 668, a continuous or periodic evaluation is performed to determine whether the copy operation is complete. If the operation is not complete, the copy operation of block 664B continues. If the copy operation of block 664B is complete, method 600 continues with block 672.

[0068] In block 672, the memory address offset 420 is stored in the offset register 241 or other specified location in memory. Thus, once the L2P table 117 is completely copied, the L2P location equation 500 (above) is used. Figure 5), any additional data accesses to L2P table 117 are made at new memory location 425.

[0069] In an alternative embodiment, CXL CC 240 knows which mapped data has been moved and which mapped data has not been moved, and accesses it in place.

[0070] The above explanation in this document assumes that the L2P table 117 fails once while stored in the original memory location 405, and is then copied (and thus, in effect, moved) to the new memory location 425. However, it should be noted that the new L2P die 305 at the new memory location 425 may also fail at some point. In this case, the method for copying the L2P table 117 from the first location to the second location will be repeated, except that instead of copying from the original L2P table location (memory location 405), it is copied from the current L2P table location (i.e., from the current new memory location 425). It will be understood that the present system and method copies the L2P table from the current L2P table location to the new L2P table address, as described in the appended claims.

[0071] The present system and method can be used with many different memory chip designs, many bus designs, many addressing systems, and various memory location schemes (both logical and hardwired / physical).

[0072] In particular, the present systems and methods address the problem that physical memory locations may fail or degrade over time.In some embodiments of the present systems and methods, a semiconductor memory system may reside on a single circuit card or even a single ASIC and may be synonymously referred to as a memory bank.

[0073] Alternative embodiments, examples and modifications that will still be encompassed by the present disclosure may be made by those skilled in the art, especially in light of the previous teachings.In addition, it should be understood that the terminology used to describe the present disclosure is intended to be in the nature of descriptive words rather than limiting words.

[0074] Those skilled in the art will also appreciate that various adaptations and modifications of the preferred and alternative embodiments described above may be configured without departing from the scope of the present disclosure. It is therefore to be understood that within the scope of the appended claims, the present disclosure may be practiced other than as specifically described herein.

[0075] For example, various aspects of the present disclosure may be implemented by software, firmware, hardware (including hardware represented by software or hardware description language instructions such as Verilog), or a combination thereof. After reading this description, it will become apparent to those skilled in the relevant art how to implement the present disclosure using other computer systems and / or computer architectures.

[0076] It should be noted that the simulation, synthesis and / or manufacture of various embodiments of the present disclosure may be accomplished in part through the use of computer-readable code, including general-purpose programming languages ​​(e.g., C or C++), hardware description languages ​​(HDLs) (including Verilog HDL, VHDL, Altera HDL (AHDL)), or other available programming and / or schematic capture tools (e.g., circuit capture tools).

[0077] This computer readable code may be disposed in or applied to any known tangible computer usable / readable storage medium, including semiconductors, magnetic disks, optical disks (e.g., CD read-only memory ROM, DVD-ROM, or the like); and as a computer data signal embodied in a computer usable (e.g., readable) transmission medium (e.g., tangible media including digital, optical, or analog-based media). Thus, the code may be transmitted from one tangible computer readable medium to another via a communication network including the Internet and intranets. It should be understood that the functions implemented and / or the structures provided by the systems and techniques described above may be represented in a core (e.g., a graphics processing unit core) that is embodied in program code and may be transformed into hardware as part of integrated circuit production.

[0078] It should be appreciated that the Detailed Description section, and not the Abstract section, is intended to be used to interpret the claims. The Abstract section may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, is not intended to limit the present disclosure and the appended claims in any way.

Claims

1. A tangible, non-transitory computer-readable storage medium comprising instructions that, when executed by a processor of a memory system, cause the processor to perform a method comprising the steps of: reading a data value from a logical-to-physical L2P table, wherein the L2P table includes a mapping from a logical memory address associated with a host system to a physical address in a compressed segment of the memory system; detecting an error in the read operation, the error indicating a failure of a memory die stored in the L2P table; When the error is detected, determining a correction for the error; as well as The L2P table is copied from the current L2P table location to the new L2P table location.

2. The computer-readable storage medium of claim 1, further comprising determining the address of the L2P table by adding a current physical memory address and an offset memory address.

3. The computer-readable storage medium of claim 1, further comprising setting an initial value of the offset memory address to 0.

4. The computer-readable storage medium of claim 1, further comprising determining whether the operation of copying the L2P table from the current L2P table location to the new L2P table location is complete.

5. A memory system comprising: Central controller; a dynamic random access memory DRAM communicatively coupled to the central controller, the DRAM comprising a plurality of dies configured to store compressed data; and a logical-to-physical L2P table stored in the plurality of dice configured to store compressed data and comprising a mapping from logical memory addresses associated with a host system to physical addresses in a compressed segment of the memory system; The controller is configured to: Reading a data value from the L2P table; detecting an error in the read operation, the error indicating a failure of a memory die used to store the L2P table; When the error is detected, determining a correction for the error; as well as The L2P table is copied from the current L2P table location to the new L2P table location.

6. The memory system of claim 5, wherein the central controller is further configured to determine the address of the L2P table by adding a current physical memory address and an offset memory address.

7. The memory system of claim 5, wherein the central controller is further configured to set an initial value of the offset memory address to 0 (zero).

8. The memory system of claim 5, wherein the central controller is further configured to determine whether the operation of copying the L2P table from the current L2P table location to the new L2P table location is complete.

9. The memory system of claim 5, wherein the central controller comprises a reliability and serviceability manager configured to trigger the copying of the L2P table upon detecting the error in the read operation.

10. A method for copying a logical-to-physical table L2P to a new L2P table location, the method comprising: reading a data value from an L2P table, wherein the L2P table includes a mapping from a logical memory address associated with a host system to a physical address in a compressed segment of the memory system; detecting an error in the read operation, the error indicating a failure of a memory die stored in the L2P table; as well as When the error is detected, determining a correction for the error; as well as The L2P table is copied from the current L2P table location to the new L2P table location.

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