Integrated circuit and operating method thereof

Abstract

The embodiment of the invention discloses an integrated circuit and an operation method thereof. The integrated circuit includes a first set of memory cells configured to store a first set of data, a second set of memory cells configured to store a second set of data, a first set of input / output (IO) circuits coupled to the first set of memory cells, a second set of IO circuits coupled to the second set of memory cells, and a third set of IO circuits coupled to the second set of memory cells. A first error correction code (ECC) circuit configured to store a first number of ECC bits, a second ECC circuit configured to store a second number of ECC bits; and a first ECC encoder / decoder circuit configured to correct at least a first number of errors in the first set of data and the second set of data based on the first number of ECC bits and the second number of ECC bits.

Description

Technical Field

[0001] Embodiments of the present application relate to an integrated circuit and an operating method thereof. Background Art

[0002] The semiconductor integrated circuit (IC) industry produces a wide variety of digital devices to solve problems in many different areas. Some of these digital devices, such as memory macros, are configured to store data. As ICs become smaller and more complex, the resistance of the wires within these digital devices also changes, affecting the operating voltage of these digital devices and the overall IC performance. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, an integrated circuit is provided, comprising: a first group of memory cells configured to store a first group of data; a second group of memory cells configured to store a second group of data; a first group of input-output (IO) circuits coupled to the first group of memory cells; a second group of IO circuits coupled to the second group of memory cells; a first error correction code (ECC) circuit configured to store a first number of ECC bits; a second ECC circuit configured to store a second number of ECC bits; and a first ECC encoder / decoder circuit configured to correct at least a first number of errors in the first group of data and the second group of data based on the first number of ECC bits and the second number of ECC bits.

[0004] According to another aspect of an embodiment of the present application, an integrated circuit is provided, comprising: a first memory cell array; a second memory cell array; a control circuit coupled to the first memory cell array and the second memory cell array; a first group of sense amplifiers coupled to the first memory cell array; a second group of sense amplifiers coupled to the second memory cell array; a first error correction code (ECC) circuit configured to store a first group of ECC check bits; a second ECC circuit configured to store a second group of ECC check bits; a first ECC encoder / decoder circuit configured to generate a first group of ECC check bits based on a first group of data stored in the first memory cell array; and a second ECC encoder / decoder circuit configured to generate a second group of ECC check bits based on a second group of data stored in the second memory cell array, wherein the first ECC circuit and the second ECC circuit are configured to correct at least a first number of errors in the first group of data and the second group of data based on the first group of ECC check bits and the second group of ECC check bits.

[0005] According to one aspect of an embodiment of the present application, a method for operating an integrated circuit is provided, the method comprising: performing a programming operation of a first group of memory cells. Performing a programming operation of the first group of memory cells comprises: storing a first group of data in a first memory cell array, and storing a second group of data in a second memory cell array; generating a first group of check bits in response to the first group of data, and generating a second group of check bits in response to the second group of data; and storing the first group of check bits in a first ECC memory cell array, and storing the second group of check bits in a second ECC memory cell array. The method also comprises: performing a read operation of the first group of memory cells; and in response to determining that the data read from the first memory cell array or the second memory cell array contains an error based on the first group of check bits and the second group of check bits, correcting the read data from the first memory cell array or the second memory cell array. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram of an integrated circuit according to some embodiments.

[0008] Figure 2 is a circuit diagram of a memory circuit according to some embodiments.

[0009] Figure 3 According to some embodiments, Figure 1 Block diagram of the integrated circuit used in.

[0010] Figure 4A is a top view of an integrated circuit according to some embodiments.

[0011] Figure 4B is a top view of an integrated circuit according to some embodiments.

[0012] Figure 5 According to some embodiments, Figure 1 Block diagram of the integrated circuit used in.

[0013] Fig. 6A is a top view of an integrated circuit according to some embodiments.

[0014] Figure 6B is a top view of an integrated circuit according to some embodiments.

[0015] Fig. 7A According to some embodiments, Figure 1Block diagram of the integrated circuit used in.

[0016] Figure 7B According to some embodiments, Figure 1 Block diagram of the integrated circuit used in.

[0017] Fig. 8A is a top view of an integrated circuit according to some embodiments.

[0018] Figure 8B is a top view of an integrated circuit according to some embodiments.

[0019] Fig. 9A is a top view of an integrated circuit according to some embodiments.

[0020] Fig. 9B is a top view of an integrated circuit according to some embodiments.

[0021] Fig.10 is a top view of an integrated circuit according to some embodiments.

[0022] Figure 11A-11B is a schematic diagram of a corresponding circuit according to some embodiments.

[0023] Figure 12A-12B is a cross-sectional view of a corresponding integrated circuit according to some embodiments.

[0024] Fig.13 is a functional flow diagram of a corresponding method of manufacturing an IC device according to some embodiments.

[0025] Fig.14 is a schematic diagram of a system according to some embodiments.

[0026] Fig.15 is a flow chart of a method of operating an integrated circuit according to some embodiments. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0028] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0029] According to some embodiments, an integrated circuit includes a first group of memory cells. In some embodiments, the first group of memory cells is configured to store a first set of data.

[0030] In some embodiments, the integrated circuit further comprises a second group of memory cells. In some embodiments, the second group of memory cells is configured to store a second group of data.

[0031] In some embodiments, the integrated circuit further comprises a first set of input-output (IO) circuits. In some embodiments, the first set of IO circuits are coupled to the first set of memory cells.

[0032] In some embodiments, the integrated circuit further comprises a second set of IO circuits. In some embodiments, the second set of IO circuits are coupled to a second set of memory cells.

[0033] In some embodiments, the integrated circuit further comprises a first error correction code (ECC) circuit. In some embodiments, the first ECC circuit is configured to store a first number of ECC bits.

[0034] In some embodiments, the integrated circuit further comprises a second ECC circuit. In some embodiments, the second ECC circuit is configured to store a second number of ECC bits.

[0035] In some embodiments, the integrated circuit further comprises a first ECC encoder / decoder circuit. In some embodiments, the first ECC encoder / decoder circuit is configured to correct at least a first number of errors in the first set of data and the second set of data based on the first number of ECC bits and the second number of ECC bits.

[0036] In some embodiments, by including at least one of the first ECC encoder / decoder circuit or the second ECC encoder / decoder circuit in the integrated circuit, the integrated circuit has error correction capability, resulting in an improved defective parts per million (DPPM) rate compared to other methods while also occupying less area than other methods.

[0037] Figure 1 is a block diagram of an integrated circuit 100 according to some embodiments. Figure 1In the exemplary embodiment, integrated circuit 100 is a memory macro.

[0038] Integrated circuit 100 includes a memory cell array 102 and a controller 104. Memory cell array 102 is coupled to controller 104. In some embodiments, memory cell array 102 is coupled to controller 104 via at least bit lines BL ( Figure 2 ) or word lines WL or other conductive lines are coupled to controller 104. Controller 104 is configured to control memory cell array 102. In some embodiments, controller 104 is configured to provide error correction coding (ECC), decoding and correction for integrated circuit 100 (as described below).

[0039] The memory cell array 102 includes a memory cell array having M rows and N columns, where M and N are positive integers (eg, Figure 2 ). In some embodiments, each memory cell in the memory cell array 102 is configured to store one (1) bit of data. In some embodiments, each memory cell in the memory cell array 102 is configured to store more than one (1) bit of data.

[0040] In some embodiments, the memory cell array 102 is a nonvolatile memory cell array including nonvolatile memory cells. In some embodiments, each memory cell in the memory cell array 102 corresponds to a one-time programmable (OTP) memory cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to an electric fuse (eFuse) memory cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to a multi-time programmable (MTP) memory cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to a magnetoresistive random access memory (MRAM) cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to a phase change memory (PCM) cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to a phase change RAM (PRAM) cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to a ferroelectric RAM (FeRAM) cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to a ferroelectric field effect transistor (FeFET) cell.

[0041] Other types of memory cells in the memory cell array 102 are within the scope of the present disclosure. Other configurations of the memory cell array 102 are within the scope of the present disclosure.

[0042] In some embodiments, the memory cell array 102 includes a first group of memory cells 102A and a second group of memory cells 102B. In some embodiments, the first group of memory cells 102A is a first group of memory arrays (e.g., such as at least Figure 3 , Figure 5 and Figure 7A-7B In some embodiments, the second group of memory cells 102B is a second group of memory cell arrays (eg, at least Figure 3 , Figure 5 and Figure 7A-7B 102A, 102B, 102B, or 102B). In some embodiments, the first group of memory cells 102A and the second group of memory cells 102B each include the same number of memory cells as each other. In some embodiments, the first group of memory cells 102A and the second group of memory cells 102B each include a different number of memory cells as each other.

[0043] Controller 104 includes X-decoder circuit 106 , Y-decoder circuit 108 , and ECC encoder / decoder 110 .

[0044] The X-decoder circuit 106 is coupled to (not shown) the memory cell array 102 via the word lines WL. The X-decoder circuit 106 is configured to generate word line signals (not shown) on corresponding word lines WL connected to the memory cell array 102. In some embodiments, the X-decoder circuit 106 includes a word line driver circuit (not shown) coupled to the word lines WL, and the word line driver circuit (not shown) is configured to generate word line signals sent to the memory cell array 102.

[0045] In some embodiments, a word line driver circuit (not shown) decodes a row address of a memory cell selected to be accessed in a read operation or a write operation in the memory cell array 102. In some embodiments, the word line driver circuit (not shown) then supplies a voltage to the selected word line corresponding to the decoded row address and supplies a different voltage to other unselected word lines. In some embodiments, the X-decoder circuit 106 is configured to generate a word line signal in response to a first set of control signals (not shown) received from the controller 104.

[0046] Other configurations of X-decoder circuit 106 are within the scope of the present disclosure.

[0047] Y-decoder circuit 108 is coupled to (not shown) memory cell array 102 via bit lines BL. Y-decoder circuit 108 is configured to generate bit line signals (not shown) on bit lines BL corresponding to memory cell array 102.

[0048] In some embodiments, the Y-decoder circuit 108 includes a bit line driver circuit (not shown) coupled to the bit line BL, and the bit line driver circuit (not shown) is configured to generate a bit line signal that is sent to the memory cell array 102 .

[0049] In some embodiments, the bit line driver circuit (not shown) decodes the column address of the memory cell selected to be accessed in the write operation in the memory cell array 102. In some embodiments, the bit line driver circuit (not shown) then supplies a voltage to the selected bit line corresponding to the decoded column address. In some embodiments, the Y-decoder circuit 108 is configured to generate a bit line signal in response to a second set of control signals (not shown) received from the controller 104.

[0050] Other configurations of the Y-decoder circuit 108 are within the scope of the present disclosure.

[0051] The ECC encoder / decoder 110 is coupled to the memory cell array 102 (not shown). The ECC encoder / decoder 110 is configured to provide ECC encoding, decoding, error detection, and error correction for data stored in the memory cell array 102. In some embodiments, the ECC encoder / decoder 110 includes at least one of a Hamming ECC encoder / decoder, a HsiaoECC encoder / decoder 110, a Reed-Solomon ECC encoder / decoder 110, a Bose–Chaudhuri–Hocquenghem (BCH) ECC encoder / decoder 110, and the like. Other ECC or error detection methods are within the scope of various embodiments.

[0052] In some embodiments, at least two or more of memory cell array 102, X-decoder circuit 106, Y-decoder circuit 108, or ECC encoder / decoder 110 are combined into a single circuit.

[0053] The ECC encoder / decoder 110 includes a first ECC encoder / decoder 110A and a second ECC encoder / decoder 110B. The first ECC encoder / decoder 110A is coupled to the first group of memory cells 102A. The second ECC encoder / decoder 110B is coupled to the second group of memory cells 102B.

[0054] The first ECC encoder / decoder circuit 110A is configured to generate a first set of ECC check bits based on a first set of data stored in the first set of memory cells 102A.

[0055] The second ECC encoder / decoder circuit 110B is configured to generate a second number of ECC check bits based on a second set of data stored in the second group of memory cells 102B.

[0056] In some embodiments, the first ECC encoder / decoder circuit 110A and the second ECC encoder / decoder circuit 110B are configured to correct at least a first number of errors in the first set of data and the second set of data based on the first set of ECC check bits and the second set of ECC check bits. In some embodiments, the first number of errors is 1 bit. In some embodiments, the first number of errors is 2 bits. In some embodiments, the first number of errors is greater than 2 bits.

[0057] In some embodiments, the first group of memory cells 102A is part of an ECC encoder / decoder 110A and the second group of memory cells 102B is part of an ECC encoder / decoder 110B.

[0058] Other configurations of ECC encoder / decoder 110 are within the scope of the present disclosure.

[0059] Other configurations of integrated circuit 100 are also within the scope of the present disclosure.

[0060] Figure 2 is a circuit diagram of a memory circuit 200 according to some embodiments.

[0061] The memory circuit 200 is Figure 1 The present invention is an embodiment of the memory cell array 102, and thus similar detailed description is omitted.

[0062] and Figure 1-Figure 14 The same or similar components in one or more of the parts are given the same figure marks, and thus their detailed description is omitted.

[0063] The memory circuit 200 includes a memory cell array 202 having M rows and N columns of memory cells MCB, where N is a positive integer corresponding to the number of columns in the memory cell array 200, and M is a positive integer corresponding to the number of rows in the memory cell array 202. The cell rows in the memory cell array 202 are arranged along a first direction X. The cell columns in the memory cell array 202 are arranged along a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X.

[0064] In some embodiments, each memory cell MCB in the memory cell array 202 is configured to store a bit of data. In some embodiments, the memory circuit 200 is a logic-based memory.

[0065] The number of rows M in the memory cell array 202 is equal to or greater than 1. The number of columns N in the memory cell array 202 is equal to or greater than 1. Different types of memory cells MCB in the memory cell array 202 are within the intended scope of the present disclosure.

[0066] The memory circuit 200 further includes N bit lines BL[1], ... BL[N] (collectively referred to as "bit lines BL"). Each column 1, ..., N in the memory cell array 202 overlaps and is coupled to a corresponding bit line BL[1], ..., BL[N]. Each bit line BL extends in the second direction Y and extends over a cell column (e.g., column 1, ..., N).

[0067] The memory circuit 200 also includes M word lines WL[1], ..., WL[M] (collectively referred to as "word lines WL"). Each row 1, ..., M in the memory cell array 202 overlaps and is coupled to a corresponding word line WL[1], ..., WL[M]. Each word line WL extends in a first direction X and extends over a cell row (e.g., row 1, ..., M).

[0068] Other configurations of the memory circuit 200 are within the scope of the present disclosure. In some embodiments, one or more of the bit lines BL or word lines WL are not included in the memory circuit 200. In some embodiments, one or more of the bit lines BL or word lines WL are replaced by corresponding source lines SL. In some embodiments, one or more source lines SL are added.

[0069] Figure 3 According to some embodiments, Figure 1 1 is a block diagram of an integrated circuit 300 used in the present invention.

[0070] Integrated circuit 300 involves Figure 1 The integrated circuit 300 is an embodiment of the integrated circuit 100, and similar detailed description is omitted.

[0071] The integrated circuit 300 includes a memory cell group 301 a , a memory cell group 301 b , an input-output (IO) circuit group 310 a , an IO circuit group 310 b , a word line driving circuit 330 , and a control circuit 332 .

[0072] In some embodiments, memory cell group 301a is Figure 1 In an embodiment of the first group of memory cells 102a, the memory cell group 301b is Figure 1 In an embodiment of the second group of memory cells 102B, IO circuit group 310a and IO circuit group 310b are Figure 1 The embodiments of the X-decoder circuit 106 and the Y-decoder circuit 108 are described in detail and similar detailed description is omitted.

[0073] In some embodiments, memory cell group 301a is Figure 2 Memory circuit 200, and similar detailed description is omitted. In some embodiments, memory cell group 301b is Figure 2 The memory circuit 200 is described below, and similar detailed description is omitted.

[0074] The memory cell array 301a includes a memory cell array 302 and an ECC memory cell array 306. In some embodiments, at least one of the memory cell array 302 or the ECC memory cell array 306 is Figure 2 The memory circuit 200 is described below, and similar detailed description is omitted.

[0075] In some embodiments, memory cell array 302 is the same type of memory cell array as ECC memory cell array 306. In some embodiments, memory cell array 302 is a different type of memory cell array than ECC memory cell array 306.

[0076] In some embodiments, the memory cell array 302 is configured to store a first set of data D1. In some embodiments, the ECC memory cell array 306 is configured to store a first set of parity bits CB1. The first set of ECC parity bits CB1 is generated based on the first set of data D1 by the ECC encoder / decoder circuit 332a. In some embodiments, the first set of ECC parity bits CB1 is a set of even or odd parity bits. In some embodiments, the number of parity bits in the first set of ECC parity bits CB1 is 3 bits. Other numbers of parity bits in the first set of parity bits CB1 are within the scope of the present disclosure.

[0077] In some embodiments, the number of rows or columns in memory cell array 302 is the same as the number of corresponding rows or columns in ECC memory cell array 306. In some embodiments, the number of rows or columns in memory cell array 302 is different from the number of corresponding rows or columns in ECC memory cell array 306.

[0078] The memory cell array 302 includes at least one or more of the memory cell arrays 302a1, 302a2, ..., 302a15, or 302a16. In some embodiments, each of the memory cell arrays 302a1, 302a2, ..., 302a16 includes L memory cell arrays, where L is an integer corresponding to the number of memory cell arrays in the memory cell arrays 302a1, 302a2, ..., 302a16. In some embodiments, L is 1 or greater.

[0079] Other numbers of memory cell arrays for memory cell arrays 302a1, 302a2, ..., 302a15, or 302a16 are within the scope of the present disclosure.

[0080] The ECC memory cell array 306 includes ECC memory cell arrays 306a1, 306a2, or 306a3. In some embodiments, each of the ECC memory cell arrays 306a1, 306a2, or 306a3 includes L ECC memory cell arrays, where L is an integer corresponding to the number of ECC memory cell arrays in the ECC memory cell arrays 306a1, 306a2, or 306a3.

[0081] Other numbers of ECC memory cell arrays for ECC memory cell arrays 306a1, 306a2, or 306a3 are within the scope of the present disclosure.

[0082] The memory cell array 301b includes a memory cell array 304 and an ECC memory cell array 308. In some embodiments, at least one of the memory cell array 304 or the ECC memory cell array 308 is Figure 2 The memory circuit 200 is described below, and similar detailed description is omitted.

[0083] In some embodiments, memory cell array 304 is the same type of memory cell array as ECC memory cell array 308. In some embodiments, memory cell array 304 is a different type of memory cell array than ECC memory cell array 308.

[0084] In some embodiments, ECC memory cell array 306 and ECC memory cell array 308 are located between memory cell array 302 and memory cell array 304. In some embodiments, IO circuit group 316 and IO circuit group 318 are located between IO circuit group 312 and IO circuit group 314.

[0085] In some embodiments, ECC memory cell array 306 and ECC memory cell array 308 are located near or in close proximity to WL driver 330. In some embodiments, IO circuit group 316 and IO circuit group 318 are located near or in close proximity to control circuit 332.

[0086] In some embodiments, the memory cell array 304 is configured to store the second group of data D2. In some embodiments, the ECC memory cell array 308 is configured to store the second group of check bits CB2. The second group of ECC check bits CB2 is generated by the ECC encoder / decoder circuit 332b based on the second group of data D2. In some embodiments, the second group of ECC check bits CB2 is a set of even or odd parity check bits. In some embodiments, the number of check bits in the second group of ECC check bits CB2 is 3 bits. Other numbers of check bits in the second group of check bits CB2 are within the scope of the present disclosure.

[0087] In some embodiments, the number of rows or columns in memory cell array 304 is the same as the corresponding number of rows or columns in memory cell array 308. In some embodiments, the number of rows or columns in memory cell array 304 is different from the corresponding number of rows or columns in memory cell array 308.

[0088] The memory cell array 304 includes at least one or more of the memory cell arrays 304a1, 304a2, ..., 304a15, or 304a16. In some embodiments, each of the memory cell arrays 304a1, 304a2, ..., 304a16 includes L memory cell arrays, where L is an integer corresponding to the number of memory cell arrays in the memory cell arrays 304a1, 304a2, ..., 304a16.

[0089] Other numbers of memory cell arrays for memory cell arrays 304a1, 304a2, ..., 304a16 are within the scope of the present disclosure.

[0090] The ECC memory cell array 308 includes ECC memory cell arrays 308a1, 308a2, or 308a3. In some embodiments, each of the ECC memory cell arrays 308a1, 308a2, or 308a3 includes L ECC memory cell arrays, where L is an integer corresponding to the number of ECC memory cell arrays in the ECC memory cell arrays 308a1, 308a2, or 308a3.

[0091] Other numbers of ECC memory cell arrays 308a1, 308a2, or 308a3 are also within the scope of the present disclosure.

[0092] In some embodiments, at least one of the memory cell arrays 302a1, 302a2, ..., 302a16, the memory cell arrays 304a1, 304a2, ..., 304a16, the ECC memory cell arrays 306a1, 306a2, or 306a3, or the ECC memory cell arrays 308a1, 308a2, or 308a3 corresponds to Figure 2 The memory circuit 200 is described below, and similar detailed description is omitted.

[0093] IO circuit group 310a is coupled to memory cell group 301a through a first set of local bit lines (not labeled). IO circuit group 310b is coupled to memory cell group 301b through a second set of local bit lines (not labeled).

[0094] The IO circuit group 310a is configured to selectively access one or more local bit lines (in the BL control signal) coupled to the memory cell group 301a based on one or more BL control signals. Figure 2 (not marked in the figure).

[0095] The IO circuit group 310b is configured to selectively access one or more local bit lines (in the BL control signal) coupled to the memory cell group 301b based on one or more BL control signals. Figure 2 In some embodiments, the IO circuit group 310a or 310b includes a bit line selection circuit. In some embodiments, each IO circuit in the IO circuit group 310a or 310b is a corresponding sense amplifier.

[0096] The IO circuit group 310 a includes an IO circuit group 312 and an IO circuit group 316 .

[0097] In some embodiments, the IO circuit group 312 is configured to read the first group of data D1 stored in the memory cell array 302. In some embodiments, the IO circuit group 316 is configured to read the first group of parity bits CB1 stored in the ECC memory cell array 306.

[0098] In some embodiments, IO circuit group 312 is the same type of IO circuit as IO circuit group 316. In some embodiments, IO circuit group 312 is a different type of IO circuit than IO circuit group 316.

[0099] IO circuit group 312 includes at least one or more of sense amplifier circuits 312a1, 312a2, ..., 312a16. In some embodiments, each of sense amplifier circuits 312a1, 312a2, ..., 312a16 is a multi-input channel sense amplifier (eg, L to 1).

[0100] Other numbers of sense amplifiers in the sense amplifier circuits 312a1, 312a2, ..., 312a16 are also within the scope of the present disclosure.

[0101] IO circuit group 316 includes at least one or more of sense amplifier circuits 316a1, 316a2, or 316a3. In some embodiments, each sense amplifier of sense amplifier circuits 316a1, 316a2, 316a3 is a multi-input channel sense amplifier (eg, L to 1).

[0102] Other numbers of sense amplifiers in sense amplifier circuits 316a1 , 316a2 , or 316a3 are also within the scope of the present disclosure.

[0103] In some embodiments, each of sense amplifier circuits 312a1, 312a2, ..., 312a16 or sense amplifier circuits 316a1, 316a2, or 316a3 is coupled to a corresponding column of memory cells in memory cell group 301a through a corresponding local bit line (not labeled).

[0104] In some embodiments, during a read operation, sense amplifier circuits 312a1, 312a2, ..., 312a16 or sense amplifier circuits 316a1, 316a2, or 316a3 are configured to read data from at least one memory cell in a corresponding column of memory cell group 301a.

[0105] Each of the sense amplifier circuits 312a1, 312a2, ..., 312a16 is coupled to a corresponding memory cell array in the memory cell array 302a1, 302a2, ..., 302a15 or 302a16 through L corresponding local bit lines (not labeled).

[0106] Each of the sense amplifier circuits 316a1, 316a2, or 316a3 is coupled to a corresponding one of the ECC memory cell arrays 306a1, 306a2, or 306a3 through L corresponding local bit lines (not labeled).

[0107] In some embodiments, each of the sense amplifier circuits 312a1, 312a2, ..., 312a16 is configured to output a corresponding output signal Q0, Q1, ..., Q15 during a corresponding read operation. In some embodiments, each of the output signals Q0, Q1, ..., Q15 is a corresponding data value stored in a corresponding memory cell array 302a1, 302a2, ..., 302a15 or 302a16. In some embodiments, the output signals Q0, Q1, ..., Q15 are a first set of data D1 stored in the memory cell array 302.

[0108] In some embodiments, each of the sense amplifier circuits 316a1, 316a2, or 316a3 is configured to output a corresponding output signal Q16, Q17, Q18. In some embodiments, each of the output signals Q16, Q17, Q18 is a corresponding data value stored in the corresponding ECC memory cell array 306a1, 306a2, 306a3. In some embodiments, each of the output signals Q16, Q17, Q18 is a corresponding ECC check bit in the first group of ECC check bits CB1 generated by the ECC encoder / decoder circuit 332a based on the output signals Q0, Q1, ..., Q15. In some embodiments, the ECC encoder / decoder circuit 332a uses the first group of ECC check bits CB1 (output signals Q16, Q17, Q18) to determine whether an error occurs in the output signals Q0, Q1, ..., Q15.

[0109] The IO circuit group 310 b includes an IO circuit group 314 and an IO circuit group 318 .

[0110] In some embodiments, the IO circuit group 314 is configured to read the second group of data D2 stored in the memory cell array 304. In some embodiments, the IO circuit group 318 is configured to read the second group of parity bits CB2 stored in the ECC memory cell array 308.

[0111] In some embodiments, IO circuit group 314 is the same type of IO circuit as IO circuit group 318. In some embodiments, IO circuit group 314 is a different type of IO circuit than IO circuit group 318.

[0112] In some embodiments, at least one of the IO circuit groups 312, 314, 316, or 318 is an IO circuit of the same type as another one of the IO circuit groups 312, 314, 316, or 318. In some embodiments, the IO circuit groups 312, 314, 316, or 318 are IO circuits of a different type than another one of the IO circuit groups 312, 314, 316, or 318.

[0113] IO circuit group 314 includes at least one or more of sense amplifier circuits 314a1, 314a2, ..., 314a16. In some embodiments, each of sense amplifier circuits 314a1, 314a2, ..., 314a16 is a multi-input channel sense amplifier (eg, L to 1).

[0114] Other numbers of sense amplifiers in the sense amplifier circuits 314a1, 314a2, ..., 314a16 are also within the scope of the present disclosure.

[0115] IO circuit group 318 includes at least one or more of sense amplifier circuits 318a1, 318a2, or 318a3. In some embodiments, each sense amplifier of sense amplifier circuits 318a1, 318a2, 318a3 is a multi-input channel sense amplifier (eg, L to 1).

[0116] Other numbers of sense amplifiers in sense amplifier circuits 318a1 , 318a2 , or 318a3 are also within the scope of the present disclosure.

[0117] In some embodiments, each of sense amplifier circuits 314a1, 314a2, ..., 314a16 or sense amplifier circuits 318a1, 318a2, or 318a3 is coupled to a corresponding column of memory cells in memory cell group 301b through a corresponding local bit line (not labeled).

[0118] In some embodiments, during a read operation, sense amplifier circuits 314a1, 314a2, ..., 314a16 or sense amplifier circuits 318a1, 318a2, or 318a3 are configured to read data from at least one memory cell in a corresponding column of memory cell group 301b.

[0119] Each of the sense amplifier circuits 314a1, 314a2, ..., 314a16 is coupled to a corresponding memory cell array in the memory cell array 304a1, 304a2, ..., 304a15 or 304a16 through L corresponding local bit lines (not labeled).

[0120] Each of the sense amplifier circuits 318a1, 318a2, or 318a3 is coupled to a corresponding ECC memory cell in the ECC memory cell array 308a1, 308a2, or 308a3 through L corresponding local bit lines (not labeled).

[0121] In some embodiments, each of the sense amplifier circuits 314a1, 314a2, ..., 314a16 is configured to output a corresponding output signal Q22, Q23, ..., Q37 during a corresponding read operation. In some embodiments, each of the output signals Q22, Q23, ..., Q37 is a corresponding data value stored in the corresponding memory cell array 304a1, 304a2, ..., 304a15 or 304a16. In some embodiments, the output signals Q22, Q23, ..., Q37 are the second set of data D2 stored in the memory cell array 304.

[0122] In some embodiments, each of the sense amplifier circuits 318a1, 318a2, or 318a3 is configured to output a corresponding output signal Q19, Q20, Q21. In some embodiments, each of the output signals Q19, Q20, Q21 is a corresponding data value stored in the corresponding ECC memory cell array 308a1, 308a2, 308a3. In some embodiments, each of the output signals Q19, Q20, Q21 is a corresponding ECC check bit in the second group of ECC check bits CB2 generated by the ECC encoder / decoder circuit 332b based on the output signals Q22, Q23, ..., Q37. In some embodiments, the ECC encoder / decoder circuit 332b uses the second group of ECC check bits CB2 (e.g., output signals Q19, Q20, Q21) to determine whether an error occurs in the output signals Q22, Q23, ..., Q37.

[0123] In some embodiments, the integrated circuit 300 includes 38 IO circuits (eg, IO circuit groups 310 a and 310 b ), and the integrated circuit 300 is configured to output 38 bits as the output signal Q (eg, output signals Q0 - Q37 ).

[0124] In some embodiments, the integrated circuit 300 is configured to correct at least a first number of errors in the first set of data D1 and the second set of data D2 based on the first set of ECC check bits CB1 and the second set of ECC check bits CB2. In some embodiments, the first number of errors is 1 bit. In some embodiments, the first number of errors is 2 bits. In some embodiments, the first number of errors is greater than 2 bits. Other numbers of errors in the first number of errors are within the scope of the present disclosure.

[0125] Other numbers of output signals Q, IO circuits, or bits are within the scope of the present disclosure.

[0126] In some embodiments, the ECC memory cell array 306 and the IO circuit group 316 are referred to as ECC circuit 305a.

[0127] In some embodiments, the ECC memory cell array 308 and the IO circuit group 318 are referred to as ECC circuit 305b.

[0128] In some embodiments, the ECC memory cell array 306 of the ECC circuit 305a is configured to store the first group of ECC check bits CB1, and the IO circuit group 316 of the ECC circuit 305a is configured to read the first group of ECC check bits CB1 from the ECC memory cell array 306 of the ECC circuit 305b.

[0129] In some embodiments, the ECC memory cell array 308 of the ECC circuit 305 b is configured to store the second group of ECC check bits CB2 , and the IO circuit group 318 of the ECC circuit 305 b is configured to read the second group of ECC check bits CB2 from the ECC memory cell array 308 of the ECC circuit 305 b .

[0130] The word line driver circuits 330 are configured to generate word line signals on corresponding word lines WL. In some embodiments, each word line driver circuit 330 is configured to output the word line signal on the corresponding word line WL to adjacent memory cells in the memory cell group 301a or 301b.

[0131] Each control circuit 332 is an electronic circuit configured to receive one or more address signals. Each control circuit 332 is configured to generate a signal corresponding to an adjacent group of memory cells identified by the one or more address signals. In some embodiments, the adjacent group of memory cells corresponds to a column of memory cells. In some embodiments, each control circuit 332 is configured to generate each signal as a complementary signal pair. In some embodiments, each control circuit 332 is configured to output a signal to a corresponding word line driver within an adjacent word line driver circuit 330.

[0132] In some embodiments, word line driver circuit 330 is located between ECC memory cell array 306 and ECC memory cell array 308. In some embodiments, control circuit 332 is located between IO circuit group 318 and IO group circuit 316.

[0133] The control circuit 332 includes an ECC encoder / decoder circuit 332a and an ECC encoder / decoder circuit 332b.

[0134] The ECC encoder / decoder circuit 332 a is configured to generate a first group of ECC check bits CB1 based on the first group of data D1 .

[0135] The ECC encoder / decoder circuit 332 b is configured to generate a second number of ECC check bits CB2 based on the second set of data D2 .

[0136] The ECC encoder / decoder circuit 332a and the ECC encoder / decoder circuit 332b are configured to correct at least a first number of errors in the first set of data D1 and the second set of data D2 based on the first set of ECC check bits CB1 and the second set of ECC check bits CB2.

[0137] In some embodiments, the ECC encoder / decoder circuits 332a and 332b are configured to correct at least a first number of errors in the output signals Q0, Q1, ..., Q15 and the output signals Q22, Q23, ..., Q37 based on the output signals Q16, Q17, Q18 and the output signals Q19, Q20, Q21.

[0138] In some embodiments, by including at least one of ECC encoder / decoder circuits 332 a and 332 b, ECC circuit 305 a, or ECC circuit 305 b in integrated circuit 300, integrated circuit 300 has error correction capabilities, resulting in an improved defective parts per million (DPPM) rate compared to other approaches, while also occupying a smaller area than other approaches.

[0139] In some embodiments, by including at least one of ECC encoder / decoder circuits 332a and 332b, ECC circuit 305a, or ECC circuit 305b in integrated circuit 300, integrated circuit 300 has error correction capability, improves DPPM compared to other approaches, and has greater area efficiency than other approaches.

[0140] Other configurations of integrated circuit 300 are also within the scope of the present disclosure.

[0141] Figure 4A is a top view of an integrated circuit 400A according to some embodiments.

[0142] The integrated circuit 400A is an embodiment of a portion of the integrated circuit 300, and thus similar detailed descriptions are omitted. For example, the integrated circuit 400A is an embodiment of a portion of the integrated circuit 300, wherein the first group of ECC check bits CB1 is located in an inner portion (e.g., side 403a2 or 403b2) of the memory cell array 401a1 or 401a2, and the second group of ECC check bits CB2 is located in an inner portion (e.g., side 403a3 or 403b3) of the memory cell array 401b1 or 401b2, and thus similar detailed descriptions are omitted.

[0143] In some embodiments, Figure 4A is a layout of a portion of integrated circuit 400A.

[0144] The integrated circuit 400A includes a memory cell array 401 a 1 , a memory cell array 402 a 2 , a memory cell array 401 b 1 , a memory cell array 401 b 2 , an IO circuit group 410 a , and an IO circuit group 410 b .

[0145] In some embodiments, the memory cell array 401a1 and the memory cell array 402a2 are Figure 3 The corresponding upper bank and lower bank of the memory cell array 301a are described below, and similar detailed description is omitted.

[0146] In some embodiments, memory cell array 401b1 and memory cell array 402b2 are Figure 3 The corresponding upper and lower banks of the memory cell array 301b are described below, and similar detailed descriptions are omitted.

[0147] In some embodiments, IO circuit group 410a is Figure 3 IO circuit group 310a, and similar detailed description is omitted. In some embodiments, IO circuit group 410a is Figure 3 IO circuit group 310b, and similar detailed description is omitted.

[0148] The memory cell array 401a1 includes a memory cell array 402a and an ECC memory cell array 406a.

[0149] The memory cell array 402a is configured to store a first set of data D1. The ECC memory cell array 406a is configured to store a first set of parity bits CB1.

[0150] In some embodiments, the memory cell array 402a is Figure 3 In some embodiments, the ECC memory cell array 406a is an upper bank of the memory cell array 302, and similar detailed description is omitted. Figure 3 The upper bank of the ECC memory cell array 306 is shown in FIG. 1 , and similar detailed description is omitted.

[0151] The memory cell array 401 a 1 further includes a first end 403 a 1 and a second end 403 a 2 opposite to the first end 403 a 1 .

[0152] The memory cell array 402a is located on a first end 403a1 of the memory cell array 401a1. The ECC memory cell array 406a is located on a second end 403a2 of the memory cell array 401a1.

[0153] The memory cell array 401a2 includes a memory cell array 402b and an ECC memory cell array 406b.

[0154] The memory cell array 402b is configured to store a first set of data D1. The ECC memory cell array 406b is configured to store a first set of parity bits CB1.

[0155] In some embodiments, memory cell array 402b is Figure 3 In some embodiments, the ECC memory cell array 406b is a lower bank of the memory cell array 302, and similar detailed description is omitted. Figure 3 The lower bank of the ECC memory cell array 306 is shown in FIG. 1 , and similar detailed description is omitted.

[0156] The memory cell array 401 a 2 further includes a first end 403 b 1 and a second end 403 b 2 opposite to the first end 403 b 1 .

[0157] The memory cell array 402b is located on the first end 403b1 of the memory cell array 401a2. The ECC memory cell array 406b is located on the second end 403b2 of the memory cell array 401a2.

[0158] The memory cell array 401 b 1 includes a memory cell array 404 a and an ECC memory cell array 408 a .

[0159] The memory cell array 404a is configured to store a second set of data D2. The ECC memory cell array 408a is configured to store a second set of parity bits CB2.

[0160] In some embodiments, the memory cell array 404a is Figure 3 In some embodiments, the ECC memory cell array 408a is an upper bank of the memory cell array 304, and similar detailed description is omitted. Figure 3 The upper bank of the ECC memory cell array 308 is shown in FIG. 1 , and similar detailed description is omitted.

[0161] The memory cell array 401 b 1 further includes a first end 403 a 3 and a second end 403 a 4 opposite to the first end 403 a 3 .

[0162] The memory cell array 404a is located on the second end 403a4 of the memory cell array 401b1. The ECC memory cell array 408a is located on the first end 403a3 of the memory cell array 401b1.

[0163] The memory cell array 401b2 includes a memory cell array 404b and an ECC memory cell array 408b.

[0164] The memory cell array 404b is configured to store a second set of data D2. The ECC memory cell array 408b is configured to store a second set of parity bits CB2.

[0165] In some embodiments, the memory cell array 404b is Figure 3 In some embodiments, the ECC memory cell array 408b is a lower bank of the memory cell array 304, and similar detailed description is omitted. Figure 3 The lower bank of the ECC memory cell array 308 is shown in FIG. 1 , and similar detailed description is omitted.

[0166] The memory cell array 401b2 further includes a first end 403b3 and a second end 403b4 opposite to the first end 403b3.

[0167] The memory cell array 404b is located on the second end 403b4 of the memory cell array 401b2. The ECC memory cell array 408b is located on the first end 403b3 of the memory cell array 401b2.

[0168] IO circuit group 410 a includes sense amplifier circuit group 412 and sense amplifier circuit group 416 .

[0169] In some embodiments, the sense amplifier circuit group 412 is Figure 3 , 312a16, and similar detailed description is omitted.

[0170] In some embodiments, the sense amplifier circuit group 416 is Figure 3 The sense amplifier circuits 316a1, 316a2, 316a3 are described below, and similar detailed description is omitted.

[0171] The IO circuit group 410 a further includes a first end 410 a 1 and a second end 410 a 2 opposite to the first end 410 a 1 .

[0172] The sense amplifier circuit group 412 is located on the first end 410a1 of the IO circuit group 410a. The sense amplifier circuit group 416 is located on the second end 410a2 of the IO circuit group 410a.

[0173] IO circuit group 410 b includes sense amplifier circuit group 414 and sense amplifier circuit group 418 .

[0174] In some embodiments, the sense amplifier circuit group 414 is Figure 3 , 314a16, and similar detailed description is omitted.

[0175] In some embodiments, sense amplifier circuit group 418 is Figure 3 The sense amplifier circuits 318a1, 318a2, 318a3 are described below, and similar detailed description is omitted.

[0176] The IO circuit group 410 b further includes a first end 410 b 1 and a second end 410 b 2 opposite to the first end 410 b 1 .

[0177] The sense amplifier circuit group 414 is located on the second end 410b2 of the IO circuit group 410b. The sense amplifier circuit group 418 is located on the first end 410b1 of the IO circuit group 410b.

[0178] Integrated circuit 400A achieves the advantages discussed herein.

[0179] Other configurations of integrated circuit 400A are also within the scope of the present disclosure.

[0180] Figure 4B is a top view of an integrated circuit 400B according to some embodiments.

[0181] The integrated circuit 400B is an embodiment of a portion of the integrated circuit 300 , and thus similar detailed description is omitted.

[0182] IC 400B is Figure 4A A variation of the integrated circuit 400A is described below and similar detailed description is omitted. Figure 4A Compared to the integrated circuit 400A, the first group of ECC check bits CB1 are located on the outer portion of the memory cell array 401a1 or 401a2 (e.g., side 403a1 or 403b1), and the second group of ECC check bits CB2 are located on the outer portion of the memory cell array 401b1 or 401b2 (e.g., side 403a4 or 403b4), so similar detailed description is omitted.

[0183] In some embodiments, Figure 4A is a layout of a portion of integrated circuit 400A.

[0184] The memory cell array 402a is located on the second end 403a2 of the memory cell array 401a1. The ECC memory cell array 406a is located on the first end 403a1 of the memory cell array 401a1.

[0185] The memory cell array 402b is located on the second end 403b2 of the memory cell array 401a2. The ECC memory cell array 406b is located on the first end 403b1 of the memory cell array 401a2.

[0186] The memory cell array 404a is located on the first end 403a3 of the memory cell array 401b1. The ECC memory cell array 408a is located on the second end 403a4 of the memory cell array 401b1.

[0187] The memory cell array 404b is located on the first end 403b3 of the memory cell array 401b2. The ECC memory cell array 408b is located on the second end 403b4 of the memory cell array 401b2.

[0188] The sense amplifier circuit group 412 is located on the second end 410a2 of the IO circuit group 410a. The sense amplifier circuit group 416 is located on the first end 410a1 of the IO circuit group 410a.

[0189] The sense amplifier circuit group 414 is located on the first end 410b1 of the IO circuit group 410b. The sense amplifier circuit group 418 is located on the second end 410b2 of the IO circuit group 410b.

[0190] Integrated circuit 400B achieves the advantages discussed herein.

[0191] Other configurations of integrated circuit 400B are also within the scope of the present disclosure.

[0192] Figure 5 According to some embodiments, Figure 1 0048. Block diagram of an integrated circuit 500 for use in FIG.

[0193] Integrated Circuit 500 Figure 1 The integrated circuit 500 is an embodiment of the integrated circuit 100, and similar detailed description is omitted.

[0194] IC 500 is Figure 3 For variations of the integrated circuit 300, similar detailed descriptions are omitted.

[0195] According to some embodiments, Figure 3 Compared to the integrated circuit 300 , the integrated circuit 500 is configured to perform ECC protection on the output signal Q using 12 bits.

[0196] According to some embodiments, Figure 3 Compared with the integrated circuit 300 , the integrated circuit 500 is configured to output an output signal Q, and the output signal Q includes 44 bits.

[0197] The integrated circuit 500 includes a memory cell group 501 a , a memory cell group 501 b , an IO circuit group 510 a , an IO circuit group 510 b , a word line driving circuit 330 , and a control circuit 332 .

[0198] and Figure 3 Compared with the integrated circuit 300 , the memory cell group 501 a replaces the memory cell group 301 a , and the memory cell group 501 b replaces the memory cell group 301 b , and thus similar detailed descriptions are omitted.

[0199] and Figure 3 Compared with the integrated circuit 300, the IO circuit group 510a replaces the IO circuit group 310a, and the IO circuit group 510b replaces the IO circuit group 310b, so similar detailed descriptions are omitted.

[0200] The memory cell array 501 a includes the memory cell array 302 and the ECC memory cell array 506 .

[0201] The ECC memory cell array 506 is Figure 3 For variations of the ECC memory cell array 306, similar detailed descriptions are omitted.

[0202] In some embodiments, the ECC memory cell array 506 is configured to store a third group of parity bits CB3. The ECC encoder / decoder circuit 332a generates a third group of ECC parity bits CB3 based on the first group of data D1. In some embodiments, the third group of ECC parity bits CB3 is a set of even or odd parity bits. In some embodiments, the number of parity bits in the third group of ECC parity bits CB3 is 6 bits. Other numbers of parity bits in the third group of parity bits CB3 are within the scope of the present disclosure.

[0203] The ECC memory cell array 506 includes ECC memory cell arrays 506a1, 506a2, 506a3, 506a4, 506a5, or 506a6. In some embodiments, each of the ECC memory cell arrays 506a1, 506a2, 506a3, 506a4, 506a5, or 506a6 is similar to one or more of the ECC memory cell arrays 306a1, 306a2, or 306a3, and similar detailed descriptions are omitted.

[0204] In some embodiments, each of the ECC memory cell arrays 506a1, 506a2, 506a3, 506a4, 506a5, or 506a6 includes L ECC memory cell arrays, where L is an integer corresponding to the number of ECC memory cells in the ECC memory cell arrays 506a1, 506a2, 506a3, 506a4, 506a5, or 506a6.

[0205] Other numbers of ECC memory cell arrays 506a1, 506a2, 506a3, 506a4, 506a5, or 506a6 are also within the scope of the present disclosure.

[0206] The memory cell array 501 b includes the memory cell array 304 and the ECC memory cell array 508 .

[0207] The ECC memory cell array 508 is Figure 3 For variations of the ECC memory cell array 308, similar detailed descriptions are omitted.

[0208] In some embodiments, the ECC memory cell array 508 is configured to store a third group of parity bits CB3. The ECC encoder / decoder circuit 332b generates a third group of ECC parity bits CB3 based on the second group of data D2. In some embodiments, the third group of ECC parity bits CB3 is a set of even or odd parity bits. In some embodiments, the number of parity bits in the fourth group of ECC parity bits CB4 is 6 bits. Other numbers of parity bits in the fourth group of parity bits CB4 are within the scope of the present disclosure.

[0209] The ECC memory cell array 508 includes ECC memory cell arrays 508a1, 508a2, 508a3, 508a4, 508a5, or 508a6. In some embodiments, each of the ECC memory cell arrays 508a1, 508a2, 508a3, 508a4, 508a5, or 508a6 is similar to one or more of the ECC memory cell arrays 308a1, 308a2, or 308a3, and similar detailed descriptions are omitted.

[0210] In some embodiments, each of the ECC memory cell arrays 508a1, 508a2, 508a3, 508a4, 508a5, or 508a6 includes L ECC memory cell arrays, where L is an integer corresponding to the number of ECC memory cells in the ECC memory cell arrays 508a1, 508a2, 508a3, 508a4, 508a5, or 508a6.

[0211] Other numbers of ECC memory cell arrays 508a1, 508a2, 508a3, 508a4, 508a5, or 508a6 are also within the scope of the present disclosure.

[0212] The IO circuit group 510 a includes the IO circuit group 312 and the IO circuit group 516 .

[0213] IO circuit group 516 is Figure 3For variations of the IO circuit group 316, similar detailed descriptions are omitted.

[0214] In some embodiments, the IO circuit group 516 is configured to read the third group of parity bits CB3 stored in the ECC memory cell array 506 .

[0215] IO circuit group 516 includes at least one or more of sense amplifier circuits 516a1, 516a2, 516a3, 516a4, 516a5, or 516a6. In some embodiments, each of sense amplifier circuits 516a1, 516a2, 516a3, 516a4, 516a5, or 516a6 is a multi-input channel sense amplifier (e.g., L to 1).

[0216] Other numbers of sense amplifiers in sense amplifier circuits 516a1 , 516a2 , 516a3 , 516a4 , 516a5 , or 516a6 are also within the scope of the present disclosure.

[0217] Each of the sense amplifier circuits 516a1, 516a2, 516a3, 516a4, 516a5, or 516a6 is coupled to a corresponding ECC memory cell array in the ECC memory cell array 506a1, 506a2, 506a3, 506a4, 506a5, or 506a6 via L corresponding local bit lines (unlabeled).

[0218] In some embodiments, each of the sense amplifier circuits 312a1, 312a2, ..., 312a16 is configured to output a corresponding output signal Q0, Q1, ..., Q15 during a corresponding read operation. In some embodiments, each of the output signals Q0, Q1, ..., Q15 is a corresponding data value stored in a corresponding memory cell array 302a1, 302a2, ..., 302a15 or 302a16. In some embodiments, the output signals Q0, Q1, ..., Q15 are a first set of data D1 stored in the memory cell array 302.

[0219] In some embodiments, each sense amplifier circuit of the sense amplifier circuit 516a1, 516a2, 516a3, 516a4, 516a5, or 516a6 is configured to output a corresponding output signal Q16, Q17, Q18, Q19, Q20, or Q21. In some embodiments, each output signal Q16, Q17, Q18, Q19, Q20, Q21 is a corresponding data value stored in the corresponding ECC memory cell array 506a1, 506a2, 506a3, 506a4, 506a5, 506a6. In some embodiments, each output signal Q16, Q17, Q18, Q19, Q20, Q21 is a corresponding ECC check bit in the third group of ECC check bits CB3 generated by the ECC encoder / decoder circuit 332a based on the output signals Q0, Q1, ..., Q15. In some embodiments, the ECC encoder / decoder circuit 332a uses the third group of ECC check bits CB3 (output signals Q16, Q17, Q18, Q19, Q20, Q21) to determine whether errors occur in the output signals Q0, Q1, ..., Q15.

[0220] The IO circuit group 510 b includes the IO circuit group 314 and the IO circuit group 518 .

[0221] IO circuit group 518 is Figure 3 For variations of the IO circuit group 318, similar detailed descriptions are omitted.

[0222] In some embodiments, the IO circuit group 518 is configured to read the fourth group of parity bits CB4 stored in the ECC memory cell array 508 .

[0223] IO circuit group 518 includes at least one or more of sense amplifier circuits 518a1, 518a2, 518a3, 518a4, 518a5, or 518a6. In some embodiments, each sense amplifier of sense amplifier circuits 518a1, 518a2, 518a3, 518a4, 518a5, or 518a6 is a multi-input channel sense amplifier (e.g., L to 1).

[0224] Other numbers of sense amplifiers in sense amplifier circuits 518a1 , 518a2 , 518a3 , 518a4 , 518a5 , or 518a6 are also within the scope of the present disclosure.

[0225] Each of the sense amplifier circuits 518a1, 518a2, 518a3, 518a4, 518a5, or 518a6 is coupled to a corresponding ECC memory cell array in the ECC memory cell array 508a1, 508a2, 508a3, 508a4, 508a5, or 508a6 via L corresponding local bit lines (unlabeled).

[0226] In some embodiments, each of the sense amplifier circuits 314a1, 314a2, ..., 314a16 is configured to output a corresponding output signal Q28, Q29, ..., Q43 during a corresponding read operation. In some embodiments, each of the output signals Q28, Q29, ..., Q43 is a corresponding data value stored in a corresponding memory cell array 304a1, 304a2, ..., 304a15 or 304a16. In some embodiments, the output signals Q28, Q29, ..., Q43 are a second set of data D2 stored in the memory cell array 304.

[0227] In some embodiments, each sense amplifier circuit of the sense amplifier circuit 518a1, 518a2, 518a3, 518a4, 518a5, or 518a6 is configured to output a corresponding output signal Q22, Q23, Q24, Q25, Q26, or Q27. In some embodiments, each output signal Q22, Q23, Q24, Q25, Q26, Q27 is a corresponding data value stored in the corresponding ECC memory cell array 508a1, 508a2, 508a3, 508a4, 508a5, 508a6. In some embodiments, each output signal Q22, Q23, Q24, Q25, Q26, Q27 is a corresponding ECC check bit in the fourth group of ECC check bits CB4 generated by the ECC encoder / decoder circuit 332b based on the output signals Q28, Q29, ..., Q43. In some embodiments, the ECC encoder / decoder circuit 332 b uses the fourth group of ECC check bits CB4 (output signals Q22 , Q23 , Q24 , Q25 , Q26 , Q27 ) to determine whether an error occurs in the output signals Q28 , Q29 , . . . , Q43 .

[0228] In some embodiments, the integrated circuit 500 includes 44 IO circuits (eg, IO circuit groups 510 a and 510 b ), and the integrated circuit 500 is configured to output 44 bits as the output signal Q (eg, output signals Q0 - Q43 ).

[0229] In some embodiments, the integrated circuit 500 is configured to correct at least a second number of errors in the first group of data D1 and the second group of data D2 based on the third group of ECC check bits CB3 and the fourth group of ECC check bits CB4. In some embodiments, the second number of errors is 2 bits. In some embodiments, the second number of errors is 1 bit. In some embodiments, the second number of errors is greater than 2 bits. Other numbers of errors of the second number of errors are within the scope of the present disclosure.

[0230] Other numbers of output signals, IO circuits, or bits as output signal Q are within the scope of the present disclosure.

[0231] In some embodiments, the ECC memory cell array 506 and the IO circuit group 516 are referred to as ECC circuit 505a.

[0232] In some embodiments, the ECC memory cell array 508 and the IO circuit group 518 are referred to as ECC circuit 505b.

[0233] In some embodiments, the ECC memory cell array 506 of the ECC circuit 505a is configured to store the third group of ECC check bits CB3, and the IO circuit 516 of the ECC circuit 505 is configured to read the third group of ECC check bits CB3 from the ECC memory cell array 506 of the ECC circuit 505b.

[0234] In some embodiments, the ECC memory cell array 508 of the ECC circuit 505b is configured to store the fourth group of ECC check bits CB4, and the IO circuit group 518 of the ECC circuit 505b is configured to read the fourth group of ECC check bits CB4 from the ECC storage cell array 508 of the ECC circuit 505b.

[0235] The ECC encoder / decoder circuit 332 a is configured to generate a third group of ECC check bits CB3 based on the first group of data D1 .

[0236] The ECC encoder / decoder circuit 332 b is configured to generate a fourth number of ECC check bits CB4 based on the second set of data D2 .

[0237] The ECC encoder / decoder circuit 332a and the ECC encoder / decoder circuit 332b are configured to correct at least a second number of errors in the first group of data D1 and the second group of data D2 based on the third group of ECC check bits CB3 and the fourth group of ECC check bits CB4.

[0238] In some embodiments, the ECC encoder / decoder circuits 332a and 332b are configured to correct at least a second number of errors in the output signals Q0, Q1, ..., Q15 and the output signals Q28, Q29, ..., Q43 based on the output signals Q16, Q17, Q18, Q19, Q20, Q21 and the output signals Q22, Q23, Q24, Q25, Q26, Q27.

[0239] In some embodiments, by including at least one of the ECC encoder / decoder circuits 332a and 332b, the ECC circuit 505a, or the ECC circuit 505b in the integrated circuit 500, the integrated circuit 500 has error correction capability, which improves DPPM compared to other approaches while also occupying less area than other approaches.

[0240] In some embodiments, by including at least one of ECC encoder / decoder circuits 332a and 332b, ECC circuit 505a, or ECC circuit 505b in integrated circuit 500, integrated circuit 500 has error correction capability, which improves DPPM while being more area efficient than other approaches.

[0241] Other configurations of integrated circuit 500 are also within the scope of the present disclosure.

[0242] Fig. 6A is a top view of an integrated circuit 600A according to some embodiments.

[0243] Integrated circuit 600A is an embodiment of a portion of integrated circuit 500, and thus similar detailed description is omitted. For example, integrated circuit 600A is an embodiment of a portion of integrated circuit 500, wherein the third group of ECC check bits CB3 is located on an inner portion (e.g., side 603a2 or 603b2) of memory cell array 601a1 or 601a2, and the fourth group of ECC check bits CB4 is located on an inner portion (e.g., side 603a3 or 603b3) of memory cell array 601b1 or 601b2, and thus similar detailed description is omitted.

[0244] In some embodiments, Fig. 6A is a layout of a portion of integrated circuit 600A.

[0245] The integrated circuit 600A includes a memory cell array 601 a 1 , a memory cell array 601 a 2 , a memory cell array 601 b 1 , a memory cell array 601 b 2 , an IO circuit group 610 a , and an IO circuit group 610 b .

[0246] IC 600A is Figure 4A For variations of the integrated circuit 400A, similar detailed descriptions are omitted.

[0247] and Figure 4A Compared with the integrated circuit 400A, the memory cell array 601a1 replaces the memory cell array 401a1, the memory cell array 601a2 replaces the memory cell array 401a2, the memory cell array 601b1 replaces the memory cell array 401b1, the memory cell array 601b2 replaces the memory cell array 401b2, the IO circuit group 610a replaces the IO circuit group 410a, and the IO circuit group 610b replaces the IO circuit group 410b, so similar detailed descriptions are omitted.

[0248] In some embodiments, the memory cell array 601a1 and the memory cell array 601a2 are Figure 5The corresponding upper and lower banks of the memory cell array 501a are described below, and similar detailed descriptions are omitted.

[0249] In some embodiments, the memory cell array 601b1 and the memory cell array 601b2 are Figure 5 The corresponding upper and lower banks of the memory cell array 501b are described below, and similar detailed descriptions are omitted.

[0250] In some embodiments, IO circuit group 610a is Figure 5 IO circuit group 510a, and similar detailed description is omitted. In some embodiments, IO circuit group 610b is Figure 5 IO circuit group 510b, and similar detailed description is omitted.

[0251] The memory cell array 601a1 includes the memory cell array 402a and the ECC memory cell array 606a.

[0252] and Figure 4A Compared to the integrated circuit 400A of FIG. 1 , the ECC memory cell array 606 a replaces the ECC memory cell array 406 a , and thus similar detailed description is omitted.

[0253] The ECC memory cell array 606 a is configured to store a third group of parity bits CB3 .

[0254] In some embodiments, the memory cell array 402a is Figure 5 In some embodiments, the ECC memory cell array 606a is an upper bank of the memory cell array 302, and similar detailed description is omitted. Figure 5 The upper bank of the ECC memory cell array 506 is shown in FIG. 5 , and similar detailed description is omitted.

[0255] The memory cell array 601a1 further includes a first end 603a1 and a second end 603a2 opposite to the first end 603a1.

[0256] The memory cell array 402a is located on a first end 603a1 of the memory cell array 601a1. The ECC memory cell array 606a is located on a second end 603a2 of the memory cell array 601a1.

[0257] The memory cell array 601a2 includes the memory cell array 402b and the ECC memory cell array 606b.

[0258] and Figure 4A Compared with the integrated circuit 400A, the ECC memory cell array 606b replaces the ECC memory cell array 406b, and thus similar detailed description is omitted.

[0259] The ECC memory cell array 606 b is configured to store a third group of parity bits CB3 .

[0260] In some embodiments, memory cell array 402b is Figure 5 In some embodiments, the ECC memory cell array 606b is a lower bank of the memory cell array 302, and similar detailed description is omitted. Figure 5 The lower bank of the ECC memory cell array 506 is shown in FIG. 5 , and similar detailed description is omitted.

[0261] The memory cell array 601 a 2 further includes a first end 603 b 1 and a second end 603 b 2 opposite to the first end 603 b 1 .

[0262] The memory cell array 402b is located on the first end 603b1 of the memory cell array 601a2. The ECC memory cell array 606b is located on the second end 603b2 of the memory cell array 601a2.

[0263] The memory cell array 601 b 1 includes the memory cell array 404 a and the ECC memory cell array 608 a .

[0264] The ECC memory cell array 608 a is configured to store a fourth set of parity bits CB4 .

[0265] In some embodiments, the memory cell array 404a is Figure 5 The upper bank of the memory cell array 304 is shown in FIG. 1 and similar detailed description is omitted. In some embodiments, the ECC memory cell array 608a is Figure 5 The upper bank of the ECC memory cell array 508 is shown in FIG. 5 , and similar detailed description is omitted.

[0266] The memory cell array 601 b 1 further includes a first end 603 a 3 and a second end 603 a 4 opposite to the first end 603 a 3 .

[0267] The memory cell array 404a is located on the second end 603a4 of the memory cell array 601b1. The ECC memory cell array 608a is located on the first end 603a3 of the memory cell array 601b1.

[0268] The memory cell array 601b2 includes the memory cell array 404b and the ECC memory cell array 608b.

[0269] The memory cell array 404b is configured to store a second set of data D2. The ECC memory cell array 608b is configured to store a fourth set of parity bits CB4.

[0270] In some embodiments, the memory cell array 404b is Figure 5 In some embodiments, the ECC memory cell array 608b is a lower bank of the memory cell array 304, and similar detailed description is omitted. Figure 5 The lower bank of the ECC memory cell array 508 is shown in FIG. 5 , and similar detailed description is omitted.

[0271] The memory cell array 601b2 further includes a first end 603b3 and a second end 603b4 opposite to the first end 603b3.

[0272] The memory cell array 404b is located on the second end 603b4 of the memory cell array 601b2. The ECC memory cell array 608b is located on the first end 603b3 of the memory cell array 601b2.

[0273] IO circuit group 610 a includes sense amplifier circuit group 412 and sense amplifier circuit group 616 .

[0274] In some embodiments, the sense amplifier circuit group 616 is Figure 5 The sense amplifier circuits 516a1, 516a2, 516a3, 516a4, 516a5 and 516a6 are described below, and similar detailed description is omitted.

[0275] The IO circuit group 610 a further includes a first end 610 a 1 and a second end 610 a 2 opposite to the first end 610 a 1 .

[0276] The sense amplifier circuit group 412 is located on the first end 610a1 of the IO circuit group 610a. The sense amplifier circuit group 616 is located on the second end 610a2 of the IO circuit group 610a.

[0277] IO circuit group 610 b includes sense amplifier circuit group 414 and sense amplifier circuit group 618 .

[0278] In some embodiments, the sense amplifier circuit group 618 is Figure 5 Sense amplifier circuits 518a1, 518a2, 518a3, 518a4, 518a5, and 518a6 are described below, and similar detailed descriptions are omitted.

[0279] The IO circuit group 610 b further includes a first end 610 b 1 and a second end 610 b 2 opposite to the first end 610 b 1 .

[0280] The sense amplifier circuit group 414 is located on the second end 610b2 of the IO circuit group 610b. The sense amplifier circuit group 618 is located on the first end 610b1 of the IO circuit group 610b.

[0281] Integrated circuit 400A achieves the advantages discussed herein.

[0282] Other configurations of integrated circuit 400A are within the scope of the present disclosure.

[0283] Figure 6B is a top view of an integrated circuit 600B according to some embodiments.

[0284] The integrated circuit 600B is an embodiment of a portion of the integrated circuit 500 , and thus similar detailed description is omitted.

[0285] IC 600B is Fig. 6A A similar detailed description is omitted for the variants of the integrated circuit 600A. Fig. 6A Compared to the integrated circuit 600A, the third group of ECC check bits CB3 are located on the outer portion of the memory cell array 601a1 or 601a2 (e.g., side 603a1 or 603b1), and the fourth group of ECC check bits CB4 are located on the outer portion of the memory cell array 601b1 or 601b2 (e.g., side 603a4 or 603b4), so similar detailed descriptions are omitted.

[0286] In some embodiments, Fig. 6A is a layout of a portion of integrated circuit 600B.

[0287] The memory cell array 402a is located on the second end 603a2 of the memory cell array 601a1. The ECC memory cell array 606a is located on the first end 603a1 of the memory cell array 601a1.

[0288] The memory cell array 402b is located on the second end 603b2 of the memory cell array 601a2. The ECC memory cell array 606b is located on the first end 603b1 of the memory cell array 601a2.

[0289] The memory cell array 404a is located on the first end 603a3 of the memory cell array 601b1. The ECC memory cell array 608a is located on the second end 603a4 of the memory cell array 601b1.

[0290] The memory cell array 404b is located on the first end 603b3 of the memory cell array 601b2. The ECC memory cell array 608b is located on the second end 603b4 of the memory cell array 601b2.

[0291] The sense amplifier circuit group 412 is located on the second end 610a2 of the IO circuit group 610a. The sense amplifier circuit group 616 is located on the first end 610a1 of the IO circuit group 610a.

[0292] The sense amplifier circuit group 414 is located on the first end 610b1 of the IO circuit group 610b. The sense amplifier circuit group 618 is located on the second end 610b2 of the IO circuit group 610b.

[0293] Integrated circuit 600B achieves the advantages discussed herein.

[0294] Other configurations of integrated circuit 600B are within the scope of the present disclosure.

[0295] Fig. 7A According to some embodiments, Figure 1 00A is a block diagram of an integrated circuit 700A used in the present invention.

[0296] Integrated Circuit 700A Figure 1 The integrated circuit 700A is an embodiment of the integrated circuit 100, and similar detailed description is omitted.

[0297] IC 700A is Figure 3 The integrated circuit 300 and Figure 5 In other words, in some embodiments, the integrated circuit 700A is a variant of the integrated circuit 500, and similar detailed description is omitted. Figure 3 The integrated circuit 300 and Figure 5 For example, in some embodiments, the integrated circuit 700A includes Figure 3 The memory cell group 301a and the IO circuit group 310a, and Figure 5 The memory cell group 501b and the I / O circuit group 510b are described in detail, and thus similar detailed descriptions are omitted.

[0298] In some embodiments, by including Figure 3 The memory cell group 301a and the IO circuit group 310a, and Figure 5 The integrated circuit 700A is configured to output an output signal Q, and the output signal Q includes 41 bits (e.g., output signals Q1-Q40). In some embodiments, the integrated circuit 700A is configured to use 9 bits of ECC protection for the output signal Q.

[0299] The integrated circuit 700A includes a memory cell group 301 a , a memory cell group 501 b , an IO circuit group 310 a , an IO circuit group 510 b , a word line driving circuit 330 , and a control circuit 332 .

[0300] In some embodiments, the ECC encoder / decoder circuits 332a and 332b are configured to correct at least a first number of errors in the output signals Q0, Q1, ..., Q15 and the output signals Q25, Q26, ..., Q40 based on the output signals Q16, Q17, Q18 and the output signals Q19, Q20, Q21, Q22, Q23, Q24.

[0301] and Figure 5 Compared to the integrated circuit 500 of FIG. 5 , in some embodiments, each of the sense amplifier circuits 314a1, 314a2, ..., 314a16 is configured to output a corresponding output signal Q25, Q26, ..., Q40 during a corresponding read operation. In some embodiments, each of the output signals Q25, Q26, ..., Q40 is a corresponding data value stored in the corresponding memory cell array 304a1, 304a2, ..., 304a15 or 304a16. In some embodiments, the output signals Q25, Q26, ..., Q40 are the second set of data D2 stored in the memory cell array 304.

[0302] In some embodiments, each sense amplifier circuit of the sense amplifier circuits 518a1, 518a2, 518a3, 518a4, 518a5, or 518a6 is configured to output a corresponding output signal Q19, Q20, Q21, Q22, Q23, or Q24. In some embodiments, each output signal Q19, Q20, Q21, Q22, Q23, Q24 is a corresponding data value stored in the corresponding ECC memory cell array 508a1, 508a2, 508a3, 508a4, 508a5, 508a6. In some embodiments, each output signal Q19, Q20, Q21, Q22, Q23, Q24 is a corresponding ECC check bit of the fourth group of ECC check bits CB4 generated by the ECC encoder / decoder circuit 332b based on the output signals Q25, Q26, ..., Q40. In some embodiments, the ECC encoder / decoder circuit 332 b uses the fourth group of ECC check bits CB4 (output signals Q19 , Q20 , Q21 , Q22 , Q23 , Q24 ) to determine whether an error occurs in the output signals Q25 , Q26 , . . . , Q40 .

[0303] In some embodiments, the integrated circuit 700A includes 41 IO circuits (eg, IO circuit groups 310a and 510b), and the integrated circuit 700 is configured to output 41 bits as the output signal Q (eg, output signals Q0-Q40).

[0304] Integrated circuit 700A achieves the advantages discussed herein.

[0305] Other configurations of integrated circuit 700A are within the scope of the present disclosure.

[0306] Figure 7B According to some embodiments, Figure 1 00B is a block diagram of an integrated circuit 700B used in.

[0307] IC 700B is Figure 3 The integrated circuit 300 and Figure 5 In other words, in some embodiments, the integrated circuit 700B is a variant of the integrated circuit 500, and similar detailed description is omitted. Figure 3 The integrated circuit 300 and Figure 5 For example, in some embodiments, the integrated circuit 700B includes Figure 5 The memory cell group 501a and the IO circuit group 510a, and Figure 3 The memory cell group 301b and the I / O circuit group 310b are described in detail, and thus similar detailed descriptions are omitted.

[0308] In some embodiments, by including Figure 5 The memory cell group 501a and the IO circuit group 510a, and Figure 3 The integrated circuit 700B is configured to output an output signal Q, and the output signal Q includes 41 bits (e.g., output signals Q0-Q40). In some embodiments, the integrated circuit 700B is configured to use 9 bits of ECC protection for the output signal Q.

[0309] The integrated circuit 700B includes a memory cell group 501 a , a memory cell group 301 b , an IO circuit group 510 a , an IO circuit group 310 b , a word line driving circuit 330 , and a control circuit 332 .

[0310] In some embodiments, the ECC encoder / decoder circuits 332a and 332b are configured to correct at least a first number of errors in the output signals Q0, Q1, ..., Q15 and the output signals Q25, Q26, ..., Q40 based on the output signals Q16, Q17, Q18, Q19, Q20, Q21 and the output signals Q22, Q23, Q24.

[0311] and Figure 3Compared to the integrated circuit 300 of FIG. 1 , in some embodiments, each of the sense amplifier circuits 314a1, 314a2, ..., 314a16 is configured to output a corresponding output signal Q25, Q26, ..., Q40 during a corresponding read operation. In some embodiments, each of the output signals Q25, Q26, ..., Q40 is a corresponding data value stored in the corresponding memory cell array 304a1, 304a2, ..., 304a15 or 304a16. In some embodiments, the output signals Q25, Q26, ..., Q40 are the second set of data D2 stored in the memory cell array 304.

[0312] In some embodiments, each sense amplifier circuit of the sense amplifier circuit 318a1, 318a2 or 318a3 is configured to output a corresponding output signal Q22, Q23 or Q24. In some embodiments, each output signal Q22, Q23, Q24 is a corresponding data value stored in the corresponding ECC memory cell array 308a1, 308a2, 308a3. In some embodiments, each output signal Q22, Q23, Q24 is a corresponding ECC check bit of the second group of ECC check bits CB2 generated by the ECC encoder / decoder circuit 332b based on the output signals Q25, Q26, ..., Q40. In some embodiments, the ECC encoder / decoder circuit 332b uses the second group of ECC check bits CB2 (output signals Q22, Q23, Q24) to determine whether an error occurs in the output signals Q25, Q26, ..., Q40.

[0313] In some embodiments, the integrated circuit 700B includes 41 IO circuits (eg, IO circuit groups 510a and 310b), and the integrated circuit 700B is configured to output 41 bits as the output signal Q (eg, output signals Q0-Q40).

[0314] Integrated circuit 700B achieves the advantages discussed herein.

[0315] Other configurations of integrated circuit 700B are within the scope of the present disclosure.

[0316] Fig. 8A is a top view of an integrated circuit 800A according to some embodiments.

[0317] Integrated circuit 800A is an embodiment of a portion of integrated circuit 700A or 700B, and thus similar detailed description is omitted. For example, integrated circuit 800A is an embodiment of a portion of integrated circuit 700A or 700B, wherein the first group of ECC check bits CB1 or the third group of ECC check bits CB3 are located on an outer portion (e.g., side 803a1) of memory cell array 801a1, and the second group of ECC check bits CB2 or the fourth group of ECC check bits CB4 are located on an inner portion (e.g., side 803a3) of memory cell array 801b1, and thus similar detailed description is omitted.

[0318] In some embodiments, Fig. 8A is a layout of a portion of integrated circuit 800A.

[0319] The integrated circuit 800A includes a memory cell array 801 a 1 and a memory cell array 801 b 1 .

[0320] IC 800A is Figure 4A A variation of the integrated circuit 400A is described below, and similar detailed description is omitted.

[0321] and Figure 4A Compared with the integrated circuit 400A, the memory cell array 801a1 replaces the memory cell array 401a1, and the memory cell array 801b1 replaces the memory cell array 401b1, so similar detailed descriptions are omitted.

[0322] The memory cell array 801a1 includes a memory cell array 802a and an ECC memory cell array 806a.

[0323] and Figure 4A Compared with the integrated circuit 400A, the memory cell array 802a replaces the memory cell array 402a, and the ECC memory cell array 806a replaces the ECC memory cell array 406a, so similar detailed descriptions are omitted.

[0324] The ECC memory cell array 806 a is configured to store the first group of ECC check bits CB1 or the third group of ECC check bits CB3 .

[0325] In some embodiments, the memory cell array 802a is Figure 7A-7B 302, and similar detailed description is omitted. In some embodiments, the ECC memory cell array 806a is Fig. 7A The ECC memory cell array 306 or Figure 7B The ECC memory cell array 506 is shown in FIG. 5 , and similar detailed description is omitted.

[0326] The memory cell array 801a1 further includes a first end 803a1 and a second end 803a2 opposite to the first end 803a1.

[0327] The memory cell array 802a is located on the second end 803a2 of the memory cell array 801a1. The ECC memory cell array 806a is located on the first end 803a1 of the memory cell array 801a1.

[0328] The memory cell array 801b1 includes a memory cell array 804a and an ECC memory cell array 808a.

[0329] and Figure 4A Compared with the integrated circuit 400A of FIG. 1 , the memory cell array 804 a replaces the memory cell array 404 a , and the ECC memory cell array 808 a replaces the ECC memory cell array 408 a , and thus similar detailed descriptions are omitted.

[0330] The ECC memory cell array 808 a is configured to store the second group of ECC check bits CB2 or the fourth group of ECC check bits CB4 .

[0331] In some embodiments, the memory cell array 804a is Figure 7A-7B 304, and similar detailed description is omitted. In some embodiments, the ECC memory cell array 808a is Fig. 7A The ECC memory cell array 508 or Figure 7B The ECC memory cell array 308 is shown in FIG. 1 , and similar detailed description is omitted.

[0332] The memory cell array 801b1 further includes a first end 803a3 and a second end 803a4 opposite to the first end 803a3.

[0333] The memory cell array 804a is located on the second end 803a4 of the memory cell array 801b1. The ECC memory cell array 808a is located on the first end 803a3 of the memory cell array 801b1.

[0334] Integrated circuit 800A achieves the advantages discussed herein.

[0335] Other configurations of integrated circuit 800A are within the scope of the present disclosure.

[0336] Figure 8B is a top view of an integrated circuit 800B according to some embodiments.

[0337] IC 800B is Fig. 8A A variation of the integrated circuit 800A is described below, and similar detailed description is omitted.

[0338] For example, integrated circuit 800B is an embodiment of a portion of integrated circuit 700A or 700B, wherein the first group of ECC check bits CB1 or the third group of ECC check bits CB3 are located on an inner portion (e.g., side 803a2) of memory cell array 801a1, and the second group of ECC check bits CB2 or the fourth group of ECC check bits CB4 are located on an outer portion (e.g., side 803a4) of memory cell array 801b1, and thus similar detailed descriptions are omitted.

[0339] exist Figure 8B In FIG. 8 , the memory cell array 802a is located on the first end 803a1 of the memory cell array 801a1. Figure 8B In the embodiment, the ECC memory cell array 806a is located on the second end 803a2 of the memory cell array 801a1.

[0340] exist Figure 8B In FIG. 8 , the memory cell array 804a is located on the first end 803a3 of the memory cell array 801b1. Figure 8B In the embodiment, the ECC memory cell array 808a is located on the second end 803a4 of the memory cell array 801b1.

[0341] Integrated circuit 800B achieves the advantages discussed herein.

[0342] Other configurations of integrated circuit 800B are within the scope of the present disclosure.

[0343] Fig. 9A is a top view of an integrated circuit 900A according to some embodiments.

[0344] IC 900A is Figure 6B For example, integrated circuit 900A is a variant of integrated circuit 600B, and similar detailed description is omitted. Figure 6B The integrated circuit 600B of the embodiment of the part, wherein the memory cell array and the ECC memory cell array are separated from each other by a distance d1 or d2, and wherein the IO circuit group and the ECC IO circuit group are separated from each other by a distance d1 or d2, and thus similar detailed description is omitted. In other words, the integrated circuit 900A is Figure 6B An embodiment of a portion of an integrated circuit 600B, wherein the memory cell array and the ECC memory cell array are part of a separate memory cell array separated from each other by an insulating material, and wherein the IO circuit group and the ECC IO circuit group are part of an independent IO circuit separated from each other by an insulating material.

[0345] and Figure 6B The IC 600B is compared to the Fig. 9A, one side of the memory cell array 402a and one side of the ECC memory cell array 606a are spaced apart from each other by a distance d1.

[0346] and Figure 6B The IC 600B is compared to the Fig. 9A , one side of the memory cell array 402b and one side of the ECC memory cell array 606b are spaced apart from each other by a distance d1.

[0347] and Figure 6B The IC 600B is compared to the Fig. 9A , one side of the memory cell array 404a and one side of the ECC memory cell array 608a are spaced apart from each other by a distance d2.

[0348] and Figure 6B The IC 600B is compared to the Fig. 9A , one side of the memory cell array 404b and one side of the ECC memory cell array 608b are spaced apart from each other by a distance d2.

[0349] In some embodiments, distance d1 is equal to distance d2. In some embodiments, distance d1 is different from distance d2.

[0350] and Figure 6B The IC 600B is compared to the Fig. 9A , one side of the IO circuit group 616 and one side of the IO circuit group 412 are spaced apart from each other by a distance d1.

[0351] and Figure 6B The IC 600B is compared to the Fig. 9A , one side of the IO circuit group 618 and one side of the IO circuit group 414 are spaced apart from each other by a distance d2.

[0352] Integrated circuit 900A achieves the advantages discussed herein.

[0353] Other configurations of integrated circuit 900A are within the scope of the present disclosure.

[0354] Fig. 9B is a top view of an integrated circuit 900B according to some embodiments.

[0355] IC 900B is Fig. 9A A variation of the integrated circuit 900A is described below, and similar detailed description is omitted. Fig. 9A Compared with the IC 900A, Fig. 9B The integrated circuit 900B further includes ECC control circuits 902a, 902b, 904a, and 904b.

[0356] The ECC control circuit 902a is located between the memory cell array 402a and the ECC memory cell 606a.

[0357] The ECC control circuit 902b is located between the memory cell array 404a and the ECC memory cell 608a.

[0358] The ECC control circuit 904a is located between the memory cell array 402b and the ECC memory cell 606b.

[0359] The ECC control circuit 904b is located between the memory cell array 404b and the ECC memory cell 608b.

[0360] In some embodiments, the ECC control circuit 902a, 902b, 904a or 904b is configured to enable or disable the corresponding ECC memory cell array 606a, 608a, 606b or 608b. In some embodiments, the ECC control circuit 902a, 902b, 904a or 904b is configured to enable or turn on the corresponding ECC memory cell array 606a, 608a, 606b or 608b when the ECC function is used. In some embodiments, the ECC control circuit 902a, 902b, 904a or 904b is configured to disable or turn off the corresponding ECC memory cell array 606a, 608a, 606b or 608b when the ECC function is not used.

[0361] Integrated circuit 900B achieves the advantages discussed herein.

[0362] Other configurations of integrated circuit 900B are within the scope of the present disclosure.

[0363] Fig.10 is a top view of integrated circuit 1000 according to some embodiments.

[0364] Integrated circuit 1000 is an embodiment of a portion of integrated circuit 900B, and thus similar detailed description is omitted. For example, integrated circuit 900B is an embodiment of ECC control circuit 902b, memory cell array 404a, and ECC memory cell 608a, and thus similar detailed description is omitted.

[0365] In some embodiments, Fig.10 is a layout of a portion of integrated circuit 1000 .

[0366] The integrated circuit 400A includes a memory cell array 1002 , an ECC memory cell array 1004 , and a circuit group 1006 .

[0367] In some embodiments, memory cell array 1002 is Fig. 9BThe memory cell array 404a, the ECC memory cell array 1004 is Fig. 9B The ECC memory cell array 608a is shown in FIG. 6 and similar detailed description is omitted.

[0368] In some embodiments, circuit group 1006 is Fig. 9B The ECC control circuit 902b is described below, and similar detailed description is omitted.

[0369] In some embodiments, circuit group 1006 includes a dummy memory cell group. In some embodiments, a dummy memory cell is a non-functional memory cell. In some embodiments, circuit group 1006 includes a stripe cell group. In some embodiments, a stripe cell group is a memory cell configured to provide voltage pickup and provide N-well or P-well biasing and is referred to as a "voltage pickup region". In some embodiments, the voltage pickup region can be used to reduce latch-up and is also referred to as a guard ring.

[0370] Integrated circuit 1000 achieves the advantages discussed herein.

[0371] Other configurations of integrated circuit 1000 are within the scope of the present disclosure.

[0372] Figure 11A-11B is a schematic diagram of corresponding circuits 1100A- 1100B according to some embodiments.

[0373] In some embodiments, circuits 1100A-1100B are Figure 2 The present invention is an embodiment of the memory circuit 200, and similar detailed description is omitted.

[0374] In some embodiments, circuits 1100A-1100B are one or more memory cells in memory cell array 102, 401a1, 401a2, 401b1, 401b2, 601a1, 601a2, 601b1, 601b2, 801a1 or 1002, memory circuit 200 or memory cell group 301a, 301b, 501a or 501b, and similar detailed description is omitted.

[0375] The circuit 1100A includes an eFuse Rfuse, a bit line BL, a word line WL0, and a programming circuit 1102a.

[0376] The eFuse Rfuse is located between the bit line BL and the programming circuit 1102a. The programming circuit 1102a is coupled between the eFuse Rfuse and a reference voltage source VSS.

[0377] The programming circuit 1102a includes at least an n-type metal oxide semiconductor (NMOS) transistor N1.

[0378] The gate of the NMOS transistor N1 is coupled to the word line WL0. The drain of the NMOS transistor N1 is coupled to the first end of the eFuse Rfuse. The source of the NMOS transistor N1 is coupled to the reference voltage source VSS. The second end of the eFuse Rfuse is coupled to the bit line BL0.

[0379] Two or more circuit elements are considered to be coupled based on a direct electrical connection, a resistive or reactive electrical connection, or an electrical connection that includes one or more additional circuit elements and can be controlled, for example, to constitute resistance or disconnection by a transistor or other switching device.

[0380] The circuit 1100B includes an eFuse Rfuse, a bit line BL, a word line WL0, and a programming circuit 1102b.

[0381] The eFuse Rfuse is located between the bit line BL and the programming circuit 1102b. The programming circuit 1102b is coupled between the eFuse Rfuse and a voltage source VDD.

[0382] The programming circuit 1102b includes at least a p-type metal oxide semiconductor (PMOS) transistor P1.

[0383] The gate of the PMOS transistor P1 is coupled to the word line WL0. The drain of the PMOS transistor P1 is coupled to the second end of the eFuse Rfuse. The source of the PMOS transistor P1 is coupled to the voltage source VDD. The first end of the eFuse Rfuse is coupled to the bit line BL0. In some embodiments, the bit line BL0 is configured to receive a bit line signal. In some embodiments, the bit line signal is equal to the voltage source VDDQ. In some embodiments, the bit line signal is equal to the reference voltage source VSS.

[0384] In some embodiments, the word line signal on word line WL0 is configured to select or deselect the bit cells comprising circuits 1100A- 1100B in a program or read operation.

[0385] Circuits 1100A-1100B are shown as 1 transistor 1 resistor (1T1R) eFuse devices. Other numbers of transistors or resistors for at least one of circuits 1100A or 1100B are within the scope of the present disclosure. Other memory types for at least one of circuits 1100A or 1100B are within the scope of the present disclosure.

[0386] The eFuse Rfuse is a circuit device including a conductive element that can be programmed by a current Ifuse whose magnitude exceeds a predetermined current level. In the non-programmed state, the resistance of the eFuse Rfuse is smaller than the resistance in the programmed state. In some embodiments, the eFuse Rfuse includes the following about Figure 12A-12B The eFuse R1 in question.

[0387] Each of the programming devices 1102A and 1102B is an IC device capable of switching between a conductive state and a resistive state in response to an input signal (e.g., a word line signal on word line WL0). In the conductive state, the programming device 1102A or 1102B has a low resistance current path between two current path terminals (not labeled), and in the resistive state, the programming devices 1102A and 1102B have a high resistance current path between the two current path terminals.

[0388] In the on state, the programming device 1102A or 1102B is capable of having a low resistance current path only for current values ​​up to a predetermined current saturation level, and having a significantly higher relative resistance path for current values ​​above the saturation level. In operation, in response to an increase in the voltage difference between the two current path terminals, the programming device 1102A or 1102B thus functions to limit the current value flowing between the two current path terminals.

[0389] In various embodiments, programming devices 1102A and 1102B are the same or different programming devices. The same programming devices have low resistance current paths having substantially the same resistance value and substantially the same saturation level. In various embodiments, different programming devices have low resistance current paths having substantially different resistance values ​​or substantially different saturation levels, one or both.

[0390] In some embodiments, one or both of the programming devices 1102A or 1102B include a transmission gate, a MOS transistor, a field effect transistor (FET), a FinFET (Fin Field Effect Transistor), a bipolar transistor, or other suitable IC device capable of switching between a conductive state and a resistive state in response to an input signal. In various embodiments, the programming devices 1102A and 1102B include FinFETs having the same number of fins and the same number of gates, or FinFETs having one or both of a different number of fins or gates.

[0391] Because programming devices 1102A and 1102B respond to separate input signals, programming devices 1102A and 1102B are individually controllable. In various embodiments, one or both of programming devices 1102A or 1102B are configured to respond to input signals having logic levels corresponding to respective conductive and resistive states.

[0392] exist Fig.11AIn the illustrated embodiment, the NMOS transistor N0 is configured to be in a conductive state in response to a word line signal having a high logic level, and to be in a resistive state in response to a word line signal having a low logic level.

[0393] exist Fig. 11B In the illustrated embodiment, the PMOS transistor P0 is configured to be in a conducting state in response to a word line signal having a low logic level, and to be in a resistive state in response to a word line signal having a high logic level.

[0394] Circuits 1100A-1100B achieve the advantages discussed herein.

[0395] Other configurations of circuits 1100A- 1100B are within the scope of the present disclosure.

[0396] Figure 12A-12B are cross-sectional views of respective integrated circuits 1200A- 1200B according to some embodiments.

[0397] Fig. 12A According to some embodiments Fig.11A or Fig. 11B A cross-sectional view of the eFuse Rfuse of the circuit 1100A or 1100B.

[0398] Fig. 12B According to some embodiments Fig.11A or Fig. 11B A cross-sectional view of the eFuse Rfuse of the circuit 1100A or 1100B.

[0399] The integrated circuit 1200A includes a conductive structure 1202a, a via 1204a, a conductive structure 1206a, and a programming device 1220a.

[0400] In some embodiments, the conductive structure 1206a is Figure 11A-11B In some embodiments, the programming device 1220a is Fig.11A or Fig. 11B The programming device 1102A or 1102B is not shown, and similar detailed description is omitted. The programming device 1220a is connected to the conductive structure 1202a, but for ease of description, Fig. 12A Not shown.

[0401] Conductive structure 1206a is above conductive structure 1202a and programming device 1220a. Conductive structure 1206a is connected to conductive structure 1202a through via 1204a. Via 1204a is located between conductive structure 1206a and conductive structure 1202a. Conductive structure 1202a is above programming device 1220a. Programming device 1220a is connected to conductive structure 1202a through other structures (not shown).

[0402] The conductive structure 1206 a has a length L1 in the first direction X.

[0403] The programming device 1220a has a length W1 in the first direction X.

[0404] In some embodiments, the conductive structure 1202a is on a metal-1 (M1) layer or a metal-3 (M3) layer. In some embodiments, the conductive structure 1206a is on a metal-2 (M2) layer or a metal-4 (M4) layer. In some embodiments, the via 1204a is on a via above the M1 (V1) layer or on a via above the M3 (V3) layer.

[0405] Fig. 12A Other configurations, arrangements on other layers, or numbers of structures are within the scope of the present disclosure.

[0406] The integrated circuit 1200B includes a conductive structure 1202b, a via 1204b, a conductive structure 1206b, and a programming device 1220b.

[0407] In some embodiments, the conductive structure 1206b is Figure 11A-11B In some embodiments, the programming device 1220b is Fig.11A or Fig. 11B The programming device 1102A or 1102B is not shown, and similar detailed description is omitted. The programming device 1220b is connected to the conductive structure 1202b, but for ease of description, Fig. 12B Not shown.

[0408] Conductive structure 1206b is above conductive structure 1202b and programming device 1220b. Conductive structure 1206b is connected to conductive structure 1202b through via 1204b. Via 1204b is located between conductive structure 1206b and conductive structure 1202b. Conductive structure 1202b is above programming device 1220b. Programming device 1220b is connected to conductive structure 1202b through other structures (not shown).

[0409] The conductive structure 1206 b has a length L2 in the first direction X. In some embodiments, the length L2 is greater than the length L1. In some embodiments, the length L2 is equal to the length L1.

[0410] The programming device 1220b has a length W2 in the first direction X. In some embodiments, the length W2 is greater than the length W1. In some embodiments, the length W2 is equal to the length W1.

[0411] In some embodiments, the conductive structure 1202b is on the M1 layer or the M3 layer. In some embodiments, the conductive structure 1206b is on the M2 layer or the M4 layer. In some embodiments, the via 1204b is on the V1 layer or the V3 layer.

[0412] Fig. 12B Other configurations, arrangements on other layers, or numbers of structures are within the scope of the present disclosure.

[0413] In some embodiments, conductive structure 1206a is an eFuse in memory cell array 1002, and conductive structure 1206b is an eFuse in ECC memory cell array 1004. In these embodiments, length L2 is greater than length L1, so conductive structure 1206a can be programmed with a lower voltage than conductive structure 1206b. In these embodiments, length W2 is greater than length W1, so conductive structure 1206a can be programmed with a lower voltage than conductive structure 1206b.

[0414] In some embodiments, conductive structure 1206a is on the M2 layer, via 1204a is on the V1 layer, conductive structure 1201a is on the M1 layer, and conductive structure 1206b is on the M4 layer, via 1204b is on the V3 layer, and conductive structure 1202b is on the M3 layer. In some embodiments, by placing conductive structure 1206a below conductive structure 1206b, integrated circuit 1200A has higher security than other methods of exposing eFuse in the memory cell array.

[0415] In some embodiments, conductive structure 1206b is an eFuse in memory cell array 1002, and conductive structure 1206a is an eFuse in ECC memory cell array 1004. In these embodiments, length L2 is greater than length L1, so conductive structure 1206b can be programmed with a lower voltage than conductive structure 1206a.

[0416] In these embodiments, the length W2 is greater than the length W1 and thus the conductive structure 1206b can be programmed with a lower voltage than the conductive structure 1206a.

[0417] In some embodiments, conductive structure 1206a is on the M4 layer, via 1204a is on the V3 layer, conductive structure 1202a is on the M2 layer, and conductive structure 1206b is on the M2 layer, via 1204b is on the V1 layer, and conductive structure 1202b is on the M1 layer. In some embodiments, by placing conductive structure 1206a above conductive structure 1206b, integrated circuit 1200B has higher security than other methods of exposing eFuse in ECC memory cell arrays.

[0418] Integrated circuits 1200A-1200B achieve the advantages discussed herein.

[0419] Other configurations of integrated circuits 1200A-1200B are also within the scope of the present disclosure.

[0420] Fig.13 is a functional flow chart of a corresponding method 1300 of manufacturing an IC device according to some embodiments. It should be understood that additional operations may be performed in Fig.13 The method 1300 shown is performed before, during, and / or after, and some other processes may be only briefly described herein.

[0421] In some embodiments, other operation orders of methods 1300 and 1500 are within the scope of the present disclosure. Methods 1300 and 1500 include exemplary operations, but these operations are not necessarily performed in the order shown. According to the spirit and scope of the disclosed embodiments, operations can be appropriately added, replaced, changed in order, and / or eliminated. In some embodiments, at least one or more operations of methods 1300 or 1500 are not performed.

[0422] In some embodiments, method 1300 may be used to manufacture or fabricate at least integrated circuit 100 , 300 , 400A, 400B, 500 , 600A, 600B, 700A, 700B, 800A, 800B, 900A, 900B, 1000 , 1200A, or 1200B, circuit 1100A or 1100B, or memory circuit 200 .

[0423] In operation 1302 of method 1300, a first group of memory cells is fabricated in a substrate. In some embodiments, the first group of memory cells of method 1300 includes at least one of memory cell arrays 301a, 401a1, 401a2, 501a, 601a1, 601a2, or 801a1. In some embodiments, the first group of memory cells of method 1300 includes at least first group of memory cells 102A.

[0424] In some embodiments, the first group of memory cells of method 1300 includes a first memory cell array and a first ECC memory cell array.

[0425] In some embodiments, the first memory cell array of method 1300 includes at least one of memory cell arrays 302 , 402 a , 402 b , 802 a , or 1002 or at least one of integrated circuits 1100A, 1100B, 1200A, or 1200B.

[0426] In some embodiments, the first ECC memory cell array of method 1300 includes at least one of ECC memory cell arrays 306, 406a, 406b, 506, 606a, 606b, 806a, or 1004 or at least one of integrated circuits 1100A, 1100B, 1200A, or 1200B.

[0427] In some embodiments, the first memory cell array of method 1300 includes a first group of fuse devices and a first group of programming devices. In some embodiments, the first group of fuse devices includes at least one of eFuse Rfuse or conductive structure 1206a or 1206b. In some embodiments, the first group of programming devices includes at least one of programming devices 1102A, 1102B, 1220a or 1220b.

[0428] In operation 1304 of method 1300, a second group of memory cells is fabricated in the substrate. In some embodiments, the second group of memory cells of method 1300 includes at least one of memory cell arrays 301b, 401b1, 401b2, 501b, 601b1, 601b2, or 801b1.

[0429] In some embodiments, the second group of memory cells of method 1300 includes at least second group of memory cells 102B.

[0430] In some embodiments, the second group of memory cells of method 1300 includes a second memory cell array and a second ECC memory cell array.

[0431] In some embodiments, the second memory cell array of method 1300 includes at least one of memory cell arrays 304, 404a, 404b, 804a, or 1002 or at least one of integrated circuits 1100A, 1100B, 1200A, or 1200B.

[0432] In some embodiments, the second ECC memory cell array of method 1300 includes at least one of ECC memory cell arrays 308, 408a, 408b, 508, 608a, 608b, 808a, or 1004 or at least one of integrated circuits 1100A, 1100B, 1200A, or 1200B.

[0433] In some embodiments, the second memory cell array of method 1300 includes a second group of fuse devices and a second group of programming devices. In some embodiments, the second group of fuse devices includes at least one of eFuse Rfuse or conductive structure 1206a or 1206b. In some embodiments, the second group of programming devices includes at least one of programming devices 1102A, 1102B, 1220a or 1220b.

[0434] In operation 1306 of method 1300, a word line driver circuit is fabricated in the substrate (330). In some embodiments, the word line driver circuit is located between the first group of memory cells and the second group of memory cells.

[0435] In some embodiments, the word line driver circuit includes at least one of word line drivers 330 .

[0436] In operation 1308 of method 1300, a first set of IO circuits are fabricated in the substrate. In some embodiments, the first set of IO circuits of method 1300 includes at least one of IO circuit groups 310a, 410a, 510a, or 610a.

[0437] In some embodiments, the first set of IO circuits of method 1300 includes a first set of sense amplifiers and a first set of ECC sense amplifiers.

[0438] In some embodiments, the first group of IO circuits of method 1300 includes at least one of sense amplifier groups 312 or 412 .

[0439] In some embodiments, the first set of IO circuits of method 1300 includes at least one of the first set of ECC sense amplifiers 316 , 416 , 516 , or 616 .

[0440] In operation 1310 of method 1300, a second set of IO circuits are fabricated in the substrate. In some embodiments, the second set of IO circuits of method 1300 includes at least one of IO circuit groups 310b, 410b, 510b, or 610b.

[0441] In some embodiments, the second set of IO circuits of method 1300 includes a second set of sense amplifiers and a second set of ECC sense amplifiers.

[0442] In some embodiments, the second group of IO circuits of method 1300 includes at least one of sense amplifier groups 314 or 414 .

[0443] In some embodiments, the second set of IO circuits of method 1300 includes at least one of the first set of ECC sense amplifiers 318 , 418 , 518 , or 618 .

[0444] In operation 1312 of method 1300 , control circuitry is fabricated in a substrate.

[0445] In some embodiments, the control circuitry of method 1300 includes at least one of controller 104, X-decoder circuit 106, Y-decoder circuit 108, ECC encoder / decoder 110, first ECC encoder / decoder 110A, second ECC encoder / decoder 110B, control circuit 332, ECC encoder / decoder circuit 332a, ECC encoder / decoder circuit 332b, ECC control circuit 902a, 902b, 904a or 904b, circuit group 1006, or system 1400.

[0446] In some embodiments, the control circuit of method 1300 includes a first ECC encoder / decoder circuit and a second ECC encoder / decoder circuit.

[0447] In some embodiments, the first ECC encoder / decoder circuit of method 1300 includes at least one of first ECC encoder / decoder 110A or ECC encoder / decoder circuit 332a.

[0448] In some embodiments, the second ECC encoder / decoder circuit of method 1300 includes at least one of the second ECC encoder / decoder 110B or the ECC encoder / decoder circuit 332b.

[0449] In some embodiments, the first ECC encoder / decoder circuit and the second ECC encoder / decoder circuit are located between the first group of IO circuits and the second group of IO circuits.

[0450] In some embodiments, at least one or more of operations 1302, 1304, 1306, 1308, 1310, or 1312 includes one or more of operations 1302a, 1302b, 1302c, or 1302d.

[0451] In some embodiments, operation 1302a includes fabricating one or more transistors, memory devices, or fuses described herein in a semiconductor wafer or substrate.

[0452] In some embodiments, operation 1302a includes fabricating source and drain regions of the transistor group in the first well. In some embodiments, the first well includes a p-type dopant. In some embodiments, the p-dopant includes boron, aluminum, or other suitable p-type dopant. In some embodiments, the first well includes an epitaxial layer grown on a substrate. In some embodiments, the epitaxial layer is doped by adding a dopant during an epitaxial process. In some embodiments, the epitaxial layer is doped by ion implantation after the epitaxial layer is formed. In some embodiments, the first well is formed by doping the substrate. In some embodiments, the doping is performed by ion implantation. In some embodiments, the dopant concentration of the first well is in the range of 1 x 10 12 Atom / cm 3 Up to 1x10 14 Atom / cm 3 .

[0453] In some embodiments, the first well includes an n-type dopant. In some embodiments, the n-type dopant includes phosphorus, arsenic, or other suitable n-type dopant. In some embodiments, the n-type dopant concentration is about 1 x 10 12 Atom / cm 3 About 1x10 14 Atom / cm 3 within the range.

[0454] In some embodiments, the formation of the source / drain component includes removing a portion of the substrate to form a recess at the edge of the spacer, and then performing a filling process by filling the recess in the substrate. In some embodiments, after removing the pad oxide layer or the sacrificial oxide layer, the recess is etched, for example, by wet etching or dry etching. In some embodiments, an etching process is performed to remove a portion of the top surface of the active area adjacent to the isolation region (e.g., STI region). In some embodiments, the filling process is performed by an epitaxial (epi) process. In some embodiments, a growth process performed simultaneously with an etching process is used to fill the recess, wherein the growth rate of the growth process is greater than the etching rate of the etching process. In some embodiments, a combination of a growth process and an etching process is used to fill the recess. For example, a layer of material is grown in the recess, and then the grown material is etched to remove part of the material. A subsequent growth process is then performed on the etched material until the desired thickness of the material in the recess is obtained. In some embodiments, the growth process continues until the top surface of the material is above the top surface of the substrate. In some embodiments, the growth process is continued until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, a portion of the first well is removed by an isotropic or anisotropic etching process. The etching process selectively etches the first well without etching the gate structure and any spacers. In some embodiments, the etching process is performed using reactive ion etching (RIE), wet etching or other suitable techniques. In some embodiments, semiconductor material is deposited in the recess to form a source / drain component. In some embodiments, an epitaxial process is performed to deposit the semiconductor material in the recess. In some embodiments, the epitaxial process includes a selective epitaxial growth (SEG) process, a CVD process, a molecular beam epitaxy (MBE), other suitable processes and / or combinations thereof. The epitaxial process uses gaseous and / or liquid precursors that interact with the composition of the substrate. In some embodiments, the source / drain component includes epitaxially grown silicon (epi-Si), silicon carbide or silicon germanium. In some cases, the source / drain component of the IC device associated with the gate structure is in-situ doped or undoped during the epitaxial process. When the source / drain component is undoped during the epitaxial process, in some cases, the source / drain component is doped during a subsequent process. The subsequent doping process is achieved by ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes and / or combinations thereof. In some embodiments, after forming the source / drain features and / or after the subsequent doping process, the source / drain features are further exposed to an annealing process.

[0455] In some embodiments, operation 1302a also includes operation 1302b. In some embodiments, operation 1302b includes forming first gate regions of the first group of transistors.

[0456] In some embodiments, operation 1302 further includes operation 1302c. In some embodiments, operation 1302c includes forming second gate regions of the second group of transistors.

[0457] In some embodiments, the first gate region and the second gate region are located between the drain region and the source region. In some embodiments, the first gate region and the second gate region are above the first well and the substrate. In some embodiments, the first and second gate regions of manufacturing operations 702a and 702c include performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, the deposition process includes chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or other processes suitable for depositing one or more material layers. In some embodiments, manufacturing the first gate region and the second gate region includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, manufacturing the first gate region and the second gate region includes forming a gate electrode or a pseudo gate electrode. In some embodiments, manufacturing the gate region includes depositing or growing at least one dielectric layer, such as a gate dielectric. In some embodiments, the gate region is formed using doped or undoped polysilicon. In some embodiments, the first gate region and the second gate region include a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0458] In some embodiments, operation 1302 also includes operation 1302d. In some embodiments, operation 1302d includes depositing a first conductive material on at least one of the first metal layer, the second metal layer, or the third metal layer to form at least one of the corresponding first, second, or third sets of conductors.

[0459] In some embodiments, one or more of operations 1302, 1304, 1306, 1308, 1310, or 1312 of method 1300 or one or more of operations 1302a, 1302b, 1302c, or 1302d include forming an opening in an insulating layer (not shown) on a substrate using a combination of photolithography and material removal processes. In some embodiments, the photolithography process includes patterning a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the photolithography process includes forming a hard mask, an anti-reflective structure, or another suitable photolithography structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, an RIE process, laser drilling, or other suitable etching processes. The opening is then filled with a conductive material, such as copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. In some embodiments, CVD, PVD, sputtering, ALD, or other suitable formation processes are used to fill the opening.

[0460] Fig.14 is a schematic diagram of a system 1400 according to some embodiments. In some embodiments, the system 1400 is at least Figure 1 The embodiments of the controller 104 are described below, and thus similar detailed description is omitted.

[0461] In some embodiments, system 1400 is an embodiment of at least one of the ECC encoder / decoder 110, the first ECC encoder / decoder 110A, the second ECC encoder / decoder 110B, the ECC encoder / decoder circuit 332a, and the ECC encoder / decoder circuit 332b, so similar detailed description is omitted.

[0462] In some embodiments, system 1400 is an embodiment of at least one of ECC control circuit 902a, ECC control circuit 904b, ECC control circuit 904a, ECC control circuit 904b, or circuit group 1006, and thus similar detailed description is omitted.

[0463] In some embodiments, system 1400 includes one or more of a logic circuit, an XOR tree, an ECC encoder, an ECC decoder, a syndrome generator, or an error logic circuit, and thus similar detailed descriptions are omitted.

[0464] In some embodiments, the system 1400 is configured to control one or more of the controller 104, the memory cell array 102, the X-decoder circuit 106, the Y-decoder circuit 108, the ECC encoder / decoder 110, the memory circuit 200, the first ECC encoder / decoder 110A, the second ECC encoder / decoder 110B, the ECC encoder / decoder circuit 332a, the ECC encoder / decoder circuit 332b, the ECC control circuit 902a, the ECC control circuit 902b, the ECC control circuit 904a, the ECC control circuit 904b, or the circuit group 1006. In some embodiments, the system 1400 is configured to perform one or more operations described herein, including the method 1500.

[0465] The system 1400 includes a hardware processor 1402 and a non-transitory computer-readable storage medium 1404 (eg, memory 1404 ) encoded with (ie, storing) computer program code 1406 (ie, a set of executable instructions 1406 ).

[0466] The computer-readable storage medium 1404 is configured to interface with at least one of the controller 104, the memory cell array 102, the X-decoder circuit 106, the Y-decoder circuit 108, the ECC encoder / decoder 110, the memory circuit 200, the first ECC encoder / decoder circuit 110A, the second ECC encoder / decoder 110B, the ECC encoder / decoder circuit 332a, the ECC encoder / decoder circuit 332b, the ECC control circuit 902a, the ECC control circuit 902b, the ECC control circuit 904a, the ECC control circuit 904b, or the circuit group 1006.

[0467] The processor 1402 is electrically coupled to the computer-readable storage medium 1404 via a bus 1408. The processor 1402 is also electrically coupled to an I / O interface 1410 via the bus 1408. A network interface 1412 is also electrically coupled to the processor 1402 via the bus 1408. The network interface 1412 is connected to a network 1414, enabling the processor 1402 and the computer-readable storage medium 1404 to be connected to external elements via the network 1414. The processor 1402 is configured to execute computer program code 1406 (non-transitory instructions) encoded in the computer-readable storage medium 1404 so that the system 1400 can be used to perform at least a portion or all of the operations described in the method 1500. In some embodiments, the network 1414 is not part of the system 1400.

[0468] In some embodiments, processor 1402 is a central processing unit (CPU), a multi-processor, a distributed processing read circuit, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0469] In some embodiments, the computer-readable storage medium 1404 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor reading circuit (or device or apparatus). For example, the computer-readable storage medium 1404 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disks, the computer-readable storage medium 1404 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0470] In some embodiments, the storage medium 1404 stores computer program code 1406 configured to cause the system 1400 to perform at least one or more operations of the method 1500. In some embodiments, the storage medium 1404 also stores information for performing at least the method 1500 and information generated during the performance of at least the method 1500, such as the table 1416, the parity check matrix, the data group 1420, the check bit group 1422, the syndrome 1424, the signal group 1426 and the user interface 1428, and / or a set of executable instructions for performing at least one or more operations of the method 1500.

[0471] In some embodiments, storage medium 1404 stores instructions (e.g., computer program code 1406) for interfacing with at least one of controller 104, memory cell array 102, X-decoder circuit 106, Y-decoder circuit 108, ECC encoder / decoder 110, memory circuit 200, first ECC encoder / decoder 110A, second ECC encoder / decoder 110B, ECC encoder / decoder circuit 332a, ECC encoder / decoder circuit 332b, ECC control circuit 902a, ECC control circuit 902b, ECC control circuit 904a, ECC control circuit 904b, or circuit group 1006. The instructions (e.g., computer program code 1406) enable the processor 1402 to generate a program that can be used by the controller 104, the memory cell array 102, the X-decoder circuit 106, the Y-decoder circuit 108, the ECC encoder / decoder 110, the memory circuit 200, the first ECC encoder / decoder 110A, the second ECC encoder / decoder 110B, the ECC encoder / decoder circuit 332a, the ECC encoder / decoder circuit 332b, the ECC control circuit 1500, or instructions read by at least one of the ECC control circuits 902a, 902b, 904a, 904b, or group of circuits 1006 to effectively implement one or more operations of at least method 1500 during operation of integrated circuit 100, 300, 400A, 400B, 500, 600A, 600B, 700A, 700B, 800A, 800B, 900A, 900B, 1000, 1200A, or 1200B.

[0472] System 1400 includes an input / output interface 1410. Input / output interface 1410 is connected to an external circuit. In some embodiments, I / O interface 1410 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys for transmitting information and commands to processor 1402.

[0473] System 1400 also includes a network interface 1412 connected to processor 1402. Network interface 1411 allows system 1400 to communicate with network 1414, and one or more other computer reading circuits are connected to network 1414. Network interface 1412 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS or WCDMA; or a wired network interface, such as Ethernet, USB or IEEE-884. In some embodiments, at least method 1500 is implemented in two or more systems 1400, and information such as tables, parity check matrices, data groups, check bit groups, syndromes, signal groups and user interfaces are exchanged between different systems 1400 through network 1414.

[0474] The system 1400 is configured to receive information related to a data set through the I / O interface 1410 or the network interface 1412. The information is stored in the computer readable medium 1404 as a data set 1420. In some embodiments, the data set includes at least a first set of data D1 or a second set of data S2.

[0475] The system 1400 is configured to receive information related to the check bit group through the I / O interface 1410 or the network interface 1412. The information is stored in the computer readable medium 1404 as the check bit group 1422. In some embodiments, the check bit group includes at least a first group of check bits CB1, a second group of check bits CB2, a third group of check bits CB3, or a fourth group of check bits CB4.

[0476] System 1400 is configured to receive information related to data groups and check bit groups via I / O interface 1410 or network interface 1412. This information is transmitted to processor 1402 via bus 1408 to determine a value for generating a syndrome. The syndrome is then stored in computer readable medium 1404 as syndrome 1424. In some embodiments, the syndrome can be used to implement ECC as described herein.

[0477] System 1400 is configured to receive information related to a signal group through I / O interface 1410 or network interface 1412. The information is stored in computer readable medium 1404 as signal group 1426. In some embodiments, the signal group includes at least one or more of the signals described herein.

[0478] The system 1400 is configured to receive information related to the user interface through the I / O interface 1410 or the network interface 1412. The information is stored in the computer readable medium 1404 as the user interface 1428.

[0479] Fig.15 is a flow chart of a method 1500 of operating an integrated circuit according to some embodiments.

[0480] In some embodiments, Fig.15 is to operate the integrated circuit 100, 300, 400A, 400B, 500, 600A, 600B, 700A, 700B, 800A, 800B, 900A, 900B, 1000, 1200A or 1200B, the circuit 1100A or 1100B, the memory circuit 200 or Fig.14 It should be understood that additional operations may be performed in the system 1400. Fig.15 The method 1500 shown is performed before, during and / or after, and some other operations may only be briefly described herein. In some embodiments, other operation sequences of the method 1500 are within the scope of the present disclosure. In some embodiments, one or more operations of the method 1500 are not performed.

[0481] The method 1500 includes exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be added, substituted, reordered, and / or eliminated as appropriate, consistent with the spirit and scope of the disclosed embodiments. It should be understood that the method 1500 utilizes the integrated circuit 100, 300, 400A, 400B, 500, 600A, 600B, 700A, 700B, 800A, 800B, 900A, 900B, 1000, 1200A, or 1200B, the circuit 1100A or 1100B, the memory circuit 200 or Fig.14 One or more features of system 1400.

[0482] In operation 1502 of method 1500, a programming operation of a first group of memory cells is performed.

[0483] In some embodiments, the first group of memory cells of method 1500 includes at least one memory cell. The first group of memory cells of method 1300 includes at least one of memory cell arrays 301a, 401a1, 401a2, 501a, 601a1, 601a2, or 801a1, or the second group of memory cells of method 1300 includes at least one of memory cell arrays 301, 401b1, 401b2, 501b, 601b1, 601b2, or 801b1.

[0484] In some embodiments, operation 1502 is performed by at least one of X-decoder circuit 106 or Y-decoder circuit 108 .

[0485] In some embodiments, operation 1502 includes one or more of operations 1504 , 1506 , or 1508 .

[0486] In some embodiments, the first group of memory cells of method 1500 includes at least one of a first group of memory cells and a second group of memory cells.

[0487] In operation 1504 of method 1500 , a first set of data is stored in a first set of memory cells and a second set of data is stored in a second set of memory cells.

[0488] In some embodiments, the first group of memory cells of method 1500 includes at least one of memory cell arrays 301a, 401a1, 401a2, 501a, 601a1, 601a2, or 801a1. In some embodiments, the first group of memory cells of method 1500 includes at least first group of memory cells 102A.

[0489] In some embodiments, the second group of memory cells of method 1500 includes at least one of memory cell arrays 301b, 401b1, 401b2, 501b, 601b1, 601b2, or 801b1.

[0490] In some embodiments, the second group of memory cells of method 1500 includes at least second group of memory cells 102B.

[0491] In some embodiments, operation 1504 is performed by at least one of X-decoder circuit 106 or Y-decoder circuit 108 .

[0492] In operation 1506 of method 1500 , a first set of check bits is generated in response to the first set of data, and a second set of check bits is generated in response to the first set of check bits.

[0493] In some embodiments, the first group of parity bits of method 1500 includes at least the first group of parity bits CB1 or the third group of parity bits CB3.

[0494] In some embodiments, the second group of check bits of method 1500 includes at least the second group of check bits CB2 or the fourth group of check bits CB4.

[0495] In some embodiments, operation 1506 is performed by ECC encoder / decoder 110, first ECC encoder / decoder 110A, second ECC encoder / decoder 110B, control circuit 332, ECC encoder / decoder circuit 332a, ECC encoder / decoder circuit 332b, ECC control circuit 902a, 902b, 904a or 904b, circuit group 1006 or system 1400.

[0496] In operation 1508 of method 1500 , a first set of parity bits are stored in a first ECC memory cell array, and a second set of parity bits are stored in a second ECC memory cell array.

[0497] In some embodiments, the first ECC memory cell array of method 1500 includes at least one of ECC memory cell arrays 306, 406a, 406b, 506, 606a, 606b, 806a, or 1004 or at least one of integrated circuits 1100A, 1100B, 1200A, or 1200B.

[0498] In some embodiments, the second memory cell array of method 1500 includes at least one of memory cell arrays 304, 404a, 404b, 804a, or 1002 or at least one of integrated circuits 1100A, 1100B, 1200A, or 1200B.

[0499] In some embodiments, operation 1508 is performed by at least one of X-decoder circuit 106 or Y-decoder circuit 108 .

[0500] In operation 1510 of method 1500, a read operation of a first group of memory cells is performed.

[0501] In some embodiments, operation 1510 is performed by at least one of IO circuit groups 310a, 410a, 510a, or 610a or IO circuit groups 310b, 410b, 510b, or 610b.

[0502] In some embodiments, operation 1510 includes one or more of operations 1512 or 1514 .

[0503] In operation 1512 of method 1500, a first set of data is read from a first set of memory cells and a second set of data is read from a second set of memory cells.

[0504] In some embodiments, operation 1512 is performed by at least one of the sense amplifier groups 312 or 412 or the sense amplifier groups 314 or 414 .

[0505] In operation 1514 of method 1500 , a first set of parity bits are read from the first ECC memory cell array, and a second set of parity bits are read from the second ECC memory cell array.

[0506] In some embodiments, operation 1516 is performed by at least one of the first set of ECC sense amplifiers 316 , 416 , 516 , or 616 or the second set of ECC sense amplifiers 318 , 418 , 518 , or 618 .

[0507] In operation 1516 of method 1500 , it is determined whether data read from the first memory cell array or the second memory cell array contains an error based on the first set of parity bits or the second set of parity bits.

[0508] In some embodiments, operation 1516 is performed by at least one of the controller 104, the ECC encoder / decoder 110, the first ECC encoder / decoder 110A, the second ECC encoder / decoder 110B, the control circuit 332, the ECC encoder / decoder circuit 332a, the ECC encoder / decoder circuit 332b, the ECC control circuit 902a, 902b, 904a or 904b, the circuit group 1006 or the system 1400.

[0509] In some embodiments, the determination of operation 1516 is performed by at least one of the controller 104, the ECC encoder / decoder 110, the first ECC encoder / decoder 110A, the second ECC encoder / decoder 110B, the control circuit 332, the ECC encoder / decoder circuit 332a, the ECC encoder / decoder circuit 332b, the ECC control circuit 902a, 902b, 904a or 904b, the circuit group 1006 or the system 1400.

[0510] In some embodiments, operation 1516 includes generating a syndrome and using the syndrome to determine whether data read from the first memory cell array or the second memory cell array contains an error.

[0511] In some embodiments, if the determination of operation 1516 is “NO”, the method 1500 proceeds to operation 1518 .

[0512] In some embodiments, if the determination of operation 1516 is “yes,” method 1500 proceeds to operation 1520 .

[0513] In operation 1518 of method 1500, method 1500 remains in an idle state until another read or program operation.

[0514] In operation 1520 of method 1500 , data read from the first or second memory cell array is corrected based on the ECC.

[0515] In some embodiments, operation 1520 is performed by at least one of the controller 104, the ECC encoder / decoder 110, the first ECC encoder / decoder 110A, the second ECC encoder / decoder 110B, the control circuit 332, the ECC encoder / decoder circuit 332a, the ECC encoder / decoder circuit 332b, the ECC control circuit 902a, 902b, 904a or 904b, the circuit group 1006 or the system 1400.

[0516] By operating at least method 1500 , the integrated circuit operates to achieve the benefits described herein.

[0517] In some embodiments, at least a portion of method 1500 is implemented as a standalone software application executed by a processor. In some embodiments, at least a portion of method 1500 is implemented as a software application that is part of an additional software application. In some embodiments, at least a portion of method 1500 is implemented as a plug-in for a software application. In some embodiments, at least a portion of method 1500 is implemented as a software application that is part of an ECC tool. In some embodiments, at least a portion of method 1500 is implemented as a software application used by an ECC tool.

[0518] In some embodiments, one or more operations of method 1500 are not performed. Figure 1-Figure 15 The various logic circuits shown in are for illustrative purposes. The embodiments of the present disclosure are not limited to specific logic circuits, and Figure 1-Figure 15 One or more of the logic circuits shown in the figure may be replaced with one or more corresponding logic circuits having different functions or equivalent functions. Similarly, the low logic values ​​or high logic values ​​of various signals used in the above description are also for illustration. When signals are activated and / or deactivated, the embodiments of the present disclosure are not limited to specific logic values. Selecting different logic values ​​is within the scope of various embodiments. Figure 1-Figure 15 Selecting a different number of logic circuits is within the scope of various embodiments.

[0519] It will be readily apparent to one of ordinary skill in the art that one or more of the disclosed embodiments achieve one or more of the above advantages. After reading the above description, one of ordinary skill in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the attached claims and their equivalents.

[0520] One aspect of the present specification relates to an integrated circuit. The integrated circuit includes a first group of memory cells configured to store a first group of data, a second group of memory cells configured to store a second group of data, a first group of input-output (IO) circuits coupled to the first group of memories, a second group of IO circuits coupled to the second group of memory cells, a first error correction code (ECC) circuit configured to store a first number of ECC bits, a second ECC circuit configured to store a second number of ECC bits; and a first ECC encoder / decoder circuit configured to correct at least a first number of errors in the first group of data and the second group of data based on the first number of ECC bits and the second number of ECC bits.

[0521] In some embodiments, the first ECC circuit includes: a first ECC memory cell array; a second ECC memory cell array; a third ECC memory cell array; a first sense amplifier coupled to the first ECC memory cell array; a second sense amplifier coupled to the second ECC memory cell array; and a third sense amplifier coupled to the third ECC memory cell array.

[0522] In some embodiments, the second ECC circuit includes: a fourth ECC memory cell array; a fifth ECC memory cell array; a sixth ECC memory cell array; a fourth sense amplifier coupled to the fourth ECC memory cell array; a fifth sense amplifier coupled to the fifth ECC memory cell array; and a sixth sense amplifier coupled to the sixth ECC memory cell array.

[0523] In some embodiments, the first ECC circuit also includes: a seventh ECC memory cell array; an eighth ECC memory cell array; a ninth ECC memory cell array; a seventh sense amplifier coupled to the seventh ECC memory cell array; an eighth sense amplifier coupled to the eighth ECC memory cell array; and a ninth sense amplifier coupled to the ninth ECC memory cell array.

[0524] In some embodiments, the first ECC circuit further includes: a tenth ECC memory cell array; an eleventh ECC memory cell array; a twelfth ECC memory cell array; a tenth sense amplifier coupled to the tenth ECC memory cell array; an eleventh sense amplifier coupled to the eleventh ECC memory cell array; and a twelfth sense amplifier coupled to the twelfth ECC memory cell array.

[0525] In some embodiments, the first number of ECC bits is 3 bits; the second number of ECC bits is 3 bits; and the first number of errors is 1 bit.

[0526] In some embodiments, the first number of ECC bits is 3 bits; the second number of ECC bits is 6 bits; and the first number of errors is 1 bit.

[0527] In some embodiments, the first number of ECC bits is 6 bits; the second number of ECC bits is 6 bits; and the first number of errors is 2 bits.

[0528] Another aspect of the present specification relates to an integrated circuit. The integrated circuit includes a first memory cell array, a second memory cell array, a control circuit coupled to the first memory cell array and the second memory cell array, a first group of sense amplifiers coupled to the first memory cell array, a second group of sense amplifiers coupled to the second memory cell array, a first error correction code (ECC) circuit configured to store a first group of ECC check bits, a second ECC circuit configured to store a second group of ECC check bits, a first ECC encoder / decoder circuit configured to generate a first group of ECC check bits based on a first group of data stored in the first memory cell array, and a second ECC encoder / decoder circuit configured to generate a second group of ECC check bits based on a second group of data stored in the second memory cell array. In some embodiments, the first ECC circuit and the second ECC circuit are configured to correct at least a first number of errors in the first group of data and the second group of data based on the first group of ECC check bits and the second group of ECC check bits.

[0529] In some embodiments, the first ECC circuit includes: a first ECC memory cell array; a second ECC memory cell array; a third ECC memory cell array; a first sense amplifier coupled to the first ECC memory cell array; a second sense amplifier coupled to the second ECC memory cell array; and a third sense amplifier coupled to the third ECC memory cell array.

[0530] In some embodiments, the second ECC circuit includes: a fourth ECC memory cell array; a fifth ECC memory cell array; a sixth ECC memory cell array; a fourth sense amplifier coupled to the fourth ECC memory cell array; a fifth sense amplifier coupled to the fifth ECC memory cell array; and a sixth sense amplifier coupled to the sixth ECC memory cell array.

[0531] In some embodiments, the first ECC memory cell array, the second ECC memory cell array, and the third ECC memory cell array are part of the first memory cell array; and the fourth ECC memory cell array, the fifth ECC memory cell array, and the sixth ECC memory cell array are part of the second memory cell array.

[0532] In some embodiments, the first sense amplifier, the second sense amplifier, and the third sense amplifier are part of a first group of sense amplifiers; and the fourth sense amplifier cell array, the fifth sense amplifier, and the sixth sense amplifier are part of a second group of sense amplifiers.

[0533] In some embodiments, the first memory cell array includes a first end and a second end opposite to the first end; the second memory cell array includes a third end and a fourth end opposite to the third end; the first ECC memory cell array, the second ECC memory cell array, and the third ECC memory cell array are located on the first end of the first memory cell array; and the fourth ECC memory cell array, the fifth ECC memory cell array, and the sixth ECC memory cell array are located on the third end of the second memory cell array.

[0534] In some embodiments, the first end of the first memory cell array is adjacent to the third end of the second memory cell array.

[0535] In some embodiments, the first end of the first memory cell array is adjacent to the fourth end of the second memory cell array.

[0536] In some embodiments, the second end of the first memory cell array is adjacent to the fourth end of the second memory cell array.

[0537] In some embodiments, the first ECC memory cell array, the second ECC memory cell array, and the third ECC memory cell array are separated from the first memory cell array by a first distance in the first direction; and the fourth ECC memory cell array, the fifth ECC memory cell array, and the sixth ECC memory cell array are separated from the second memory cell array by a second distance in the first direction.

[0538] In some embodiments, the first memory cell array, the second memory cell array, the first ECC memory cell array, the second ECC memory cell array, the third ECC memory cell array, the fourth ECC memory cell array, the fifth ECC memory cell array, and the sixth ECC memory cell array include one-time programmable memory.

[0539] Another aspect of the specification relates to a method of manufacturing an integrated circuit. In some embodiments, the method includes manufacturing a first group of memory cells in a substrate, the first group of memory cells including a first memory cell array and a first ECC memory cell array. In some embodiments, the method also includes manufacturing a second group of memory cells in the substrate, the second group of memory cells including a second memory cell array and a second ECC memory cell array. In some embodiments, the method also includes manufacturing a word line driver circuit in the substrate, the word line driver being located between the first group of memory cells and the second group of memory cells. In some embodiments, the method also includes manufacturing a first group of input / output (IO) circuits in the substrate, the first group of IO circuits including a first group of sense amplifiers and a first group of error correction code (ECC) sense amplifiers. In some embodiments, the method also includes manufacturing a second group of IO circuits in the substrate, the second group of I / O circuits including a second group of sense amplifiers and a second group of ECC sense amplifiers. In some embodiments, the method also includes manufacturing a control circuit in the substrate, the control circuit including a first ECC encoder / decoder circuit and a second ECC encoder / decoder circuit, the first ECC encoder / decoder circuit and the second ECC encoder / decoder circuit being located between the first group of IO circuits and the second group of IO circuits.

[0540] Another aspect of the present specification relates to a method of operating an integrated circuit, the method comprising: performing a programming operation of a first group of memory cells, performing the programming operation of the first group of memory cells comprising: storing a first group of data in a first memory cell array and storing a second group of data in a second memory cell array; generating a first group of check bits in response to the first group of data and generating a second group of check bits in response to the second group of data; and storing the first group of check bits in a first ECC memory cell array and storing the second group of check bits in a second ECC memory cell array. The method also comprises: performing a read operation of the first group of memory cells; in response to determining that the data read from the first memory cell array or the second memory cell array contains an error based on the first group of check bits and the second group of check bits, correcting the read data from the first memory cell array or the second memory cell array.

[0541] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. An integrated circuit, comprising: a first set of memory cells configured to store a first set of data; a second set of memory cells configured to store a second set of data; a first set of input-output circuits coupled to the first set of memory cells; a second set of input-output circuits coupled to the second set of memory cells; a first error correction code circuit configured to store a first number of error correction code bits; a second error correction code circuit configured to store a second number of error correction code bits; as well as A first error correction code encoder / decoder circuit is configured to correct at least a first number of errors in the first set of data and the second set of data based on the first number of error correction code bits and the second number of error correction code bits.

2. The integrated circuit according to claim 1, wherein: The first error correction code circuit comprises: a first error correction code memory cell array; a second error correction code memory cell array; a third error correction code memory cell array; a first sense amplifier coupled to the first error correction code memory cell array; a second sense amplifier coupled to the second error correction code memory cell array; and A third sense amplifier is coupled to the third error correction code memory cell array.

3. The integrated circuit according to claim 2, wherein: The second error correction code circuit comprises: a fourth error correction code memory cell array; a fifth error correction code memory cell array; a sixth error correction code memory cell array; a fourth sense amplifier coupled to the fourth error correction code memory cell array; a fifth sense amplifier coupled to the fifth error correction code memory cell array; and A sixth sense amplifier is coupled to the sixth error correction code memory cell array.

4. The integrated circuit according to claim 3, wherein: The first error correction code circuit also includes: a seventh error correction code memory cell array; an eighth error correction code memory cell array; a ninth error correction code memory cell array; a seventh sense amplifier coupled to the seventh error correction code memory cell array; an eighth sense amplifier coupled to the eighth error correction code memory cell array; and A ninth sense amplifier is coupled to the ninth error correction code memory cell array.

5. The integrated circuit according to claim 4, wherein: The second error correction code circuit further includes: a tenth error correction code memory cell array; an eleventh error correction code memory cell array; a twelfth error correction code memory cell array; a tenth sense amplifier coupled to the tenth error correction code memory cell array; an eleventh sense amplifier coupled to the eleventh error correction code memory cell array; and A twelfth sense amplifier is coupled to the twelfth error correction code memory cell array.

6. An integrated circuit comprising: a first memory cell array; a second memory cell array; a control circuit coupled to the first memory cell array and the second memory cell array; a first set of sense amplifiers coupled to the first memory cell array; a second set of sense amplifiers coupled to the second memory cell array; a first error correction code circuit configured to store a first set of error correction code check bits; a second error correction code circuit configured to store a second set of error correction code check bits; a first error correction code encoder / decoder circuit configured to generate the first set of error correction code check bits based on a first set of data stored in the first memory cell array; as well as a second error correction code encoder / decoder circuit configured to generate the second set of error correction code check bits based on a second set of data stored in the second memory cell array, The first error correction code circuit and the second error correction code circuit are configured to correct at least a first number of errors in the first set of data and the second set of data based on the first set of error correction code check bits and the second set of error correction code check bits.

7. The integrated circuit according to claim 6, wherein: The first error correction code circuit comprises: a first error correction code memory cell array; a second error correction code memory cell array; a third error correction code memory cell array; a first sense amplifier coupled to the first error correction code memory cell array; a second sense amplifier coupled to the second error correction code memory cell array; and A third sense amplifier is coupled to the third error correction code memory cell array.

8. The integrated circuit according to claim 7, wherein: The second error correction code circuit comprises: a fourth error correction code memory cell array; a fifth error correction code memory cell array; a sixth error correction code memory cell array; a fourth sense amplifier coupled to the fourth error correction code memory cell array; a fifth sense amplifier coupled to the fifth error correction code memory cell array; and A sixth sense amplifier is coupled to the sixth error correction code memory cell array.

9. The integrated circuit of claim 8, wherein the first error correction code memory cell array, the second error correction code memory cell array, and the third error correction code memory cell array are separated from the first memory cell array by a first distance in a first direction; and The fourth error correction code memory cell array, the fifth error correction code memory cell array, and the sixth error correction code memory cell array are separated from the second memory cell array by a second distance in the first direction.

10. A method of operating an integrated circuit, the method comprising: Performing a programming operation on a first group of memory cells, performing the programming operation on the first group of memory cells comprises: storing a first set of data in a first memory cell array and storing a second set of data in a second memory cell array; generating a first set of check bits in response to the first set of data, and generating a second set of check bits in response to the second set of data; and storing the first set of parity bits in a first error correction code memory cell array, and storing the second set of parity bits in a second error correction code memory cell array; performing a read operation of the first group of memory cells; and In response to determining that data read from the first memory cell array or the second memory cell array contains an error based on the first set of parity bits and the second set of parity bits, the read data from the first memory cell array or the second memory cell array is corrected.

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