Input / output expander register addressing

Abstract

The invention relates to input / output expander register addressing. A method includes receiving, via a decoder coupled to a feature register that resides on a memory device interface and includes a first feature register portion and a second feature register portion, a bit string including at least one bit indicating a selection between the first feature register portion and the second feature register portion; and selecting the first feature register portion in response to the at least one bit indication, writing the bit string to at least one memory die among a plurality of memory dies addressed by the first feature register portion, or selecting the second feature register portion in response to the at least one bit indication, the bit string is written to at least one memory die among a plurality of memory dies addressed by the second feature register portion.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to input / output (IO) expander (IOE) register addressing. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure is directed to a method for register addressing, comprising: receiving, via a decoder coupled to a feature register comprising a first feature register portion and a second feature register portion residing on a memory device interface, a bit string comprising at least one bit indicating a selection between the first feature register portion and the second feature register portion; and writing the bit string to the first feature register portion of the memory device interface in response to the at least one bit indicating a selection of the first feature register portion, or writing the bit string to the second feature register portion of the memory device interface in response to the at least one bit indicating a selection of the second feature register portion.

[0004] In another aspect, the present disclosure is directed to an apparatus for register addressing, comprising: a controller; a plurality of memory dies; and a memory device interface to transmit communications between the controller and the plurality of memory dies, wherein the memory device interface comprises: a feature register comprising a first feature register portion and a second feature register portion, wherein the first feature register portion and the second feature register portion are assigned to circuitry associated with a single output channel; a decoder coupled to a first input of the first feature register portion and a second input of the second feature register portion; and an address decode bit written to the first feature register portion to specify a selection between the first feature register portion and the second feature register portion upon receiving a signal from the decoder.

[0005] On the other hand, the present disclosure relates to a system for register addressing, comprising: a memory subsystem comprising a non-volatile memory device; and a processing device coupled to the memory subsystem through a memory device interface, the memory device interface comprising: a feature register comprising a first plurality of designated feature register portions designated to circuit systems associated with a first group of output channels and a second plurality of designated feature register portions designated to circuit systems associated with a second group of output channels; a first decoder coupled to a first input of the first plurality of designated feature register portions; a second decoder coupled to a second input of the second plurality of designated feature register portions; a multiplexer coupled to an input of the second decoder; and a third decoder coupled to an input of the first decoder and an input of the multiplexer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 A system including a multi-channel input / output expander according to some embodiments of the present disclosure is described.

[0009] Figure 3 An apparatus for IO expander register addressing according to some embodiments of the present disclosure is described.

[0010] Figure 4 A system for IO expander register addressing according to some embodiments of the present disclosure is described.

[0011] Figure 5 A system for IO expander register addressing according to some embodiments of the present disclosure is described.

[0012] Figure 6 A system for IO expander register addressing according to some embodiments of the present disclosure is described.

[0013] Figure 7 is a flow chart corresponding to a method for IO expander register addressing according to some embodiments of the present disclosure.

[0014] Figure 8 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure relate to IO expander register addressing, and more particularly to a memory subsystem including a register addressing component. The memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system, such as a solid state drive (SSD). Figure 1 Examples of storage devices and memory modules are described in and elsewhere. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0016] The memory device may be a non-volatile memory device. One example of a non-volatile memory device is a NAND memory device (also known as flash technology). As used herein, a NAND memory device may include a set of flash memory dies or a combination of a flash memory die and a non-volatile memory (NVM) controller. The NVM controller may include circuitry for performing read / write operations as described herein. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may be composed of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. A block hereinafter refers to a unit of a storage device for storing data and may include a group of memory cells, a word line group, a word line, or an individual memory cell. For some memory devices, a block (hereinafter also referred to as a "memory block") is the smallest erasable area. Pages cannot be erased individually, and only the entire block can be erased.

[0017] Each of the memory devices may include one or more arrays of memory cells. Depending on the cell type, a cell may be written to so as to store one or more binary bits of information and have various logic states related to the number of bits stored. The logic states may be represented by binary values, such as "0" and "1", or a combination of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), three-level cells (TLCs), and four-level cells (QLCs). For example, an SLC may store one bit of information and have two logic states.

[0018] Some NAND memory devices employ a floating gate architecture in which memory access is controlled based on relative voltage changes between a bit line and a word line. Other examples of NAND memory devices may employ a replacement gate architecture, which may include the use of a word line layout that may allow a charge corresponding to a data value to be trapped within a memory cell based on the properties of the material used to construct the word line.

[0019] In some previous methods, an input / output expander (IOE) device may be placed between a host and a memory die. For example, an IOE device may be placed between a host device and a plurality of NAND dies (or "LUNs"). In some embodiments, an IOE device may be referred to as a buffer chip or a buffer chip device. The host side of an IOE device may be referred to as a front end, and the memory die side of an IOE device may be referred to as a back end. An IOE device may allow a host to see a single die load at the front end (e.g., front side (FS), etc.) of an IOE device. The NAND die load may be distributed across multiple IOE back end (e.g., back side (BS), etc.) channels. These previous IOE devices may implement a crossbar switch to route the intended traffic to a target NAND die. As used herein, a crossbar switch includes a set of switches arranged in a matrix configuration. A crossbar switch may have a plurality of input lines and output lines forming a cross pattern of interconnect lines, and connections may be established between the plurality of input lines and output lines by closing a switch (element of a matrix) located at each intersection.

[0020] In some previous approaches, the IOE device can be implemented with a buffered architecture to allow the crossbar switch to function. In this implementation, all signals from the host to the NAND and from the NAND to the host are buffered inside the IOE die and distributed to the required ports of the crossbar switch. In these approaches, as a larger number of NAND dies are added to the system, the load or load average between the host and the NAND can be reduced. That is, as a larger number of NAND dies are added to the system, the previous IOE will have a lower load capacity between the host and the NAND.

[0021] In some previous approaches, IOE devices are limited to a specific number of NAND dies. For example, an IOE may have a feature register that can be used to address an incoming bit string at the front end of the IOE to a specific NAND die at the back end of the IOE. In some previous approaches, the ONFI standard supports 8-bit feature addresses, resulting in a 1 kilobyte (KB) feature register space. In these approaches, the 1KB feature address space may not be sufficient to support the configuration of an IOE device that is coupled to a number of NAND dies or LUNs on the back end that is greater than or equal to 8. In this way, previous approaches may be limited to the number of NAND dies or LUNs that can be supported on the back end and / or accessible by a host coupled to the front end.

[0022] Aspects of the present disclosure address the above and other deficiencies by employing an IOE device that utilizes IO expander register addressing. For example, aspects of the present disclosure may utilize a register addressing component and a feature register that is divided into a first feature register portion and a second feature register portion. In these embodiments, the feature register may be expanded from a single 1KB portion (as is popular in current approaches) to multiple 1KB portions. In this way, the present disclosure allows support for the ONFI standard while increasing the number of NAND dies that the IOE can support due to the greater number of registers to which it provides accessibility during operation. In some embodiments, one or more of the feature register portions include an address decoding bit that is written to the register to select one of the multiple feature register portions.

[0023] Figure 1 An example computing system including a memory subsystem 110 according to some embodiments of the present disclosure is illustrated. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0024] The memory subsystem 110 may be a memory device, a memory module, or a mixture of a memory device and a memory module. Examples of memory devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other vehicles), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a device included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, and the like.

[0027] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0028] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., memory device 130) when the memory subsystem 110 is coupled to the host system 120 through a PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without having to erase the non-volatile memory cells in advance. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130, 140 may include one or more arrays of memory cells. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages that may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] Although nonvolatile memory components such as a three-dimensional cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0033] As described above, the memory component may be a memory die or a memory package that forms at least a portion of the memory device 130. In some embodiments, a block of memory cells may form one or more "super blocks". As used herein, a "super block" generally refers to a group of data blocks that span multiple memory dies and are written in an interleaved manner. For example, in some embodiments, each of several interleaved NAND blocks may be deployed across multiple memory dies having multiple planes and / or pages associated therewith. Given the context of the present disclosure, the terms "super block", "block", "block of memory cells" and / or "interleaved NAND block" and variations thereof may be used interchangeably.

[0034] The memory subsystem controller 115 (or controller 115 for simplicity) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may be a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses, physical media addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0038] In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140. For example, in some embodiments, memory device 140 may be a DRAM and / or SRAM configured to operate as a cache for memory device 130. In such examples, memory device 130 may be NAND.

[0039] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. Memory subsystem 110 may also include additional circuitry or components not illustrated.

[0040] The memory subsystem 110 may include a register addressing component 113, which is referred to herein in the alternative as a "controller." Figure 1100 to avoid obscuring the diagram, but register addressing component 113 may include various circuitry to facilitate aspects of IOE expander register addressing, as described in detail herein. In some embodiments, register addressing component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry that may allow register addressing component 113 to orchestrate and / or perform the operations described herein.

[0041] In some embodiments, the memory subsystem controller 115 includes at least a portion of the register addressing component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the register addressing component 113 is part of the host system 110, an application, or an operating system.

[0042] In a non-limiting example, a device (e.g., computing system 100) may include register addressing component 113. Register addressing component 113 may reside on memory subsystem 110. As used herein, the term "resides on" refers to something that is physically located on a particular component. For example, register addressing component 113 "resides on memory subsystem 110" refers to a condition in which the hardware circuitry including register addressing component 113 is physically located on memory subsystem 110. The term "resides on" may be used interchangeably with other terms herein, such as "deployed on" or "located on".

[0043] As referenced in this article Figures 2 to 6 Further describing, the memory subsystem 110 may include an IOE device, the IOE device includes a feature register including a first feature register portion and a second feature register portion. In this embodiment, the first feature register portion and the second feature register portion are assigned to a single output channel. In these embodiments, the first feature register portion is a first specified memory address map, and the second feature register portion is a second specified memory address map. For example, the first specified memory address map may include a first 1 kilobyte address map, and the second specified memory address map may include a second 1 kilobyte address map. In this example, the ONFI standard may be a feature register with a 1 kilobyte address map, and thus the IOE device may comply with the ONFI standard while also providing additional feature register space to allow the host to see additional memory resources.

[0044] In some embodiments, the memory subsystem 110 includes a decoder coupled to a first input of the first feature register portion and a second input of the second feature register portion. In these embodiments, the memory subsystem 110 includes address decoding bits written to the first feature register portion to specify a selection between the first feature register portion and the second feature register portion. In some embodiments, the register addressing component 113 may be configured to write the address decoding bits to the first feature register portion.

[0045] Although two feature address portions are described, the present disclosure is not so limited. For example, multiple additional feature register portions may be specified, and a decoder capable of providing a signal to each of the additional feature register portions may be utilized. In this example, the register addressing component 113 may write or encode address decode bits to a particular feature register portion to specify the selection of the multiple feature register portions and / or the order in which the selections are made from the multiple feature register portions. In this manner, the decoder may provide a signal from the host to a particular feature register portion within the feature register based on the address decode bits.

[0046] Figure 2 A system 221 including a multi-channel input / output (IO) expander (IOE device) 222 according to some embodiments of the present disclosure is described. The IOE device 222 may include a device utilizing a first input channel 223-1 and a second input channel 223-2 that may be connected to a host device or a host system. In some embodiments, the IOE device 222 may operate in a single channel mode and / or a dual channel mode. In these embodiments, the IOE device 222 may utilize only the first input channel 223-1 in the single channel mode, and may utilize both the first input channel 223-1 and the second input channel 223-2 in the dual channel mode. In some embodiments, the second input channel 223-2 is disabled to utilize the first input channel 223-1 to perform the single channel mode.

[0047] In some embodiments, the IOE device 222 may include a first plurality of output channels 224-1, 224-2 and a second plurality of output channels 224-3, 224-4. In some embodiments, the first output channel 224-1 may be coupled to a first portion of the LUN 225-1, the second output channel 224-2 may be coupled to a second portion of the LUN 225-2, the third output channel 224-3 may be coupled to a third portion of the LUN 225-3, and the fourth output channel 224-4 may be coupled to a fourth portion of the LUN 225-4. In single channel mode, the first input channel 223-1 may be used to access multiple LUNs 225-1, 225-2, 225-3, 225-4. In dual channel mode, the first input channel 223-1 can be used to access the first part of LUN 225-1 and the second part of LUN 225-2 through the first plurality of output channels 224-1, 224-2, and the second input channel 223-2 can be used to access the third part of LUN 225-3 and the fourth part of LUN 225-4 through the second plurality of output channels 224-3, 224-4.

[0048] In some previous embodiments, each of the first plurality of output channels 224-1, 224-2 and the second plurality of output channels 224-3, 224-4 may utilize a feature register to address signals from the first input channel 223-1 and / or the second input channel 223-2. As described herein, the feature register may be an industry standard (e.g., an ONFI standard, a 1-kilobyte standard, etc.). In these embodiments, due to the size of the feature register, the number of LUNs 225-1, 225-2, 225-3, 225-4 may be limited to a certain number. In this way, by utilizing multiple feature register portions for each of the first plurality of output channels 224-1, 224-2 and the second plurality of output channels 224-3, 224-4, the present disclosure may be utilized to expand the number of LUNs 225-1, 225-2, 225-3, 225-4.

[0049] Figure 3 The device 331 for IO expander register addressing according to some embodiments of the present disclosure is described. The device 331 may be an IOE device (e.g., Figure 2 Device 331 may include feature register 332. Feature register 332 may include memory resources that may be used to register address information of signals provided between a host device and a plurality of LUNs.

[0050] The device 331 may include a decoder 335 that may provide a signal received from a host or other circuitry to the feature register 332. In some examples, the decoder 335 may be used to provide a signal from the host to one of the first feature register portion 333-1 or the second feature register portion 333-2. In this manner, the decoder 335 may provide a first signal received from the host to the first feature register portion 333-1 and a second signal received from the host to the second feature register portion 333-2. In this embodiment, the decoder 335 may alternate between the first feature register portion 333-1 and the second feature register portion 333-2 to allow for additional feature register resources while still providing standard feature register resources. For example, the first feature register portion 333-1 may be a standard feature register size and the second feature register portion 333-2 may be a standard feature register size; however, by providing two such register portions and allowing access to each register portion based on commands and / or signaling received by the device 331, as described herein, aspects of the present disclosure may allow for an increase in the total amount of feature register resources available to IOE devices while maintaining backward compatibility with the ONFI standard.

[0051] In some embodiments, the first feature register portion 333-1 and / or the second feature register portion 333-2 may include address decode bits 334. The address decode bits 334 may be a bit string written to the first feature register portion 333-1. The address decode bits 334 may be used to instruct the decoder 335 to select between the first feature register portion 333-1 and the second feature register portion 333-2 for a particular signal received at the decoder 335. In this way, the host is able to send signals as if utilizing a single feature register of a standard size. Although Figure 3 The decoder 335 illustrated in is a 1:2 decoder, but the embodiments are not so limited, and other decoder architectures are considered within the scope of the present disclosure. In some embodiments, the device 331 may include combinatorial logic that can be used to provide signals (e.g., other signals, etc.) from the decoded bits 334 and / or other devices.

[0052] Figure 4 A system 441 for IO expander register addressing according to some embodiments of the present disclosure is illustrated. The system 441 corresponds to an IOE device (e.g., Figure 2222, etc.) as referenced in . In some embodiments, system 441 may include a first input channel 223-1 and a second input channel 223-2. As described herein, first input channel 223-1 and / or second input channel 223-2 may be used by the host to communicate with memory resources 225 (e.g., NAND devices, LUNs, etc.). In some embodiments, system 441 may include a data path switch 442, which may be part of a first portion of IOE data path circuitry 439-1 and / or a second portion of IOE data path circuitry 439-2.

[0053] In some embodiments, the first input channel 223-1 may be coupled to a first command decoder 438-1, and the second input channel 223-2 may be coupled to a second command decoder 438-2. As used herein, a command decoder may be used to decompose a command into multiple parts that may be provided to a circuit system. For example, the first command decoder 438-1 may be used to divide a command or bit string from the first input channel 223-1 into multiple parts that are provided to the multiplexer 436. In a similar manner, the second command decoder 438-2 may be used to divide a command or bit string from the second input channel 223-2 into multiple parts that are provided to the multiplexer 436 (MUX).

[0054] In some embodiments, decoder 437 may be a 1:2 decoder that may provide a single input to one of two outputs. That is, decoder 437 may receive an input signal from first command decoder 438-1 and provide an output signal to first feature register decoder 335-1 or to multiplexer 436. In some embodiments, decoder 437 may receive a signal at input "D". A signal may be received at input "D" from address decode bits 334, a combined signal from address decode bits 334 and a signal from input "C" of multiplexer 436, and / or a combined signal from address decode bits 334 and a signal from other devices.

[0055] The multiplexer 436 may be a component that can receive multiple input signals and provide a single output signal. For example, the multiplexer 436 may receive signals from the second command decoder 438-2 and / or the decoder 437. In this way, the multiplexer 436 may receive signals from both the first input channel 223-1 and the second input channel 223-2. The multiplexer 436 may provide the received signal to the second feature register decoder 335-2. In some embodiments, the multiplexer 436 may include an input "C" that can be used to receive a front side mode selection signal. For example, the input "C" may receive a single channel mode or a dual channel mode, as described herein.

[0056] As described herein, the first feature register decoder 335-1 may be used to provide a signal to the first feature register 332-1, and the second feature register decoder 335-2 may be used to provide a signal to the second feature register 332-2. Figure 3 The first feature register decoder 335-1 may provide a signal to one of the first feature register portion or the second feature register portion of the first feature register 332-1. In a similar manner, the second feature register decoder 335-2 may provide a signal to one of the third feature register portion or the fourth feature register portion of the second feature register 332-2. In some embodiments, the first feature register decoder 335-1 may include an input "A" that may receive a signal from the address decoding bit 334 and / or optionally receive a signal from other devices. In a similar manner, the second feature register decoder 335-2 may include an input "B" that may receive a signal from the address decoding bit 334 and / or optionally receive a signal from other devices.

[0057] In some embodiments, the first feature register portion of the first feature register may include first address decoding bits (e.g., as in Figure 3 , etc.), which can be used to select a particular feature register portion to receive a particular signal from the first feature register decoder 335-1. For example, the first address decode bit can select the first feature register portion of the first feature register 332-1 to receive the first signal, and select the second feature register portion of the first feature register 332-2 to receive the second signal.

[0058] As described herein, a first feature register 332-1 having a first feature register portion and a second feature register portion may be coupled to a first portion of an IOE data path circuit system 439-1 coupled to a first portion of a LUN (e.g., a first portion of a memory resource 225, etc.). This coupling between the first feature register 332-1 and the first portion of the IOE data path circuit system 439-1 may be used by the host to adjust and optimize the properties of the first portion of the IOE data path circuit system 439-1. For example, the properties of the first portion of the IOE data path circuit system 439-1 may be optimized to fine-tune the timing through the data path circuit system to support a higher data transfer speed between the host and the LUN, or vice versa. In a similar manner, a second feature register 332-2 having a third feature register portion and a fourth feature register portion may be coupled to a second portion of the IOE data path circuit system 439-2 coupled to a second portion of a LUN (e.g., a second portion of a memory resource 225, etc.).

[0059] In some embodiments, the first input channel 223-1 can be used by the host to send a signal to the first set of output channels 224-1 through the first portion of the IOE data path circuit system 439-1. In this way, the host can communicate with the first portion of the memory resource 225 (e.g., LUN, etc.) through the first set of output channels 224-1. In a similar manner, the second input channel 223-2 can be used by the host to send a signal to the second set of output channels 224-2 through the second portion of the IOE data path circuit system 439-2. In this way, the host can communicate with the second portion of the memory resource through the second set of output channels 224-2. In some embodiments, the first input channel 223-1 can be used by the host to send a signal through the second feature register 332-2 using the multiplexer 436. In this way, the host can adjust the properties of the second portion of the IOE data path circuit system 439-2 to achieve optimal communication between the host and the second portion of the memory resource 225 through the second set of output channels 224-2.

[0060] Figure 5 A system 551 for IO expander register addressing according to some embodiments of the present disclosure is described. The system 551 may include Figure 4 For example, system 551 may illustrate using the same or similar elements as system 441 referenced in the foregoing. Figure 3 The IOE device of the device 331 referenced in Figure 2 IOE 222 cited in .

[0061] In some embodiments, the system 551 includes a first input channel 223-1 and a second input channel 223-2 that can be coupled to a host device or a host system. In some embodiments, the first input channel 223-1 and the second input channel 223-2 can be referred to as a front end of the system 551. In some embodiments, the host device can provide a signal (e.g., a write operation, a read operation, a bit string, etc.) to the first input channel 223-1 and / or the second input channel 223-2. In these embodiments, the signal provided to the first input channel 223-1 can be provided to the first command decoder 438-1, and the signal provided to the second input channel 223-2 can be provided to the second command decoder 438-2.

[0062] The signal at the first command decoder 438-1 may be provided to the first feature register decoder 335-1. As described herein, the first feature register decoder 335-1 may include multiple outputs to provide a signal from the first command decoder 438-1 to one of the multiple feature register portions of the first feature register 332-1. In a specific example, the first feature register decoder 335-1 is a 1:2 decoder that can receive a signal from the first command decoder 438-1 and provide the signal to one of the two feature register portions. As described herein, one of the feature register portions may include an address decoding bit that is written to one of the feature register portions. In these embodiments, the address decoding bit may be utilized to select which of the multiple feature register portions receives the signal from the feature register decoder 335-1. In this way, the feature register decoder 335-1 may provide a first signal to the first feature register portion of the first feature register 332-1, and provide a second signal to the second feature register portion of the first feature register 332-1.

[0063] The signal from the first feature register 332-1 may be provided to a first portion of the IOE data path circuitry 439-1 coupled to a first set of output channels 224-1 coupled to a first portion of the memory resource 225-1. As described herein, the first set of output channels 224-1 may include a plurality of output channels that may each be coupled to a portion of the first portion of the memory resource 225-1. For example, a first output channel in the first set of output channels 224-1 may be coupled to a first set of LUNs, and a second output channel in the first set of output channels 224-1 may be coupled to a second set of LUNs.

[0064] In a similar manner to the first input channel 223-1, the second input channel 223-2 can be used by the host to provide a signal to the second command decoder 438-2. The signal from the second command decoder 438-2 can be provided to the second feature register decoder 335-2. The second feature register decoder 335-2 can provide a signal from the second command decoder 438-2 to one of the plurality of feature register portions of the second feature register 332-2 based on the address decode bits written to one of the plurality of feature register portions. The signal from the feature register portion can be provided to a second portion of the IOE data path circuit system 439-2 coupled to the second set of output channels 224-2 coupled to the second portion of the memory resource 225-2.

[0065] Figure 5The IOE device may be described as operating in dual channel mode. As described herein, dual channel mode may allow the first input channel 223-1 to be used to communicate with a first portion of the memory resource 225-1, and allow the second input channel 223-2 to be used to communicate with a second portion of the memory resource 225-2. In some embodiments, the memory resources 225-1 and / or 225-2 may include one or more LUNs, as described above in conjunction with Figure 2 described.

[0066] Figure 6 A system 661 for IO expander register addressing according to some embodiments of the present disclosure is described. The system 661 may include a Figure 4 The system cited in 441 and Figure 5 For example, system 661 may illustrate using the same or similar elements as system 551 referenced in the foregoing. Figure 3 The IOE device of the device 331 referenced in Figure 2 IOE 222 cited in . Figure 6 The IOE device may indicate when it is operating in single channel mode or single channel mode. In this way, the first input channel 223-1 may be used to communicate with the first portion of the memory resource 225-1 and the second portion of the memory resource 225-2. In some embodiments, the single channel mode may indicate when the IOE device is operating in single channel mode or single channel mode. Figure 5 The second input channel 223-2 referenced in is deactivated.

[0067] In some embodiments, the system 661 includes a first input channel 223-1 that can be coupled to a host device or a host system. In some embodiments, the host device can provide a signal (e.g., a write operation, a read operation, a bit string, etc.) to the first input channel 223-1. In these embodiments, the signal provided to the first input channel 223-1 can be provided to the first command decoder 438-1.

[0068] The signals at the first command decoder 438 may be provided to a decoder 437. The decoder 437 may be used to provide the signals to one of the first feature register decoder 335-1 or the second feature register decoder 335-2. In some embodiments, the signals directed to the first portion of the memory resource 225-1 travel through a first portion of the IOE data path circuitry 439-1 whose attributes are controlled by the first feature register 332-1, and the signals directed to the second portion of the memory resource 225-2 travel through a second portion of the IOE data path circuitry 439-2 whose attributes are controlled by the second feature register 332-2.

[0069] As described herein, the first feature register decoder 335-1 may include multiple outputs to provide a signal from the decoder 437 to one of the multiple feature register portions of the first feature register 332-1. As described herein, one of the feature register portions may include address decoding bits that are written to one of the feature register portions. In these embodiments, the address decoding bits may be utilized to select which of the multiple feature register portions receives a signal from the feature register decoder 335-1. In this way, the feature register decoder 335-1 may provide a first signal to a first feature register portion of the first feature register 332-1 and provide a second signal to a second feature register portion of the first feature register 332-1.

[0070] The signal from the first feature register 332-1 may be provided to a first portion of the IOE data path circuitry 439-1 coupled to a first set of output channels 224-1 coupled to a first portion of the memory resource 225-1. As described herein, the first set of output channels 224-1 may include a plurality of output channels that may each be coupled to a portion of the first portion of the memory resource 225-1. For example, a first output channel in the first set of output channels 224-1 may be coupled to a first set of LUNs, and a second output channel in the first set of output channels 224-1 may be coupled to a second set of LUNs.

[0071] In a similar manner, the signal from the decoder 437 provided to the second feature register decoder 335-2 may be provided to one of the plurality of feature register portions of the second feature register decoder 332-2 based on the address decode bits written to the one of the plurality of feature register portions. The signal from the feature register portion may be provided to a second portion of the IOE data path circuitry 439-2 coupled to the second set of output channels 224-2 to be provided to a second portion of the memory resource 225-2.

[0072] Figure 7 is a flow chart corresponding to a method 771 for IO expander register addressing according to some embodiments of the present disclosure. The method 771 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 771 is performed by Figure 1113. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0073] At operation 772, method 771 may include receiving a bit string including at least one bit indicating a selection between the first feature register portion and the second feature register portion via a decoder coupled to a feature register including a first feature register portion and a second feature register portion residing on a memory device interface. As described herein, the decoder may be a feature register decoder (e.g., feature register decoder 335-1, 335-2, etc.) that may receive a signal from an input channel or other circuitry. An input of the decoder may be coupled to an input channel coupled to a host device, and an output of the decoder may be coupled to the feature register.

[0074] As described herein, a feature register may include at least a first feature register portion and a second feature register portion. One of the feature register portions may include a bit string, such as address decoding bits, to select the feature register portion to receive a particular signal from a decoder. In this way, the decoder may distribute the signal to multiple feature register portions based on the bit string. In this way, additional feature register resources may be utilized while still maintaining industry standards for feature register sizes (e.g., 1 kilobyte, etc.). That is, each of the multiple feature register portions may be an industry standard size or number of memory resources and operate as a single feature register having an industry standard size.

[0075] At operation 773, method 771 may be performed to write a bit string to a first feature register portion of a memory device interface in response to at least one bit indicating selection of the first feature register portion. In some embodiments, when the bit string or address decode bit selects the first feature register portion, the signal is received by the encoder and provided to the first feature register portion. In these embodiments, the signal is stored by the first feature register portion before being provided to the first portion of the IOE data path circuitry of the IOE device.

[0076] At operation 774, method 771 includes writing the bit string to a second feature register portion of the memory device interface in response to at least one bit indicating selection of the second feature register portion. In some embodiments, when the bit string or address decode bit selects the second feature register portion, the signal is received by the encoder and provided to the second feature register portion. In these embodiments, the signal is stored by the second feature register portion before being provided to the second portion of the IOE data path circuitry of the IOE device.

[0077] As described herein, the first feature register portion is a first specified memory address mapping, and the second feature register portion is a second specified memory address mapping. In some embodiments, the first feature register portion and the second feature register portion are assigned to a first portion of an IOE data path circuit system coupled to a single output channel. As described herein, the number of LUNs or memory resources coupled to an output channel may be limited by a feature register. In order to expand the number of LUNs that can be used for a specific output channel, the first feature register portion and the second feature register portion may be coupled to the same IOE data path circuit system. In some embodiments, method 771 includes directly accessing one of the first feature register portion or the second feature register portion based on an address decoding bit. As described herein, when the address decoding bit selects the first feature register portion, the first feature register portion may be directly accessed, and when the address decoding bit selects the second feature register portion, the second feature register portion may be directly accessed.

[0078] In some embodiments, method 771 includes receiving a signal from a first input channel at an input of a decoder. In these embodiments, method 771 may include receiving a signal from a multiplexer coupled to the first input channel and the second input channel at the input of the decoder. As described herein, the multiplexer may be used to allow the first input channel to access a plurality of feature registers. In these embodiments, each of the plurality of feature registers may include a feature register portion. In some embodiments, each of the plurality of feature registers may include a feature register portion having an address decoding bit for selecting the feature register portion for receiving a particular signal from the decoder.

[0079] Figure 8 8 is a block diagram of an example computer system 800 in which embodiments of the present disclosure may operate. For example, Figure 8 An example machine illustrating a computer system 800 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 800 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1110), or may be used to execute operations of the controller (eg, execute an operating system to execute operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The computer may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0080] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0081] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0082] The processing device 802 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 802 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 800 may further include a network interface device 808 for communicating over a network 820.

[0083] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methodologies or functions described herein. During execution of the instructions 826 by the computer system 800, the instructions 826 may also reside, in whole or in part, within the main memory 804 and / or within the processing device 802, which also constitute machine-readable storage media. The machine-readable storage medium 824, the data storage system 818, and / or the main memory 804 may correspond to Figure 1 Memory subsystem 110.

[0084] In one embodiment, instruction 826 includes instructions for implementing a register addressing component (e.g., Figure 1 113) of the register addressing component 113. Although the machine-readable storage medium 824 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0085] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common sense reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0086] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0087] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0088] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0089] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer).

[0090] In some embodiments, machine-readable (e.g., computer-readable) media include machine (e.g., computer) readable storage media, such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc. In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method for register addressing, comprising: receiving, via a decoder (335, 335-1, 335-2) coupled to a feature register (332, 332-1, 332-2) residing on a memory device interface (222) comprising a first feature register portion (333-1) and a second feature register portion (333-2), a bit string including at least one bit (334) indicating a selection between the first feature register portion (333-1) and the second feature register portion (333-2); as well as writing the bit string to the first feature register portion (333-1) of the memory device interface (222) in response to the at least one bit (334) indicating selection of the first feature register portion (333-1), or In response to the at least one bit (334) indicating selection of the second feature register portion (333-2), the bit string is written to the second feature register portion (333-2) of the memory device interface (222).

2. The method of claim 1, wherein the first feature register portion and the second feature register portion are assigned to circuitry associated with a single output channel.

3. The method of claim 1 , further comprising receiving a signal at an input of the decoder from a first input channel (223-1), and receiving the signal at the input of the decoder from a multiplexer (436) coupled to the first input channel (223-1) and a second input channel (223-2).

4. The method of claim 1 , wherein the first feature register portion is a first specified memory address map and the second feature register portion is a second specified memory address map, and the first specified memory address map comprises a first 1 kilobyte address map and the second specified memory address map comprises a second 1 kilobyte address map.

5. The method of claim 1, further comprising directly accessing one of the first feature register portion or the second feature register portion based on address decode bits.

6. A device (441) for register addressing, comprising: Controller (110); a plurality of memory dies (225-1, 225-2, 225-3, 225-4); and A memory device interface (222) for transmitting communications between the controller (110) and the plurality of memory dies (225-1, 225-2, 225-3, 225-4), wherein the memory device interface (222) comprises: a feature register (332-1) comprising a first feature register portion (333-1) and a second feature register portion (333-2), wherein the first feature register portion (333-1) and the second feature register portion (333-2) are assigned to circuitry associated with a single output channel (223-1); a decoder (335-1) coupled to a first input of the first feature register portion (333-1) and a second input of the second feature register portion (333-2); and An address decoding bit (334) which is written to the first feature register portion (333-1) to specify selection between the first feature register portion (333-1) and the second feature register portion (333-2) upon receiving a signal from the decoder (335-1).

7. The apparatus of claim 6, wherein the first feature register portion (333-1) is a standard address mapped amount of memory and the second feature register portion (333-2) is the standard address mapped amount of memory.

8. The apparatus of claim 6, comprising a multiplexer (436), wherein an output of the multiplexer (436) is coupled to an input of the decoder (335-1), and an input of the multiplexer (436) is coupled to a first input channel (223-1) and a second input channel (223-2).

9. The apparatus of claim 6, comprising a third feature register portion and a fourth feature register portion coupled to an output of an additional decoder, wherein the third feature register portion and the fourth feature register portion are assigned to the circuitry associated with an output channel different from the single output channel.

10. Apparatus according to claim 9, comprising additional address decoding bits written to the third feature register portion to specify selection between the third feature register portion and the fourth feature register portion when a signal is received from the additional decoder.

11. The apparatus of claim 6, wherein the memory device interface operates in one of a single channel mode and a dual channel mode.

12. A system (661) for register addressing, comprising: a memory subsystem (110) comprising a non-volatile memory device (130); and A processing device (117) coupled to the memory subsystem (110) via a memory device interface (222), the memory device interface (222) comprising: a signature register (332) comprising a first plurality of designated signature register portions (332-1) designated to circuitry associated with a first set of output channels (224-1) and a second plurality of designated signature register portions (332-2) designated to circuitry associated with a second set of output channels (224-2); a first decoder (335-1) coupled to a first input of the first plurality of specified feature register portions (332-1); a second decoder (335-2) coupled to a second input of the second plurality of specified feature register portions (332-2); a multiplexer (436) coupled to an input of the second decoder (335-2); and A third decoder (437) is coupled to an input of the first decoder (335-1) and an input of the multiplexer (436).

13. The system of claim 12, wherein the processing device is configured to: writing first address decode bits to the first plurality of designated feature register portions to designate selection among the first plurality of designated feature register portions for a signal received from the first decoder; and A second address decode bit is written to the second plurality of designated feature register portions to designate selection among the second plurality of designated feature register portions for a signal received from the second decoder.

14. The system of claim 12, comprising a first input channel coupled to the third decoder and a second input channel coupled to the multiplexer, wherein the second input channel is disabled to perform a single channel mode with the first input channel.

15. The system of claim 12, wherein the first set of output channels includes a first output channel coupled to a first portion of a NAND die and a second output channel coupled to a second portion of the NAND die.

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