A DMA method, device and system based on synchronous time

Abstract

The present invention discloses a method, device and system for DMA based on synchronous time, including a DMA basic counter, the value of which increases by a fixed value every at least one clock cycle, and also includes: presetting at least one DMA timing value, presetting the DMA handling task corresponding to each DMA timing value, and presetting the trigger condition; comparing the value of the DMA basic counter with the preset DMA timing value; when the trigger condition is met, executing the DMA handling task corresponding to the DMA timing value, the DMA handling task is to carry the data on the DMA source address to the DMA destination address. The present invention adopts a method for DMA based on synchronous time, and according to the preset, the data on the DMA source address in the chip is carried to the DMA destination address; thereby realizing the efficient handling of a large amount of timing data, especially realizing the efficient handling of a large amount of timing discontinuous address data.

Description

Technical Field

[0001] The present invention relates to a method, device and system for DMA based on synchronous time, in particular to a method, device and system for DMA based on synchronous time in a controller chip and its software. Background Art

[0002] With the development of chip technology, more and more functional modules are integrated into the chip, and the amount of calculation of the controller chip is getting larger and larger. The controller chip needs to efficiently transport a large amount of timed data. In order to improve the computing speed of the entire chip and without occupying processor resources, there are the following requirements: to achieve efficient transportation of a large amount of timed data, especially to achieve efficient transportation of a large amount of timed discontinuous address data. For example, the 32-channel discontinuous address I2S timed data transportation of the car audio, a large number of loop BUFFERs in the timing calculation, etc.; another example is to efficiently and high-speed timed view of a large number of individual discontinuous address data inside the controller chip to realize the function of oscilloscope or logic analyzer, and another example is to efficiently and high-speed timed transportation to change a large number of individual discontinuous address variables inside the controller chip to realize the signal source function, etc.

[0003] There are two main methods for implementing the need for "transporting a large amount of timing data, especially the transport of a large amount of timing discontinuous address data": 1. Using "general timer (TIMER) function in the controller chip + DMA" to implement, but the number of general timers in the controller chip is small, and the cost of general timers is generally high. For example, ST's STM32F407 has only 14 general timers, which can only realize the transport of 14 timing discontinuous address data, and cannot realize the efficient transport of a large amount of timing discontinuous address data. 2. Using "software + general timer function in controller chip + DMA" to implement, due to the intervention of software in the controller chip, the processor resources are occupied, the efficiency of the processor is significantly reduced, and the practicality is significantly reduced. At the same time, the intervention of software makes the operation of the processor very complicated. Summary of the invention

[0004] The present application provides a method, device and system based on synchronous time DMA, which is used to realize efficient transfer of a large amount of timing data without occupying processor resources, especially to realize efficient transfer of a large amount of timing discontinuous address data, as follows:

[0005] A synchronous time-based DMA method includes a DMA base counter, wherein the value of the DMA base counter increases by a fixed value every at least one clock cycle, including:

[0006] Preset at least one DMA timing value, preset a DMA handling task corresponding to each DMA timing value, and preset a trigger condition;

[0007] Compare the value of the DMA base counter with the preset DMA timing value;

[0008] When the trigger condition is met, the DMA handling task corresponding to the DMA timing value is executed;

[0009] The trigger condition is: the value of the DMA basic counter is equal to any preset DMA timing value, or the value of the DMA basic counter is less than any preset DMA timing value, or the value of the DMA basic counter is greater than any preset DMA timing value;

[0010] The DMA transfer task includes a DMA source address and a DMA destination address, and executing the DMA transfer task is to transfer the data on the DMA source address to the DMA destination address.

[0011] Furthermore, the DMA transfer task may be performed once or multiple times, and the data transferred each time may be 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes or other integer multiples of bytes.

[0012] Furthermore, the DMA transfer task is multiple transfers, and the DMA source address remains unchanged after each transfer and / or the DMA destination address remains unchanged after each transfer.

[0013] Furthermore, the DMA handling task is multiple handlings, and also includes:

[0014] Preset DMA source address upper limit, preset DMA source address lower limit and preset DMA source address increment each time;

[0015] Calculate the DMA source address after each transfer. The DMA source address after each transfer is calculated by the following formula: (DMA source address before each transfer - DMA source address lower limit + DMA source address increment each time) % (DMA source address upper limit - DMA source address lower limit) + DMA source address lower limit; and / or,

[0016] Preset DMA destination address upper limit, preset DMA destination address lower limit and preset DMA destination address increment each time;

[0017] Calculate the DMA destination address after each transfer. The DMA destination address after each transfer is calculated using the following formula: (DMA destination address before each transfer - DMA destination address lower limit + DMA destination address increment each time) % (DMA destination address upper limit - DMA destination address lower limit) + DMA destination address lower limit.

[0018] Furthermore, it also includes:

[0019] Preset the threshold of DMA base counter;

[0020] The value of the DMA base counter is compared with a preset threshold of the DMA base counter. When the value of the DMA base counter is greater than or equal to the preset threshold of the DMA base counter, the value of the DMA base counter is reset to 0.

[0021] Furthermore, each DMA timing value corresponds to multiple DMA transfer tasks.

[0022] Further, when the value of the DMA base counter is greater than or equal to the threshold of the DMA base counter, the DMA source address is one of the following:

[0023] The value of the DMA source address remains unchanged;

[0024] The value of the DMA source address is equal to a preset value; and / or,

[0025] The DMA destination address is one of the following:

[0026] The value of the DMA destination address remains unchanged;

[0027] The value of the DMA destination address is equal to the preset value.

[0028] Furthermore, the value of the DMA basic counter is obtained before each DMA transfer, which is recorded as the time before DMA transfer. The value of the DMA basic counter is obtained after the DMA transfer, which is recorded as the time after DMA transfer. DMA transfer time = (time after DMA transfer - time before DMA transfer + threshold of DMA basic counter) % threshold of DMA basic counter.

[0029] Furthermore, the fixed numerical value is a preset value.

[0030] A synchronous time-based DMA device includes a DMA base counter, wherein the value of the DMA base counter increases by a fixed value every at least one clock cycle, including:

[0031] A first preset module, the first preset module is used to preset at least one DMA timing value, preset a DMA handling task corresponding to each DMA timing value, and preset a trigger condition;

[0032] A first comparison module, the first comparison module is used to compare the value of the DMA basic counter with a preset DMA timing value;

[0033] A first execution module, when a trigger condition is met, the first execution module is used to execute the DMA handling task corresponding to the DMA timing value;

[0034] The trigger condition is: the value of the DMA basic counter is equal to any preset DMA timing value, or the value of the DMA basic counter is less than any preset DMA timing value, or the value of the DMA basic counter is greater than any preset DMA timing value;

[0035] The DMA transfer task includes a DMA source address and a DMA destination address, and executing the DMA transfer task is to transfer the data on the DMA source address to the DMA destination address.

[0036] Furthermore, the DMA transfer task is multiple transfers, and the DMA device based on synchronous time also includes:

[0037] A second preset module, the second preset module is used to preset the DMA source address upper limit, preset the DMA source address lower limit and preset each increment of the DMA source address;

[0038] The first operation module is used to calculate the DMA source address after each transfer. The DMA source address after each transfer is calculated by the following formula: (DMA source address before each transfer - DMA source address lower limit + DMA source address increment each time) % (DMA source address upper limit - DMA source address lower limit) + DMA source address lower limit; and / or,

[0039] A third preset module, the third preset module is used to preset the DMA destination address upper limit, preset the DMA destination address lower limit and preset each increment of the DMA destination address;

[0040] The second operation module is used to calculate the DMA destination address after each transfer. The DMA destination address after each transfer is calculated by the following formula: (DMA destination address before each transfer - DMA destination address lower limit + DMA destination address increment each time) % (DMA destination address upper limit - DMA destination address lower limit) + DMA destination address lower limit.

[0041] Further, the synchronous time-based DMA apparatus further includes a second execution module, the second execution module being configured to execute the following tasks when the value of the DMA basic counter is greater than or equal to a threshold value of the DMA basic counter;

[0042] The DMA source address is one of the following:

[0043] The value of the DMA source address remains unchanged;

[0044] The value of the DMA source address is equal to a preset value; and / or,

[0045] The DMA destination address is one of the following:

[0046] The value of the DMA destination address remains unchanged;

[0047] The value of the DMA destination address is equal to the preset value.

[0048] Further, the device based on synchronous time DMA also includes:

[0049] A fourth preset module, the fourth preset module is used to preset a threshold value of a DMA basic counter;

[0050] The second comparison module is used to compare the value of the DMA basic counter with a preset threshold of the DMA basic counter. When the value of the DMA basic counter is greater than or equal to the preset threshold of the DMA basic counter, the value of the DMA basic counter is reset to 0.

[0051] Furthermore, the synchronous time-based DMA device further includes a fifth preset module, and the fifth preset module is used to preset a fixed value.

[0052] A DMA system based on synchronous time includes any of the above-mentioned devices, and the system also includes embedded software, a chip and a debugging terminal. The device moves data on the DMA source address in the chip to the DMA destination address according to the preset of the embedded software or the debugging terminal.

[0053] Beneficial effects of this application:

[0054] In the case of a large amount of timed synchronous data transfer, especially to achieve a large amount of timed discontinuous address data transfer, such as 32-way discontinuous address I2S timed data transfer, a large number of cyclic BUFFERs in timed calculations, etc., high-speed timed viewing of a large number of individual discontinuous address data inside the controller chip to achieve oscilloscope or logic analyzer functions, high-speed timed transfer to change a large number of individual discontinuous address variables inside the controller chip to achieve signal source functions. This application only requires a DMA basic counter, the value of the DMA basic counter increases by a fixed value every at least one clock cycle, by presetting at least one DMA timing value, presetting trigger conditions, and presetting the DMA transfer task corresponding to each DMA timing value, when the trigger condition is met, the DMA transfer task corresponding to the DMA timing value is executed to transfer the data on the DMA source address to the DMA destination address.

[0055] Compared with the "general timer (TIMER) function + DMA in the controller chip" in the prior art, this application only needs one DMA basic counter and does not require a large number of timers (TIMER) to achieve efficient transportation of a large amount of timing data, especially the efficient transportation of a large amount of timing discontinuous address data, saving a large number of general timers and saving costs.

[0056] Compared with the existing technology of "software + general timer function in the controller chip + DMA", because there is no intervention of processor software, it does not occupy processor resources, improves processor efficiency, and the real-time performance is much better, and the software will not become complicated. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0058] Figure 1 is a flow chart of an embodiment of the method of the present invention;

[0059] Figure 2 is a flow chart of another embodiment of the method of the present invention;

[0060] Figure 3 is a schematic diagram of data storage in one embodiment of the method of the present invention;

[0061] Figure 4 is a schematic diagram of the execution timing of an embodiment of the method of the present invention;

[0062] Figure 5 is another execution timing diagram of an embodiment of the method of the present invention;

[0063] Figure 6 It is a structural framework diagram of an embodiment of the device of the present invention;

[0064] Figure 7 It is a structural framework diagram of an embodiment of the system of the present invention. DETAILED DESCRIPTION

[0065] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0066] It should be noted that, unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0067] In the present invention, unless otherwise specified, the directional words used, such as "up, down, top, bottom", usually refer to the directions shown in the drawings, or to the components themselves in the vertical, perpendicular or gravity directions; similarly, for ease of understanding and description, "inside and outside" refer to the inside and outside relative to the outline of each component itself, but the above-mentioned directional words are not used to limit the present invention.

[0068] It should be pointed out that in various embodiments of the present invention, only for the convenience of explanation, the corresponding functional units are modularized. In fact, these functional units can also be distributed in various functional modules of the chip, and then complete the corresponding functions together.

[0069] First of all, it should be noted that in various embodiments of the present invention, the terms involved are explained as follows:

[0070] Processor: It is the abbreviation of processor core. As the computing and control core of the controller chip, it is the final execution unit of information processing, data processing, and program running. It is an important component of the controller chip, such as RISC-V core CPU, ARM's M3, or other DSP cores, etc. The processor in this application is not a separate CPU like INTEL Pentium in a traditional PC computer.

[0071] MCU: A general term for a microcontroller chip, which includes a processor and other related functional modules (such as program memory, data memory, PWM module, UART, etc.).

[0072] MPU: Microprocessor chip, a processor used in embedded systems, different from the CPU used in PCs.

[0073] Controller chip, short for embedded controller chip, includes: MCU, DSP and MPU, etc.

[0074] Chip: Also known as integrated circuit (IC). It refers to a small silicon chip containing an integrated circuit, which is often part of a computer or other electronic device. The chip in this application is an embedded controller chip.

[0075] Embedded software: It is the operating system and application software embedded in the hardware. Generally speaking, in the system, the program is a specific embodiment of embedded software.

[0076] Embedded system: includes one of the following: embedded hardware, embedded hardware includes chips; embedded software.

[0077] Embedded: is the abbreviation of embedded system.

[0078] Instruction: A code that tells the processor to do something. A program is a collection of instructions grouped together to perform a specific function; in particular, individual instructions are also part of a program.

[0079] Address: includes program address and data address.

[0080] Program address: refers to the actual address of the program in storage when it is scheduled to run by the processor. The address of the instruction accessed by the processor can be called the instruction address or the program address.

[0081] Functional module: A unit in a chip that performs a specific function and can be directly or indirectly accessed or updated by a processor at a specific time; also known as peripherals, peripheral modules, peripheral functional modules, etc. Generally, in a chip, functional modules include but are not limited to storage (e.g. ROM, OTP, FLASH, SRAM, SDRAM, etc.), TIMER, GPIO module, PWM module, etc. In particular, in a multi-processor chip, at a specific time, some processors can also be accessed or updated by other processors as functional modules.

[0082] Module address: The address where the content of a functional module is accessed or updated as data by the processor.

[0083] Data includes but is not limited to: content stored in a data storage device during a program, or content that can be queried, updated, etc. by a processor.

[0084] Data address: The address corresponding to the processor's operations such as querying and updating data. In particular, programs and data can be stored in the memory (including but not limited to ROM, OTP, FLASH, SRAM, SDRAM, etc.). In addition to the address of the instruction corresponding to the software running at a specific moment as the program address, the addresses of other instructions can be used as both program addresses and data addresses.

[0085] Memory: A functional module that can store programs and data, including but not limited to ROM, OTP, FLASH, SRAM, SDRAM, etc.

[0086] Debug terminal: short for intelligent terminal, a device with input and output and information processing capabilities; including but not limited to: PC, mobile phone, tablet, embedded device, etc.

[0087] Information: refers to the objects transmitted and processed by audio, messages, and communication systems, and generally refers to all content disseminated by human society. For chips, information can also be the values ​​of one or more registers on the chip, the values ​​of one or more combinational circuits, the values ​​of one or more memories, or a combination of the above.

[0088] Access, including processor query and update actions on the module (i.e., read and write).

[0089] Manipulate data, including the processor's query and set actions on data.

[0090] Print: A commonly used embedded term, which refers to outputting information through external interfaces such as UART, USB, etc. on the chip.

[0091] DMA, Direct Memory Access, enables data to be sent from one address to another; including peripheral to peripheral, peripheral to memory, memory to peripheral, memory to memory, etc.

[0092] TIMER, generally refers to a timer, also known as "Timer" and "timer", which outputs a signal according to a preset time. It includes: a counter, a timing value, and a small amount of other circuits. Timers are divided into dedicated timers and general timers; dedicated timers generally have special and dedicated uses, and only general timers can realize the "counter + timing value" of the present invention in conjunction with the DMA function. There are only 14 general timers in STM32F407, recorded as TIM1, TIM2...TIM14. The "DMA basic counter" in the present invention belongs to a counter.

[0093] %: In computer programming, the percent sign means to find the remainder. And the "%" operation level is higher than "+" and "-".

[0094] A controller chip contains a processor with a main frequency of 168MHz. The internal program address of the chip corresponds to: 0~0x1fff; the internal data address of the chip corresponds to 0x2000~0x2fff, and each address stores 1 byte of data (i.e. 8 bits); the internal peripheral address of the chip corresponds to 0x3000~0x3fff, and the address 0x3100 is the output data register address of the I2S module. For some information, please refer to Figure 3 shown.

[0095] See also Figure 1 As shown, Figure 1 The flowchart of one embodiment of the method of the present invention is shown in FIG.

[0096] A method for DMA based on synchronous time includes a DMA basic counter, wherein the value of the DMA basic counter increases by a fixed value every at least one clock cycle. The value of the DMA basic counter may increase by a fixed value every clock cycle, or may increase by a fixed value every multiple clock cycles. The fixed value may be a hardware-fixed number, usually 1, and may be a positive number or a negative number. The fixed value may also be a preset value, such as one that may be set by an external input device.

[0097] Also includes:

[0098] S100, preset at least one DMA timing value, preset a DMA transfer task corresponding to each DMA timing value, and preset a trigger condition.

[0099] One or more DMA timing values ​​may be preset. Each DMA timing value may correspond to one or more DMA transfer tasks.

[0100] S200, comparing the value of the DMA basic counter with a preset DMA timing value.

[0101] S300, when the trigger condition is met, executing the DMA transfer task corresponding to the DMA timing value.

[0102] The trigger condition is: the value of the DMA basic counter is equal to any preset DMA timing value, or the value of the DMA basic counter is less than any preset DMA timing value, or the value of the DMA basic counter is greater than any preset DMA timing value; the trigger condition can also be a logical combination of these.

[0103] When the trigger condition is that the value of the DMA basic counter is less than any preset DMA timing value or when the trigger condition is that the value of the DMA basic counter is greater than any preset DMA timing value, the DMA transfer task corresponding to the DMA timing value can be executed and only executed once, or the DMA transfer task corresponding to the DMA timing value can be executed every time.

[0104] The DMA transfer task includes a DMA source address and a DMA destination address. Executing the DMA transfer task is to transfer the data at the DMA source address to the DMA destination address.

[0105] The meaning of "moving the data at the DMA source address to the DMA destination address" is to move the data at the DMA source address to the DMA destination address space; "moving the data at the DMA source address to the DMA destination address" and "moving the data at the DMA source address to the DMA destination address" both express the same meaning of "moving the data at the DMA source address to the DMA destination address".

[0106] When there are multiple DMA transfer tasks corresponding to the DMA timing value and the trigger condition is met, the DMA transfer tasks with no hardware resource conflicts can be executed in parallel or in series, and the DMA transfer tasks with hardware resource conflicts can be executed in series.

[0107] For example, the value of the DMA basic counter is initially 0 and increases by 1 every clock cycle; a DMA timing value is preset to be 5; the DMA transfer task D1 corresponding to the preset DMA timing value is as follows: Figure 3As shown, the DMA source address of D1 is 0x2a01, and the DMA destination address of D1 is 0x3101; when the trigger condition is preset and the value of the DMA basic counter is equal to the DMA timing value 5, the data 0xa8 at address 0x2a01 is moved to address 0x3101.

[0108] The method of the present application also includes: a method that is or includes the operations of step S100, step S200 and step S300; a method that is or is indirectly implemented by exchanging the order of transformation, or is equivalent to, or can be converted into the operations of step S100, step S200 and step S300.

[0109] In yet another embodiment, see Figure 2 As shown, the method based on synchronous time DMA also includes:

[0110] S210, preset a threshold of a DMA basic counter;

[0111] S220 , comparing the value of the DMA base counter with a preset threshold of the DMA base counter, and when the value of the DMA base counter is greater than or equal to the preset threshold of the DMA base counter, the value of the DMA base counter is reset to 0.

[0112] Through step S210 and step S220, the DMA basic counter can realize cycle counting, that is, it can count upwards by itself, or count downwards by itself. Other methods for realizing cycle counting are equivalent to "the value of the DMA basic counter increases by a fixed value every at least one clock cycle" + step S210 + step S220 of the present application.

[0113] When the value of the DMA base counter is greater than or equal to the DMA base counter threshold, the DMA source address is one of the following:

[0114] The value of the DMA source address remains unchanged;

[0115] The value of the DMA source address is equal to a preset value; and / or,

[0116] The DMA destination address is one of the following:

[0117] The value of the DMA destination address remains unchanged;

[0118] The value of the DMA destination address is equal to the preset value.

[0119] When the DMA base counter starts a new cycle counting, the value of the DMA source address and / or the DMA destination address remains unchanged or equal to a preset value.

[0120] The DMA transfer task can be performed once or multiple times. The data transferred each time can be 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes or other integer multiples of bytes. The data transferred each time can also be of other widths, such as 4 bits, 11 bits, etc.

[0121] The DMA transfer task may also be multiple transfers, and the DMA source address remains unchanged after each transfer and / or the DMA destination address remains unchanged after each transfer.

[0122] In yet another embodiment, see Figure 2 As shown, the DMA handling task is multiple handlings, and also includes:

[0123] S310, preset the DMA source address upper limit, preset the DMA source address lower limit and preset the DMA source address increment each time;

[0124] S320, calculating the DMA source address after each transfer, the DMA source address after each transfer is calculated by the following formula: (DMA source address before each transfer - DMA source address lower limit + DMA source address increment each time) % (DMA source address upper limit - DMA source address lower limit) + DMA source address lower limit;

[0125] and / or,

[0126] S330, preset the DMA destination address upper limit, preset the DMA destination address lower limit and preset the DMA destination address increment each time;

[0127] S340, calculating the DMA destination address after each transfer, the DMA destination address after each transfer is calculated by the following formula: (DMA destination address before each transfer - DMA destination address lower limit + DMA destination address increment each time) % (DMA destination address upper limit - DMA destination address lower limit) + DMA destination address lower limit.

[0128] After each transfer is completed, the DMA source address and the DMA destination address after the transfer are calculated by the above method, and the calculated DMA source address is used as the DMA source address of the next transfer, and the calculated DMA destination address is used as the DMA destination address of the next transfer.

[0129] After each transfer is completed, the DMA source address and / or the DMA destination address are cyclically increased or cyclically decreased. By adding and / or subtracting the DMA source address and / or the DMA destination address after the transfer, and then assigning values ​​to the DMA source address and / or the DMA destination address at a fixed time to achieve cyclic addition or decrease, it is equivalent to the method of the present invention.

[0130] For example, if the DMA transfer task is multiple transfers, the DMA source address is 0x2100, the DMA source address upper limit is 0x2105, the preset DMA source address lower limit is 0x2100, and the preset DMA source address increment is 1 each time; then the DMA source address after each transfer is calculated by the following formula: (DMA source address before each transfer - 0x2100 + 1) % (0x2105 - 0x2100) + 0x2100; where "%" means to find the remainder, and the "%" operation level is higher than "+" and "-". In the first 7 clock cycles, the DMA source address after each transfer is shown in Table 1:

[0131] Table 1

[0132] Clock cycle 1 2 3 4 5 6 7 …… DMA source address before each transfer 0x2100 0x2101 0x2102 0x2103 0x2104 0x2100 0x2101 …… DMA source address after each transfer 0x2101 0x2102 0x2103 0x2104 0x2100 0x2101 0x2102 ……

[0133] Before each DMA transfer, the value of the DMA basic counter is obtained, which is recorded as the DMA transfer time before. After the DMA transfer, the value of the DMA basic counter is obtained, which is recorded as the DMA transfer time after. DMA transfer time = (DMA transfer time after - DMA transfer time before + DMA basic counter threshold) % DMA basic counter threshold. For example: the DMA transfer time before is 1, the DMA transfer time after is 2, the DMA basic counter threshold is 336, and the DMA transfer time is 1 clock cycle.

[0134] The method of the present application also includes: 1. A method that is invisible or includes step S100, step S200 and step S300, and explicitly or implicitly combines some or all of the operations in step S210, step S220, step S310, step S320, step S330 and step S340; 2. An operation method that is indirectly implemented, equivalent to, or can be converted into 1 by exchanging the order of transformation.

[0135] For example Figure 3 As shown, the data (each data 1 byte) at 32 discontinuous address locations (such as 0x2000, 0x2100, 0x2150, 0x2200, etc.) in the data storage in the memory is displayed on the test terminal at a speed of 500K times per second to achieve continuous observation, which is equivalent to the oscilloscope or logic analyzer performing timed measurement or observation on internal variables or signals. We move the data at these 32 discontinuous address locations to the data storage of the USB module, and then transmit them to the test terminal by the USB module to achieve the observation purpose. Figure 4 As shown, the data at each discontinuous address location is moved to the data memory of the USB module, which is a DMA task, denoted as D. Figure 4 D1 in the figure indicates that the first data in the 32 discontinuous address locations is moved to the data memory location 1 of the USB module; Figure 4 D2 in the figure indicates that the second data is transferred to the data memory location 2 of the USB module... Figure 4 Here, D32 indicates that the 32nd data is moved to the data memory location 32 of the USB module. The processor frequency is 168MHz, and the clock cycle is about 5.95ns; the value of the DMA basic counter increases by 1 every clock cycle, and the threshold of the basic counter is 336. When the value of the DMA basic counter is greater than or equal to 336, the value of the DMA basic counter is reset to 0; we set the DMA timing value to 1, and preset the corresponding D1 as the corresponding DMA transfer task... We set the DMA timing value to 32, and preset the corresponding D32 as the corresponding DMA transfer task; each DMA transfer task has preset the DMA source address (32 discontinuous address locations) and DMA destination address (the corresponding location of the USB module's data memory) as above, such as: the first DMA transfer task D1 has preset the DMA source address (the first data address in the data at the 32 discontinuous address locations) and DMA destination address (data memory location 1 of the USB module); the DMA transfer task is one transfer, and each time 1 byte is transferred; the DMA source address and DMA destination address remain unchanged after each transfer; when the value of the DMA basic counter is greater than or equal to the threshold of the DMA basic counter, the DMA source address and DMA destination address remain unchanged. Figure 4 As shown, after making these presets, the value of the DMA basic counter increases cyclically. When the trigger condition is met, the data at the 32 discontinuous address locations can be moved to the data storage of the USB module without the need for processor access, which is completed efficiently.

[0136] For such a demand, the current implementation method takes ST's STM32F407 or domestic MCU compatible with STM32F407 as an example. The operating frequency is 168MHz. There are only 14 general timers in STM32F407 (14 timers, respectively recorded as TIM1, TIM2...TIM14), which can only realize 14 timed discontinuous address data transfer. After comprehensive consideration, it is necessary to use the "software + general timer function in the controller chip + DMA" method to achieve, such as Figure 5As shown, 11 timers are used, and the software is used to implement the task in 3 groups. Specifically, 32 DMA handling tasks are first divided into 3 groups, and the number of DMA handling tasks in each group is 11, 11, and 10 respectively; these 11 general timers and DMA modules first implement the first group of 11 DMA handling tasks (D1~D11), and when the TIM11 timing arrives, while executing the DMA handling tasks, the processor is triggered by an interrupt, and the processor associates the 11 general timers and DMA modules with the second group of 11 DMA handling tasks (D12~D22); as time goes by, these 11 general timers and DMA modules implement the second group of 11 DMA handling tasks (D12~D22), and when the TIM11 timing arrives, while executing the DMA handling tasks, the processor is triggered by an interrupt, and the processor associates the 10 general timers and DMA modules with the third group of 10 DMA handling tasks (D23~D32), and so on. In the process of implementing 32 DMA transfer tasks, the processor will be involved 3 times, each time taking up about 30 clock cycles, a total of 90 clock cycles of the processor, with a processing cycle of 500KHz (clock is 168MHz, 336 clock cycles), accounting for about 26% of the processing time. It can be seen that this implementation method will not only add 10 timers, but also take up 26% of the processing time.

[0137] The present application only requires a DMA basic counter, the value of which increases by a fixed value every at least one clock cycle. By presetting at least one DMA timing value, presetting the trigger condition, and presetting the DMA transfer task corresponding to each DMA timing value, when the trigger condition is met, at least the DMA transfer task corresponding to the DMA timing value is executed to transfer the data on the DMA source address to the DMA destination address.

[0138] Compared with the "general timer (TIMER) function + DMA in the controller chip" in the prior art, this application only needs one DMA basic counter and does not require a large number of timers (TIMER) to achieve efficient transportation of a large amount of timing data, especially the efficient transportation of a large amount of timing discontinuous address data, saving a large number of general timers and saving costs.

[0139] Compared with the existing technology of "software + general timer function in the controller chip + DMA", because there is no intervention of processor software, it does not occupy processor resources, improves processor efficiency, and the real-time performance is much better, and the software will not become complicated.

[0140] Therefore, compared with the current implementation method, the method of the present invention has the following advantages: 1. It has 10 fewer timers; 2. It does not occupy processor resources because there is no intervention of processor software, which improves the processor processing efficiency by 26% compared with the current implementation method; 3. In particular, the more tasks there are for carrying timed discontinuous address data, the more obvious the advantages are.

[0141] To achieve the timed change of multiple discontinuous address variables, it is equivalent to the signal source function, which is the reverse process of the above example.

[0142] See also Figure 6 As shown, Figure 6 It is a structural framework diagram of an embodiment of the device of the present invention.

[0143] A synchronous time-based DMA device includes a DMA base counter, wherein the value of the DMA base counter increases by a fixed value every at least one clock cycle, including:

[0144] The fifth preset module M800 is used to preset a fixed value.

[0145] A first preset module M100, the first preset module is used to preset at least one DMA timing value, preset a DMA handling task corresponding to each DMA timing value, and preset a trigger condition;

[0146] A first comparison module M200, the first comparison module is used to compare the value of the DMA basic counter with a preset DMA timing value;

[0147] A first execution module M300, when a trigger condition is met, the first execution module M300 is used to execute a DMA handling task corresponding to the DMA timing value;

[0148] The trigger condition is: the value of the DMA basic counter is equal to any preset DMA timing value, or the value of the DMA basic counter is less than any preset DMA timing value, or the value of the DMA basic counter is greater than any preset DMA timing value;

[0149] The DMA transfer task includes a DMA source address and a DMA destination address, and executing the DMA transfer task is to transfer the data on the DMA source address to the DMA destination address.

[0150] The DMA transfer task can be performed once or multiple times, and the data transferred each time can be 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes or other integer multiples of bytes.

[0151] The DMA transfer task is multiple transfers, and the DMA source address remains unchanged after each transfer and / or the DMA destination address remains unchanged after each transfer.

[0152] DMA handling tasks include multiple handlings, including:

[0153] A second preset module M400, the second preset module is used to preset the DMA source address upper limit, preset the DMA source address lower limit and preset each increment of the DMA source address;

[0154] The first operation module M900 is used to calculate the DMA source address after each transfer. The DMA source address after each transfer is calculated by the following formula: (DMA source address before each transfer - DMA source address lower limit + DMA source address increment each time) % (DMA source address upper limit - DMA source address lower limit) + DMA source address lower limit; and / or,

[0155] A third preset module M500, the third preset module is used to preset the DMA destination address upper limit, preset the DMA destination address lower limit and preset each increment of the DMA destination address;

[0156] The second operation module M910 is used to calculate the DMA destination address after each transfer. The DMA destination address after each transfer is calculated by the following formula: (DMA destination address before each transfer - DMA destination address lower limit + DMA destination address increment each time) % (DMA destination address upper limit - DMA destination address lower limit) + DMA destination address lower limit.

[0157] The device of the present invention further comprises:

[0158] A fourth preset module M600, the fourth preset module is used to preset the threshold of the DMA basic counter;

[0159] The second comparison module M700 is used to compare the value of the DMA basic counter with a preset threshold of the DMA basic counter. When the value of the DMA basic counter is greater than or equal to the preset threshold of the DMA basic counter, the value of the DMA basic counter is reset to 0.

[0160] The device of the present invention further comprises:

[0161] There are multiple DMA transfer tasks corresponding to the DMA timing value.

[0162] The device of the present invention further includes a second execution module M310, which is used to execute the following tasks when the value of the DMA basic counter is greater than or equal to the threshold of the DMA basic counter;

[0163] The DMA source address is one of the following:

[0164] The value of the DMA source address remains unchanged;

[0165] The value of the DMA source address is equal to a preset value; and / or,

[0166] The DMA destination address is one of the following:

[0167] The value of the DMA destination address remains unchanged;

[0168] The value of the DMA destination address is equal to the preset value.

[0169] The device of the present invention also includes: obtaining the value of the DMA basic counter before each DMA transfer, recorded as the DMA transfer time before, obtaining the value of the DMA basic counter after the DMA transfer, recorded as the DMA transfer time after, DMA transfer time = (DMA transfer time after - DMA transfer time before + DMA basic counter threshold) % DMA basic counter threshold.

[0170] The device of the present application also includes: 1. Invisibly being or invisibly including M100, M200 and M300; 2. In the chip, realizing the combination of the functions of M100, M200 and M300, and these combinations are the combination of different parts scattered in the chip; 3. Including 1 or 2, and explicitly or implicitly combining with part or all of M400, M500, M600, M700, M800, M900 and M910; 4. By exchanging the order of transformation, or indirectly realizing, or being equivalent to, or being convertible into a device of 1 or 2 or 3.

[0171] See also Figure 7 As shown, Figure 7 It is a structural framework diagram of an embodiment of the system of the present invention.

[0172] A DMA system based on synchronous time includes a DMA device based on synchronous time. The system also includes embedded software, a chip and a debugging terminal. The embedded software is in a program memory. The device moves data on a DMA source address in the chip to a DMA destination address according to the preset of the embedded software or the debugging terminal.

[0173] Obviously, the above-described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0174] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0175] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.

[0176] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for DMA based on synchronous time, comprising a DMA base counter, wherein the value of the DMA base counter increases by a fixed value every at least one clock cycle, characterized in that: include: Preset at least one DMA timing value, preset a DMA handling task corresponding to each DMA timing value, and preset a trigger condition; Comparing the value of the DMA base counter with the preset DMA timing value; When the trigger condition is met, executing the DMA handling task corresponding to the DMA timing value; The trigger condition is: the value of the DMA basic counter is equal to any preset DMA timing value, or the value of the DMA basic counter is less than any preset DMA timing value, or the value of the DMA basic counter is greater than any preset DMA timing value; The DMA transfer task includes a DMA source address and a DMA destination address, and executing the DMA transfer task is to transfer the data at the DMA source address to the DMA destination address; The DMA transfer task is multiple transfers, and the data transferred each time is 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes or other integer multiples of bytes; After each transfer, the DMA source address and / or the DMA destination address are calculated by the following method; The DMA source address remains unchanged after each transfer and / or the DMA destination address remains unchanged after each transfer; or, Preset the upper limit of the DMA source address, preset the lower limit of the DMA source address and preset each increment of the DMA source address; Calculate the DMA source address after each transfer, and the DMA source address after each transfer is calculated by the following formula: (the DMA source address before each transfer - the DMA source address lower limit + the DMA source address increment each time) % (the DMA source address upper limit - the DMA source address lower limit) + the DMA source address lower limit; or, Preset the upper limit of the DMA destination address, preset the lower limit of the DMA destination address and preset each increment of the DMA destination address; Calculate the DMA destination address after each transfer. The DMA destination address after each transfer is calculated by the following formula: (the DMA destination address before each transfer - the DMA destination address lower limit + the DMA destination address increment each time) % (the DMA destination address upper limit - the DMA destination address lower limit) + the DMA destination address lower limit.

2. The method of DMA based on synchronous time according to claim 1, characterized in that: Also includes: Presetting a threshold of the DMA basic counter; The value of the DMA base counter is compared with a preset threshold of the DMA base counter, and when the value of the DMA base counter is greater than or equal to the preset threshold of the DMA base counter, the value of the DMA base counter is reset to 0.

3. The method of DMA based on synchronous time according to claim 1, characterized in that: Each of the DMA timing values ​​corresponds to a plurality of DMA transfer tasks.

4. The method of DMA based on synchronous time according to claim 2, characterized in that: When the value of the DMA base counter is greater than or equal to the threshold of the DMA base counter, the DMA source address is one of the following: The value of the DMA source address remains unchanged; The value of the DMA source address is equal to a preset value; and / or, The DMA destination address is one of the following: The value of the DMA destination address remains unchanged; The value of the DMA destination address is equal to a preset value.

5. The method of DMA based on synchronous time according to claim 2, characterized in that: The value of the DMA basic counter is obtained before each DMA transfer, which is recorded as the time before DMA transfer. The value of the DMA basic counter is obtained after the DMA transfer, which is recorded as the time after DMA transfer. DMA transfer time = (the time after DMA transfer - the time before DMA transfer + the threshold of the DMA basic counter) % the threshold of the DMA basic counter.

6. The method of DMA based on synchronous time according to claim 1, characterized in that: The fixed value is a preset value.

7. A synchronous time-based DMA device, comprising a DMA base counter, wherein the value of the DMA base counter increases by a fixed value every at least one clock cycle, wherein: include: A first preset module, the first preset module is used to preset at least one DMA timing value, preset a DMA handling task corresponding to each of the DMA timing values, and preset a trigger condition; A first comparison module, the first comparison module is used to compare the value of the DMA basic counter with the preset DMA timing value; A first execution module, when the trigger condition is met, the first execution module is used to execute the DMA handling task corresponding to the DMA timing value; The trigger condition is: the value of the DMA basic counter is equal to any preset DMA timing value, or the value of the DMA basic counter is less than any preset DMA timing value, or the value of the DMA basic counter is greater than any preset DMA timing value; The DMA transfer task includes a DMA source address and a DMA destination address, and executing the DMA transfer task is to transfer the data at the DMA source address to the DMA destination address; The DMA transfer task is multiple transfers, and the data transferred each time is 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes or other integer multiples of bytes; The synchronous time-based DMA device also includes: The DMA source address remains unchanged after each transfer and / or the DMA destination address remains unchanged after each transfer; or, A second preset module, the second preset module is used to preset the upper limit of the DMA source address, preset the lower limit of the DMA source address, and preset each increment of the DMA source address; A first calculation module, the first calculation module is used to calculate the DMA source address after each transfer, and the DMA source address after each transfer is calculated by the following formula: (the DMA source address before each transfer-the DMA source address lower limit+the DMA source address increment each time)%(the DMA source address upper limit-the DMA source address lower limit)+the DMA source address lower limit; or, A third preset module, the third preset module is used to preset the upper limit of the DMA destination address, preset the lower limit of the DMA destination address, and preset each increment of the DMA destination address; The second operation module is used to calculate the DMA destination address after each transfer. The DMA destination address after each transfer is calculated by the following formula: (the DMA destination address before each transfer - the DMA destination address lower limit + the DMA destination address increment each time) % (the DMA destination address upper limit - the DMA destination address lower limit) + the DMA destination address lower limit.

8. The device based on synchronous time DMA according to claim 7, characterized in that: Also includes: A fourth preset module, the fourth preset module is used to preset the threshold of the DMA basic counter; The second comparison module is used to compare the value of the DMA basic counter with a preset threshold of the DMA basic counter. When the value of the DMA basic counter is greater than or equal to the preset threshold of the DMA basic counter, the value of the DMA basic counter is reset to 0.

9. The device based on synchronous time DMA according to claim 7, characterized in that: Each of the DMA timing values ​​corresponds to a plurality of DMA transfer tasks.

10. The synchronous time-based DMA device according to claim 8, characterized in that: Also included is a second execution module, wherein the second execution module is used to perform the following tasks when the value of the DMA basic counter is greater than or equal to the threshold value of the DMA basic counter; The DMA source address is one of the following: The value of the DMA source address remains unchanged; The value of the DMA source address is equal to a preset value; and / or, The DMA destination address is one of the following: The value of the DMA destination address remains unchanged; The value of the DMA destination address is equal to a preset value.

11. The device based on synchronous time DMA according to claim 8, characterized in that: The value of the DMA basic counter is obtained before each DMA transfer, which is recorded as the time before DMA transfer. The value of the DMA basic counter is obtained after the DMA transfer, which is recorded as the time after DMA transfer. DMA transfer time = (the time after DMA transfer - the time before DMA transfer + the threshold of the DMA basic counter) % the threshold of the DMA basic counter.

12. The device based on synchronous time DMA according to claim 7, characterized in that: It also includes a fifth preset module, and the fifth preset module is used to preset a fixed value.

13. A system based on synchronous time DMA, characterized in that: The system comprises the device as claimed in any one of claims 7 to 12, wherein the system further comprises embedded software, a chip and a debugging terminal, and the device moves the data at the DMA source address in the chip to the DMA destination address according to the preset of the embedded software or the debugging terminal.

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