Sparse matrix operation method, device and computing equipment

Abstract

The embodiments disclosed in the present application belong to the field of computing technology, and particularly relate to a sparse matrix operation method, processor, and computing device. The processor includes a sparse matrix processing unit and a sparse vector operation unit. The operation method executed by the processor includes: the sparse matrix processing unit obtains a first numerical matrix and a first index matrix corresponding to the first sparse matrix, and a second numerical matrix and a second index matrix corresponding to the second sparse matrix. The sparse vector operation unit determines the target elements that need to be dot-producted in each row element of the first numerical matrix and each column element of the second numerical matrix based on each row element of the first index matrix and each column element included in the second index matrix, and performs a dot product operation on the target elements to obtain a first result matrix of the sparse multiplication operation performed on the first sparse matrix and the second sparse matrix. By adopting the present application, the number of zero elements involved in sparse matrix multiplication can be reduced, and the efficiency of performing sparse matrix multiplication can be improved.

Description

[0001] This application is a divisional application. The application number of the original application is 202311240428.9, and the original application date is September 22, 2023. The entire content of the original application is incorporated into this application by reference.

[0002] This application and the Chinese application with application number 202311240428.9 both claim priority to the Chinese patent application with application number 202310781382.5 filed on June 28, 2023, with invention name “A Sparse Matrix Multiplication Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computing technology, and in particular to a sparse matrix operation method, processor, and computing device. Background Art

[0004] Matrix multiplication is widely used in various scientific computing scenarios. Due to the varying density of the matrices involved, matrix multiplication is primarily categorized into dense and sparse matrix multiplication. Dense matrix multiplication is typically used in traditional machine learning and neural network model computations, while sparse matrix multiplication is primarily used in graph computing, graph neural networks, and multigrid solvers.

[0005] Since a sparse matrix includes a large number of zero elements, a large number of zero elements will participate in the matrix multiplication operation during the execution of sparse matrix multiplication, which leads to low efficiency of matrix operation. Summary of the Invention

[0006] The embodiments of the present application provide a sparse matrix operation method, processor, and computing device, which can improve the execution efficiency of sparse matrix multiplication. The corresponding technical solutions are as follows:

[0007] In a first aspect, a sparse matrix operation method is provided, the method being executed by a processor including a sparse matrix processing unit and a sparse vector operation unit, the method comprising:

[0008] The sparse matrix processing unit inputs the first numerical matrix and the first index matrix corresponding to the first sparse matrix processed by the sparse matrix processing unit, and the second numerical matrix and the second index matrix corresponding to the second sparse matrix to the sparse vector operation unit, wherein each non-zero element in the first index matrix is used to indicate the column number corresponding to the non-zero element at the same position in the first numerical matrix, and each non-zero element in the second index matrix is used to indicate the row number corresponding to the non-zero element at the same position in the second numerical matrix. The sparse vector operation unit determines the target elements that need to be dot-producted among the non-zero elements in each row of the first numerical matrix and the non-zero elements in each column of the second numerical matrix based on the non-zero elements in each row of the first index matrix and the non-zero elements in each column of the second index matrix, and performs the dot product operation on the target elements to obtain a first result matrix of the sparse multiplication operation performed on the first sparse matrix and the second sparse matrix.

[0009] Among them, the first numerical matrix is obtained by compressing the non-zero elements in the first sparse matrix in the row direction, and the second numerical matrix is obtained by compressing the non-zero elements in the second sparse matrix in the column direction. In the solution provided by the present application, the sparse matrix processing unit can determine the target elements in the first numerical matrix and the second data matrix that need to be dot-producted according to the row number and column number indicated by the non-zero elements in each row of the first index matrix and each column of the second index matrix, and perform the dot product operation on the target elements, thereby obtaining the first result matrix of the sparse multiplication operation performed on the first sparse matrix and the second sparse matrix. It can be seen that the solution shown in the present application can avoid the operation of a large number of zero elements in the sparse multiplication process, and can improve the efficiency of the processor in performing sparse multiplication operations.

[0010] In one implementable manner, the sparse vector operation unit determines, based on each row of elements included in the first index matrix and the second index matrix, target elements requiring dot product operation in each row of elements in the first numerical matrix and the second numerical matrix, and performs the dot product operation on the target elements to obtain a first result matrix of the sparse multiplication operation performed on the first sparse matrix and the second sparse matrix, including:

[0011] The sparse vector operation unit determines the first position of the mth row and the second position of the nth column of the same non-zero element included in the mth row of the first index matrix and the nth column of the second index matrix, respectively. A dot product operation is performed on the target element at the first position of the mth row of the first data matrix and the target element at the second position of the nth column of the second data matrix to obtain the element at the mth row and nth column of the first result matrix.

[0012] In one implementable manner, the method further includes: the sparse matrix processing unit obtains a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix, wherein the third numerical matrix includes a plurality of first numerical matrix blocks, the third index matrix includes a first index matrix block corresponding to each first numerical matrix block, the fourth numerical matrix includes a plurality of second numerical matrix blocks, and the fourth index matrix includes a plurality of second index matrix blocks corresponding to each second numerical matrix block. The sparse matrix processing unit determines the Cartesian product of the first numerical matrix block of the non-zero matrix block in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix block in the j-th column of the fourth numerical matrix.

[0013] Before the sparse matrix processing unit inputs the first numerical matrix and the first index matrix corresponding to the first sparse matrix obtained by the sparse matrix processing unit and the second numerical matrix and the second index matrix corresponding to the second sparse matrix obtained by the sparse matrix processing unit into the sparse vector operation unit, it also includes: the sparse matrix processing unit determines that the first numerical matrix block and the second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are respectively the first numerical matrix and the second numerical matrix, determines that the first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determines that the second index matrix block corresponding to the second numerical matrix block is the second index matrix.

[0014] In one implementable manner, the method further includes: the sparse matrix processing unit sums the first result matrix corresponding to each group of numerical matrix blocks included in the Cartesian product to obtain the matrix block in the i-th row and j-th column of the second result matrix in which the third sparse matrix and the fourth sparse matrix perform sparse multiplication operations.

[0015] In the scheme shown in the present application, the sparse matrix processing unit compresses the third sparse matrix and the fourth sparse matrix that perform sparse multiplication operations into a third numerical matrix, a third index matrix, a fourth numerical matrix and a fourth index matrix, respectively, and divides the third numerical matrix, the third index matrix, the fourth numerical matrix and the fourth index matrix into blocks to obtain multiple first numerical matrix blocks, second numerical matrix blocks, first index matrix blocks and second index matrix blocks. In this way, the second result matrix is calculated respectively by the above-mentioned numerical matrix blocks and index matrix blocks, which can avoid the zero matrix block from participating in the sparse multiplication operation process, and can improve the efficiency of the processor in performing sparse multiplication operations.

[0016] In addition, for each set of numerical matrix blocks included in the Cartesian product, namely the first numerical matrix block and the second numerical matrix block for performing the matrix multiplication operation, the first numerical matrix block is determined to be the above-mentioned first numerical matrix, and the second numerical matrix block is determined to be the above-mentioned second numerical matrix. According to the above-mentioned operation method for calculating the first numerical matrix and the second numerical matrix, the operation of the first numerical matrix block and the second numerical matrix block is performed, which can further improve the efficiency of the processor in performing the sparse multiplication operation.

[0017] In one achievable embodiment, the third numerical matrix includes L×M first numerical matrix sections, each of which includes at least one first numerical matrix block. The third index matrix includes L×M third index matrix sections, each of which includes at least one first index matrix block. The fourth numerical matrix includes M×N second numerical matrix sections, each of which includes at least one second numerical matrix block. The fourth index matrix includes M×N second index matrix sections, each of which includes at least one second index matrix block.

[0018] In the solution shown in the present application, the third numerical matrix, the third index matrix, the fourth numerical matrix, and the fourth index matrix can be partitioned, and then the second result matrix corresponding to the third sparse matrix and the fourth sparse matrix can be calculated based on the first numerical matrix area, the first index matrix area, the second numerical matrix area, and the second index matrix area, respectively. The zero matrix area in the first numerical matrix area and the second numerical matrix area can be excluded from the calculation, thereby improving the efficiency of the processor in performing sparse multiplication operations.

[0019] In one implementable manner, the method further includes: the sparse matrix processing unit determining the number of non-zero matrix regions in the L×N matrix regions included in the second result matrix based on the first position of the zero matrix region in the third numerical matrix, the second position of the non-zero matrix region in the third numerical matrix, and the third position of the zero matrix region in the fourth numerical matrix and the fourth position of the non-zero matrix region in the fourth numerical matrix among the M×N second numerical matrix regions. Storage space is allocated in a memory for the second result matrix based on the number of non-zero matrix regions.

[0020] In the scheme shown in the present application, storage space is applied for the second result matrix in the memory according to the number of non-zero matrix areas included in the second result matrix. On the one hand, the storage space occupied by the second result matrix can be reduced. On the other hand, according to the positions of the zero matrix area and the non-zero matrix area of the first numerical matrix area and the second numerical matrix area, the number of non-zero matrix areas included in the second result matrix is determined, which can reduce the complexity of the alignment judgment.

[0021] In one implementable manner, the sparse matrix processing unit determines the Cartesian product of the first numerical matrix block of the non-zero matrix block in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix block in the j-th column of the fourth numerical matrix, including: if the sparse matrix processing unit determines that the k-th first numerical matrix block group in the i-th row and the k-th second numerical matrix block group in the j-th column meet the operation condition, then determines the Cartesian product of the first numerical matrix block of each non-zero matrix block and the second numerical matrix block of each non-zero matrix block included in the k-th first numerical matrix block group and the k-th second numerical matrix block group. Wherein, the first numerical matrix block group includes the first numerical matrix block in the same first numerical matrix area in the i-th row, and the second numerical matrix block group includes the second numerical matrix block in the same second numerical matrix area in the j-th column, and the operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

[0022] In the scheme shown in the present application, the sparse matrix processing unit can avoid the numerical matrix blocks that do not include non-zero numerical matrix blocks from participating in sparse multiplication operations by performing bitwise judgment on the numerical matrix block group, thereby improving the efficiency of the processor in performing sparse multiplication operations.

[0023] In a second aspect, a processor is provided, the processor including a sparse matrix processing unit and a sparse vector operation unit, wherein:

[0024] a sparse matrix processing unit, configured to input into the sparse vector operation unit a first numerical matrix and a first index matrix corresponding to the first sparse matrix, and a second numerical matrix and a second index matrix corresponding to the second sparse matrix, obtained after processing by the sparse matrix processing unit, wherein each non-zero element in the first index matrix is used to indicate a column number corresponding to a non-zero element at a same position in the first numerical matrix, and each non-zero element in the second index matrix is used to indicate a row number corresponding to a non-zero element at a same position in the second numerical matrix;

[0025] The sparse vector operation unit is used to determine the target elements in each row of elements in the first numerical matrix and the second numerical matrix that need to be subjected to dot product operation based on each row of elements included in the first index matrix and the second index matrix, and perform the dot product operation on the target elements to obtain a first result matrix of the sparse multiplication operation performed on the first sparse matrix and the second sparse matrix.

[0026] In one implementable manner, the sparse vector operation unit is configured to determine the first position in the mth row and the second position in the nth row of the same element included in the mth row of the first index matrix and the nth row of the second index matrix, respectively;

[0027] The sparse vector operation unit is used to perform a dot product operation on the target element at the first position of the mth row of the first data matrix and the target element at the second position of the nth row of the second data matrix to obtain the element at the mth row and nth column in the first result matrix.

[0028] In one implementable manner, the sparse matrix processing unit is configured to obtain a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix, wherein the third numerical matrix includes a plurality of first numerical matrix blocks, the third index matrix includes a first index matrix block corresponding to each first numerical matrix block, the fourth numerical matrix includes a plurality of second numerical matrix blocks, and the fourth index matrix includes a plurality of second index matrix blocks corresponding to each second numerical matrix block;

[0029] The sparse matrix processing unit is used to determine the Cartesian product of the first numerical matrix block of the non-zero matrix block in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix block in the j-th column of the fourth numerical matrix.

[0030] The sparse matrix processing unit is also used to determine that the first numerical matrix block and the second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are respectively the first numerical matrix and the second numerical matrix, determine that the first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determine that the second index matrix block corresponding to the second numerical matrix block is the second index matrix.

[0031] The sparse matrix processing unit is also used to sum the first result matrix corresponding to each group of numerical matrix blocks included in the Cartesian product to obtain the matrix block in the i-th row and j-th column of the second result matrix of the sparse multiplication operation performed by the third sparse matrix and the fourth sparse matrix.

[0032] In one implementable manner, the third numerical matrix includes L×M first numerical matrix areas, each first numerical matrix area includes at least one first numerical matrix block, and the third index matrix includes L×M third index matrix areas, each first index matrix area includes at least one first index matrix block;

[0033] The fourth numerical matrix includes M×N second numerical matrix areas, each of which includes at least one second numerical matrix block. The fourth index matrix includes M×N second index matrix areas, each of which includes at least one second index matrix block.

[0034] In one implementable manner, the sparse matrix processing unit is configured to determine the number of non-zero matrix regions in the L×N matrix regions included in the second result matrix based on a first position of a zero matrix region in the third numerical matrix, a second position of a non-zero matrix region in the third numerical matrix, and a third position of a zero matrix region in the fourth numerical matrix, and a fourth position of a non-zero matrix region in the fourth numerical matrix among the M×N second numerical matrix regions;

[0035] The sparse matrix processing unit is configured to apply for storage space for the second result matrix in the memory based on the number of non-zero matrix regions.

[0036] In one implementable manner, the sparse matrix processing unit, configured to determine the Cartesian product of a first numerical matrix block of non-zero matrix blocks in an i-th row of a third numerical matrix and a second numerical matrix block of non-zero matrix blocks in a j-th column of a fourth numerical matrix, includes:

[0037] A sparse matrix processing unit is configured to determine a Cartesian product of a first numerical matrix block of each non-zero matrix block and a second numerical matrix block of each non-zero matrix block included in the kth first numerical matrix block group and the kth second numerical matrix block group if it is determined that the kth first numerical matrix block group in the i-th row and the kth second numerical matrix block group satisfy an operation condition; wherein,

[0038] The first numerical matrix block group includes the first numerical matrix block in the same first numerical matrix area in the i-th row, and the second numerical matrix block group includes the second numerical matrix block in the same second numerical matrix area in the j-th column. The operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

[0039] In a third aspect, a computing device is provided, comprising a memory and a processor as described in the second aspect above, wherein the memory stores at least one instruction, and the processor executes at least one instruction to execute the method described in the first aspect and / or any achievable method of the first aspect.

[0040] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program code. When the computer program code is executed by a computer device, the computer device executes the method described in the first aspect and / or any achievable method of the first aspect.

[0041] In a fifth aspect, a computer program product comprising instructions is provided, which, when executed on a computing device, enables the computing device to execute the method described in the first aspect and / or any achievable method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic diagram of performing matrix multiplication operation in related art;

[0043] Figure 2 is a structural diagram of a computing device provided in an embodiment of the present application;

[0044] Figure 3 This is a schematic diagram of compressing a sparse matrix provided in an embodiment of the present application;

[0045] Figure 4 This is a schematic diagram of compressing a sparse matrix provided in an embodiment of the present application;

[0046] Figure 5 This is a flow chart of a sparse matrix operation method provided in an embodiment of the present application;

[0047] Figure 6 This is a schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0048] Figure 7 This is a flow chart of a sparse matrix operation method provided in an embodiment of the present application;

[0049] Figure 8 This is a schematic diagram of a sparse matrix operation method provided in an embodiment of the present application;

[0050] Figure 9 This is a schematic diagram of a sparse matrix operation method provided in an embodiment of the present application;

[0051] Figure 10 This is a schematic diagram of a sparse matrix operation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0053] Matrix multiplication is widely used in various scientific computing scenarios. The density of the matrices involved varies across different computing scenarios, and matrix multiplication is primarily categorized into dense and sparse matrix multiplication. Dense matrix multiplication is typically used in traditional machine learning and neural network model calculations, while sparse matrix multiplication is primarily used in graph computing, graph neural networks, and multigrid solvers.

[0054] Dense matrix multiplication refers to multiplying a dense matrix, while sparse matrix multiplication refers to multiplying a sparse matrix. A sparse matrix is one in which the percentage of non-zero elements is very small (e.g., less than 5%), while a dense matrix is one in which the percentage of non-zero elements is large.

[0055] Currently, the optimization method for matrix multiplication is only effective for dense matrix multiplication. For example, the matrix to be multiplied can be tiled, and then the result matrix of the matrix multiplication can be calculated using the tiling matrix after tiling. Figure 1 This is a schematic diagram of matrix multiplication in related technologies. Figure 1 As shown, for matrix A and matrix B that perform matrix multiplication operations, matrix A can be divided into Tiling matrix A 0,0 , Tiling matrix A 0,1 , Tiling matrix A 1,0 , Tiling matrix A 1,1 , the matrix B can be divided into the Tiling matrix B 0,0 , Tiling matrix B 0,1 , Tiling matrix B 1,0 , Tiling matrix B 1,1 Among them, the result matrix C of matrix multiplication operation performed on matrix A and matrix B can be divided into tiling matrix C 0,0 , Tiling matrix C 0,1 , Tiling matrix C 1,0 , Tiling matrix C 1,1 To calculate the Tiling matrix C 0,0 For example, the Tiling matrix C 0,0 Equal to the Tiling matrix A 0,0 and the Tiling matrix B 0,0 The product of and the tiling matrix A 0,1 and the Tiling matrix B 0,1 This can reduce the size of the matrix and thus reduce the complexity of the matrix multiplication operation, thereby improving the efficiency of the matrix multiplication operation.

[0056] However, sparse matrices contain a large number of zero elements. Even after tiling, the resulting tiling matrix still contains a large number of zero elements, and even some tiling matrices are zero matrices. This constant presence of zero elements during matrix multiplication consumes significant computing and storage resources, resulting in low sparse matrix multiplication efficiency.

[0057] The embodiment of the present application provides a sparse matrix operation method, which can optimize sparse matrix multiplication by combining the characteristics of sparse matrices, and can further improve the execution efficiency of sparse matrix multiplication. Figure 2It is a computing device for executing a sparse matrix operation method provided in an embodiment of the present application. Figure 2 As shown, the computing device 200 may include: a bus 202, a processor 204, a memory 206, and optionally the computing device 200 may further include a communication interface 208. The processor 204, the memory 206 and the communication interface 208 communicate with each other via the bus 202. The computing device 200 may be a server or a terminal device. It should be understood that the present application does not limit the number of processors and memories in the computing device 200. The computing device 200 may be a device for running a model, a terminal or a server. When the computing device 200 is a terminal, the computing device 200 includes but is not limited to a desktop computer, a mobile phone, a notebook, a tablet computer, etc. When the computing device 200 is a server, the computing device 200 may be a separate server, or a server cluster consisting of multiple servers, or a physical machine, or a virtual machine or container virtualized by virtualization technology.

[0058] The bus 202 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a value bus, a control bus, etc. For ease of representation, Figure 2 The fact that only one line is used in the figure does not mean that there is only one bus or only one type of bus. Bus 202 may include a path for transmitting information between various components of computing device 200 (eg, memory 206, processor 204, communication interface 208).

[0059] The processor 204 may include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP). The processor 204 may further include a vector operation unit and a matrix operation unit, wherein the vector operation unit may be a scalable vector extension (SVE) that can be used to perform vector operations involved in sparse matrix multiplication. The matrix operation unit may be a scalable matrix unit (SME) that can be used for matrix operations involved in sparse matrix multiplication.

[0060] The processor 204 includes one or more processor cores. The instructions that the processor core can process include SIMD instructions, SVE instructions, and SME instructions. The data types used and the calculations performed by the processor core when processing different instructions are different. For example, when the processor core processes SIMD instructions, it processes fixed-length data (such as integer data, floating-point data) and performs addition, subtraction, or other calculations on the data. For another example, when the processor core processes SVE instructions, it processes variable-length data (such as integer data, floating-point data) and performs addition, subtraction, or other calculations on the data. For another example, when the processor processes SME instructions, it performs matrix calculations on matrices (such as matrix inner product, matrix outer product). In an embodiment of the present application, the instructions that the processor can process may also include sparse scalable vector extension (SparseSVE, SPSVE) instructions. When the processor core processes SPSVE instructions, it can implement the sparse vector operation method provided in the embodiment of the present application.

[0061] The memory 206 may include a volatile memory, such as a random access memory (RAM). The memory 206 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD). The memory 206 stores an executable program code, and the processor 204 executes the executable program code to implement the sparse matrix operation method provided in the embodiment of the present application.

[0062] The communication interface 208 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 200 and other devices or a communication network.

[0063] To facilitate understanding of the sparse matrix operation method provided in the embodiment of the present application, the sparse compressed Tile matrix used in the embodiment of the present application is first introduced below:

[0064] The sparse compressed tile matrix consists of a data matrix and an index matrix. The data matrix is obtained by sequentially arranging the zero and non-zero elements in the sparse matrix by row or column.

[0065] In one example, the non-zero elements and zero elements included in each row (column) in the sparse matrix can be rearranged continuously to obtain a numerical matrix corresponding to the sparse matrix. The index matrix and the numerical matrix have the same size, and the distribution of zero elements and non-zero elements in the index matrix is consistent with the distribution of zero elements and non-zero elements in the numerical matrix. When the zero elements and non-zero elements in the sparse matrix are rearranged continuously according to rows to obtain the corresponding numerical matrix, each non-zero element in the index matrix is used to indicate the column number of the non-zero elements at the same position in the data matrix in the sparse matrix. When the zero elements and non-zero elements in the sparse matrix are rearranged continuously according to rows and columns to obtain the corresponding data matrix, each non-zero element in the index matrix is used to indicate the row number of the non-zero elements at the same position in the data matrix in the sparse matrix. Wherein, the non-zero elements and zero elements are rearranged continuously respectively, and the non-zero elements can be arranged before the zero elements or after the zero elements.

[0066] like Figure 3 As described above, for a sparse matrix S, if the non-zero elements and zero elements are continuously rearranged by row, the corresponding data matrix A1 and the corresponding index matrix A2 can be obtained. If the non-zero elements and zero elements are continuously rearranged by column, the corresponding data matrix B1 and the corresponding index matrix B2 can be obtained. For example, the value in the 3rd row and 1st column of the index matrix A2 is used to indicate that the element in the 3rd row and 1st column of the data matrix A1 is in the 2nd column of the sparse matrix S. For another example, the value in the 3rd row and 3rd column of the index matrix B2 is used to indicate that the element in the 3rd row and 3rd column of the data matrix B1 is in the 4th row of the sparse matrix S.

[0067] In another example, the sparse matrix can be partitioned first, and then the non-zero elements and zero elements of each row (column) in the matrix block (block) corresponding to each partition are continuously rearranged to obtain the numerical matrix corresponding to the sparse matrix. The index matrix and the numerical matrix have the same size, and the distribution of zero elements and non-zero elements in the index matrix is consistent with the distribution of zero elements and non-zero elements in the numerical matrix. When the zero elements and non-zero elements of the matrix block corresponding to each partition of the sparse matrix are continuously rearranged according to rows to obtain the corresponding data matrix, each non-zero element in the index matrix is used to indicate the column number of the non-zero elements at the same position in the data matrix in the matrix block of the sparse matrix. When the zero elements and non-zero elements of the matrix block corresponding to each partition of the sparse matrix are continuously rearranged according to columns to obtain the corresponding data matrix, each non-zero element in the index matrix is used to indicate the row number of the non-zero elements at the same position in the data matrix in the matrix block of the sparse matrix.

[0068] like Figure 4 As described above, the sparse matrix S can be divided into four partitions, and the matrix regions S corresponding to the four partitions are 0,0 , matrix area S0,1 , matrix area S 1,0 , matrix area S 1,1 If the non-zero elements and zero elements in each matrix region are continuously rearranged by row, the corresponding data matrix A3 and the corresponding index matrix A4 can be obtained. If the non-zero elements and zero elements in each matrix region are continuously rearranged by column, the corresponding data matrix B3 and the corresponding index matrix B4 can be obtained. For example, the value of the 5th row and 5th column in the index matrix A4 is used to indicate that the element of the 5th row and 5th column in the data matrix A3 is in the matrix region S. 1,1 For another example, the value of the 5th row and 6th column in the index matrix B4 is used to indicate that the element of the 5th row and 6th column in the data matrix A3 is in the matrix area S. 1,1 2nd row.

[0069] In the above two examples, before continuously rearranging the non-zero and zero elements by row, if there is a row in the sparse matrix that is all zero, then this row of all zeros can be deleted to reduce the size of the generated data matrix and index matrix. Before continuously rearranging the non-zero and zero elements by column, if there is a column in the sparse matrix that is all zeros, then this column of all zeros can be deleted to reduce the size of the generated data matrix and index matrix.

[0070] Figure 5 This is a flow chart of a sparse matrix operation method provided by an embodiment of the present application. Figure 2 The computing device 200 shown in FIG. 200 is executed, and specifically can be executed by the processor 204. Figure 6 As shown, the processor 204 may include at least a sparse matrix processing unit and a sparse vector operation unit. The sparse matrix processing unit is a hardware part of the processor 204 for processing sparse matrices for performing sparse multiplication operations, such as a processor core. In addition, the sparse matrix processing unit may also refer to a software program run by the processor to process sparse matrices. The sparse vector operation unit (SPSVE) is a vector operation unit in the processor 204 for performing operations on sparse vectors in the present application. In one example, the sparse vector operation unit may be a vector operation unit improved on the basis of the vector operation unit for performing the sparse vector multiplication operations provided in the present application.

[0071] See also Figure 5 , the sparse matrix operation method provided in the embodiment of the present application includes:

[0072] Step 501: The sparse matrix processing unit inputs a first numerical matrix and a first index matrix corresponding to a first sparse matrix processed by the sparse matrix processing unit, and a second numerical matrix and a second index matrix corresponding to a second sparse matrix to a sparse vector operation unit.

[0073] In one example, a computing device may be running an application involving sparse matrix multiplication, such as a high-performance computing (HPC) application, an artificial intelligence (AI) application, or a graph computing application. During operation, when the application needs to perform sparse matrix multiplication, it may send a matrix multiplication operation request to the processor. In response to the matrix multiplication operation request, the processor reads the two sparse matrices to be multiplied from a memory (e.g., a hard disk).

[0074] The above two sparse matrices can be in formats such as CSC (Compressed Sparse Column Format), CSR (Compressed Sparse Row Format), COO (Coordinate Format), etc. Figure 3 or Figure 4 The sparse compressed Tile matrix shown in FIG. 1 can be converted into the sparse compressed Tile matrix used in the embodiment of the present application. The specific conversion method can refer to the above Figure 3 or Figure 4 The content will not be introduced in detail this time.

[0075] Wherein, each row element in the first numerical matrix corresponding to the first sparse matrix is obtained by sequentially arranging the zero elements and non-zero elements in each row element of the first sparse matrix, and the non-zero elements in the first index matrix are the column numbers of the non-zero elements with the same position in the first numerical matrix in the first sparse matrix. Each column element in the second numerical matrix corresponding to the second sparse matrix is obtained by sequentially arranging the zero elements and non-zero elements in each column element of the second sparse matrix, and the non-zero elements in the second index matrix are the row numbers of the non-zero elements with the same position in the second numerical matrix in the second sparse matrix.

[0076] After obtaining the first numerical matrix, the first index matrix, the second numerical matrix, and the second index matrix, the sparse matrix processing unit can sequentially input the first numerical matrix, the first index matrix, including elements of each row, and the second numerical matrix and the second index matrix, including elements of each column, into the sparse vector operation unit to complete the sparse multiplication operation on the first sparse matrix and the second sparse matrix. In one example, the first numerical matrix, the elements of the mth row of the first index matrix, and the elements of the nth column of the second numerical matrix and the second index matrix can be input into the sparse vector operation unit, and the sparse vector operation unit inputs the elements of the mth row and the nth column of the first result matrix corresponding to the first sparse matrix and the second sparse matrix.

[0077] The sparse matrix operation method provided in this application can be written by a technician as a processing function of sparse matrix multiplication, and then added to a mathematical library. The mathematical library can be stored in a computing device that executes the application, including a large number of processing functions, which can be used to implement various mathematical calculations involved in the application. When sparse matrix multiplication needs to be performed in the application, an execution request for sparse matrix multiplication can be sent to the processor, and then the processor can call the processing function of sparse matrix multiplication to implement the processing included and implicitly included in step 501 to step 502.

[0078] Step 502: The sparse vector operation unit determines the target elements that need to be dot-producted among the non-zero elements in each row of the first numerical matrix and the non-zero elements in each column of the second numerical matrix based on the non-zero elements in each row of the first index matrix and the non-zero elements in each column of the second index matrix, performs the dot product operation on the target elements, and obtains a first result matrix of the sparse multiplication operation performed on the first sparse matrix and the second sparse matrix.

[0079] The multiplication operation of any two matrices can be represented as performing a vector dot product operation on the elements of the mth row of the first matrix and the elements of the nth column of the second matrix, and obtaining the elements of the mth row and nth column in the result matrix corresponding to the multiplication operation performed on the two matrices. In an embodiment of the present application, the non-zero elements in the first index matrix are the column numbers of the non-zero elements at the same position in the first data matrix in the first sparse matrix, and the non-zero elements in the second index matrix are the row numbers of the non-zero elements at the same position in the second data matrix in the second sparse matrix. If there are non-zero elements of the same value in one row of the first index matrix and one column of the second index matrix, it means that when the vector dot product operation is performed on the row elements of the corresponding first sparse matrix and the column elements of the second sparse matrix, there is a dot product operation of the non-zero elements in the corresponding position. The position of the non-zero elements in the row of the first numerical matrix is the same as the position of the non-zero elements of the same value in the row of the first index matrix, and the position of the non-zero elements in the row of the second numerical matrix is the same as the position of the non-zero elements of the same value in the row of the second index matrix.

[0080] like Figure 3 As shown, if the two first sparse matrices and the second sparse matrix undergoing sparse multiplication are both sparse matrices S, then the numerical matrix A1 is the first numerical matrix, the index matrix A2 is the first index matrix, the numerical matrix B1 is the second numerical matrix, and the index matrix B2 is the second index matrix. Taking the vector dot product operation of the first row element "11100000" of the first sparse matrix and the second column element "10010000" of the second sparse matrix as an example, where the first row element of the first index matrix is "12300000" and the first column element of the second index matrix is "13000000", it can be seen that the first non-zero element in the first row of the first index matrix is the same as the first non-zero element in the second column of the second index matrix, and the third non-zero element in the first row of the first index matrix is the same as the second non-zero element in the second column of the second index matrix. Therefore, a dot product operation can be performed on the first element and the third element in the first row element "11100000" of the first data matrix and the first element and the second element in the second column element "11000000" of the second data matrix, and the dot product operation result is "2", that is, the vector dot product operation result of the first row element of the first sparse matrix and the second column element of the second sparse matrix is obtained.

[0081] In one example, the processing performed by the sparse vector operation unit in step 502 can be called a sparse vector multiplication operation, and the processor can execute the SPSVE instruction to instruct the sparse vector operation unit to implement the processing of step 502. Therefore, for the operation of the mth row of the first sparse matrix and the nth column of the second sparse matrix, it is converted by the sparse vector operation unit into: the sparse vector operation unit determines that the same non-zero elements included in the mth row of the first index matrix and the nth column of the second index matrix are respectively at the first position in the mth row and the second position in the nth column. The sparse vector operation unit performs a dot product operation on the target element at the first position of the mth row of the first data matrix and the target element at the second position of the nth column of the second data matrix to obtain the element of the mth row and nth column in the first result matrix. After the processor obtains the elements corresponding to each row or column of the first result matrix, it can return the obtained first result matrix to the corresponding application.

[0082] It can be seen that in the embodiment of the present application, the sparse vector operation unit can determine the non-zero elements in the first numerical matrix and the second numerical matrix that need to be subjected to the dot product operation through the first index matrix and the second index matrix, and perform the dot product operation on the corresponding non-zero elements, thereby obtaining a first result matrix of the sparse multiplication operation performed on the first sparse matrix and the second sparse matrix. Since the first sparse matrix and the second sparse matrix only include a small number of non-zero elements, the operation of a large number of zero elements can be avoided, thereby improving the efficiency of the processor in performing the sparse multiplication operation.

[0083] Figure 7 This is a flow chart of another sparse matrix operation method provided by the embodiment of the present application. Figure 2 The computing device 200 shown in FIG. Figure 6 The processor 204 shown executes. Figure 7 Another sparse matrix operation method provided in an embodiment of the present application includes:

[0084] Step 701: The sparse matrix processing unit obtains a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix.

[0085] The process of obtaining the third sparse matrix and the fourth sparse matrix in step 701 is similar to the process of obtaining the first sparse matrix and the second sparse matrix in step 701 above, and will not be repeated here. Figure 7 In the corresponding embodiment, the first sparse matrix may be a matrix block in the third sparse matrix, and the second sparse matrix may be a matrix block in the fourth sparse matrix.

[0086] Each row element in the third numerical matrix corresponding to the third sparse matrix is obtained by sequentially arranging the zero elements and non-zero elements in each row of the third sparse matrix, and the non-zero elements in the third index matrix are the column numbers of the non-zero elements with the same position in the third numerical matrix. Each column element in the fourth numerical matrix corresponding to the fourth sparse matrix is obtained by sequentially arranging the zero elements and non-zero elements in each column of the fourth sparse matrix, and the non-zero elements in the fourth index matrix are the row numbers of the non-zero elements with the same position in the fourth numerical matrix.

[0087] After obtaining the third sparse matrix and the fourth sparse matrix, tiling can be performed on the third numerical matrix, the third index matrix, the fourth numerical matrix, and the fourth index matrix according to the same size to obtain a plurality of first data matrix blocks corresponding to the third data matrix, a plurality of first index matrix blocks corresponding to the third index matrix, a plurality of second data matrix blocks corresponding to the fourth data matrix, and a plurality of second index matrix blocks corresponding to the fourth index matrix. The first data matrix blocks, the first index matrix blocks, the second data matrix blocks, and the second index matrix blocks constitute a tiling matrix.

[0088] For example, Figure 3 The numerical matrix A1 shown may be the third numerical matrix, the index matrix A2 may be the third index matrix, the numerical matrix B1 may be the fourth numerical matrix, and the index matrix B2 may be the fourth index matrix. Correspondingly, Figure 8The numerical matrix A1, index matrix A2, numerical matrix B1 and index matrix B2 shown in the figure can be arranged in a 2×2 size. Figure 3 The diagram shows the numerical matrix A1, index matrix A2, numerical matrix B1 and index matrix B2 after tiling. Figure 8 The second numerical matrix C shown refers to a second result matrix corresponding to the sparse multiplication operation performed on the third sparse matrix and the fourth sparse matrix.

[0089] In one example, there are a large number of zero matrix blocks in the first data matrix block, the first index matrix block, the second data matrix block and the second index matrix block. Therefore, when storing the first data matrix block, the first index matrix block, the second data matrix block and the second index matrix block corresponding to the third sparse matrix and the fourth sparse matrix, only the non-zero matrix blocks in the first data matrix block, the first index matrix block, the second data matrix block and the second index matrix block can be stored, thereby reducing the storage space occupied by storing the third sparse matrix and the fourth sparse matrix.

[0090] Step 702: The sparse matrix processing unit determines the Cartesian product of the first numerical matrix block of the non-zero matrix blocks in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix blocks in the j-th column of the fourth numerical matrix.

[0091] The Cartesian product of the first numerical matrix block of the non-zero matrix block and the second numerical matrix block of the non-zero matrix block means that the first numerical matrix block of each non-zero matrix block is paired with the second numerical matrix block of each non-zero matrix block to obtain multiple groups of numerical matrix blocks, each group of numerical matrix blocks includes a first numerical matrix block and a second numerical matrix block.

[0092] like Figure 8 As shown, the first numerical matrix block of the non-zero matrix blocks in the first row of the numerical matrix A1 includes A00_data: A01_data: The second numerical matrix block of the non-zero matrix block in the first column of the numerical matrix B1 includes B01_data: Correspondingly, the Cartesian product of the first numerical matrix block of the non-zero matrix block in the first row of the numerical matrix A1 and the second numerical matrix block of the non-zero matrix block in the first column of the numerical matrix B1 includes: "A00_data, B01_data", "A01_data, B01_data".

[0093] The matrix obtained by performing the sparse multiplication operation on the third sparse matrix and the fourth sparse matrix can be referred to as a second result matrix. The Cartesian product of the first numerical matrix block of the non-zero matrix blocks in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix blocks in the j-th column of the fourth numerical matrix is determined. The matrix block in the i-th row and j-th column included in the second result matrix is equal to the matrix block obtained by performing matrix multiplication on each pair of numerical matrix blocks included in the determined Cartesian product, and then summing the result matrices obtained by performing the matrix multiplication on each pair of numerical matrix blocks.

[0094] Step 703: The sparse matrix processing unit determines that the first numerical matrix block and the second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are respectively the first numerical matrix and the second numerical matrix, determines that the first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determines that the second index matrix block corresponding to the second numerical matrix block is the second index matrix.

[0095] In one example, the sparse matrix processing unit obtained in step 501 obtains a first numerical matrix and a first index matrix corresponding to the first sparse matrix, and a second numerical matrix and a second index matrix corresponding to the second sparse matrix, which may be one of the multiple numerical matrix blocks included in the Cartesian product in step 703. That is, the first numerical matrix block included in the one set of numerical matrix blocks in the Cartesian product may be used as the first numerical matrix in step 501, the second numerical matrix block included may be used as the second numerical matrix in step 501, the first index matrix block corresponding to the first numerical matrix block may be used as the first index matrix in step 501, and the second index matrix block corresponding to the second numerical matrix block may be obtained as the second index matrix in step 501.

[0096] The matrix multiplication operation corresponding to each group of numerical matrix blocks in the Cartesian product may adopt the sparse matrix operation method shown in steps 501 to 502 above, thereby obtaining a first result matrix corresponding to each group of numerical matrix blocks.

[0097] For example, for Figure 8 The first numerical matrix block A00_index corresponding to A00_data: The second numerical matrix block B01_index corresponding to B01_data: The corresponding matrix multiplication operation of A00_data and B01_data includes: inputting the first row element [1, 2] corresponding to A00_index, the first column element [1, 4] corresponding to B01_index, the first row element [1, 1] corresponding to A00_data, and the first column element [1, 1] corresponding to B01_data into the sparse vector operation unit, respectively. The sparse vector operation unit determines that the first element in the first row element of A00_index and the first column element of B01_index are both "1". The sparse vector operation unit can multiply the first elements corresponding to the first row element of A00_data and the first column element of B01_data, respectively, to obtain the element in the first row and first column of the result matrix of the matrix multiplication operation of A00_data and B01_data. Referring to the above example, the elements in the first row and second column, the second row and first column, and the second row and second column of the result matrix of the matrix multiplication operation of A00_data and B01_data can be calculated in sequence.

[0098] Step 704: The sparse matrix processing unit sums the first result matrix corresponding to each group of numerical matrix blocks included in the Cartesian product to obtain the matrix block in the i-th row and j-th column of the second result matrix obtained by performing sparse multiplication operation on the third sparse matrix and the fourth sparse matrix.

[0099] After obtaining the first result matrix corresponding to each group of numerical matrix blocks in the Cartesian product of the first numerical matrix block of the non-zero matrix block in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix block in the j-th column of the fourth numerical matrix, the sparse matrix processing unit can sum the first result matrix corresponding to each group of numerical matrix blocks, thereby obtaining the matrix block in the i-th row and j-th column of the second result matrix of the sparse multiplication operation performed by the third sparse matrix and the fourth sparse matrix.

[0100] In this way, in the process of executing the sparse multiplication operation corresponding to the third sparse matrix and the fourth sparse matrix, on the one hand, the zero matrix blocks included in the first numerical matrix block and the second numerical matrix block can be screened out through the Cartesian product, thereby avoiding the zero matrix blocks from participating in the operation process. On the other hand, the sparse vector multiplication operation provided by the present application can be used to operate on each group of numerical matrix blocks in the Cartesian product, thereby avoiding the operation of a large number of zero elements, and further improving the efficiency of the processor in executing the sparse multiplication operation.

[0101] In the embodiment of the present application, the third sparse matrix and the fourth sparse matrix obtained in step 701 are obtained according to Figure 4In the illustrated conversion method, when generating a third numerical matrix, a third index matrix, a fourth numerical matrix, and a fourth index matrix, the third numerical matrix includes L×M first numerical matrix sections, each of which includes at least one first numerical matrix block; the third index matrix includes L×M third index matrix sections, each of which includes at least one first index matrix block; the fourth numerical matrix includes M×N second numerical matrix sections, each of which includes at least one second numerical matrix block; and the fourth index matrix includes M×N second index matrix sections, each of which includes at least one second index matrix block. The values of L, M, and N may be equal or unequal.

[0102] In one possible implementation, the sparse matrix processing unit may record the first position of the zero matrix area in the third numerical matrix, the second position of the non-zero matrix area in the third numerical matrix, and the third position of the zero matrix area in the fourth numerical matrix, and the fourth position of the non-zero matrix area in the fourth numerical matrix, among the L×M first numerical matrix areas. Before executing step 701, the first position and third position corresponding to the zero matrix area and the second position and fourth position corresponding to the non-zero matrix area may be aligned to determine the number of non-zero matrix areas in the L×N matrix areas included in the second result matrix, and then storage space is applied for the second result matrix based on the number.

[0103] like Figure 9 As shown, the first numerical matrix can be a numerical matrix A3, and the second numerical matrix can be a numerical matrix B4. The non-zero matrix area corresponding to the numerical matrix A3 is in the 1st row and 1st column, and the 2nd row and 1st column of the numerical matrix A3, and the corresponding zero matrix area is in the 1st row and 2nd column, and the 2nd row and 1st column of the numerical matrix A3. The non-zero matrix area corresponding to the numerical matrix B3 is in the 1st row and 1st column, and the 2nd row and 1st column of the numerical matrix B3, and the corresponding zero matrix area is in the 1st row and 2nd column, and the 2nd row and 1st column of the numerical matrix B3. In one example, the first position, second position, third position and fourth position corresponding to the corresponding first numerical matrix and the second numerical matrix can be recorded by a matrix. That is, the first position, second position, third position and fourth position corresponding to the numerical matrix A3 and the numerical matrix B3 can be recorded as For example, if the first row and first column of the first numerical matrix and the second numerical matrix are both non-zero matrix areas, then the matrix area of the first row and first column in the second result matrix is a non-zero matrix area. If the second row and second column of the first numerical matrix and the second numerical matrix are both non-zero matrix areas, then the matrix area of the second row and second column in the second result matrix is a non-zero matrix area. After bit alignment judgment, it can be determined that the second result matrix includes two non-zero matrix areas, and then only storage space corresponding to the two non-zero matrix areas can be requested in the memory.

[0104] It can be seen that in the embodiment of the present application, by performing the alignment judgment results of the matrix blocks included in the stored numerical matrix and applying for storage space for the result matrix in the memory, on the one hand, the storage space of the result matrix in the memory can be reduced, and on the other hand, compared with traditional technologies, the efficiency of the alignment judgment can also be improved.

[0105] In the embodiment of the present application, the third sparse matrix and the fourth sparse matrix obtained in step 701 are obtained according to Figure 4 In the case where the conversion method shown in FIG. 1 generates a third numerical matrix, a third index matrix, a fourth numerical matrix, and a fourth index matrix, the processing of step 702 may include:

[0106] If the sparse matrix processing unit determines that the nth first numerical matrix block group in the i-th row and the nth second numerical matrix block group in the j-th column meet the operation condition, the sparse matrix processing unit determines the Cartesian product of the first numerical matrix block of each non-zero matrix block and the second numerical matrix block of each non-zero matrix block included in the nth first numerical matrix block group and the nth second numerical matrix block group. The first numerical matrix block group includes the first numerical matrix blocks in the same first numerical matrix region in the i-th row, and the second numerical matrix block group includes the second numerical matrix blocks in the same second numerical matrix region in the j-th column. The operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

[0107] After partitioning the third sparse matrix and the fourth sparse matrix, the sparse matrix processing unit can determine the Cartesian product of the first numerical matrix block of the non-zero matrix block in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix block in the j-th column of the fourth numerical matrix, taking the numerical matrix area as a unit, and respectively determine the Cartesian product of the non-zero matrix block in the i-th row of the third numerical matrix located in each first data matrix area and the non-zero matrix block in the j-th column of the fourth numerical matrix located in the corresponding position.

[0108] For example, the Cartesian product corresponding to the non-zero matrix block located in the first first data matrix area in the i-th row of the third numerical matrix and the non-zero matrix block located in the first second data matrix area in the j-th row of the fourth numerical matrix is determined. The Cartesian product corresponding to the non-zero matrix block located in the second second data matrix area in the i-th row of the third numerical matrix and the non-zero matrix block located in the second second data matrix area in the j-th row of the fourth numerical matrix is determined. The Cartesian product corresponding to the non-zero matrix block located in the k-th first data matrix area in the i-th row of the third numerical matrix and the non-zero matrix block located in the k-th second data matrix area in the j-th row of the fourth numerical matrix is determined. Then, the first result matrix corresponding to each group of numerical matrix blocks included in the k Cartesian products is added to obtain the matrix block in the i-th row and j-th column of the second result matrix of the sparse multiplication operation performed on the third sparse matrix and the fourth sparse matrix. Wherein, k is the number of data matrix areas corresponding to each row of the third numerical matrix or each column of the fourth numerical matrix.

[0109] Since the data matrix blocks located in the data matrix area may be zero matrix blocks, before determining the Cartesian product, the numerical matrix block groups included in each data matrix area can be aligned and judged, wherein the numerical matrix block group refers to the data matrix blocks located in the same numerical matrix area in a row or a column of the data matrix. If there is a numerical matrix block group in the first numerical matrix of the aligned position and the second numerical matrix of the aligned position, both of which are zero matrix blocks, then the Cartesian product of the first numerical matrix block group and the second numerical matrix block group can be determined. If there are non-zero matrix blocks in the first numerical matrix of the aligned position and the second numerical matrix block group in the second numerical matrix, then the Cartesian product of the first numerical matrix block group and the second numerical matrix block group can be determined.

[0110] like Figure 9 As shown, the first first data matrix block group in the first row of numerical matrix A3 and the first second data matrix block group in the first column of numerical matrix A4 both include non-zero matrix blocks, and the second first data matrix block group in the first row of numerical matrix A3 and the second second data matrix block group in the first column of numerical matrix A4 both include zero matrix blocks. Then, the Cartesian product corresponding to the first data matrix block in the first row of numerical matrix A3 and the second data matrix block in the second row of numerical matrix A4 can be determined only by the non-zero matrix blocks included in the first first data matrix block group in the first row of numerical matrix A3 and the first second data matrix block group in the first column of numerical matrix A4. In this way, by performing alignment judgment on the data matrix block groups, the process of zero matrix blocks participating in sparse multiplication operations can be reduced, thereby improving the execution efficiency of sparse multiplication operations.

[0111] In an example, the above result matrix (the first result matrix or the second result matrix) may further correspond to a result index matrix, wherein each non-zero element in the result index matrix is used to indicate the column where each non-zero element in the result matrix is located.

[0112] For the result index matrix, the value of each column corresponding to the element is the column number corresponding to each column of the index matrix (the second index matrix or the fourth index matrix mentioned above) corresponding to the data matrix in which the non-zero elements are compressed in the column direction. Figure 10 As shown, the fourth index matrix is index matrix B4, and the result index matrix is result index matrix C4. Figure 10 It can be seen that the values corresponding to the elements in the first 4 columns of the result index matrix C4 are all the column numbers corresponding to the elements in the first 4 columns of the index matrix B4 in the corresponding second index matrix block, and the values corresponding to the elements in the last 4 columns of the index matrix C4 are all the column numbers corresponding to the elements in the last 4 columns of the index matrix B4 in the corresponding second index matrix block. Figure 10 The column numbers in the are arranged starting from "1", that is, the element in the first column corresponds to column number "1". Optionally, the column numbers can also be arranged starting from other values, such as "0".

[0113] In one example, by Figure 3 and Figure 4 It can be seen from the corresponding embodiment that when converting a sparse matrix into a numerical matrix, if there is a column in the sparse matrix that is all 0 before rearranging the non-zero elements and zero elements by column, the column that is all 0 can be deleted. In this case, when setting the column number for each column of the numerical matrix block and the index matrix block, the column that is all 0 can be skipped. For example, the sparse matrix corresponding to the index matrix B4 has the second column deleted and is all 0, then Figure 10 The column numbers corresponding to the first four columns of the index matrix B4 are 1, 3, 4, and 5 respectively.

[0114] All of the above optional technical solutions can be combined in any way to form optional embodiments of the present application, and the embodiments of the present application will not be described in detail one by one.

[0115] The embodiment of the present application further provides a processor, which includes a sparse matrix processing unit and a sparse vector operation unit, such as Figure 6 As shown, the processor provided in the embodiment of the present application performs the sparse matrix operation method provided in the present application, including:

[0116] a sparse matrix processing unit, configured to input into the sparse vector operation unit a first numerical matrix and a first index matrix corresponding to the first sparse matrix, and a second numerical matrix and a second index matrix corresponding to the second sparse matrix, obtained after processing by the sparse matrix processing unit, wherein each non-zero element in the first index matrix is used to indicate a column number corresponding to a non-zero element at a same position in the first numerical matrix, and each non-zero element in the second index matrix is used to indicate a row number corresponding to a non-zero element at a same position in the second numerical matrix;

[0117] The sparse vector operation unit is used to determine the target elements in each row of elements in the first numerical matrix and the second numerical matrix that need to be subjected to dot product operation based on each row of elements included in the first index matrix and the second index matrix, and perform the dot product operation on the target elements to obtain a first result matrix of the sparse multiplication operation performed on the first sparse matrix and the second sparse matrix.

[0118] In one implementable manner, the sparse vector operation unit is configured to determine the first position in the mth row and the second position in the nth row of the same element included in the mth row of the first index matrix and the nth row of the second index matrix, respectively;

[0119] The sparse vector operation unit is used to perform a dot product operation on the target element at the first position of the mth row of the first data matrix and the target element at the second position of the nth row of the second data matrix to obtain the element at the mth row and nth column in the first result matrix.

[0120] In one implementable manner, the sparse matrix processing unit is configured to obtain a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix, wherein the third numerical matrix includes a plurality of first numerical matrix blocks, the third index matrix includes a first index matrix block corresponding to each first numerical matrix block, the fourth numerical matrix includes a plurality of second numerical matrix blocks, and the fourth index matrix includes a plurality of second index matrix blocks corresponding to each second numerical matrix block;

[0121] The sparse matrix processing unit is used to determine the Cartesian product of the first numerical matrix block of the non-zero matrix block in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix block in the j-th column of the fourth numerical matrix.

[0122] The sparse matrix processing unit is also used to determine that the first numerical matrix block and the second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are respectively the first numerical matrix and the second numerical matrix, determine that the first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determine that the second index matrix block corresponding to the second numerical matrix block is the second index matrix.

[0123] The sparse matrix processing unit is also used to sum the first result matrix corresponding to each group of numerical matrix blocks included in the Cartesian product to obtain the matrix block in the i-th row and j-th column of the second result matrix of the sparse multiplication operation performed by the third sparse matrix and the fourth sparse matrix.

[0124] In one implementable manner, the third numerical matrix includes L×M first numerical matrix areas, each first numerical matrix area includes at least one first numerical matrix block, and the third index matrix includes L×M third index matrix areas, each first index matrix area includes at least one first index matrix block;

[0125] The fourth numerical matrix includes M×N second numerical matrix areas, each of which includes at least one second numerical matrix block. The fourth index matrix includes M×N second index matrix areas, each of which includes at least one second index matrix block.

[0126] In one implementable manner, the sparse matrix processing unit is configured to determine the number of non-zero matrix regions in the L×N matrix regions included in the second result matrix based on a first position of a zero matrix region in the third numerical matrix, a second position of a non-zero matrix region in the third numerical matrix, and a third position of a zero matrix region in the fourth numerical matrix, and a fourth position of a non-zero matrix region in the fourth numerical matrix among the M×N second numerical matrix regions;

[0127] The sparse matrix processing unit is configured to apply for storage space for the second result matrix in the memory based on the number of non-zero matrix regions.

[0128] In one implementable manner, the sparse matrix processing unit, configured to determine the Cartesian product of a first numerical matrix block of non-zero matrix blocks in an i-th row of a third numerical matrix and a second numerical matrix block of non-zero matrix blocks in a j-th column of a fourth numerical matrix, includes:

[0129] A sparse matrix processing unit is configured to determine a Cartesian product of a first numerical matrix block of each non-zero matrix block and a second numerical matrix block of each non-zero matrix block included in the kth first numerical matrix block group and the kth second numerical matrix block group if it is determined that the kth first numerical matrix block group in the i-th row and the kth second numerical matrix block group satisfy an operation condition; wherein,

[0130] The first numerical matrix block group includes the first numerical matrix block in the same first numerical matrix area in the i-th row, and the second numerical matrix block group includes the second numerical matrix block in the same second numerical matrix area in the j-th column. The operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

[0131] The processor provided in the embodiment of the present application can be used to perform the operation method of the sparse matrix provided in the embodiment of the present application. For the specific execution process, the introduction content of the operation method of the sparse matrix in the above embodiment can be seen, which will not be repeated here. The processor provided in the embodiment of the present application is used to perform sparse multiplication operations. The processor can determine the target elements that need to perform dot product operations in the first numerical matrix and the second data matrix according to the row number and column number indicated by the non-zero elements of each row of the first index matrix and each column of the second index matrix, and perform dot product operations on the target elements, thereby obtaining the first result matrix of the first sparse matrix and the second sparse matrix performing sparse multiplication operations. In this way, the operation of a large number of zero elements in the sparse multiplication process can be avoided, and the efficiency of the processor in performing sparse multiplication operations can be improved.

[0132] The present application also provides a computer program product comprising instructions. The computer program product may be software or a program product comprising instructions that can be run on a computing device or stored in any available medium. When the computer program product is run on at least one computing device, the at least one computing device executes the sparse matrix operation method provided in the present application.

[0133] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a computing device or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to execute the sparse matrix operation method of the embodiment of the present application.

[0134] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first" and "second", nor is there a limit on quantity or execution order. It should also be understood that although the following description uses the terms "first", "second", etc. to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the various examples, a first data matrix may be referred to as a second data matrix, and similarly, a second data matrix may be referred to as a first data matrix. The first data matrix and the second data matrix may both be collectively referred to as data matrices, and in some cases, may be separate and different data matrices.

[0135] The term "at least one" in this application means one or more, and the term "plurality" in this application means two or more.

[0136] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A sparse matrix operation method, characterized in that: The method is executed by a processor, the processor including a sparse matrix processing unit and a sparse vector operation unit, and the method includes: The sparse vector operation unit obtains a first numerical matrix and a first index matrix, a second numerical matrix and a second index matrix, wherein the first numerical matrix and the first index matrix are obtained by the sparse matrix processing unit processing the first sparse matrix, and the second numerical matrix and the second index matrix are obtained by the sparse matrix processing unit processing the second sparse matrix; each non-zero element in the first index matrix is used to indicate the column number of the column where the non-zero element at the same position in the first numerical matrix is located, and each non-zero element in the second index matrix is used to indicate the row number of the row where the non-zero element at the same position in the second numerical matrix is located; The sparse vector operation unit determines that the same non-zero elements included in the mth row of the first index matrix and the nth column of the second index matrix are located at a first position in the mth row and a second position in the nth column respectively; The sparse vector operation unit performs a dot product operation on the target element at the first position in the mth row of the first numerical matrix and the target element at the second position in the nth column of the second numerical matrix to obtain the element in the mth row and nth column of the first result matrix, where the first result matrix is the result of the sparse multiplication operation performed on the first sparse matrix and the second sparse matrix.

2. The method according to claim 1, characterized in that The method further includes: the sparse matrix processing unit acquiring a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix, wherein the third numerical matrix includes a plurality of first numerical matrix blocks, the third index matrix includes a first index matrix block corresponding to each first numerical matrix block, the fourth numerical matrix includes a plurality of second numerical matrix blocks, and the fourth index matrix includes a plurality of second index matrix blocks corresponding to each second numerical matrix block; The sparse matrix processing unit determines the Cartesian product of the first numerical matrix block of the non-zero matrix blocks in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix blocks in the j-th column of the fourth numerical matrix; Before the sparse matrix processing unit inputs the first numerical matrix and the first index matrix corresponding to the first sparse matrix, and the second numerical matrix and the second index matrix corresponding to the second sparse matrix obtained by processing by the sparse matrix processing unit into the sparse vector operation unit, it also includes: the sparse matrix processing unit determines that the first numerical matrix block and the second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are the first numerical matrix and the second numerical matrix respectively, determines that the first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determines that the second index matrix block corresponding to the second numerical matrix block is the second index matrix.

3. The method according to claim 2, characterized in that The third numerical matrix includes L×M first numerical matrix areas, each of which includes at least one first numerical matrix block; the third index matrix includes L×M third index matrix areas, each of which includes at least one first index matrix block; The fourth numerical matrix includes M×N second numerical matrix areas, each of which includes at least one second numerical matrix block. The fourth index matrix includes M×N second index matrix areas, each of which includes at least one second index matrix block.

4. The method according to claim 3, characterized in that The method further comprises: The sparse matrix processing unit determines the number of non-zero matrix regions in the L×N matrix regions included in a second result matrix based on a first position of a zero matrix region in the third numerical matrix, a second position of a non-zero matrix region in the third numerical matrix, and a third position of a zero matrix region in the fourth numerical matrix and a fourth position of a non-zero matrix region in the fourth numerical matrix among the M×N second numerical matrix regions, where the second result matrix is a result of a sparse multiplication operation performed on the third sparse matrix and the fourth sparse matrix; The sparse matrix processing unit applies for storage space for the second result matrix in a memory based on the number of the non-zero matrix regions.

5. The method according to any one of claims 2 to 4, characterized in that The sparse matrix processing unit determines the Cartesian product of a first numerical matrix block of non-zero matrix blocks in an i-th row of the third numerical matrix and a second numerical matrix block of non-zero matrix blocks in a j-th column of the fourth numerical matrix, including: If the sparse matrix processing unit determines that the nth first numerical matrix block group in the i-th row and the nth second numerical matrix block group in the j-th column meet the operation condition, then determine the Cartesian product of the first numerical matrix block of each non-zero matrix block included in the nth first numerical matrix block group and the nth second numerical matrix block group and the second numerical matrix block of each non-zero matrix block; wherein, The first numerical matrix block group includes the first numerical matrix block in the same first numerical matrix area in the i-th row, and the second numerical matrix block group includes the second numerical matrix block in the same second numerical matrix area in the j-th column. The operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

6. A processor, characterized in that: The processor includes a sparse matrix processing unit and a sparse vector operation unit, wherein: The sparse vector operation unit is used to obtain a first numerical matrix and a first index matrix, a second numerical matrix and a second index matrix, wherein the first numerical matrix and the first index matrix are obtained by the sparse matrix processing unit on the first sparse matrix, and the second numerical matrix and the second index matrix are obtained by the sparse matrix processing unit on the second sparse matrix; each non-zero element in the first index matrix is used to indicate the column number of the column where the non-zero element at the same position in the first numerical matrix is located, and each non-zero element in the second index matrix is used to indicate the row number of the row where the non-zero element at the same position in the second numerical matrix is located; The sparse vector operation unit is used to determine the first position in the mth row and the second position in the nth column of the same non-zero element included in the mth row of the first index matrix and the nth column of the second index matrix respectively; The sparse vector operation unit is used to perform a dot product operation on the target element at the first position in the mth row of the first numerical matrix and the target element at the second position in the nth column of the second numerical matrix to obtain the element in the mth row and nth column of the first result matrix, where the first result matrix is the result of the sparse multiplication operation performed on the first sparse matrix and the second sparse matrix.

7. The processor according to claim 6, wherein: The sparse matrix processing unit is configured to obtain a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix, wherein the third numerical matrix includes a plurality of first numerical matrix blocks, the third index matrix includes a first index matrix block corresponding to each first numerical matrix block, the fourth numerical matrix includes a plurality of second numerical matrix blocks, and the fourth index matrix includes a plurality of second index matrix blocks corresponding to each second numerical matrix block; The sparse matrix processing unit is used to determine the Cartesian product of a first numerical matrix block of non-zero matrix blocks in the i-th row of the third numerical matrix and a second numerical matrix block of non-zero matrix blocks in the j-th column of the fourth numerical matrix; The sparse matrix processing unit is also used to determine that the first numerical matrix block and the second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are respectively the first numerical matrix and the second numerical matrix, determine that the first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determine that the second index matrix block corresponding to the second numerical matrix block is the second index matrix.

8. The processor according to claim 7, wherein: The third numerical matrix includes L×M first numerical matrix areas, each of which includes at least one first numerical matrix block; the third index matrix includes L×M third index matrix areas, each of which includes at least one first index matrix block; The fourth numerical matrix includes M×N second numerical matrix areas, each of which includes at least one second numerical matrix block. The fourth index matrix includes M×N second index matrix areas, each of which includes at least one second index matrix block.

9. The processor according to claim 8, wherein: The sparse matrix processing unit is configured to determine, based on a first position of a zero matrix region in the third numerical matrix, a second position of a non-zero matrix region in the third numerical matrix, and a third position of a zero matrix region in the fourth numerical matrix, and a fourth position of a non-zero matrix region in the fourth numerical matrix, among the M×N second numerical matrix regions, a second result matrix that is a result of a sparse multiplication operation performed on the third sparse matrix and the fourth sparse matrix; The sparse matrix processing unit is used to apply for storage space for the second result matrix in the memory based on the number of the non-zero matrix regions.

10. The processor according to any one of claims 7 to 9, characterized in that: The sparse matrix processing unit is configured to determine the Cartesian product of a first numerical matrix block of non-zero matrix blocks in the i-th row of the third numerical matrix and a second numerical matrix block of non-zero matrix blocks in the j-th column of the fourth numerical matrix, comprising: The sparse matrix processing unit is configured to determine the Cartesian product of the first numerical matrix block of each non-zero matrix block and the second numerical matrix block of each non-zero matrix block included in the nth first numerical matrix block group and the nth second numerical matrix block group if it is determined that the nth first numerical matrix block group in the i-th row and the nth second numerical matrix block group satisfy an operation condition; wherein, The first numerical matrix block group includes the first numerical matrix block in the same first numerical matrix area in the i-th row, and the second numerical matrix block group includes the second numerical matrix block in the same second numerical matrix area in the j-th column. The operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

11. A computing device, characterized in that The computing device includes a memory and a processor as described in any one of claims 6 to 10 above, wherein the memory stores at least one instruction, and the processor executes the at least one instruction to execute the method as described in any one of claims 1 to 5.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program code, which, when executed by a computer device, enables the computer device to perform the method according to any one of claims 1 to 5.

13. A computer program product comprising instructions, characterized in that When the computer program product is run on a computing device, the computing device is caused to execute the method according to any one of claims 1 to 5.

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