A multi-axis stress control method and system for three-dimensional stacked chips

Abstract

The present invention discloses a multi-axis stress control method and system for three-dimensional stacked chips, belonging to the field of semiconductor technology, which specifically includes: collecting chip parameter data, establishing a preliminary finite element model, and using an adaptive mesh refinement algorithm to perform mesh division; then setting a multi-axis stress control target, performing multi-axis stress analysis on the model, generating a stress distribution map and a temperature change map, and marking core stress points; then formulating and implementing a multi-axis stress control strategy based on the analysis results, generating a chip stacking plan; finally, thinning and performing performance testing on the stacked chips, evaluating the stress control effect, and generating an evaluation report. This method can effectively improve the reliability and performance of three-dimensional stacked chips.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and specifically relates to a multi-axis stress control method and system for three-dimensional stacked chips. Background Art

[0002] With the continuous development of semiconductor technology, 3D stacked chip technology has been widely used in mobile devices, servers, data centers, and high-performance computing systems due to its advantages of shortening the connection distance between chips, increasing communication speed, reducing power consumption, and improving integration. However, 3D stacked chips also face challenges in thermal management, signal integrity, and reliability. In particular, uneven stress distribution during the stacking process may lead to chip performance degradation or even damage.

[0003] For example, the Chinese patent with the authorization announcement number CN108321094B discloses a method for improving the reflectivity of a vertical structure LED chip reflector based on stress regulation, including: the steps of growing LED epitaxial wafers, growing nano-Ag reflectors of different thicknesses, performing a series of characterization tests on the grown nano-Ag reflectors, bonding and substrate transfer steps, preparing a passivation layer and an n-electrode, and summarizing the relationship between stress and LED light output power. By regulating the thickness of the reflector Ag layer to change the residual stress of the reflector, and then controlling the surface morphology of the reflector, the clustering phenomenon of the Ag-based reflector is improved to a great extent, thereby improving the reflectivity of the reflector and the light output efficiency of the vertical structure LED chip.

[0004] The above existing technologies all have the following problems: involving multiple complex steps, including the growth of LED epitaxial wafers, the growth and characterization testing of nano-Ag reflectors, bonding and substrate transfer, etc., which increases the production cost and technical threshold; the process stability and controllability are poor; they are mainly aimed at vertical structure LED chips, and different process parameters and control strategies may be required for different types of LED chips or reflector materials, which limits their scalability and flexibility. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention proposes a multi-axis stress control method and system for three-dimensional stacked chips, collects chip parameter data, establishes a preliminary finite element model, and uses an adaptive mesh refinement algorithm to perform mesh division; then sets a multi-axis stress control target, performs multi-axis stress analysis on the model, generates stress distribution diagrams and temperature change diagrams, and marks core stress points; then formulates and implements a multi-axis stress control strategy based on the analysis results, generates a chip stacking solution; finally, thins the stacked chips and performs performance tests, evaluates the stress control effect, and generates an evaluation report. This method can effectively improve the reliability and performance of three-dimensional stacked chips.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A multi-axis stress control method for three-dimensional stacked chips, comprising:

[0008] Step S1: collecting chip parameter data of the three-dimensional stacked chip, establishing a preliminary finite element model of the three-dimensional stacked chip according to the collected chip parameter data, and meshing the preliminary finite element model of the three-dimensional stacked chip using an adaptive mesh refinement algorithm based on error estimation to obtain a finite element mesh model of the three-dimensional stacked chip;

[0009] Step S2: setting a multi-axis stress control target, performing a multi-axis stress analysis on the finite element mesh model of the three-dimensional stacked chip, calculating the stress distribution and temperature change of the chip under different working conditions, and generating a stress distribution diagram and a temperature change diagram based on the calculation results of the multi-axis stress analysis, and marking the position of the core stress point;

[0010] Step S3: formulating a multi-axis stress control strategy according to the multi-axis stress analysis result, and implementing the formulated multi-axis stress control strategy during the chip stacking process to generate a chip stacking solution including the multi-axis stress control strategy;

[0011] Step S4: According to the chip stacking scheme, the stacked chips are thinned and performance tested, and based on the test results, the stress regulation effect of the stacked chips is evaluated, and a stress regulation effect evaluation report is generated.

[0012] Specifically, the specific steps of step S1 include:

[0013] S1.1: Collect chip parameter data of the three-dimensional stacked chip, and use the modeling function in the finite element analysis software to establish a preliminary finite element model of the three-dimensional stacked chip based on the collected chip parameter data;

[0014] S1.2: Set the initial parameters of meshing and use the adaptive mesh refinement algorithm based on error estimation to estimate the error of the preliminary finite element model of the three-dimensional stacked chip. The formula is: , where e represents the error estimation result, represents the H norm of the error estimation result, represents the maximum element size in the grid, C represents a constant, and u represents the exact solution of the error estimate;

[0015] S1.3: According to the error estimation result e, by sorting the error estimation result e, mark the unit area with the largest error, and refine the grid of the marked unit area with the largest error until ,in, Indicates the preset tolerance value;

[0016] S1.4: Check the meshing results, optimize the mesh according to the inspection results, and generate a three-dimensional stacked chip finite element mesh model.

[0017] Specifically, the specific steps of S2 include:

[0018] S2.1: Set the target value of multi-axis stress control, and apply boundary conditions and loads according to the working conditions of the chip;

[0019] S2.2: Use the solver of the finite element analysis software to perform multi-axis stress analysis on the finite element mesh model of the three-dimensional stacked chip to calculate the stress distribution and temperature change of the chip under different working conditions. The formula is: ,in, represents the stress tensor, D represents the elastic matrix of the chip material, represents the strain tensor, represents the thermal stress caused by temperature change, represents the thermal expansion coefficient, E represents the elastic modulus, T represents the current temperature, represents reference temperature, P represents heat source, c represents specific heat capacity, Indicates the density of chip material, represents the Nabra operator, represents the temperature gradient, k represents the thermal conductivity, represents the net rate of heat flow, Represents partial derivative.

[0020] Specifically, the specific steps of S2 also include:

[0021] S2.3: Obtain the stress distribution and temperature change results of the chip in S2.2 under different working conditions, and use visualization software to import the obtained stress tensor data and temperature data respectively;

[0022] S2.4: Generate stress distribution map by setting color mapping and arrows according to the magnitude and direction of stress tensor data;

[0023] S2.5: Generate a temperature change graph by setting color mapping according to the size of the temperature data;

[0024] S2.6: In the stress distribution diagram, find the point with the largest stress value as the core stress point. At the same time, use the annotation function in the visualization tool to mark the position of the core stress point in the diagram and attach the stress value information;

[0025] S2.7: Check and adjust the stress distribution diagram and temperature change diagram parameters, and export and save the stress distribution diagram and temperature change diagram with annotations.

[0026] Specifically, the specific steps of step S3 include:

[0027] S3.1: Obtain the multi-axial stress analysis results in step S2, and interpret the results of the multi-axial stress analysis to obtain stress distribution, stress concentration points, and stress gradient information;

[0028] S3.2: Based on the obtained stress distribution, stress core point, and stress gradient information, identify stress problems and potential risks that occur during chip stacking, and determine the stress areas and stress levels that need to be regulated;

[0029] S3.3: Based on the identification results, formulate a multi-axis stress control strategy, which includes optimizing the chip stacking structure, adjusting material parameters, and introducing a stress relief structure;

[0030] S3.4: In the initial stage of chip stacking, the formulated multi-axis stress control strategy is incorporated and implemented according to the formulated multi-axis stress control strategy;

[0031] S3.5: Monitor stress changes during stacking in real time and adjust the multi-axis stress control strategy in time according to the monitoring results;

[0032] S3.6: Generate a chip stacking solution including the multi-axis stress control strategy based on the implementation of the multi-axis stress control strategy.

[0033] Specifically, in addition to the multi-axis stress control strategy, the chip stacking solution also includes stress distribution, stress concentration points, stress gradient information and the implementation of the multi-axis stress control strategy.

[0034] A multi-axis stress control system for three-dimensional stacked chips, comprising: a collection and modeling module, a meshing module, a multi-axis stress analysis module, a strategy formulation module, and an effect evaluation module;

[0035] The collection and modeling module is used to collect parameter data of the three-dimensional stacked chips and establish a preliminary finite element model based on the parameter data of the three-dimensional stacked chips;

[0036] The meshing module is used to mesh the preliminary finite element model using an adaptive mesh refinement algorithm based on error estimation, and optimize the meshing result;

[0037] The multi-axis stress analysis module is used to perform multi-axis stress analysis on the finite element mesh model of the three-dimensional stacked chip, calculate the stress distribution and temperature change of the chip under different working conditions, and identify the core stress points;

[0038] The strategy formulation module is used to formulate a multi-axis stress control strategy according to the multi-axis stress analysis results, and implement the multi-axis stress control strategy during the chip stacking process;

[0039] The effect evaluation module is used to perform thinning processing and performance testing on the stacked chips and evaluate the stress regulation effect of the stacked chips.

[0040] Specifically, the grid division module includes: a grid division unit and an optimization unit;

[0041] The meshing unit is used to perform preliminary meshing of the preliminary finite element model by introducing an adaptive mesh refinement algorithm based on error estimation according to the geometric characteristics of the preliminary finite element model and the expected stress distribution;

[0042] The optimization unit dynamically adjusts the density and shape of the grid according to the geometric features of the chip and the expected stress distribution characteristics, thereby obtaining a three-dimensional stacked chip finite element grid model.

[0043] Specifically, the multi-axis stress analysis module includes: a multi-axis stress analysis unit and a stress point identification unit;

[0044] The multi-axis stress analysis unit is used to perform multi-axis stress analysis on the finite element mesh model of the three-dimensional stacked chip using finite element analysis software to calculate stress distribution and temperature change;

[0045] The stress point identification unit is used to generate a stress distribution diagram and a temperature change diagram according to the analysis results, and mark the position of the core stress point.

[0046] Specifically, the policy formulation module includes: a policy formulation unit and a policy implementation unit;

[0047] The strategy formulation unit is used to formulate a targeted multi-axis stress control strategy according to the location of the core stress point and the stress distribution characteristics;

[0048] The strategy implementation unit is used to adjust chip parameters according to the formulated strategy during the chip stacking process to generate a chip stacking solution including a multi-axis stress regulation strategy.

[0049] Compared with the prior art, the present invention has the following beneficial effects:

[0050] 1. The present invention proposes a multi-axis stress control method for three-dimensional stacked chips. By accurately collecting chip parameter data and establishing a finite element model, combined with an adaptive mesh refinement algorithm, accurate simulation and analysis of the internal stress distribution of the three-dimensional stacked chips is achieved, which helps to identify potential stress concentration points and temperature change areas in the chip design stage, so as to take countermeasures in advance and reduce the risk of chip failure in actual use.

[0051] 2. The present invention proposes a multi-axis stress control method for three-dimensional stacked chips, and also formulates detailed stress control strategies based on the multi-axis stress analysis results, and implements these strategies in the chip stacking process, which not only improves the stacking quality and reliability of the chip, but also further improves the performance and stability of the chip by optimizing the stress distribution and temperature changes; finally, the effectiveness of the stress control strategy can be verified through performance testing and effect evaluation. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A schematic diagram of a multi-axis stress control method for three-dimensional stacked chips according to the present invention;

[0053] Figure 2 This is a principle flow chart of a multi-axis stress control method for three-dimensional stacked chips according to the present invention;

[0054] Figure 3 This is an architecture diagram of a multi-axis stress control system for three-dimensional stacked chips according to the present invention. DETAILED DESCRIPTION

[0055] Example 1

[0056] See also Figure 1 and Figure 2 , an embodiment provided by the present invention: a multi-axis stress control method for three-dimensional stacked chips, comprising the following steps:

[0057] Step S1: collecting chip parameter data of the three-dimensional stacked chip, establishing a preliminary finite element model of the three-dimensional stacked chip according to the collected chip parameter data, and meshing the preliminary finite element model of the three-dimensional stacked chip using an adaptive mesh refinement algorithm based on error estimation to obtain a finite element mesh model of the three-dimensional stacked chip;

[0058] Among them, the chip parameter data includes the chip's geometric dimensions, material properties, stacking method, and interconnection structure.

[0059] Step S2: setting a multi-axis stress control target, performing a multi-axis stress analysis on the finite element mesh model of the three-dimensional stacked chip, calculating the stress distribution and temperature change of the chip under different working conditions, and generating a stress distribution diagram and a temperature change diagram based on the calculation results of the multi-axis stress analysis, and marking the position of the core stress point;

[0060] Step S3: formulating a multi-axis stress control strategy according to the multi-axis stress analysis result, and implementing the formulated multi-axis stress control strategy during the chip stacking process to generate a chip stacking solution including the multi-axis stress control strategy;

[0061] Step S4: According to the chip stacking scheme, the stacked chips are thinned and performance tested, and based on the test results, the stress regulation effect of the stacked chips is evaluated, and a stress regulation effect evaluation report is generated.

[0062] Furthermore, the specific steps of step S4 include:

[0063] (1) Chip stacking plan execution: Complete the chip stacking operation according to the established chip stacking plan, and ensure that various parameters in the stacking process, such as temperature, pressure, and time, meet the plan requirements;

[0064] (2) Thinning: Thinning the stacked chips to meet packaging or application requirements. The thinning process uses chemical mechanical polishing, and the thinning rate and uniformity must be controlled during the thinning process to avoid introducing additional stress or damage. The chemical mechanical polishing method is a prior art in the art and is not an inventive solution of the present application, so it will not be described in detail here.

[0065] (3) Performance test preparation: Prepare the equipment and test environment required for the performance test, and set the test parameters to ensure that the test can accurately reflect the stress regulation effect of the chip;

[0066] (4) Performance test execution: Execute performance tests, including electrical performance tests, thermal performance tests, and reliability tests, and record test data for subsequent analysis;

[0067] (5) Evaluation of stress control effect: Analyze the stress distribution and changes of the chip based on the test data, and evaluate the stress control effect by comparing the test data before and after stress control;

[0068] (6) Generate an evaluation report: Organize the test data and evaluation results to form a stress control effect evaluation report, which should include the test method, test data, evaluation results and conclusions.

[0069] The specific steps of step S1 include:

[0070] S1.1: collecting chip parameter data of the three-dimensional stacked chip, using the modeling function in the finite element analysis software, and establishing a preliminary finite element model of the three-dimensional stacked chip according to the collected chip parameter data. In the present invention, ANSYS finite element analysis software is used;

[0071] S1.2: Set the initial parameters of meshing and use the adaptive mesh refinement algorithm based on error estimation to estimate the error of the preliminary finite element model of the three-dimensional stacked chip. The formula is: , where e represents the error estimation result, represents the H norm of the error estimation result, represents the maximum element size in the grid, C represents a constant, and u represents the exact solution of the error estimate;

[0072] S1.3: According to the error estimation result e, by sorting the error estimation result e, mark the unit area with the largest error, and refine the grid of the marked unit area with the largest error until ,in, Indicates the preset tolerance value;

[0073] Furthermore, the specific steps of S1.3 include:

[0074] (1) Using the error estimation function in the finite element analysis software, calculate the error estimation result e of each unit, where the error estimation result e is usually calculated based on the discontinuity or rate of change of stress, temperature or other physical quantities within the unit;

[0075] (2) According to the error estimation result e, find the unit area with the largest error by sorting the error results;

[0076] (3) Refine the mesh of the marked cell area with the largest error. The refinement methods include increasing the number of cells, reducing the cell size, or increasing the cell order. At the same time, during the refinement process, it is necessary to ensure that the newly generated mesh is consistent with the original mesh on the boundary to avoid generating a discontinuous mesh.

[0077] S1.4: Check the meshing results, optimize the mesh according to the inspection results, and generate a three-dimensional stacked chip finite element mesh model.

[0078] Furthermore, the specific steps of S1.4 include:

[0079] (1) Use finite element analysis software or meshing tools to check the initially generated mesh, including checking the integrity, continuity and consistency of the mesh, ensuring that there are no missing, overlapping or broken parts of the mesh, and evaluating the density and distribution of the mesh to ensure that there is sufficient mesh density in core areas such as stress concentration areas and areas with drastic temperature changes, while the mesh can be appropriately sparse in non-critical areas;

[0080] (2) Repair the mesh problems found, such as filling missing parts, deleting overlapping parts, or adjusting the connection of broken parts, and adjust the density and distribution of the mesh as needed to ensure that the mesh can better capture and analyze the physical phenomena in the three-dimensional stacked chips. At the same time, the mesh needs to be smoothed to reduce the distortion and deformation of the mesh and improve the accuracy and stability of the analysis;

[0081] (3) After completing the mesh optimization, use finite element analysis software or meshing tools to generate the final 3D stacked chip finite element mesh model to ensure that the mesh in the 3D stacked chip finite element mesh model matches the actual structure of the 3D stacked chip, including the number of chip layers, the size and shape of each layer, and the connections between layers;

[0082] (4) Save and export the mesh model for subsequent finite element analysis and calculation.

[0083] The specific steps of S2 include:

[0084] S2.1: Set the target value of multi-axis stress control, and apply boundary conditions and loads according to the working conditions of the chip;

[0085] Furthermore, the specific steps of S2.1 include:

[0086] (1) Setting the target value of multi-axis stress control: Determine the target value of multi-axis stress control based on the design requirements, working environment and expected performance of the three-dimensional stacked chip. These target values ​​may include maximum stress limit, stress distribution uniformity requirements, and temperature variation range;

[0087] (2) Analyze chip working conditions: Understand the working conditions of three-dimensional stacked chips, including environmental factors such as temperature, pressure, and vibration, and consider the stress distribution and load conditions of the chips under normal operation, extreme conditions, or specific application scenarios;

[0088] (3) Apply boundary conditions: Determine boundary conditions based on the working conditions of the chip, where the boundary conditions include the chip fixing method, the position of the support point, and temperature control. In the finite element analysis software, set the corresponding boundary conditions, such as the displacement or rotational freedom of the constraint node;

[0089] (4) Applying load: Apply corresponding loads according to the working conditions and stress distribution requirements of the chip. The loads include static loads and dynamic loads. Static loads include gravity and pressure, and dynamic loads include vibration and impact. At the same time, set the load size, direction and loading method in the finite element analysis software.

[0090] S2.2: Use the solver of the finite element analysis software to perform multi-axis stress analysis on the finite element mesh model of the three-dimensional stacked chip to calculate the stress distribution and temperature change of the chip under different working conditions. The formula is: ,in, represents the stress tensor, D represents the elastic matrix of the chip material, represents the strain tensor, represents the thermal stress caused by temperature change, represents the thermal expansion coefficient, E represents the elastic modulus, T represents the current temperature, represents reference temperature, P represents heat source, c represents specific heat capacity, Indicates the density of chip material, represents the Nabra operator, represents the temperature gradient, k represents the thermal conductivity, The net rate of heat flow is the net rate at which heat flows into or out of a unit volume. , it means that heat is flowing out of the volume, that is, the volume is losing heat. , it means that heat is flowing into the volume, that is, the volume is gaining heat, represents partial derivative;

[0091] S2.3: Obtain the stress distribution and temperature change results of the chip in S2.2 under different working conditions, and use visualization software to import the obtained stress tensor data and temperature data respectively. In the present invention, the visualization software uses Matplotlib, which is a prior art content in this field and is not an inventive solution of the present application, and will not be described in detail here;

[0092] S2.4: Generate stress distribution map by setting color mapping and arrows according to the magnitude and direction of stress tensor data;

[0093] S2.5: Generate a temperature change graph by setting color mapping according to the size of the temperature data;

[0094] S2.6: In the stress distribution diagram, find the point with the largest stress value as the core stress point. At the same time, use the annotation function in the visualization tool to mark the position of the core stress point in the diagram and attach the stress value information;

[0095] Furthermore, the specific steps of S2.6 include:

[0096] (1) In the finite element analysis software, open the completed stress analysis result file. In the software, a stress distribution diagram is usually automatically generated, showing the stress magnitude of different areas in a color-coded manner;

[0097] (2) In the stress distribution diagram, find the point with the maximum stress value by color coding or numerical labeling. This can usually be achieved through the query function or maximum value marking function of the software;

[0098] (3) Use the annotation function in the visualization tool to mark the location of the maximum stress point on the stress distribution diagram. At the same time, add stress value information, that is, display the specific stress value of the point next to or above the annotation.

[0099] S2.7: Check and adjust the parameters of the stress distribution diagram and the temperature change diagram, and export and save the stress distribution diagram and the temperature change diagram with annotations. Adjusting the parameters of the stress distribution diagram and the temperature change diagram includes adjusting the annotation style, size, color and other parameters to ensure that they are clearly visible in the diagram.

[0100] The specific steps of step S3 include:

[0101] S3.1: Obtain the multi-axial stress analysis results in step S2, and interpret the results of the multi-axial stress analysis to obtain stress distribution, stress concentration points, and stress gradient information;

[0102] S3.2: Based on the obtained stress distribution, stress core point, and stress gradient information, identify stress problems and potential risks that occur during chip stacking, and determine the stress areas and stress levels that need to be regulated;

[0103] Furthermore, the specific steps of S3.2 include:

[0104] (1) Obtain stress distribution, stress concentration points, and stress gradient information, process and analyze the collected stress data, and identify stress concentration areas and high stress level areas, that is, compare the stress distribution with the preset safe stress range and identify stress areas that exceed the safe range;

[0105] (2) Based on the identification results, the stress problems and potential risks that may occur during the chip stacking process, such as chip cracking and connection failure, are obtained;

[0106] (3) Based on the results of problem identification, determine the stress areas that need to be regulated. These stress areas that need to be regulated are usually areas of stress concentration or high stress levels.

[0107] S3.3: Based on the identification results, formulate a multi-axis stress control strategy, which includes optimizing the chip stacking structure, adjusting material parameters, and introducing a stress relief structure;

[0108] S3.4: In the initial stage of chip stacking, the formulated multi-axis stress control strategy is incorporated and implemented according to the formulated multi-axis stress control strategy;

[0109] S3.5: Monitor stress changes during stacking in real time and adjust the multi-axis stress control strategy in time according to the monitoring results;

[0110] S3.6: Generate a chip stacking solution including the multi-axis stress control strategy based on the implementation of the multi-axis stress control strategy.

[0111] In addition to the multi-axis stress control strategy, the chip stacking solution also includes stress distribution, stress concentration points, stress gradient information and the implementation of the multi-axis stress control strategy.

[0112] Example 2

[0113] See also Figure 3 Another embodiment provided by the present invention is a multi-axis stress control system for three-dimensional stacked chips, comprising:

[0114] Collection and modeling module, meshing module, multi-axis stress analysis module, strategy formulation module, and effect evaluation module;

[0115] A collection and modeling module, used to collect parameter data of three-dimensional stacked chips and establish a preliminary finite element model based on the parameter data of three-dimensional stacked chips;

[0116] Meshing module, which is used to mesh the preliminary finite element model using an adaptive mesh refinement algorithm based on error estimation, and optimize the meshing results to improve the accuracy and efficiency of the analysis;

[0117] Multi-axis stress analysis module, used to perform multi-axis stress analysis on the finite element mesh model of three-dimensional stacked chips, calculate the stress distribution and temperature changes of the chips under different working conditions, and identify the core stress points;

[0118] A strategy formulation module, which is used to formulate a multi-axis stress control strategy based on the multi-axis stress analysis results and implement the multi-axis stress control strategy during the chip stacking process;

[0119] The effect evaluation module is used to perform thinning and performance testing on the stacked chips and evaluate the stress regulation effect of the stacked chips.

[0120] The collection and modeling module includes: data collection unit and preliminary modeling unit;

[0121] A data collection unit is used to collect chip geometry, material properties, stacking methods and other parameter data from design documents and test reports;

[0122] The preliminary modeling unit is used to establish a preliminary finite element model of the three-dimensional stacked chip according to the collected three-dimensional stacked chip parameter data using finite element analysis software.

[0123] The grid division module includes: a grid division unit and an adaptive optimization unit;

[0124] A meshing unit is used to perform preliminary meshing of the preliminary finite element model by introducing an adaptive mesh refinement algorithm based on error estimation according to the geometric characteristics of the preliminary finite element model and the expected stress distribution;

[0125] The optimization unit dynamically adjusts the density and shape of the grid according to the geometric characteristics of the chip and the expected stress distribution characteristics to obtain a three-dimensional stacked chip finite element grid model.

[0126] The multi-axis stress analysis module includes: a multi-axis stress analysis unit and a stress point identification unit;

[0127] A multi-axis stress analysis unit is used to perform multi-axis stress analysis on a 3D stacked chip finite element mesh model using finite element analysis software to calculate stress distribution and temperature changes;

[0128] The stress point identification unit is used to generate stress distribution diagrams and temperature change diagrams based on the analysis results, and mark the locations of core stress points.

[0129] The strategy formulation module includes: a strategy formulation unit and a strategy implementation unit;

[0130] Strategy formulation unit, used to formulate targeted multi-axis stress control strategies according to the location of the core stress point and stress distribution characteristics;

[0131] The strategy implementation unit is used to adjust the chip's geometric dimensions, material properties, stacking methods and other parameters according to the formulated strategy during the chip stacking process, and generate a chip stacking solution that includes a multi-axis stress control strategy.

[0132] The effect evaluation module includes: a thinning processing unit, a performance testing unit, and an effect evaluation unit;

[0133] A thinning processing unit, used for thinning the chip according to the stacking scheme;

[0134] Performance test unit, which is used to integrate multiple performance test methods, such as reliability test, power consumption test, signal integrity test, etc., to conduct comprehensive performance test on the stacked chips;

[0135] The effect evaluation unit is used to evaluate the stress regulation effect of the stacked chips according to the test results and generate a stress regulation effect evaluation report.

[0136] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0137] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0138] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in the field may also change, modify, replace and modify the above-mentioned embodiments without departing from the purpose and scope of protection of the present invention, and all of these are within the protection of the present invention.

Claims

1. A multi-axis stress control method for three-dimensional stacked chips, characterized in that: include: Step S1: collecting chip parameter data of the three-dimensional stacked chip, establishing a preliminary finite element model of the three-dimensional stacked chip according to the collected chip parameter data, and meshing the preliminary finite element model of the three-dimensional stacked chip using an adaptive mesh refinement algorithm based on error estimation to obtain a finite element mesh model of the three-dimensional stacked chip; Step S2: setting a multi-axis stress control target, performing a multi-axis stress analysis on the finite element mesh model of the three-dimensional stacked chip, calculating the stress distribution and temperature change of the chip under different working conditions, and generating a stress distribution diagram and a temperature change diagram based on the calculation results of the multi-axis stress analysis, and marking the position of the core stress point; Step S3: formulating a multi-axis stress control strategy according to the multi-axis stress analysis result, and implementing the formulated multi-axis stress control strategy during the chip stacking process to generate a chip stacking solution including the multi-axis stress control strategy; S3.1: Obtain the multi-axial stress analysis results in step S2, and interpret the results of the multi-axial stress analysis to obtain stress distribution, stress concentration points, and stress gradient information; S3.2: Based on the obtained stress distribution, stress core point, and stress gradient information, identify stress problems and potential risks that occur during chip stacking, and determine the stress areas and stress levels that need to be regulated; S3.3: Based on the identification results, formulate a multi-axis stress control strategy, which includes optimizing the chip stacking structure, adjusting material parameters, and introducing a stress relief structure; S3.4: In the initial stage of chip stacking, the formulated multi-axis stress control strategy is incorporated and implemented according to the formulated multi-axis stress control strategy; S3.5: Monitor stress changes during stacking in real time and adjust the multi-axis stress control strategy in time according to the monitoring results; S3.6: generating a chip stacking scheme including the multi-axis stress control strategy according to the implementation of the multi-axis stress control strategy; Step S4: According to the chip stacking scheme, the stacked chips are thinned and performance tested, and based on the test results, the stress regulation effect of the stacked chips is evaluated, and a stress regulation effect evaluation report is generated.

2. A multi-axis stress control method for three-dimensional stacked chips according to claim 1, characterized in that: The specific steps of step S1 include: S1.1: Collect chip parameter data of the three-dimensional stacked chip, and use the modeling function in the finite element analysis software to establish a preliminary finite element model of the three-dimensional stacked chip based on the collected chip parameter data; S1.2: Set the initial parameters of meshing and use the adaptive mesh refinement algorithm based on error estimation to estimate the error of the preliminary finite element model of the three-dimensional stacked chip. The formula is: Among them, e represents the error estimation result, ||e|| H The H norm of the error estimation result, h max represents the maximum element size in the grid, C represents a constant, and u represents the exact solution of the error estimate; S1.3: According to the error estimation result e, by sorting the error estimation result e, mark the unit area with the largest error, and refine the grid of the marked unit area with the largest error until e≤e tol , where e tol Indicates the preset tolerance value; S1.4: Check the meshing results, optimize the mesh according to the inspection results, and generate a three-dimensional stacked chip finite element mesh model.

3. A multi-axis stress control method for three-dimensional stacked chips according to claim 2, characterized in that: The specific steps of S2 include: S2.1: Set the target value of multi-axis stress control, and apply boundary conditions and loads according to the working conditions of the chip; S2.2: Use the solver of the finite element analysis software to perform multi-axis stress analysis on the finite element mesh model of the three-dimensional stacked chip to calculate the stress distribution and temperature change of the chip under different working conditions. The formula is: Among them, σ represents the stress tensor, D represents the elastic matrix of the chip material, ε represents the strain tensor, σ th represents the thermal stress caused by temperature change, α represents the thermal expansion coefficient, E represents the elastic modulus, T represents the current temperature, T ref represents the reference temperature, P represents the heat source, c represents the specific heat capacity, ρ represents the chip material density, β represents the Nabra operator, ▽T represents the temperature gradient, k represents the thermal conductivity, β×(-k▽T) represents the net rate of heat flow, Represents partial derivative.

4. A multi-axis stress control method for three-dimensional stacked chips according to claim 3, characterized in that: The specific steps of S2 also include: S2.3: Obtain the stress distribution and temperature change results of the chip in S2.2 under different working conditions, and use visualization software to import the obtained stress tensor data and temperature data respectively; S2.4: Generate stress distribution map by setting color mapping and arrows according to the magnitude and direction of stress tensor data; S2.5: Generate temperature changes by setting color mapping according to the size of temperature data. S2.6: In the stress distribution diagram, find the point with the largest stress value as the core stress point. At the same time, use the annotation function in the visualization tool to mark the position of the core stress point in the diagram and attach the stress value information; S2.7: Check and adjust the stress distribution diagram and temperature change diagram parameters, and export and save the stress distribution diagram and temperature change diagram with annotations.

5. A multi-axis stress control method for three-dimensional stacked chips according to claim 4, characterized in that: In addition to the multi-axis stress control strategy, the chip stacking solution also includes stress distribution, stress concentration points, stress gradient information and the implementation of the multi-axis stress control strategy.

6. A multi-axis stress control system for three-dimensional stacked chips, which is used to implement a multi-axis stress control method for three-dimensional stacked chips according to any one of claims 1 to 5, characterized in that: include: Collection and modeling module, meshing module, multi-axis stress analysis module, strategy formulation module, and effect evaluation module; The collection and modeling module is used to collect parameter data of the three-dimensional stacked chips and establish a preliminary finite element model based on the parameter data of the three-dimensional stacked chips; The meshing module is used to mesh the preliminary finite element model using an adaptive mesh refinement algorithm based on error estimation, and optimize the meshing result; The multi-axis stress analysis module is used to perform multi-axis stress analysis on the finite element mesh model of the three-dimensional stacked chip, calculate the stress distribution and temperature change of the chip under different working conditions, and identify the core stress points; The strategy formulation module is used to formulate a multi-axis stress control strategy according to the multi-axis stress analysis results, and implement the multi-axis stress control strategy during the chip stacking process; The effect evaluation module is used to perform thinning processing and performance testing on the stacked chips and evaluate the stress regulation effect of the stacked chips.

7. A multi-axis stress control system for three-dimensional stacked chips according to claim 6, characterized in that: The grid division module includes: a grid division unit and an optimization unit; The meshing unit is used to perform preliminary meshing of the preliminary finite element model by introducing an adaptive mesh refinement algorithm based on error estimation according to the geometric characteristics of the preliminary finite element model and the expected stress distribution; The optimization unit dynamically adjusts the density and shape of the grid according to the geometric features of the chip and the expected stress distribution characteristics, thereby obtaining a three-dimensional stacked chip finite element grid model.

8. A multi-axis stress control system for three-dimensional stacked chips according to claim 7, characterized in that: The multi-axis stress analysis module includes: a multi-axis stress analysis unit and a stress point identification unit; The multi-axis stress analysis unit is used to perform multi-axis stress analysis on the finite element mesh model of the three-dimensional stacked chip using finite element analysis software to calculate stress distribution and temperature change; The stress point identification unit is used to generate a stress distribution diagram and a temperature change diagram according to the analysis results, and mark the position of the core stress point.

9. A multi-axis stress control system for three-dimensional stacked chips according to claim 8, characterized in that: The policy formulation module includes: a policy formulation unit and a policy implementation unit; The strategy formulation unit is used to formulate a targeted multi-axis stress control strategy according to the location of the core stress point and the stress distribution characteristics; The strategy implementation unit is used to adjust chip parameters according to the formulated strategy during the chip stacking process to generate a chip stacking solution including a multi-axis stress regulation strategy.

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