A clock and control method for sharing PLL of multiple parallel ports PHY

Abstract

The purpose of the present invention is to provide a clock and control method for multiple parallel port PHYs sharing a PLL, the method comprising: a SOC phase-locked loop, multiple PHYs and multiple memory controllers; the SOC phase-locked loop is connected to the PHY and the memory controller to provide a clock signal. The present invention adopts a clock scheme in which multiple parallel port PHYs share an external PLL, which saves the number of PLLs in the chip, reduces the area and power consumption of the chip, and is particularly suitable for chips with a small area and ultra-low power consumption requirements. It is not only suitable for systems with a single parallel port PHY, but also suitable for systems with multiple parallel port PHYs, making the integration of parallel port PHYs in SoC systems more flexible and diversified.

Description

Technical Field

[0001] The present invention relates to the technical field of memory control, and in particular to a clock and control method of a multi-parallel-port PHY shared PLL. Background Art

[0002] ‌Parallel PHY system refers to the role and function of the physical layer (PHY) in computer networks. In computer networks, the PHY layer is the lowest layer of the OSI model and is responsible for converting data into electrical or optical signals that can be transmitted through physical media. PHY chips are the hardware that implements the functions of this layer. They connect the devices of the data link layer (such as MAC) and the physical media (such as optical fiber or copper cable). ‌Shared PLL‌ is a phase-locked loop (PLL) technology in which multiple devices or channels share a PLL to achieve frequency and phase synchronization and control. This technology is often used in high-speed, high-performance, and low-power multi-channel applications to ensure signal synchronization between multiple channels. The implementation of shared PLL can vary depending on the application. For example, in FPGAs, some models of FPGAs have an additional shared PLL per quad, or QPLL, which is a shared LCPLL designed to support high-speed, high-performance, and low-power multi-channel applications.

[0003] With the development of various memory technologies, such as DDR (Double Data Rate), HBM (High Bandwidth Memory) and ONFI (Open NAND Flash Interface), the speed of parallel PHY systems is getting higher and higher. For example, HBM3e is currently as high as 9600MT / s, so the working clock frequency of PHY is as high as (4800MHz). However, since MC (Memory Controller) generally implements more complex scheduling algorithms and ECC algorithms, the logic depth of these algorithms is generally long. According to the current process level, it is difficult to work at such a high clock frequency. Therefore, a frequency ratio system is generally introduced in parallel digital systems such as DDR / HBM / ONFI, that is, frequency ratio conversion is performed between MC (memory controller) and PHY. The most commonly used interface between MC and PHY is DFI (DDR PHY Interface). In the following text, DFI interface is used to represent the interface between MC and PHY.

[0004] The DFI interface supports the frequency ratio conversion system, where DFI clock is the working clock frequency of MC, and DFI PHYclock is the working clock frequency of PHY. The clock frequencies of MC and PHY generally support a frequency ratio of 1:1, 1:2, and 1:4, that is, MC works at a divided clock frequency or PHY works at a doubled clock frequency. Figure 2The solution of using a single PHY instance exclusively for a PLL clock is not applicable in some application scenarios. For example, when multiple PHY instances may need to be instantiated within an SoC and there is only one external SoC PLL, an independent PLL may not be desired inside the PHY because multiple PLLs mean an increase in area and power consumption. Summary of the invention

[0005] The purpose of the present invention is to provide a clock and control method for multiple parallel port PHYs sharing a PLL. The method adopts a clock scheme in which multiple parallel port PHYs share an external PLL, which saves the number of PLLs in the chip and reduces the area and power consumption of the chip. The method is particularly suitable for chips with a small area and ultra-low power consumption requirements. It is not only suitable for systems with a single parallel port PHY, but also for systems with multiple parallel port PHYs, making the integration of parallel port PHYs in SoC systems more flexible and diversified.

[0006] A clock for sharing PLL by multiple parallel port PHYs, comprising: a SOC phase-locked loop, multiple PHYs and multiple memory controllers;

[0007] The SOC phase-locked loop is connected to the PHY and the memory controller to provide a clock signal.

[0008] Preferably, the PHY comprises: a DFI clock path and a DFI PHY clock path;

[0009] The clock signal of the DFI PHY clock path is directly provided by the SOC phase-locked loop;

[0010] The clock signal of the DFI clock path is provided by a signal output by the SOC phase-locked loop after passing through a frequency dividing circuit.

[0011] Preferably, the PHY further comprises: a 2 / 4 frequency divider;

[0012] The 2 / 4 frequency divider is connected to the SOC phase-locked loop and the DFI PHY clock path, and is used to divide the high-speed clock input to the PHY to generate an internal low-speed clock.

[0013] Preferably, the DFI clock path includes a clock signal input terminal from the SOC phase-locked loop to a first trigger and a fourth trigger inside the PHY;

[0014] The DFI PHY clock path includes a clock signal input terminal from the SOC phase-locked loop to a second trigger and a third trigger inside the PHY.

[0015] Preferably, the first path from the first trigger to the second trigger includes:

[0016] Start the clock: the clock signal generated by the SOC phase-locked loop enters the PHY from the first port, and then the clock signal goes from the first port to the clock signal input terminal of the first trigger;

[0017] Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal goes from the second port to the clock signal input terminal of the second trigger.

[0018] Preferably, the second path from the third trigger to the fourth trigger includes:

[0019] Start the clock: the clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal goes from the second port to the clock signal input terminal of the third trigger;

[0020] Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the first port, and then the clock signal goes from the first port to the clock signal input terminal of the fourth trigger.

[0021] Preferably, the DFI PHY clock path includes a 2 / 4 frequency divider from the SOC phase-locked loop to the inside of the PHY, and the 2 / 4 frequency divider transmits the clock signal to the clock signal input terminals of the fifth trigger and the eighth trigger;

[0022] The DFI PHY clock path also includes a clock signal input terminal from the SOC phase-locked loop to a sixth flip-flop and a seventh flip-flop.

[0023] Preferably, the first path from the fifth trigger to the sixth trigger includes:

[0024] Start clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and after passing through the 2 / 4 frequency divider inside the PHY, the clock signal reaches the clock signal input terminal of the fifth trigger;

[0025] Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal reaches the clock signal input terminal of the sixth trigger from the second port.

[0026] Preferably, the second path from the seventh trigger to the eighth trigger includes:

[0027] Start the clock: the clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal reaches the clock signal input terminal of the seventh trigger from the second port;

[0028] Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port. After passing through the 2 / 4 frequency divider inside the PHY, the clock signal reaches the clock signal input terminal of the eighth trigger.

[0029] A clock control method for a multi-parallel-port PHY sharing PLL is applied to a clock of a multi-parallel-port PHY sharing PLL, comprising:

[0030] The SOC phase-locked loop provides clock signals to the PHY and memory controller;

[0031] The clock signal goes all the way into the PHY;

[0032] The clock signal is divided into two paths after passing through a 2 / 4 frequency divider, one path entering the memory controller and the other path entering the PHY.

[0033] The beneficial effects of the present invention are as follows: 1. The present invention adopts a clock scheme in which multiple parallel port PHYs share an external PLL, which saves the number of PLLs in the chip, reduces the area and power consumption of the chip, and is particularly suitable for chips with a small area and ultra-low power consumption requirements; 2. The present invention adopts a simple frequency division circuit inside the PHY, which solves the problem of mismatch between the input high-speed and low-speed clocks in the external clock network latency in the scheme in which multiple parallel port PHYs share the PLL at a relatively low cost; 3. The present invention uses the frequency division circuit inside the PHY to generate a low-speed Internal DFI clock to replace the external input low-speed DFI clock. This scheme allows the timing path on the DFI interface to work at a low-speed clock, simplifies the timing convergence on the DFI interface, and makes the SoC integrated PHY more friendly; 4. The present invention is not only applicable to systems with a single parallel port PHY, but also to systems with multiple parallel port PHYs, making the integration of parallel port PHY in the SoC system more flexible and diversified. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0036] Figure 1 A schematic diagram of a clock structure of a multi-parallel-port PHY sharing PLL according to the present invention;

[0037] Figure 2 A schematic diagram of a solution for a single PHY instance to exclusively use the Internal PLL clock of the present invention;

[0038] Figure 3 A schematic diagram of Clock Latency of high-speed and low-speed clocks in the SoC of the present invention;

[0039] Figure 4 A schematic diagram of a clock scheme for generating an Internal DFI clock by an internal frequency divider of the present invention;

[0040] Figure 5 The frequency divider of the present invention is flipped from the p0 phase of the DFI clock;

[0041] Figure 6 The frequency divider of the present invention starts flipping from the p1 phase of the DFI clock. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0044] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0045] The DFI interface supports the frequency ratio conversion system, where DFI clock is the working clock frequency of MC, and DFI PHYclock is the working clock frequency of PHY. The clock frequencies of MC and PHY generally support a frequency ratio of 1:1, 1:2, and 1:4, that is, MC works at a divided clock frequency or PHY works at a doubled clock frequency. Figure 2The solution of using a single PHY instance exclusively for a PLL clock is not applicable in some application scenarios. For example, when multiple PHY instances may need to be instantiated within an SoC and there is only one external SoC PLL, an independent PLL may not be desired inside the PHY because multiple PLLs mean an increase in area and power consumption.

[0046] The present invention adopts a clock solution in which multiple parallel port PHYs share an external PLL, thereby saving the number of PLLs in the chip, reducing the area and power consumption of the chip, and is particularly suitable for chips with a small area and ultra-low power consumption requirements; the present invention adopts a simple frequency division circuit inside the PHY, and solves the problem of mismatch between the input high-speed and low-speed clocks in the external clock network latency in the solution in which multiple parallel port PHYs share the PLL at a relatively low cost; the present invention adopts the frequency division circuit inside the PHY to generate a low-speed Internal DFI clock to replace the external input low-speed DFI clock. This solution allows the timing path on the DFI interface to work under the low-speed clock, simplifies the timing convergence on the DFI interface, and makes the SoC integrated PHY more friendly; the present invention is not only applicable to a system with a single parallel port PHY, but also to a system with multiple parallel port PHYs, making the integration method of the parallel port PHY in the SoC system more flexible and diversified.

[0047] Example 1

[0048] A multi-parallel port PHY shared PLL clock, reference Figure 1 , including: SOC phase-locked loop, multiple PHYs and multiple memory controllers;

[0049] The SOC phase-locked loop is connected to the PHY and memory controller to provide a clock signal.

[0050] The present invention proposes a new clock scheme technology based on the current parallel port PHY supporting the frequency ratio system. In some current mainstream parallel port PHYs, an external SOC PLL generally generates a DFI clock and sends it to the MC and PHY respectively. In the PHY, an internal PLL uses the DFI clock as a reference clock to multiply the frequency to generate a high-speed DFI PHY clock scheme, such as Figure 2 As shown in the figure: a low-speed DFI clock is generated through an external SoC PLL, and an Internal PLL is used inside the PHY to multiply the DFI clock into a high-speed DFI PHY clock.

[0051] For the above Figure 2The single PHY instance exclusive PLL clock solution described in the above is not applicable in some application scenarios. For example, when a SoC may need to instantiate multiple PHY instances and there is only one external SoC PLL, it may not be desirable to have an independent PLL inside the PHY, because multiple PLLs mean an increase in area and power consumption. In order to reduce chip area and power consumption and reduce the number of PLLs in the entire SoC, the present invention proposes a method of using multiple PHY instances to share an external SoC PLL, and the PHY external SoC PLL provides high-speed and low-speed clocks. The solution of multiple PHY instances sharing an external SoC PLL is as follows: Figure 1 As shown: Taking two PHY instances as an example, a high-speed DFI PHY clock is generated by the SoC PLL and sent to the upper and lower PHY instances respectively. In addition, a 2 / 4 frequency division circuit is used to divide the frequency to generate a low-speed DFI clock and send it to the upper and lower MCs and PHYs respectively.

[0052] Preferably, the PHY comprises: a DFI clock path and a DFI PHY clock path;

[0053] The clock signal of the DFI PHY clock path is directly provided by the SOC phase-locked loop;

[0054] The clock signal of the DFI clock path is provided by the signal output by the SOC phase-locked loop after passing through the frequency division circuit.

[0055] For the above Figure 1 In the solution where multiple PHYs share an external SoC PLL clock, there are two key design points for optimizing area and power consumption: one is that there is no PLL inside the PHY, the high-speed clock DFI PHY clock is provided by the external SoC PLL, and the low-speed DFI clock is obtained by dividing the high-speed clock by 2 / 4 (selected according to the frequency ratio); the second is that two PHY instances share an external SoC PLL.

[0056] However, there is still a problem in this design, which is described in detail as follows:

[0057] In the design of parallel port PHY system, PHY is generally delivered in harden mode, that is, PHY is implemented independently by IP vendor and then delivered to customers in GDS form. When IP vendor implements PHY independently, from the perspective of PHY, there are two clock sources: one is the low-speed DFI clock; the other is the high-speed DFI PHY clock. Both clocks are derived from the external SoC PLL, but they pass through different clock networks externally. For PHY, it is impossible to perceive the latency of these two clocks in the clock network outside PHY ( Figure 1 Therefore, for the path between the DFI clock and the DFI PHY clock, even if the timing convergence is performed inside the PHY, it is still a "false" timing convergence, because the clock network latency of these two clocks outside the PHY is not considered and cannot be considered during the timing convergence.

[0058] After the IP is delivered to the customer, since the IP is hardened, the customer can see the external clock network latency of the two clocks, but cannot see the timing path inside the PHY. Therefore, when the external SoC is timing converged, the timing convergence of the timing path between the DFI clock and the DFI PHY clock cannot be guaranteed.

[0059] Preferably, the PHY further comprises: a frequency divider for dividing the frequency by 2 / 4;

[0060] The 2 / 4 frequency divider is connected to the SOC phase-locked loop and the DFI PHY clock path to divide the high-speed clock input to the PHY to generate an internal low-speed clock.

[0061] A frequency divider is an electronic circuit or device that is used to reduce the frequency of an input signal to a lower frequency, usually by dividing, counting or performing logical operations on the input signal. The main working principle of a frequency divider is to divide the input periodic signal into multiple signals with longer periods according to a specific frequency division ratio. For example, a 2-way divider divides each cycle of the input signal into two cycles, thereby reducing the frequency by half. A frequency divider can convert high-frequency signals into low-frequency signals to adapt to different application requirements and realize functions such as signal processing, synchronization and control. ‌Division-2 and 4-way are commonly used concepts in signal processing and audio engineering, mainly used to describe the division and processing of signal frequencies. Dividing by two is the process of dividing an audio signal into two frequency bands, which is usually used in sound systems to divide the signal into low-frequency and high-frequency parts. In a speaker system, a 2-way network sends low-frequency signals (such as bass) to a woofer (low-frequency unit) and high-frequency signals (such as treble) to a tweeter (high-frequency unit) to improve the sound quality and ensure that the sound of different frequency bands is played by the most suitable speaker. Four-way is the process of dividing an audio signal into four frequency bands, which is usually used in more complex sound systems.

[0062] The present invention adds a 2 / 4 frequency divider inside the PHY. The frequency divider uses the DFI PHY clock to sample the phase of the DFI clock, and then divides the DFI PHY clock by 2 or 4 according to the sampled phase, thereby obtaining an Internal DFI clock with the same frequency and phase as the DFI clock. The source of this clock is derived from the DFI PHY clock, but its frequency and phase are the same as those of the DFI clock. Using this clock instead of the DFI clock inside the PHY can avoid the problem of mismatch between the external latency of the launch clock and the capture clock in the timing path.

[0063] Preferably, the DFI clock path includes a clock signal input terminal from the SOC phase-locked loop to the first trigger and the fourth trigger inside the PHY;

[0064] The DFI PHY clock path includes a clock signal input terminal from the SOC phase-locked loop to the second flip-flop and the third flip-flop inside the PHY.

[0065] Preferably, the first path from the first trigger to the second trigger includes:

[0066] Start the clock: the clock signal generated by the SOC phase-locked loop enters the PHY from the first port, and then the clock signal goes from the first port to the clock signal input terminal of the first trigger;

[0067] Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal goes from the second port to the clock signal input terminal of the second trigger.

[0068] as follows Figure 3 As shown,

[0069] For path1, the latency of its launch clock and capture clock is as follows:

[0070] Launch clock latency = A->C latency + C->E latency

[0071] Capture clock latency = A->B latency + B->D latency

[0072] From the above expression, we can see that the launch clock of path1 is input from the C port of PHY, and the capture clock is input from the B port of PHY. Their clock network latencies outside PHY are different, one is the delay from A->C, and the other is the delay from A->B.

[0073] Preferably, the second path from the third trigger to the fourth trigger includes:

[0074] Start the clock: the clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal goes from the second port to the clock signal input terminal of the third trigger;

[0075] Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the first port, and then the clock signal goes from the first port to the clock signal input terminal of the fourth trigger.

[0076] For path2, the latency of its launch clock and capture clock is as follows:

[0077] Launch clock latency = A->B latency + B->D latency

[0078] Capture clock latency = A->C latency + C->E latency

[0079] It can also be seen from the above expression that the launch clock of path2 is input from the B port of PHY, and the capture clock is input from the C port of PHY. Their clock network latencies outside PHY are different, one is the delay from A->B, and the other is the delay from A->C.

[0080] According to the above analysis, the Launch clock of path1 is the DFI clock, and the Capture clock is the DFI PHY clock; the Launch clock of path2 is the DFI PHY clock, and the Capture clock is the DFI clock; for path1 and path2, regardless of their Launch clock or Capture clock, the entire clock network is divided into two parts, one part is inside the PHY (the path of C->E, the path of B->D), and the other part is outside the PHY (the path of A->C, the path of A->B). When the PHY is independently implemented in the backend, the latency of the clock network outside the PHY cannot be calculated.

[0081] Preferably, the DFI PHY clock path includes a 2 / 4 frequency divider from the SOC phase-locked loop to the PHY, and the 2 / 4 frequency divider transmits the clock signal to the clock signal input terminals of the fifth trigger and the eighth trigger;

[0082] The DFI PHY clock path also includes a clock signal input terminal from the SOC phase-locked loop to the sixth flip-flop and the seventh flip-flop.

[0083] Regarding the above Figure 3The present invention further improves the problem described in , by adding a 2 / 4 frequency divider inside the PHY, through which the high-speed clock DFI PHY clock input to the PHY is divided to generate an internal low-speed clock Internal DFI clock, and the Internal DFI clock is used to replace the DFIclock inside the PHY, thereby ensuring that the clocks of all paths inside the PHY are input from the port (Port B) of the DFI PHY clock of the PHY; for all timing paths inside the PHY, in the DFI PHY clock network, the part of the clock network outside the PHY is the same (for the timing path inside the PHY, this part of the clock network belongs to the common path); therefore, when the harden PHY is integrated into the SoC, the timing path inside the PHY that has converged will not be affected during the SoC timing analysis, such as Figure 4 shown.

[0084] Preferably, the first path from the fifth trigger to the sixth trigger includes:

[0085] Start clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and after passing through the 2 / 4 frequency divider inside the PHY, the clock signal reaches the clock signal input terminal of the fifth trigger;

[0086] Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal reaches the clock signal input terminal of the sixth trigger from the second port.

[0087] like Figure 4 , for path1, the latency of its launch clock and capture clock is as follows:

[0088] Launch clock latency = A->B latency + B->E latency + E->F latency

[0089] Capture clock latency = A->B latency + B->D latency

[0090] From the above expressions, it can be seen that the launch clock and capture clock of path1 are both derived from the DFI PHY clock, and their external clock network latency is the same as the delay from A->B.

[0091] Preferably, the second path from the seventh trigger to the eighth trigger includes:

[0092] Start the clock: the clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal reaches the clock signal input terminal of the seventh trigger from the second port;

[0093] Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port. After passing through the 2 / 4 frequency divider inside the PHY, the clock signal reaches the clock signal input terminal of the eighth trigger.

[0094] For path2, the latency of its launch clock and capture clock is as follows:

[0095] Launch clock latency = A->B latency + B->D latency

[0096] Capture clock latency = A->B latency + B->E latency + E->F latency

[0097] It can also be seen from the above expression that the launch clock and capture clock of path2 are both derived from the DFI PHY clock, and their external clock network latency is the same as the delay of A->B.

[0098] Therefore, no matter in the case of path 1 or path 2, it can be seen that their launch clock and capture clock are input from the same port of PHY (B), so the external clock network belongs to the common path. Therefore, when the SoC performs timing convergence, in addition to meeting the PHY's restrictions on the clock latency of the input clock, it does not affect the timing of the timing path inside the PHY.

[0099] Example 2

[0100] A clock control method for a multi-parallel-port PHY sharing PLL is applied to a clock of a multi-parallel-port PHY sharing PLL, comprising:

[0101] S100, the SOC phase-locked loop provides clock signals to the PHY and memory controller;

[0102] Phase Locked Loop (PLL) is a negative feedback control system that uses the voltage generated by phase synchronization to tune the voltage-controlled oscillator to generate the target frequency. It is a typical feedback control circuit that uses an external reference signal to control the frequency and phase of the oscillation signal inside the loop to achieve automatic tracking of the output signal frequency to the input signal frequency. Phase-locked loops are generally used in closed-loop tracking circuits and are a method of making the frequency more stable in radio transmission. The phase-locked loop is mainly composed of a voltage-controlled oscillator (VCO) and a phase-locked loop integrated circuit (PLL IC), in which the voltage-controlled oscillator gives a signal, one part of which is used as output, and the other part is compared with the local oscillator signal generated by the PLL IC through frequency division. If there is a change in phase difference, the voltage at the voltage output end of the phase detector changes to control the VCO until the phase difference is restored to achieve the purpose of phase locking. In this way, the phase-locked loop can keep the frequency and phase of the controlled oscillator in a certain relationship with the input signal.

[0103] The memory controller is an important component of the computer system that controls the memory and exchanges data between the memory and the CPU through the memory controller. The memory controller determines important parameters such as the maximum memory capacity, number of memory banks, memory type and speed, memory particle data depth and data width that the computer system can use, thus having a great impact on the overall performance of the computer system. The main functions of the memory controller include interface conversion, converting the read and write commands issued by the host device into signals that the memory can recognize, and completing the address decoding and data format conversion between the host device and the memory. In addition, the memory controller also undertakes functions such as compression, encryption and data randomization, making the memory controller more intelligent and requiring certain computing power to perform these operations. In terms of technical implementation, the memory controller communicates with the memory bar through address / command lines and data lines. The address / command line is unidirectional, from the memory controller to the memory chip, including a bit-wide address line and a bit-wide command line; the data line is bidirectional, including a bit-wide data line. These details explain how the memory controller interacts with the memory at the hardware level to ensure the correct transmission and processing of data.

[0104] S200, the clock signal goes all the way to the PHY;

[0105] The clock signal plays a vital role in digital circuits. It provides a reference frequency so that all circuit elements can work in the same rhythm. At each rising or falling edge of the clock signal, the operation in the circuit is triggered to execute. The frequency of the clock signal determines the operation rate of the circuit. The clock signal can be generated by a variety of methods. Common generation methods include using external clock sources (such as quartz crystal oscillators, RC / LC oscillation circuits, etc.) and internal clock sources (such as phase-locked loops PLL, frequency division circuits, etc.). These methods are selected according to the requirements of specific applications. The clock signal enters the PHY all the way to provide a standard time reference to ensure the synchronization and accuracy of data transmission. In the physical layer of the OSI model, the PHY (physical layer) is responsible for connecting the devices of the data link layer (such as MAC) to the physical medium (such as optical fiber or copper cable). A typical PHY includes PCS (physical coding sublayer) and PMD (physical medium dependent sublayer). PCS encodes and decodes the information being sent and received in order to make it easier for the receiver to recover the signal. The clock signal enters the PHY, providing the necessary clock reference for data transmission, ensuring the synchronous transmission and correct reception of data. This is because in data communication, maintaining data synchronization is crucial to avoiding data errors and ensuring communication quality. The PHY chip receives analog signals such as electricity or light, demodulates and converts them into A / D signals, and then passes the signals to the MAC chip for processing through the MII interface, relying on precise clock signals to ensure the accuracy and reliability of data transmission.

[0106] S300, the clock signal is divided into two paths after passing through a 2 / 4 frequency divider, one path enters the memory controller and the other path enters the PHY.

[0107] exist Figure 4 In the figure, we can also see that the 2 / 4 divider inside the PHY has an additional input DFI clock compared to the 2 / 4 divider of the external SoC. It should be noted that in this divider, the DFI clock is not used as a clock, but is sampled by the DFI PHY clock as a data to obtain the phase relationship between the DFI PHY clock and the DFI clock. The purpose of this is to ensure that the phase of the Internal DFI clock obtained by dividing the DFI PHY clock is consistent with that of the DFI clock.

[0108] The following example uses the frequency divider setting of 2 as an example. If the DIV2 / 4 frequency divider inside the PHY directly divides the DFI PHY clock without considering the phase of the DFI clock, the phase relationship of the output divided clock domain DFI clock may exist in the following two situations:

[0109] The first case is as follows Figure 5 As shown in the figure, when the divider starts working from time T0, that is, the output of the divider starts to flip at the p0 phase of DFIclock, then the output divided clock Internal DFI clock also flips from time T0, and its phase is aligned with the DFI clock.

[0110] In the second case, Figure 6 As shown in the figure, when the divider starts working from time T1, that is, the output of the divider starts to flip at the p1 phase of DFIclock, then the output divided clock Internal DFI clock starts to flip from time T1, and its phase differs from that of DFI clock by half a DFI clock cycle. This situation is undesirable.

[0111] Therefore, in the present invention, the input DFI clock is sampled in the DIV2 / 4 divider inside the PHY to obtain whether the current DFI PHY clock cycle is in the p0 phase or the p1 phase of the DFI clock, so that the divider output is flipped from the p0 phase of the DFI clock, thereby ensuring that the output divided clock Internal DFI clock is aligned in phase with the DFI clock.

[0112] The present invention adopts a clock solution in which multiple parallel port PHYs share an external PLL, thereby saving the number of PLLs in the chip, reducing the area and power consumption of the chip, and is particularly suitable for chips with a small area and ultra-low power consumption requirements; the present invention adopts a simple frequency division circuit inside the PHY, and solves the problem of mismatch between the input high-speed and low-speed clocks in the external clock network latency in the solution in which multiple parallel port PHYs share the PLL at a relatively low cost; the present invention adopts the frequency division circuit inside the PHY to generate a low-speed Internal DFI clock to replace the external input low-speed DFI clock. This solution allows the timing path on the DFI interface to work under the low-speed clock, simplifies the timing convergence on the DFI interface, and makes the SoC integrated PHY more friendly; the present invention is not only applicable to a system with a single parallel port PHY, but also to a system with multiple parallel port PHYs, making the integration method of the parallel port PHY in the SoC system more flexible and diversified.

[0113] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A clock of multiple parallel port PHYs sharing PLL, characterized in that: include: SOC phase-locked loop, multiple PHYs, and multiple memory controllers; The SOC phase-locked loop is connected to the PHY and the memory controller to provide a clock signal; The PHY further includes: a frequency divider for dividing the frequency by 2 / 4; The 2 / 4 frequency divider is connected to the SOC phase-locked loop and the DFI PHY clock path, and is used to divide the high-speed clock input to the PHY to generate an internal low-speed clock; The PHY includes: a DFI clock path and a DFI PHY clock path; The clock signal of the DFI PHY clock path is directly provided by the SOC phase-locked loop; The clock signal of the DFI clock path is provided by the signal output by the SOC phase-locked loop after passing through a frequency division circuit; The DFI clock path includes a clock signal input terminal from the SOC phase-locked loop to a first trigger and a fourth trigger inside the PHY; The DFI PHY clock path includes a clock signal input terminal from the SOC phase-locked loop to a second trigger and a third trigger inside the PHY.

2. The multi-parallel-port PHY shared PLL clock according to claim 1, characterized in that: A first path from the first trigger to the second trigger includes: Start the clock: the clock signal generated by the SOC phase-locked loop enters the PHY from the first port, and then the clock signal goes from the first port to the clock signal input terminal of the first trigger; Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal goes from the second port to the clock signal input terminal of the second trigger.

3. The clock of a multi-parallel-port PHY sharing PLL according to claim 2, characterized in that: The second path from the third flip-flop to the fourth flip-flop includes: Start the clock: the clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal goes from the second port to the clock signal input terminal of the third trigger; Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the first port, and then the clock signal goes from the first port to the clock signal input terminal of the fourth trigger.

4. The clock of a multi-parallel-port PHY sharing PLL according to claim 3, characterized in that: The DFI PHY clock path includes a 2 / 4 frequency divider from the SOC phase-locked loop to the PHY, and the 2 / 4 frequency divider transmits the clock signal to the clock signal input terminals of the fifth flip-flop and the eighth flip-flop; The DFI PHY clock path also includes a clock signal input terminal from the SOC phase-locked loop to a sixth flip-flop and a seventh flip-flop.

5. The clock of a multi-parallel-port PHY sharing PLL according to claim 4, characterized in that: The first path from the fifth flip-flop to the sixth flip-flop includes: Start clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and after passing through the 2 / 4 frequency divider inside the PHY, the clock signal reaches the clock signal input terminal of the fifth trigger; Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal reaches the clock signal input terminal of the sixth trigger from the second port.

6. The clock of a multi-parallel-port PHY sharing PLL according to claim 5, characterized in that: The second path from the seventh flip-flop to the eighth flip-flop includes: Start the clock: the clock signal generated by the SOC phase-locked loop enters the PHY from the second port, and then the clock signal reaches the clock signal input terminal of the seventh trigger from the second port; Capture clock: The clock signal generated by the SOC phase-locked loop enters the PHY from the second port. After passing through the 2 / 4 frequency divider inside the PHY, the clock signal reaches the clock signal input terminal of the eighth trigger.

7. A clock control method for a multi-parallel-port PHY sharing PLL, applied to a clock of a multi-parallel-port PHY sharing PLL as claimed in any one of claims 1 to 6, characterized in that: include: The SOC phase-locked loop provides clock signals to the PHY and memory controller; The clock signal is divided into two paths after passing through a 2 / 4 frequency divider, one path entering the memory controller and the other path entering the PHY.

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