A method, apparatus, device, medium and product for adjusting a design layout

Abstract

The application discloses a method, device, equipment, medium and product for adjusting a design layout, and applies to the field of photolithography technology. The method first performs clustering operation according to the distribution density of each bad point on the original design layout in the overall bad point information database, and divides each bad point into a plurality of local design layouts. Then, the local design layout is adjusted to obtain a target local design layout, and a final target design layout is obtained. The scheme provided in the embodiment of the application can quickly determine the local design layout where the bad points are located by performing clustering operation according to the distribution density of each bad point on the original design layout, and then modify the graphics at the corresponding position, which consumes less time. Moreover, only the local design layout needs to be adjusted, and compared with overall adjustment of the entire design layout, the scheme consumes less computing resource and computing time, thereby meeting the actual production demand.

Description

Technical Field

[0001] This application belongs to the field of photolithography technology, and in particular relates to a method, apparatus, equipment, medium and product for adjusting a design layout. Background Technology

[0002] As advanced semiconductor node sizes continue to shrink and processes become increasingly complex, the concept of design technology co-optimization (DTCO) has emerged. Its core idea is to bridge the gap between the previously separate technology areas of design and manufacturing, feeding back defect information from manufacturing to the design phase for collaborative optimization. In manufacturing, the mask layout output from optical proximity correction may fail to produce the expected imaging results, resulting in defects and impacting the final chip yield. In such cases, the problem may not be solvable at the manufacturing stage, requiring adjustments to the design layout to eliminate the defects.

[0003] In traditional solutions, the design team adjusts the entire design layout based on defect information reported by the manufacturing team. However, this method requires processing too much information, consuming significant computing resources and time, and cannot meet actual production needs. Summary of the Invention

[0004] This application provides a method, apparatus, device, medium, and product for adjusting a design layout, which can quickly and accurately adjust the design layout to eliminate bad pixels, thereby saving computing resources and time.

[0005] On one hand, embodiments of this application provide a method for adjusting a design layout, including:

[0006] Photolithography simulation is performed based on the original design layout to determine the corresponding overall defect information database;

[0007] Based on the distribution density of each defective point in the overall defective point information database on the original design layout, a clustering operation is performed to divide each defective point into multiple local design layouts.

[0008] Determine the local defect information database corresponding to the local design layout;

[0009] Based on the local defect information database, the local design layout is adjusted to eliminate each defect in the local defect information database, thereby obtaining the target local design layout;

[0010] The target partial design layout is merged with the unprocessed areas of the original design layout, excluding the partial design layout, to obtain the target design layout.

[0011] On the other hand, the process of performing photolithography simulation based on the original design layout to determine the corresponding overall defect information database includes:

[0012] Photolithography simulation was performed based on the original design layout to determine the initial overall defect information database;

[0013] Select target bad points from the initial overall bad point information database; the target bad points are those that can be eliminated by modifying the line width;

[0014] Each of the target bad pixels is determined as part of the overall bad pixel information database.

[0015] On the other hand, the step of performing photolithography simulation based on the original design layout to determine the initial overall defect information database includes:

[0016] Based on photolithography simulation tools, the original design layout is simulated to obtain the overall photoresist development outline information;

[0017] The overall photoresist development contour information is subjected to photolithography rule checks to obtain the initial overall defect information database.

[0018] On the other hand, determining the local defect information database corresponding to the local design layout includes:

[0019] Based on photolithography simulation tools, the local design layout is simulated to obtain local photoresist development outline information;

[0020] The local photoresist development contour information is subjected to photolithography rule inspection to obtain the local defect information database.

[0021] On the other hand, adjusting the local design layout based on the local defect information database to eliminate each defect in the local defect information database and obtain the target local design layout includes:

[0022] Determine the target edge of the defective pixel to be eliminated in the local design layout;

[0023] Determine the defect category of the defect to be eliminated;

[0024] Based on the defect category of the defect to be eliminated, the target edge is moved to obtain the target local design layout.

[0025] On the other hand, the step of moving the target edge based on the defect category of the defect to be eliminated to obtain the target local design layout includes:

[0026] Obtain the defect size value and expected value of the defect to be eliminated; the defect size value is the distance between the two edges that caused the defect, and when the distance between the two edges that caused the defect is the expected value, the defect to be eliminated is eliminated;

[0027] Determine the difference between the defect size value and the expected value;

[0028] Based on the defect category of the defect to be eliminated, the target edge is shifted by the difference to obtain the first corrected layout.

[0029] Determine whether the first revised layout meets the iteration stop condition;

[0030] If the first revised layout does not meet the iteration stopping condition, the target edge is moved by a preset step size to obtain the second revised layout.

[0031] The second revised layout is determined as the new first revised layout, and the step of determining whether the first revised layout meets the iteration stopping condition is returned until the first revised layout meets the iteration stopping condition; the iteration stopping condition includes the elimination of the bad points to be eliminated or the layout design rules restrict the continued movement of the target edge.

[0032] On the other hand, after merging the target partial design layout with the unprocessed areas of the original design layout other than the partial design layout to obtain the target design layout, the method further includes:

[0033] Determine the direction and distance of movement of the target edge;

[0034] Based on the overall defect information database, the moving direction and moving distance of the target edge, the target design layout is adjusted.

[0035] In another aspect, embodiments of this application provide an apparatus for adjusting a design layout, including: a processor and a memory storing computer program instructions;

[0036] When the processor executes the computer program instructions, it implements the method for adjusting the design layout as described above.

[0037] In another aspect, embodiments of this application provide a computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement the method for adjusting the design layout as described above.

[0038] In another aspect, embodiments of this application provide a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform the method of adjusting the design layout as described above.

[0039] This application provides a method for adjusting a design layout. First, clustering is performed based on the distribution density of each defective pixel in the overall defective pixel information database on the original design layout, dividing each defective pixel into multiple local design layouts. Then, the local design layouts are adjusted to obtain the target local design layout, resulting in the final target design layout. The proposed solution, by clustering the distribution density of each defective pixel on the original design layout, can quickly determine the local design layout where the defective pixel is located, and then modify the graphics at the corresponding location, with less time consumption. Furthermore, because only local design layouts need to be adjusted, compared to adjusting the entire design layout, this solution consumes fewer computational resources and time, thus meeting actual production needs. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A flowchart illustrating a method for adjusting a design layout according to an embodiment of this application is shown;

[0042] Figure 2 This illustration shows a schematic diagram of a graphic merging process provided in one embodiment of this application;

[0043] Figure 3 This illustration shows a complete flowchart of an embodiment of the present application for adjusting the design layout;

[0044] Figure 4(a) shows the graph corresponding to the bad spots in the pinch category;

[0045] Figure 4(b) shows the graph corresponding to the bad points of the bridge category;

[0046] Figure 5 This illustration shows a flowchart of adjusting graphic line width according to an embodiment of this application;

[0047] Figure 6 This invention provides a schematic diagram of the structure of an apparatus for adjusting a design layout according to an embodiment of the present application.

[0048] Figure 7 A schematic diagram of the hardware structure of the device with an adjusted design layout provided in an embodiment of this application is shown. Detailed Implementation

[0049] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0050] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0051] To address the problems of traditional solutions, embodiments of this application provide a method, apparatus, device, medium, and product for adjusting a design layout. The method for adjusting a design layout provided in this application embodiment will be described first below. Figure 1 A flowchart illustrating a method for adjusting a design layout according to an embodiment of this application is shown. Figure 1 As shown, the method includes the following steps: S101 to S105.

[0052] S101: Perform photolithography simulation based on the original design layout to determine the corresponding overall defect information database.

[0053] First, an initial overall defect information database (N0) of the original design layout needs to be obtained. A signed-off design layout is identified as the processing object, and a photolithography simulation tool is used to simulate the design layout to obtain the photoresist development contour information. Then, a Litho Rule Check (LRC) tool is used to set the defect detection category and defect definition range to detect the simulated photoresist development contour, obtaining the initial overall defect information database (N0), including the x / y coordinates of the defect, the defect category, and the defect size (unit: nm). The defect categories are mainly pinch, bridge, and contact size, and can be expanded as needed.

[0054] After obtaining the initial overall bad pixel information database (N0), the design tool uses Design Rules Check (DRC) to filter the initial overall bad pixel information database (N0), removing bad pixel locations that cannot be optimized by modifying the line width, thus avoiding invalid optimizations, resulting in a new overall bad pixel information database (N1). The overall bad pixel information database (N1) only retains target bad pixels, which are those that can be eliminated by modifying the line width.

[0055] S102: Perform clustering operations based on the distribution density of each defective pixel in the overall defective pixel information database on the original design layout, and divide each defective pixel into multiple local design layouts.

[0056] In this embodiment, based on the defect density of each defect in the overall defect information database on the original design layout, clustering is performed on each defect in the overall defect information database to determine multiple local design layouts. By optimizing each of the multiple local design layouts separately, the optimization of the entire design layout can be completed quickly.

[0057] The defective pixels in the overall defective pixel information database (N1) are clustered using a clustering algorithm. The clustering algorithm divides the design layout by determining the defective pixel density based on their location, and then encloses these defective pixels in boxes, thus obtaining multiple boxes (i.e., local design layouts). The appropriate clustering algorithm can be selected based on the specific requirements to obtain the local design layout.

[0058] S103: Determine the database of local defect information corresponding to the local design layout.

[0059] To adjust the local design layout, it is necessary to first determine the local defect information database corresponding to the local design layout. It should be noted that the information of the overall defect information database (N1) in the previous steps can be directly reused, or the local design layout within the box can be re-simulated to obtain the contour and LRC check to obtain the local defect information database. This is because there may be errors between the overall calculation and the local calculation of defects, and recalculation can eliminate this error.

[0060] In the above overall and local calculations, appropriate simulation lithography tools can be selected to obtain the lithography development contour, such as the traditional optical proximity correction (OPC) method or the lithography feedback tool method based on artificial intelligence.

[0061] S104: Based on the local defect information database, adjust the local design layout to eliminate each defect in the local defect information database and obtain the target local design layout.

[0062] Each defective pixel has two values: defect size (the distance between the two edges that caused the defective pixel) and spec (the expected range of the defective pixel is defined as the distance between the two edges that caused the defective pixel if it exceeds this value).

[0063] This step performs an overall optimization of the predicted defective points. The defect size (defect size) and expected value (spec) of the defective point to be eliminated are subtracted to obtain the difference. Then, based on the defective point's category, the edge corresponding to the defective point's location is moved, with the moving distance being this difference. Since the distance the edge moves and the corresponding contour moves are not necessarily equal, a step size needs to be set for some defective points. A check is performed after each step, and this process is iterated until the defective point is resolved or cannot be moved due to design rules.

[0064] It should be noted that the adjustment methods for different types of bad pixels are different. This application targets bad pixels that can optimize the design layout by modifying the line width. Bad pixel categories include pinch and bridge. The two edges that cause the bad pixel are the target edge lines. The target edge lines can be moved according to the corresponding category (i.e., the corresponding line width is changed).

[0065] S105: Merge the target local design layout with the unprocessed areas in the original design layout, excluding the local design layout, to obtain the target design layout.

[0066] Finally, the target local design layout (i.e., the optimized graphic within the box) is obtained. The optimized graphic within the box and the unoptimized graphic outside the box are merged to obtain the desired target design layout.

[0067] Figure 2 This illustration shows a schematic diagram of a graphic merging process provided in one embodiment of this application; as shown Figure 2 As shown, the design includes an original design layout 201, a partial design layout 202, a target partial design layout 203, an unprocessed area 204, and a target design layout 205. Clustering is performed on the defects in the overall defect information database to identify the partial design layout 202 and the unprocessed area 204 within the original design layout 201. Then, based on the partial defect information database, the partial design layout 202 is adjusted to obtain the target partial design layout 203. Finally, the target partial design layout 203 is merged with the unprocessed area 204 (excluding the partial design layout) in the original design layout to obtain the target design layout 205.

[0068] Figure 3 This illustration shows a complete flowchart of an embodiment of the modified design layout provided in this application; as follows: Figure 3 As shown, the steps include: S301 to S309.

[0069] S301: Obtain the original design layout D0.

[0070] S302: Simulation is performed based on the original design layout D0 to obtain the photoresist development contour information, and the initial overall bad pixel information database N0 is obtained based on the photolithography rules.

[0071] S303: Filter the data using design tools to obtain the overall bad pixel information database N1.

[0072] S304: Cluster the overall bad pixel information database N1 to obtain multiple boxes.

[0073] S305: Optimize the graphics within each box separately.

[0074] S306: Merge the optimized graphic within the box with the unprocessed graphic outside the box to obtain the target design layout.

[0075] S307: Compare the original design layout D0 and the target design layout D1 to obtain optimization information, and save the target design layout D1 as a text file.

[0076] S308: Further optimize the design layout based on optimization information and text files.

[0077] S309: Output the final design layout.

[0078] Because the above optimizations only target linewidth, their effect is limited. Therefore, the entire optimization process information can be summarized and transmitted to the design optimization tool for final optimization of the design layout. First, the original design layout is compared with the optimized target design layout obtained in the above steps. The optimized graphic processing information is saved as a guide text file, including information from the initial overall defect information database N0, such as the x / y coordinates of the defective pixels, their category, and size, as well as optimization information, namely the direction and distance of the target edge movement. Then, the obtained guide file is transmitted to the design optimization tool. Since the optimization in the above steps mainly considers linewidth and graphic spacing in the DRC, its effect is limited. Therefore, the design layout still needs further modification and optimization by the design optimization tool at the design end. Based on a more comprehensive DRC and other physical design constraints, combined with the guide file information, the design layout is optimized to obtain the final design layout.

[0079] As can be seen, the solution proposed in this application first requires defining a single layer of the original design layout after signoff. A photolithography simulation model is used to simulate the original design layout, obtaining the simulated photoresist development outline. Then, an LRC tool is used to predict defective pixels on the simulated photoresist development outline of the entire design layout. The design tool then uses DRC to filter out defective pixels in unchangeable areas. Next, for the defective pixels across the entire layout, local graphics are iteratively optimized based on their location and category. Finally, the optimized design layout is compared with the initial design layout to obtain information such as optimization processing locations and methods. This information is converted into guide information and saved as a text file, then transmitted to the design tool. The design tool then judges the information in the guide file according to DRC rules, ultimately completing the optimization of the design layout. This results in an overall reduction in the number of predicted defective pixels across the entire design layout, improving manufacturing yield.

[0080] This solution extends traditional methods of local mask repair to local design layout fine-tuning. Using a progressive strategy, it feeds back defect information and repair methods to the design team, allowing them to further address lithographic defects and improve yield while adhering to DRC (Depth Rectification Rules). By generating boxes through clustering algorithms and iteratively modifying and optimizing the graphics within these local boxes, processing only the linewidth and spacing of local graphics, it saves significant computational resources and time.

[0081] Design and manufacturing are two relatively separate technical areas, typically handled by two different companies. Furthermore, the high level of information confidentiality in the chip industry limits and inefficiencies in information exchange between the two. As technology evolves, processes become increasingly complex, raising the information barriers between design and manufacturing. Currently, there are no products that combine manufacturing feedback with tools for local design optimization, leading to repeated iterations during the tape-out process. In the semiconductor industry, the timeframe from tape-out to final yield for new products is very long. Therefore, if the design side could obtain more comprehensive process information and establish a technological bridge for automatic feedback and collaborative optimization, this process could be significantly simplified and accelerated, thereby improving yield and reducing costs.

[0082] This application provides a comprehensive tool that integrates process information feedback and design optimization tools. Process feedback information, combined with design optimization tools, enables targeted local optimization of the layout design, allowing the technologies of the two regions to automatically achieve collaborative optimization. By combining process and design information, the previously fragmented design and manufacturing technical regions are connected. Furthermore, the technology allows both sides to automatically complete optimization through programs, significantly reducing labor costs and barriers to technology use.

[0083] This method provides a new direction for exploring DTCO in the field of computational lithography, accelerating the interaction of process information and design information throughout the entire chain from design to manufacturing, forming a synchronous optimization mode of mutual feedback, overcoming the bottleneck of lithography process, and ultimately achieving the goal of improving yield and reliability.

[0084] This application provides a method for adjusting a design layout. First, clustering is performed based on the distribution density of each defective pixel in the overall defective pixel information database on the original design layout, dividing each defective pixel into multiple local design layouts. Then, the local design layouts are adjusted to obtain the target local design layout, resulting in the final target design layout. The proposed solution, by clustering the distribution density of each defective pixel on the original design layout, can quickly determine the local design layout where the defective pixel is located, and then modify the graphics at the corresponding location, with less time consumption. Furthermore, because only local design layouts need to be adjusted, compared to adjusting the entire design layout, this solution consumes fewer computational resources and time, thus meeting actual production needs.

[0085] The above embodiments mention that photolithography simulation is needed based on the original design layout to determine the corresponding overall defect information database. However, in practical applications, the initial overall defect information database determined by photolithography simulation based on the original design layout contains some defects that cannot be eliminated by modifying the linewidth. Therefore, it is necessary to filter out these defects and retain only the target defects. That is, target defects are selected from the initial overall defect information database, and the target defects are those that can be eliminated by modifying the linewidth. Then, each target defect is determined as the overall defect information database.

[0086] This application embodiment only processes the distance between the edges of local graphics. By modifying the line width of the graphics, it meets the optimization requirements of the design end, thereby avoiding invalid optimization adjustments to other bad points and saving computing resources and time.

[0087] In practical applications, a corresponding scheme can be selected to determine the initial overall defect information database according to actual needs. This application provides a specific implementation scheme, which determines the initial overall defect information database based on photolithography simulation of the original design layout, including:

[0088] Based on photolithography simulation tools, the original design layout is simulated to obtain the overall photoresist development outline information; the overall photoresist development outline information is then checked for photolithography rules to obtain an initial overall defect information database.

[0089] The embodiments of this application obtain the resist development contour information through simulation, and then perform photolithography rule inspection, which can efficiently determine the database of bad pixel information.

[0090] As mentioned in the above embodiments, directly reusing the information from the overall bad pixel information database (N1) in the aforementioned steps may lead to errors when determining the local bad pixel information database. Therefore, in this embodiment, instead of reusing the information, a new local bad pixel information database corresponding to the local design layout is determined. Specifically, the local design layout is first simulated using a photolithography simulation tool to obtain local photoresist development contour information; then, photolithography rule checks are performed on the local photoresist development contour information to obtain the local bad pixel information database.

[0091] In this embodiment, after identifying a local design layout with defective pixels, a new local defective pixel information database is determined for the local design layout, instead of reusing information from the overall defective pixel information database, thereby avoiding errors caused by using information from the overall defective pixel information database.

[0092] As mentioned in the above embodiments, the adjustment methods for different categories of bad pixels are different. This embodiment provides a specific solution: based on a local bad pixel information database, the local design layout is adjusted to eliminate each bad pixel in the local bad pixel information database and obtain the target local design layout, including:

[0093] First, determine the target edge line of the defective pixel to be eliminated in the local design layout. Then, determine the defective pixel category. Finally, based on the defective pixel category, move the target edge line to obtain the target local design layout.

[0094] Figure 4(a) shows the graphic corresponding to the pinch category defect. As shown in Figure 4(a), for the pinch category defect, there is a risk of breakage due to necking. In this case, it is necessary to increase the line width and move it towards the space on both sides of the graphic (i.e., the distance between the graphics). Figure 4(b) shows the graphic corresponding to the bridge category defect. As shown in Figure 4(b), the bridge defect is due to insufficient space, and there is a risk of the two graphics sticking together. It is necessary to increase the space, that is, to reduce the line width and move the two target edges inward into the graphic.

[0095] The embodiments of this application move the target edge line according to the corresponding movement method based on the corresponding defect category, which can improve optimization efficiency.

[0096] In practical applications, since the distance the edge of a graphic moves and the corresponding distance the contour moves are not necessarily equal, when adjusting the line width of a graphic, a combination of one-step movement (the movement distance is the difference between the bad value and the expected value) and setting a step size to iteratively optimize the movement can be used. Figure 5 This illustration shows a flowchart of adjusting graphic line width according to an embodiment of this application; as shown Figure 5 As shown, the steps include: S501 to S505.

[0097] S501: Obtain the defect size value and expected value of the defective pixel to be eliminated.

[0098] The defect size is the distance between the two edges that caused the defect. If the distance between the two edges that caused the defect is the expected value, the defect to be eliminated is eliminated.

[0099] S502: Determine the difference between the defect size value and the expected value.

[0100] S503: Based on the defect category of the defective pixel to be eliminated, shift the target edge by the difference to obtain the first corrected layout.

[0101] S504: Determine whether the first revised layout meets the iteration stopping condition; if the first revised layout does not meet the iteration stopping condition, proceed to S505; if the first revised layout meets the iteration stopping condition, proceed to S507.

[0102] S505: Move the target edge line by a preset step size to obtain the second corrected layout;

[0103] S506: Determine the second revised version as the new first revised version and return to S504.

[0104] S507: Iteration stops, and the target local design layout is obtained.

[0105] The above iteration stopping conditions include the elimination of the bad points to be eliminated or the layout design rules restricting the continued movement of the target edge.

[0106] Since the distance the edges of a graphic move and the corresponding distance the contour moves are not necessarily equal, and the moving distance is limited due to design rules, this embodiment first moves the distance corresponding to the difference between the defective point size value and the expected value when moving the target edge, and then iterates repeatedly to move it, thereby efficiently and accurately optimizing the graphic.

[0107] The scheme in the above embodiments only moves the target edge to optimize the line width, and the optimization effect on the design layout is limited. Therefore, in practical applications, after obtaining the target design layout, the moving direction and moving distance of the target edge can be determined, and the target design layout can be further adjusted based on the initial overall bad pixel information database (specifically, the initial overall bad pixel information database can be used), the moving direction and moving distance of the target edge.

[0108] Since the graphic optimization in the above scheme mainly considers the line width in the design rules, this optimization is limited. Therefore, the final design optimization tool on the design side needs to further optimize the design layout based on more comprehensive DRC rules and other physical design constraints.

[0109] To address the aforementioned technical problems, embodiments of this application also provide an apparatus for adjusting a design layout. Figure 6 A schematic diagram of the structure of the apparatus for adjusting the design layout provided in an embodiment of this application is shown. Figure 6 As shown, the device includes the following modules:

[0110] The first determining module 601 is used to perform photolithography simulation based on the original design layout and determine the corresponding overall bad pixel information database.

[0111] Clustering module 602 is used to perform clustering operations based on the distribution density of each defective point in the overall defective point information database on the original design layout, and to divide each defective point into multiple local design layouts.

[0112] The second determining module 603 is used to determine the local defect information database corresponding to the local design layout;

[0113] The adjustment module 604 is used to adjust the local design layout based on the local bad pixel information database to eliminate each bad pixel in the local bad pixel information database and obtain the target local design layout.

[0114] The merging module 605 is used to merge the target local design layout with the unprocessed areas of the original design layout other than the local design layout to obtain the target design layout.

[0115] In some embodiments, the first determining module is specifically used for:

[0116] Photolithography simulation was performed based on the original design layout to determine the initial overall defect information database;

[0117] Select target bad pixels from the initial overall bad pixel information database; target bad pixels are those that can be eliminated by modifying the line width.

[0118] Each target defect is identified as part of the overall defect information database.

[0119] In some embodiments, the first determining module is specifically used to: simulate the original design layout based on a photolithography simulation tool to obtain overall photoresist development outline information;

[0120] The overall photoresist development outline information is checked for lithographic rules to obtain an initial overall defect information database.

[0121] In some embodiments, the second determining module is specifically used for:

[0122] Based on photolithography simulation tools, the local design layout is simulated to obtain local photoresist development outline information;

[0123] Photolithography rules are checked on the local photoresist development contour information to obtain a database of local defective pixel information.

[0124] In some embodiments, the adjustment module is specifically used for:

[0125] Determine the target edge of the defect to be eliminated in the local design layout;

[0126] Determine the category of the defective pixels to be eliminated;

[0127] Based on the defect category of the defective pixels to be eliminated, the target edge is moved to obtain the target local design layout.

[0128] In some embodiments, the adjustment module is specifically used for:

[0129] Obtain the defect size value and expected value of the defect to be eliminated; the defect size value is the distance between the two edges that caused the defect, and if the distance between the two edges that caused the defect is the expected value, the defect to be eliminated is eliminated;

[0130] Determine the difference between the defective pixel size and the expected value;

[0131] Based on the defect category of the defect to be eliminated, the target edge is shifted by the difference to obtain the first corrected layout;

[0132] Determine whether the first revised layout meets the iteration stopping condition;

[0133] If the first revised layout does not meet the iteration stopping condition, the target edge is moved by a preset step size to obtain the second revised layout.

[0134] The second revised layout is determined as the new first revised layout, and the process returns to the step of determining whether the first revised layout meets the iteration stopping condition, until the first revised layout meets the iteration stopping condition; the iteration stopping condition includes the elimination of the bad points to be eliminated or the layout design rules restrict the continued movement of the target edge.

[0135] In some embodiments, the apparatus for adjusting the design layout further includes: a third determining module, configured to determine the moving direction and moving distance of the target edge after merging the target partial design layout with the unprocessed area other than the partial design layout in the original design layout to obtain the target design layout;

[0136] The adjustment module is also used to adjust the target design layout based on the initial overall bad spot information database, the movement direction and movement distance of the target edge.

[0137] The apparatus provided in this application is the same as the method in the above embodiments, and therefore both have the same embodiments and beneficial effects, which will not be repeated here.

[0138] Figure 7 A schematic diagram of the hardware structure of a device with an adjusted design layout provided in an embodiment of this application is shown. For example... Figure 7 As shown, the device for adjusting the design layout may include a processor 701 and a memory 702 storing computer program instructions.

[0139] Specifically, the processor 701 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0140] Memory 702 may include mass storage for data or instructions. For example, and not limitingly, memory 702 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 702 may include removable or non-removable (or fixed) media. Where appropriate, memory 702 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 702 is non-volatile solid-state memory.

[0141] Memory 702 may include read-only memory (ROM), random access memory (RAM), disk storage media device, optical storage media device, flash memory device, electrical, optical, or other physical / tangible memory storage device. Therefore, typically, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to one aspect of this disclosure.

[0142] The processor 701 reads and executes computer program instructions stored in the memory 702 to implement any of the methods for adjusting the design layout in the above embodiments.

[0143] In one example, the device for adjusting the design layout may also include a communication interface 703 and a bus 704. The processor 701, memory 702, and communication interface 703 are connected via the bus 704 and communicate with each other.

[0144] The communication interface 703 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0145] Bus 704 includes hardware, software, or both, that couples components of a device that shapes a design layout together. For example, and not limitingly, the bus may include an Accelerated Graphical Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 704 may include one or more buses. Although specific buses are described and illustrated in the embodiments of this application, this application considers any suitable bus or interconnection.

[0146] Furthermore, in conjunction with the method for adjusting the design layout in the above embodiments, this application embodiment can provide a computer storage medium for implementation. This computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the methods for adjusting the design layout in the above embodiments.

[0147] This application also provides a computer program product, including a computer program that, when executed, implements any of the methods for adjusting the design layout described in the above embodiments.

[0148] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0149] The functional blocks shown in the structural diagram above can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, ASICs, appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on machine-readable media or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable media" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, compact disc read-only memory (CD-ROM), optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0150] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0151] The foregoing flowcharts and / or block diagrams describing a method, apparatus, device, medium, and product for adjusting a design layout according to embodiments of the present disclosure have described various aspects of the present disclosure. It should be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowcharts and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by dedicated hardware performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0152] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for adjusting a design layout, characterized in that, include: Photolithography simulation is performed based on the original design layout to determine the corresponding overall defect information database; Based on the distribution density of each defective point in the overall defective point information database on the original design layout, a clustering operation is performed to divide each defective point into multiple local design layouts. Determine the local defect information database corresponding to the local design layout; Based on the local defect information database, the local design layout is adjusted to eliminate each defect in the local defect information database, thereby obtaining the target local design layout; The target partial design layout is merged with the unprocessed areas of the original design layout except for the partial design layout to obtain the target design layout; The step of adjusting the local design layout based on the local defect information database to eliminate each defect in the local defect information database and obtain a target local design layout includes: determining the target edge line of the defect to be eliminated in the local design layout; determining the defect category of the defect to be eliminated; and moving the target edge line based on the defect category of the defect to be eliminated to obtain the target local design layout.

2. The method for adjusting the design layout according to claim 1, characterized in that, The process of performing photolithography simulation based on the original design layout to determine the corresponding overall defect information database includes: Photolithography simulation was performed based on the original design layout to determine the initial overall defect information database; Select target bad points from the initial overall bad point information database; the target bad points are those that can be eliminated by modifying the line width; Each of the target bad pixels is determined as part of the overall bad pixel information database.

3. The method for adjusting the design layout according to claim 2, characterized in that, The process of performing photolithography simulation based on the original design layout to determine the initial overall defect information database includes: Based on photolithography simulation tools, the original design layout is simulated to obtain the overall photoresist development outline information; The overall photoresist development contour information is subjected to photolithography rule checks to obtain the initial overall defect information database.

4. The method for adjusting the design layout according to claim 1, characterized in that, The process of determining the local defect information database corresponding to the local design layout includes: Based on photolithography simulation tools, the local design layout is simulated to obtain local photoresist development outline information; The local photoresist development contour information is subjected to photolithography rule inspection to obtain the local defect information database.

5. The method for adjusting the design layout according to claim 1, characterized in that, The step of moving the target edge based on the defect category of the defect to be eliminated to obtain the target local design layout includes: Obtain the defect size value and expected value of the defect to be eliminated; the defect size value is the distance between the two edges that caused the defect, and when the distance between the two edges that caused the defect is the expected value, the defect to be eliminated is eliminated; Determine the difference between the defect size value and the expected value; Based on the defect category of the defect to be eliminated, the target edge is shifted by the difference to obtain the first corrected layout. Determine whether the first revised layout meets the iteration stop condition; If the first revised layout does not meet the iteration stopping condition, the target edge is moved by a preset step size to obtain the second revised layout. The second revised layout is determined as the new first revised layout, and the step of determining whether the first revised layout meets the iteration stopping condition is returned until the first revised layout meets the iteration stopping condition; the iteration stopping condition includes the elimination of the bad points to be eliminated or the layout design rules restrict the continued movement of the target edge.

6. The method for adjusting the design layout according to claim 1 or 5, characterized in that, After merging the target partial design layout with the unprocessed areas of the original design layout (excluding the partial design layout) to obtain the target design layout, the method further includes: Determine the direction and distance of movement of the target edge; Based on the overall defect information database, the moving direction and moving distance of the target edge, the target design layout is adjusted.

7. A device for adjusting a design layout, characterized in that, include: Processor and memory storing computer program instructions; When the processor executes the computer program instructions, it implements the method for adjusting the design layout as described in any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, implement the method for adjusting the design layout as described in any one of claims 1 to 6.

9. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device performs the method of adjusting the design layout as described in any one of claims 1 to 6.

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