Verification method and device of design rule inspection tool, equipment, medium and product

Abstract

The invention discloses a verification method and device for a design rule inspection tool, equipment, a medium and a product, and relates to the technical field of chip layout inspection. The verification method for the design rule checking tool comprises the steps that according to tool attributes of the chip layout design rule checking tool, test layout hierarchies corresponding to the tool attributes are constructed, and the tool attributes are used for representing features of chip layout hierarchies which can be processed by the chip layout design rule checking tool; according to layout design parameters included in a layout design rule corresponding to the chip layout, multiple test cases corresponding to each layout design parameter under the test layout level are created, and the layout design rule is used for representing a mandatory specification set of design content of the chip layout; and respectively executing each test case through the chip layout design rule checking tool, and determining the tool reliability of the chip layout design rule checking tool.

Description

Technical Field

[0001] The present application belongs to the technical field of chip layout inspection, and in particular, relates to a verification method, device, equipment, medium and product of a design rule checking tool. Background Art

[0002] Before integrated circuit chips are mass-produced, layout checking tools are needed to perform design rule checking (DRC) on the chip layout. Only chip layouts that pass the design rule check can ensure the success of tape-out. In order to ensure the accuracy of the chip layout check results, the reliability of the layout checking tools needs to be verified in advance.

[0003] In the existing method, the reliability of the layout checking tool is verified based on the test cases which are manually input.

[0004] However, the types of test cases input manually are relatively single, and are prone to problems such as incomplete test types and low test coverage, resulting in poor verification reliability of layout checking tools. Summary of the invention

[0005] The embodiments of the present application provide a verification method, apparatus, device, medium and product of a design rule checking tool, which can improve the verification reliability of the design rule checking tool.

[0006] In one aspect of an embodiment of the present application, a verification method of a design rule checking tool is provided, comprising:

[0007] According to the tool attributes of the chip layout design rule checking tool, a test layout hierarchy corresponding to the tool attributes is constructed, wherein the tool attributes are used to characterize the characteristics of the chip layout hierarchy that can be processed by the chip layout design rule checking tool;

[0008] According to each layout design parameter included in the layout design rule corresponding to the chip layout, a plurality of test cases corresponding to each layout design parameter at the test layout level are created, wherein the layout design rule is used to represent a set of mandatory regulations for the design content of the chip layout;

[0009] Each test case is executed separately through the chip layout design rule checking tool to determine the tool reliability of the chip layout design rule checking tool.

[0010] In one aspect of an embodiment of the present application, a verification device for a design rule checking tool is provided, comprising:

[0011] A hierarchy construction module, used for constructing a test layout hierarchy corresponding to a tool attribute of a chip layout design rule checking tool according to the tool attribute of the tool, wherein the tool attribute is used for characterizing the characteristics of the chip layout hierarchy that can be processed by the chip layout design rule checking tool;

[0012] A use case creation module, used to create multiple test cases corresponding to each layout design parameter at the test layout level according to each layout design parameter included in the layout design rule corresponding to the chip layout, wherein the layout design rule is used to represent a set of mandatory regulations for the design content of the chip layout;

[0013] The use case execution module is used to execute each test case separately through the chip layout design rule checking tool to determine the tool reliability of the chip layout design rule checking tool.

[0014] In one aspect of an embodiment of the present application, an electronic device is provided, which includes: a memory and a program or instruction stored in the memory and executable on a processor, wherein when the program or instruction is executed by the processor, a verification method of a design rule checking tool as provided in any aspect of the above-mentioned embodiment of the present application is implemented.

[0015] In one aspect of an embodiment of the present application, a readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, a verification method of a design rule checking tool provided in any aspect of the above-mentioned embodiment of the present application is implemented.

[0016] In one aspect of an embodiment of the present application, a computer program product is provided. When instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes a verification method of a design rule checking tool provided in any aspect of the above-mentioned embodiment of the present application.

[0017] In the verification method of the design rule checking tool provided in the embodiment of the present application, first, according to the tool attributes of the chip layout design rule checking tool, a test layout hierarchy corresponding to the tool attributes is constructed, so that each chip layout hierarchy that the layout checking tool can be applied to is verified separately. At the same time, according to each layout design parameter included in the layout design rule corresponding to the chip layout, multiple test cases corresponding to each layout design parameter under the test layout hierarchy are created. Starting from the layout design rules of the chip layout, corresponding test cases are created for each layout design parameter involved in the layout design rules, so that each layout design parameter involved in the layout design rules is fully verified. In this way, the embodiment of the present application is fully verified by each chip layout hierarchy that the layout checking tool can be applied to, and each layout design parameter involved in the layout design rules. The function and performance of the layout checking tool are verified under the hierarchical structure of various features, avoiding the problems of incomplete test types and low test coverage, thereby improving the verification reliability of the layout checking tool. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 It is a flowchart of a verification method of a first design rule checking tool provided by an embodiment of the present application;

[0020] Figure 2 It is a flowchart of a verification method of a second design rule checking tool provided by an embodiment of the present application;

[0021] Figure 3 It is a structural schematic diagram of a verification device of a design rule checking tool provided by an embodiment of the present application;

[0022] Figure 4 It is a structural diagram of a verification device of a design rule checking tool provided in one embodiment of the present application. DETAILED DESCRIPTION

[0023] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0024] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0025] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application are in compliance with the relevant provisions of national laws and regulations.

[0026] It should be noted that in the embodiments of the present application, certain software, components, models and other existing solutions in the industry may be mentioned, and they should be regarded as exemplary. Their purpose is only to illustrate the feasibility of implementing the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.

[0027] The existing methods rely on manually inputting test cases to verify the reliability of the layout checking tool. However, the types of manually input test cases are relatively single, which may lead to problems such as incomplete test types and low test coverage, resulting in poor verification reliability of the layout checking tool.

[0028] The purpose of the present application is to provide a verification method, device, equipment, medium and product of a design rule checking tool. In the verification method of the design rule checking tool provided in the embodiment of the present application, first, according to the tool attributes of the chip layout design rule checking tool, a test layout hierarchy corresponding to the tool attributes is constructed, so that each chip layout hierarchy that the layout checking tool can be applied to is verified separately. At the same time, according to each layout design parameter included in the layout design rule corresponding to the chip layout, multiple test cases corresponding to each layout design parameter under the test layout hierarchy are created. Starting from the layout design rules of the chip layout, for each layout design parameter involved in the layout design rules, corresponding test cases are created respectively, so that each layout design parameter involved in the layout design rules is fully verified. In this way, the embodiment of the present application is fully verified by each chip layout hierarchy that the layout checking tool can be applied to, and each layout design parameter involved in the layout design rules. The function and performance of the layout checking tool are verified under the hierarchical structure of various features, avoiding the problem of incomplete test types and low test coverage, thereby improving the verification reliability of the layout checking tool.

[0029] The following describes specific embodiments of the verification method, device, equipment, medium and product of the design rule checking tool provided by the embodiments of the present application. First, the verification method of the design rule checking tool is introduced.

[0030] Figure 1 A flow chart of a verification method of a design rule checking tool is provided. The verification method of the design rule checking tool can be applied to a server. The verification method of the design rule checking tool can include the following S101 to S103.

[0031] S101, constructing a test layout hierarchy corresponding to the tool attributes of a chip layout design rule checking tool according to the tool attributes, wherein the tool attributes are used to characterize the features of the chip layout hierarchy that can be processed by the chip layout design rule checking tool.

[0032] In this embodiment, the tool attributes are used to reflect the chip layout hierarchy that the DRC tool can process. For example, the chip layout hierarchy may include orthogonally rotated chip units and non-orthogonally rotated chip units, chip units mirrored along the x-axis and chip units mirrored along the y-axis, and chip units with a scaling factor greater than 1 and chip units with a scaling factor less than 1.

[0033] The test layout level is used to characterize the chip layout level set to verify the DRC tool. For example, the test layout level can be all chip layout levels that the DRC tool can process, or can be part of the chip layout levels that the DRC tool can process.

[0034] As an example, the server analyzes the technical documentation and user manual of the DRC tool and lists all layout levels it supports, such as the maximum / minimum supported sizes, spacing rules, alignment requirements, etc.

[0035] Then, based on the above information, a series of test layout hierarchies are constructed in the electronic design automation software. Each test layout hierarchy should be specifically designed to highlight the performance of the DRC tool on a specific attribute. For example, one hierarchy may focus on testing minimum spacing rules, while another hierarchy focuses on testing alignment requirements.

[0036] S102, creating multiple test cases corresponding to each layout design parameter at the test layout level according to each layout design parameter included in the layout design rule corresponding to the chip layout, wherein the layout design rule is used to represent a set of mandatory regulations for the design content of the chip layout.

[0037] In this embodiment, the layout design rules are a set of mandatory regulations for the design content of the chip layout. For example, the layout design rules may include metal line width, spacing, via size, power grid requirements, etc.

[0038] As an example, the server designs multiple test cases in the constructed test layout hierarchy for each layout design parameter (such as line width and spacing) included in the layout design rules. For example, for line width rules, multiple metal line test cases with different widths can be created; for spacing rules, metal line pairs with different spacings can be designed.

[0039] At the same time, the server marks the expected DRC result for each test case, that is, whether the test case should trigger a DRC error.

[0040] S103, executing each test case respectively by using the chip layout design rule checking tool to determine the tool reliability of the chip layout design rule checking tool.

[0041] In this embodiment, the server uses a DRC tool to perform rule checking on each test case and records the DRC result of each test case.

[0042] The output of the DRC tool is then compared to the expected DRC results to check that the DRC tool correctly identified all violations and did not falsely report compliance.

[0043] Based on the comparison results, the accuracy (number of correctly identified violations / total number of violations) and false alarm rate (number of falsely reported compliances / total number of compliances) of the DRC tool are calculated. If the accuracy is high and the false alarm rate is low, the DRC tool is considered to have high reliability.

[0044] In the verification method of the design rule checking tool provided in the present embodiment, first, according to the tool attributes of the chip layout design rule checking tool, a test layout hierarchy corresponding to the tool attributes is constructed, so that each chip layout hierarchy applicable to the layout checking tool is verified separately in the future. At the same time, according to each layout design parameter included in the layout design rule corresponding to the chip layout, multiple test cases corresponding to each layout design parameter under the test layout hierarchy are created. Starting from the layout design rules of the chip layout, corresponding test cases are created for each layout design parameter involved in the layout design rules, so that each layout design parameter involved in the layout design rules is fully verified. In this way, the embodiment of the present application is fully verified by each chip layout hierarchy applicable to the layout checking tool, and each layout design parameter involved in the layout design rules. The function and performance of the layout checking tool are verified under the hierarchical structure of various features, avoiding the problems of incomplete test types and low test coverage, thereby improving the verification reliability of the layout checking tool.

[0045] As an optional embodiment, the multiple test cases are real test cases or extended test cases;

[0046] Real use cases are used to represent use cases actually obtained at the actual design end of the chip layout;

[0047] The extended use case is used to represent the use case that is generated by extending the layout design parameters included in the layout design rules.

[0048] In this embodiment, the server obtains real design data from the actual design end of the chip layout, including but not limited to the position, size, connection relationship, etc. of various layout elements (such as transistors, resistors, capacitors, etc.). These real design data are organized into real use cases for subsequent verification processes.

[0049] At the same time, according to the layout design parameters included in the layout design rules (such as minimum line width, minimum spacing, maximum density, etc.), a series of extended use cases are generated through the algorithm. These extended use cases cover possible design boundary conditions and abnormal situations, and are used to test the performance of the layout design under these extreme conditions.

[0050] Through this embodiment, the number and types of test cases are enriched according to real use cases and extended use cases, thereby enriching the test types of the DRC tool, improving the test coverage of the DRC tool, and further improving the verification reliability of the layout inspection tool.

[0051] As an optional embodiment, the plurality of test cases are extended test cases;

[0052] S102 may specifically include:

[0053] The following steps are executed repeatedly until all layout design parameters included in the layout design rules are traversed:

[0054] Obtaining a parameter value range corresponding to a target layout design parameter, where the target layout design parameter is any one of the layout design parameters;

[0055] The parameter values ​​of the target layout design parameters are set to multiple valid values ​​within the parameter value range in sequence, and the parameter values ​​of the reference layout design parameters are set to preset default values, so as to form multiple extended use cases corresponding to the target layout design parameters at the test layout level. The reference layout design parameters are the layout design parameters corresponding to the layout design rules except the target layout design parameters.

[0056] In this embodiment, the parameter value range covers all valid values ​​that the layout design parameter can take in actual design.

[0057] Specifically, the server performs the following steps respectively for each target layout design parameter included in the layout design rule:

[0058] First, a parameter value range corresponding to a target layout design parameter is obtained, and then within the parameter value range, the parameter value of the target layout design parameter is sequentially set to multiple valid values. This can be implemented programmatically, for example, using a loop structure to traverse all values ​​within the parameter value range.

[0059] At the same time, the parameter values ​​of each reference layout design parameter except the target layout design parameter in each layout design parameter corresponding to the layout design rule are set to preset default values. Among them, these default values ​​should be set based on actual design experience or standards to ensure the accuracy and effectiveness of the test.

[0060] According to the above settings, multiple extended use cases corresponding to the target layout design parameters at the test layout level are formed. Each extended use case includes a specific target layout design parameter value and a preset reference layout design parameter value.

[0061] For example, it is assumed that the layout design rule includes two layout design parameters: parameter A and parameter B. The value range of parameter A is 1 to 10, and the value range of parameter B is 5 to 20. The preset default values ​​are parameter A=5 and parameter B=10.

[0062] During the loop traversal process, parameter A is tested first. The value of parameter A is set to each valid value between 1 and 10, while the value of parameter B is kept at the preset default value of 10. In this way, 10 extended use cases for parameter A can be generated.

[0063] Then, test parameter B. Set the value of parameter B to each valid value between 5 and 20, while keeping the value of parameter A at the preset default value of 5. In this way, 16 extended use cases for parameter B can be generated.

[0064] Through this embodiment, for each layout design parameter included in the layout design rule, multiple extended use cases are created according to the corresponding parameter value range. In this way, the verification accuracy of the DRC tool for each layout design parameter in the layout design rule can be comprehensively evaluated, and the verification reliability of the layout checking tool can be improved.

[0065] As an optional embodiment, the plurality of extended use cases include a forward extended use case and a reverse extended use case, the forward test case is used to characterize an extended use case consisting of valid values ​​that satisfy the layout design rules, and the reverse test case is used to characterize an extended use case consisting of invalid values ​​that do not satisfy the layout design rules;

[0066] After obtaining the parameter value range corresponding to the target layout design parameter, the verification method of the design rule checking tool may further include:

[0067] The parameter values ​​of the target layout design parameters are sequentially set to multiple invalid values ​​that are not within the parameter value range, and the parameter values ​​of the reference layout design parameters are set to preset default values, so as to form multiple reverse extension use cases corresponding to the target layout design parameters at the test layout level;

[0068] The parameter values ​​of the target layout design parameters are sequentially set to multiple valid values ​​within the parameter value range, and the parameter values ​​of the reference layout design parameters are set to preset default values, so as to form multiple extended use cases corresponding to the target layout design parameters at the test layout level, which may specifically include:

[0069] The parameter values ​​of the target layout design parameters are sequentially set to multiple valid values ​​within the parameter value range, and the parameter values ​​of the reference layout design parameters are set to preset default values, thereby forming multiple positive expansion use cases corresponding to the target layout design parameters at the test layout level.

[0070] In this embodiment, in order to verify the behavior of the target layout design parameters when they do not comply with the rules, the server further constructs a reverse extension use case.

[0071] Specifically, after obtaining the parameter value range corresponding to the target layout design parameter, the server selects multiple invalid values ​​that are not within the parameter value range, wherein these invalid values ​​may be lower than the minimum value or higher than the maximum value.

[0072] Then, the parameter values ​​of the target layout design parameters are set to these invalid values ​​in turn, while keeping other reference layout design parameters as preset default values.

[0073] According to the above settings, multiple reverse extension use cases corresponding to the target layout design parameters are constructed at the test layout level.

[0074] Through this embodiment, forward expansion use cases and reverse expansion use cases are constructed to fully cover the value ranges of each target layout design parameter. At the same time, according to the forward expansion use cases and reverse expansion use cases, it is easy to identify the false positive / missing negative problems of the DRC tool. In this way, this embodiment can improve the integrity and accuracy of DRC verification.

[0075] As an optional embodiment, the multiple extended use cases include a first extended use case and a second extended use case;

[0076] The first extended use case is used to characterize an extended use case corresponding to a command for generating a layout element corresponding to a layout design parameter;

[0077] The second extended use case is used to characterize the extended use case corresponding to the command for filtering out layout elements corresponding to the layout design parameters.

[0078] In this embodiment, the first extended use case is an extended use case of the generate command, and the generate command is used to generate or produce data, files or rules related to layout design.

[0079] The first extended use case is an extended use case of the filter command. The filter command is used to filter, screen or check the layout design to comply with specific design rules.

[0080] Through this embodiment, the first extended use case and the second extended use case are constructed to fully cover the test cases corresponding to various commands. In this way, this embodiment can improve the integrity and accuracy of DRC verification by covering the test cases corresponding to various commands.

[0081] As an optional embodiment, S103 may specifically include:

[0082] Execute each test case respectively through the chip layout design rule checking tool to obtain the test results corresponding to each test case;

[0083] Compare each test result with the expected result corresponding to the test case to determine whether each test result meets the test expectation;

[0084] The tool reliability of the chip layout design rule checking tool is determined based on the number of test results that meet the test expectations and the number of test results that do not meet the test expectations.

[0085] In this embodiment, the server uses the DRC tool to execute each test case separately. The DRC tool will automatically analyze the layout design in the test case and check it according to the built-in design rule library. After the check is completed, the tool will generate the test results corresponding to each test case.

[0086] The server then compares the test results of each test case with the expected results. If the test results are consistent with the expected results, the test case is considered to have passed the test; if the test results are inconsistent with the expected results, the test case is considered to have failed the test and the specific differences are recorded.

[0087] Finally, count the number of test results that meet the test expectations and the number of test results that do not meet the test expectations. Based on the statistical results, calculate the reliability indicators of the tool, such as pass rate, error rate, etc.

[0088] As an example, the server can also automatically send the test results corresponding to each test case to a preset email address to facilitate users to view the verification results of the chip layout design rule checking tool.

[0089] Through this embodiment, each test case is executed separately using the chip layout design rule checking tool, so that the reliability of the chip layout design rule checking tool can be automatically tested, thereby improving the verification reliability and verification efficiency of the layout checking tool.

[0090] As an optional embodiment, Figure 2 As shown, after S103, the verification method of the design rule checking tool may further include the following S201-S202:

[0091] S201, obtaining test running information of each test case during execution, where the test running information includes at least one of a test running state, a test running time, a test running memory peak value, and a number of logs generated during the running;

[0092] S202, collecting statistics on the test running information and test results of each test case, and generating a test report corresponding to the chip layout design rule checking tool.

[0093] In this embodiment, the test running status is used to indicate whether the DRC tool runs the test case normally. It records the execution status of the test case, such as being executed, executed successfully, executed failed, etc. This helps developers understand the execution progress and results of the test case.

[0094] Test run time is used to characterize the time information consumed by the DRC tool during the test case execution process. It records the total time from the start to the end of the test case execution. This helps to evaluate the execution efficiency and performance of the tool.

[0095] Test Run Memory Peak is used to characterize the peak memory information used by the DRC tool during the test case execution process. It records the peak memory occupied by the test case during execution. This helps to understand the tool's demand for memory resources and usage.

[0096] The number of logs generated during the run is used to represent the number of log lines generated by the DRC tool during the test case run. It records the number of log lines generated during the test case execution. This helps developers understand the execution details and potential problems of the test case.

[0097] As an example, after obtaining the test running information and test results of each test case, the server collects statistics on the obtained test running information and test results and generates a detailed test report.

[0098] Through this embodiment, the test operation information of the test case during the execution process is fully obtained, and a detailed test report is generated. In this way, the test report will clearly show the execution status, performance and test results of each test case, thereby helping developers to better understand the performance and stability of the tool.

[0099] As an optional embodiment, after S202, the verification method of the design rule checking tool may further include:

[0100] Determine the test deviation value between the test running information of each test case and the preset benchmark running information according to the test report corresponding to the chip layout design rule checking tool;

[0101] When the test deviation value is greater than the preset deviation threshold, determining the test deviation cause of the test deviation value according to the test case corresponding to the test deviation value;

[0102] When the cause of the test deviation does not belong to the preset normal cause, a test abnormality prompt message is generated.

[0103] In this embodiment, the preset benchmark operation information is an ideal test operation state preset according to chip design specifications and performance requirements.

[0104] As an example, the server compares the test running information in the test report with the preset benchmark running information, and calculates the test deviation value of each test case through comparison, that is, the difference between the test running information of the actual test case and the preset benchmark running information.

[0105] Then, the calculated test deviation value is compared with a preset deviation threshold value. The preset deviation threshold value is set according to the tolerance range and performance requirements of the chip design and is used to determine whether the test deviation is within an acceptable range.

[0106] If the test deviation value is greater than the preset deviation threshold, it means that the test run result is significantly different from the expected result, and further analysis of the cause of the test deviation is required. Based on the test case corresponding to the test deviation value, combined with possible factors in the chip layout design and manufacturing process, such as process parameters, material properties, and layout layout, a comprehensive analysis is performed to determine the specific cause of the test deviation.

[0107] Compare the reasons for the test deviation obtained by analysis with the preset normal reasons. The preset normal reasons include some common and acceptable deviation reasons, such as process fluctuations, measurement errors, etc. If the reason for the test deviation does not belong to the preset normal reasons, it means that the test deviation is caused by abnormal factors.

[0108] If the reason for the test deviation does not belong to the preset normal reason, a test abnormality prompt message is generated. The test abnormality prompt message should include detailed information of the test case, the test deviation value, and the reason for the test deviation, so that relevant personnel can find the problem in time and take corresponding corrective measures.

[0109] Through this embodiment, the deviation value and deviation cause in the chip layout design rule checking tool test can be accurately and quickly determined, providing strong support for quality control in the chip design and manufacturing process. At the same time, by generating test abnormality prompt information, the efficiency of problem discovery and resolution is improved, which helps to improve the overall performance and reliability of the chip layout design rule checking tool.

[0110] Verification method based on design rule checking tool. Accordingly, the present application also provides a specific embodiment of a verification device of a design rule checking tool.

[0111] like Figure 3 As shown, the verification device 300 based on the design rule checking tool provided in the embodiment of the present application includes a hierarchy construction module 310 , a use case creation module 320 and a use case execution module 330 .

[0112] A hierarchy construction module 310, for constructing a test layout hierarchy corresponding to a tool attribute of a chip layout design rule checking tool according to the tool attribute of the chip layout design rule checking tool, wherein the tool attribute is used to characterize the characteristics of the chip layout hierarchy that can be processed by the chip layout design rule checking tool;

[0113] A test case creation module 320 is used to create a plurality of test cases corresponding to each layout design parameter at a test layout level according to each layout design parameter included in the layout design rule corresponding to the chip layout, wherein the layout design rule is used to represent a set of mandatory regulations for the design content of the chip layout;

[0114] The test case execution module 330 is used to execute each test case respectively through the chip layout design rule checking tool to determine the tool reliability of the chip layout design rule checking tool.

[0115] As an optional embodiment, the plurality of test cases are extended test cases;

[0116] The use case creation module 320 specifically includes the following units:

[0117] The loop execution unit is used to loop the following units until all layout design parameters included in the layout design rules are traversed:

[0118] A range acquisition unit, used to acquire a parameter value range corresponding to a target layout design parameter, where the target layout design parameter is any one of the layout design parameters;

[0119] A parameter value setting unit is used to set the parameter values ​​of the target layout design parameters to multiple valid values ​​within the parameter value range in sequence, and set the parameter values ​​of the reference layout design parameters to preset default values, thereby forming multiple extended use cases corresponding to the target layout design parameters at the test layout level. The reference layout design parameters are the layout design parameters corresponding to the layout design rules except the target layout design parameters.

[0120] As an optional embodiment, the plurality of extended use cases include a forward extended use case and a reverse extended use case, the forward test case is used to characterize an extended use case consisting of valid values ​​that satisfy the layout design rules, and the reverse test case is used to characterize an extended use case consisting of invalid values ​​that do not satisfy the layout design rules;

[0121] After obtaining the parameter value range corresponding to the target layout design parameter, the use case creation module 320 further includes the following units:

[0122] The parameter value setting unit is further used to sequentially set the parameter values ​​of the target layout design parameters to multiple invalid values ​​that do not belong to the parameter value range, and set the parameter values ​​of the reference layout design parameters to preset default values, so as to form multiple reverse expansion use cases corresponding to the target layout design parameters at the test layout level;

[0123] The parameter value setting unit is also used to set the parameter values ​​of the target layout design parameters to multiple valid values ​​within the parameter value range in sequence, and set the parameter values ​​of the reference layout design parameters to preset default values, thereby forming multiple positive expansion use cases corresponding to the target layout design parameters at the test layout level.

[0124] As an optional embodiment, the use case execution module 330 specifically includes the following units:

[0125] A test case execution unit, used to execute each test case respectively through a chip layout design rule checking tool to obtain a test result corresponding to each test case;

[0126] A result comparison unit is used to compare each test result with the expected result corresponding to the test case to determine whether each test result meets the test expectation;

[0127] The reliability determination unit is used to determine the tool reliability of the chip layout design rule checking tool according to the number of test results that meet the test expectations and the number of test results that do not meet the test expectations.

[0128] As an optional embodiment, after executing each test case respectively through the chip layout design rule checking tool to determine the tool reliability of the chip layout design rule checking tool, the verification device 300 based on the design rule checking tool may further include the following modules:

[0129] An information acquisition module is used to obtain the test running information of each test case during the execution process, and the test running information includes at least one of the test running status, the test running time, the test running memory peak value and the number of logs generated by the running;

[0130] The report generation module is used to collect statistics on the test running information and test results of each test case and generate a test report corresponding to the chip layout design rule checking tool.

[0131] As an optional embodiment, after collecting statistics on the test running information and test results of each test case and generating a test report corresponding to the chip layout design rule checking tool, the verification device 300 based on the design rule checking tool may further include the following modules:

[0132] A deviation value determination module, used to determine the test deviation value between the test running information of each test case and the preset benchmark running information according to the test report corresponding to the chip layout design rule checking tool;

[0133] A cause determination module, for determining a test deviation cause of the test deviation value according to a test case corresponding to the test deviation value when the test deviation value is greater than a preset deviation threshold;

[0134] The abnormal prompt module is used to generate test abnormal prompt information when the cause of the test deviation does not belong to the preset normal cause.

[0135] Verification method based on design rule checking tool. Accordingly, the present application also provides a specific embodiment of a verification device of a design rule checking tool.

[0136] Figure 4 A schematic diagram of the hardware structure of a verification device of a design rule checking tool provided in an embodiment of the present application is shown.

[0137] The verification apparatus of the design rule checking tool may include a processor 401 and a memory 402 storing computer program instructions.

[0138] Specifically, the processor 401 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0139] Memory 402 may include a large capacity memory for data or instructions. By way of example and not limitation, memory 402 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, memory 402 may include a removable or non-removable (or fixed) medium. In appropriate cases, memory 402 may be inside or outside of an integrated gateway disaster recovery device. In a specific embodiment, memory 402 is a non-volatile solid-state memory.

[0140] The processor 401 reads and executes the computer program instructions stored in the memory 402 to implement any one of the verification methods of the design rule checking tool in the above embodiments.

[0141] In one example, the verification device of the design rule checking tool may further include a communication interface 403 and a bus 410. Figure 4 As shown, the processor 401, the memory 402, and the communication interface 403 are connected via a bus 410 and communicate with each other.

[0142] The communication interface 403 is mainly used to implement communication between various modules, devices, layout units and / or equipment in the embodiments of the present application.

[0143] Bus 410 includes hardware, software or both, and the parts of the verification equipment of the design rule checking tool are coupled to each other.For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 410 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the application considers any suitable bus or interconnection.

[0144] In addition, in combination with the verification method of the design rule checking tool in the above embodiment, the embodiment of the present application can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, the verification method of any one of the design rule checking tools in the above embodiment is implemented.

[0145] In addition, in combination with the verification method of the design rule checking tool in the above-mentioned embodiments, the embodiments of the present application may provide a computer program product for implementation. When the instructions in the computer program product are executed by the processor of an electronic device, the electronic device executes the verification method of the design rule checking tool provided by any aspect of the above-mentioned embodiments of the present application.

[0146] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0147] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0148] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0149] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0150] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the system, module and layout unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A verification method for a design rule checking tool, characterized in that: include: According to the tool attributes of the chip layout design rule checking tool, constructing a test layout hierarchy corresponding to the tool attributes, wherein the tool attributes are used to characterize the features of the chip layout hierarchy that can be processed by the chip layout design rule checking tool; According to each layout design parameter included in the layout design rule corresponding to the chip layout, a plurality of test cases corresponding to each of the layout design parameters at the test layout level are created, wherein the layout design rule is used to represent a set of mandatory regulations for the design content of the chip layout; The chip layout design rule checking tool is used to execute each of the test cases to determine the tool reliability of the chip layout design rule checking tool.

2. The method according to claim 1, characterized in that The multiple test cases are real test cases or extended test cases; The real use case is used to represent the use case actually obtained at the actual design end of the chip layout; The extended use case is used to characterize the use case generated by extension according to each layout design parameter included in the layout design rule.

3. The method according to claim 2, characterized in that The multiple test cases are the extended test cases; The step of creating, according to each layout design parameter included in the layout design rule corresponding to the chip layout, a plurality of test cases corresponding to each of the layout design parameters at the test layout level, comprises: The following steps are executed in a loop until all the layout design parameters included in the layout design rules are traversed: Obtaining a parameter value range corresponding to a target layout design parameter, wherein the target layout design parameter is any one of the layout design parameters; The parameter values ​​of the target layout design parameters are sequentially set to multiple valid values ​​within the parameter value range, and the parameter values ​​of the reference layout design parameters are set to preset default values, thereby forming multiple extended use cases corresponding to the target layout design parameters under the test layout level, and the reference layout design parameters are the layout design parameters corresponding to the layout design rules except the target layout design parameters.

4. The method according to claim 3, characterized in that The multiple extended use cases include forward extended use cases and reverse extended use cases, the forward test cases are used to characterize extended use cases consisting of valid values ​​that satisfy the layout design rules, and the reverse test cases are used to characterize extended use cases consisting of invalid values ​​that do not satisfy the layout design rules; After obtaining the parameter value range corresponding to the target layout design parameter, the method further includes: The parameter values ​​of the target layout design parameters are sequentially set to multiple invalid values ​​that do not belong to the parameter value range, and the parameter values ​​of the reference layout design parameters are set to preset default values, so as to form multiple reverse extension use cases corresponding to the target layout design parameters at the test layout level; The parameter value of the target layout design parameter is sequentially set to a plurality of valid values ​​within the parameter value range, and the parameter value of the reference layout design parameter is set to a preset default value, so as to form a plurality of extended use cases corresponding to the target layout design parameter at the test layout level, including: The parameter values ​​of the target layout design parameters are sequentially set to multiple valid values ​​within the parameter value range, and the parameter values ​​of the reference layout design parameters are set to preset default values, thereby forming multiple positive expansion use cases corresponding to the target layout design parameters at the test layout level.

5. The method according to claim 2, characterized in that: The extended use case includes a first extended use case and a second extended use case; The first extended use case is used to characterize an extended use case corresponding to a command for generating a layout element corresponding to the layout design parameter; The second extended use case is used to characterize the extended use case corresponding to the command for filtering out the layout elements corresponding to the layout design parameters.

6. The method according to claim 1, characterized in that The method of executing each of the test cases by the chip layout design rule checking tool to determine the tool reliability of the chip layout design rule checking tool includes: Execute each of the test cases respectively through the chip layout design rule checking tool to obtain test results corresponding to each of the test cases; Compare each of the test results with the expected results corresponding to the test cases to determine whether each of the test results meets the test expectations; The tool reliability of the chip layout design rule checking tool is determined according to the number of test results that meet the test expectations and the number of test results that do not meet the test expectations.

7. The method according to any one of claims 1 to 6, characterized in that: After executing each of the test cases respectively by the chip layout design rule checking tool to determine the tool reliability of the chip layout design rule checking tool, the method further includes: Acquire test running information of each of the test cases during execution, wherein the test running information includes at least one of a test running state, a test running time, a test running memory peak value, and a number of logs generated by the running; The test running information and test results of each of the test cases are counted to generate a test report corresponding to the chip layout design rule checking tool.

8. The method according to claim 7, characterized in that After collecting statistics on the test running information and the test results of each test case and generating a test report corresponding to the chip layout design rule checking tool, the method further includes: Determine, according to the test report corresponding to the chip layout design rule checking tool, a test deviation value between the test running information of each of the test cases and the preset benchmark running information; In the case where the test deviation value is greater than a preset deviation threshold, determining a test deviation cause of the test deviation value according to the test case corresponding to the test deviation value; When the cause of the test deviation does not belong to the preset normal cause, a test abnormality prompt message is generated.

9. An electronic device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the verification method of the design rule checking tool according to any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the verification method of the design rule checking tool according to any one of claims 1 to 8 is implemented.

11. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the verification method of the design rule checking tool as described in any one of claims 1 to 8.

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