Time controller, display device and image data processing method

Abstract

A timing controller is disclosed, comprising: a clock frequency switching unit, configured to receive a control signal and, based on the control signal, generate a clock frequency switching signal after the effective display end time of the current image when it is determined that the vertical down blanking time of the current image is greater than the minimum vertical down blanking time; and a pixel clock signal generation unit, configured to receive the master clock signal and, when the vertical down blanking time of the current image is greater than the minimum vertical down blanking time, receive the clock frequency switching signal and, in response to the clock frequency switching signal, generate a pixel clock signal having a frequency K times that of the master clock signal, wherein 0 ≤ K < 1. A display device using the timing controller and a method for processing image data using the timing controller are also disclosed.

Description

TECHNICAL FIELD

[0001] The present application relates generally to a timing controller, and more particularly to a timing controller capable of reducing power consumption, a display device using the same, and a method of processing image data using the same. BACKGROUND

[0002] With the development of information technology, the importance of display devices, which are a medium for connecting users and information, is being emphasized. For example, the use of display devices such as liquid crystal display devices, organic light emitting display devices, plasma display devices, etc. is increasing.

[0003] In a conventional display device, the image frame rate output by an external host processor (such as a GPU) to a display panel fluctuates all the time due to the load of the host processor itself, and when the load of the host processor is high, the image frame rate output is low, and when the load of the host processor is low, the image frame rate output is high. When the refresh rate of the display panel does not match the image frame rate, phenomena such as screen freezing and tearing occur, thereby affecting the user experience.

[0004] The current technology for solving the mismatch between the image frame rate output by the host processor and the refresh rate of the display panel is mainly the VRR (Variable Refresh Rate) technology, which controls the image frame rate output by the host processor by stretching or compressing the V-blank time while keeping the effective display time constant. However, since the VRR technology only extends the V-blank time, when the image frame rate output by the host processor is low, the frequency of the pixel clock signal generated by the timing controller (TCON) of the display device is still the same as the frequency of the pixel clock signal generated by the timing controller of the display device when the host processor outputs the highest image frame rate, which significantly increases the useless power consumption of the timing controller. SUMMARY

[0005] In order to be able to solve the technical problems existing in the prior art, according to an embodiment of the present application, a timing controller capable of reducing power consumption, a display device using the same, and a method of processing image data using the same are provided.

[0006] According to an aspect of an embodiment of the present application, a timing controller receiving a main clock signal and a control signal of a current image from an external host processor, the timing controller comprising: a clock frequency switching unit configured to receive the control signal and generate a clock frequency down switching signal after an end of active display time of the current image in a case where a vertical blanking time of the current image is greater than a minimum vertical blanking time according to the control signal; and a pixel clock signal generating unit configured to receive the main clock signal and generate a pixel clock signal having a frequency of K times of a frequency of the main clock signal in response to the clock frequency down switching signal in a case where the vertical blanking time of the current image is greater than the minimum vertical blanking time.

[0007] In one example of the timing controller according to the above aspect, the clock frequency switching unit is further configured to generate a clock frequency up switching signal before a start of active display time of a next image in a case where the vertical blanking time of the current image is greater than the minimum vertical blanking time according to the control signal; and the pixel clock signal generating unit is further configured to receive the clock frequency up switching signal in a case where the vertical blanking time of the current image is greater than the minimum vertical blanking time and generate a pixel clock signal having a frequency of the main clock signal in response to the clock frequency up switching signal.

[0008] In one example of the timing controller according to the above aspect, the clock frequency switching unit is further configured to generate a clock frequency hold signal in a case where the vertical blanking time of the current image is equal to the minimum vertical blanking time according to the control signal; and the pixel clock signal generating unit is further configured to receive the clock frequency hold signal in a case where the vertical blanking time of the current image is equal to the minimum vertical blanking time and generate a pixel clock signal having a frequency of the main clock signal in response to the clock frequency hold signal.

[0009] In one example of the timing controller according to the above aspect, the timing controller further receives input pixel data of the current image from the external host processor, and the timing controller further comprises an image processing unit configured to generate a scan control signal, a data control signal and output pixel data of the current image according to the control signal, the input pixel data and the pixel clock signal having a frequency of the main clock signal.

[0010] In one example of the timing controller according to the above aspect, the K is 1 / 2 or 1 / 4 or 1 / 8 or 0.

[0011] According to another aspect of an embodiment of the present application, a display device comprises the timing controller according to the above aspect.

[0012] According to a further aspect of the embodiments of the present application, a method for processing image data is provided, which comprises: receiving a main clock signal and a control signal of a current image from an external host processor; determining, according to the control signal, that a vertical blanking time of the current image is greater than a minimum vertical blanking time; generating a clock frequency down switching signal after an end of active display time of the current image; and generating a pixel clock signal having a frequency of K times of a frequency of the main clock signal in response to the clock frequency down switching signal, where 0≤K<1.

[0013] In one example of the method for processing image data provided in the above aspect, the method further comprises: generating a clock frequency up switching signal before a start of active display time of a next image in the case that the vertical blanking time of the current image is greater than the minimum vertical blanking time; and generating a pixel clock signal having a frequency of the frequency of the main clock signal in response to the clock frequency up switching signal.

[0014] In one example of the method for processing image data provided in the above aspect, the method further comprises: determining, according to the control signal, that the vertical blanking time of the current image is equal to the minimum vertical blanking time, and generating a clock frequency maintaining signal; and generating a pixel clock signal having a frequency of the frequency of the main clock signal in response to the clock frequency maintaining signal.

[0015] In one example of the method for processing image data provided in the above aspect, the method further comprises: receiving input pixel data of the current image from the external host processor; and generating a scan control signal, a data control signal and output pixel data of the current image according to the control signal, the input pixel data and a pixel clock signal having a frequency of the frequency of the main clock signal.

[0016] Beneficial effects: the timing controller according to the embodiments of the present application generates a pixel clock signal having the same frequency as the main clock signal during the active display time of a frame of image, and generates a pixel clock signal having a frequency lower than the frequency of the main clock signal during the rest of time of the frame of image except the active display time (e.g. vertical blanking time and vertical blanking time), thus effectively reducing the power consumption of the timing controller. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and other aspects, features and advantages of embodiments of the present application will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a block diagram of a display device according to the embodiments of the present application;

[0019] Figure 2is a display state diagram of a display panel in a column direction according to an embodiment of the present invention;

[0020] Figure 3 is a block diagram of a timing controller according to an embodiment of the present invention;

[0021] Figure 4 is a flowchart of a processing method of image data according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following detailed description is provided to aid in understanding the present application. However, various changes and modifications to the application described herein will be apparent to those skilled in the art from the detailed description. Further, the description is not to be taken as limiting on the scope of the application. Moreover, for the sake of brevity, the description is not always provided with a full list of components describing the integration and / or combination of features that constitute the present application. Additionally, the description is not to be taken as limiting on the scope of the application.

[0023] The features described herein can be implemented in different forms and should not be construed as limited to the examples described herein. Rather, these examples are provided as illustrative of only a few of the many possible implementations of the methods, devices, and / or systems described herein, which implementations will be apparent to those skilled in the art from the disclosure.

[0024] As used herein, the term "and / or" includes any one of the associated listed items, as well as any combination of any two or more of the associated listed items.

[0025] The terminology used herein is for the purpose of describing various examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including" and "has" specify the presence of stated features, numbers, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, components, elements, and / or combinations thereof.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs when the same is read in light of the present disclosure. Unless otherwise explicitly defined herein, the terms (such as "comprises," "comprising," "includes," "including," and the like) are to be construed as incorporating by reference the broadest meaning given to such terms in the relevant art and are intended to be assigned the same meaning and to be equivalent to the term "comprising," as such terms are interpreted in the appended claims.

[0027] Also, in the description of the examples, detailed descriptions of well-known related structures or functions are omitted so as not to obscure the disclosure of the present application.

[0028] Figure 1is a block diagram of a display apparatus according to an embodiment of the present application.

[0029] Referring to Figure 1 The display apparatus 100 according to an embodiment of the present application can include a display panel 110 including a plurality of pixels PX, a scan driver 120 providing a scan signal SS to the plurality of pixels PX, a data driver 130 providing a data voltage VD to the plurality of pixels PX, and a timing controller 140 controlling the scan driver 120 and the data driver 130.

[0030] The display panel 110 can include a plurality of scan lines SL1 to SLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX (assuming that n and m are integers greater than or equal to 2). Each of the scan lines SL1 to SLn can extend in a first direction (e.g., a row direction), and each of the data lines DL1 to DLm can extend in a second direction (e.g., a column direction) intersecting the first direction. The scan lines SL1 to SLn and the data lines DL1 to DLm can be insulated from each other. The plurality of pixels PX can be arranged in regions where the scan lines SL1 to SLn and the data lines DL1 to DLm intersect.

[0031] In an embodiment, each of the plurality of pixels PX can include a switching transistor transmitting the data voltage VD in response to the scan signal SS, a storage capacitor storing the data voltage VD transmitted by the switching transistor, a driving transistor generating a driving current based on the data voltage VD stored in the storage capacitor, and a light emitting element emitting light based on the driving current generated by the driving transistor. For example, the light emitting element can include a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting element, and other similar light emitting elements.

[0032] The scan driver 120 can provide the scan signal SS to the plurality of pixels PX through the plurality of scan lines SL1 to SLn based on a scan control signal SCTRL received from the timing controller 140. In an embodiment, the scan driver 120 can sequentially provide the scan signal SS to the plurality of pixels PX in a row unit.

[0033] The data driver 130 can receive a data control signal DCTRL and output image data ODAT from the timing controller 140. The data driver 130 can provide the data voltage VD to the plurality of pixels PX through the plurality of data lines DL1 to DLm based on the data control signal DCTRL and the output image data ODAT.

[0034] The timing controller 140 can receive input image data IDAT, a main clock signal CLK, and a control signal CTRL from an external host processor. For example, the host processor can be an application processor ("AP"), a graphics processing unit ("GPU"), or a graphics card. In an embodiment, the input image data IDAT can be RGB image data including red image data, green image data, and blue image data. The main clock signal CLK is an external pixel clock signal provided by the external host processor. In addition, the control signal CTRL can include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an enable signal DE, etc., but is not limited thereto.

[0035] The timing controller 140 can generate a scan control signal SCTRL, a data control signal DCTRL, and output image data ODAT based on the input image data IDAT and the control signal CTRL. The timing controller 140 can control the operation of the scan driver 120 by providing the scan control signal SCTRL to the scan driver 120, and control the operation of the data driver 130 by providing the output image data ODAT and the data control signal DCTRL to the data driver 130.

[0036] Figure 2 A display state diagram of a display panel in a column direction according to an embodiment of the present application.

[0037] Referring to Figure 2 , the display panel 110 according to an embodiment of the present application includes, in a vertical direction (a column direction) when displaying one frame of a picture, mainly: a vertical synchronization area V1, a vertical upper inactive line area V2, an active display area AF, and a vertical lower inactive line area V3. Among them, during the display of one frame of a picture, the time occupied by the vertical synchronization area V1 and the vertical upper inactive line area V2 is a vertical upper blanking time T1; the time occupied by the vertical lower inactive line area V3 is a vertical lower blanking time T2; the active display area AF is the effective display of one frame of a picture, and the time it occupies is an effective display time T3, which is equal to the time experienced from an effective display start time T31 to an effective display end time T32.

[0038] Figure 3 is a block diagram of a timing controller according to an embodiment of the present application.

[0039] Referring to Figure 3 The timing controller 140 according to an embodiment of the present application can include a clock frequency switching unit 141, a pixel clock signal generation unit 142, and an image processing unit 143.

[0040] The clock frequency switching unit 141 can determine the vertical blanking time T2 of the corresponding current image based on the main clock signal CLK and the control signal CTRL (specifically, the horizontal synchronization signal Hsync and the enable signal DE in the control signal CTRL) input by the external host processor. The clock frequency switching unit 141 can compare the vertical blanking time T2 with the shortest vertical blanking time. The clock frequency switching unit 141 can generate the clock frequency down switching signal after the end of the active display time T32 of the corresponding current image in a case where it determines that the vertical blanking time T2 is greater than or equal to the shortest vertical blanking time.

[0041] Here, the shortest vertical blanking time refers to a case where the display panel 110 has the highest refresh rate (for example, 60 Hz), and when the external host processor inputs a signal corresponding to one frame of image to the timing controller 140 at a frame rate (for example, 60 Hz) corresponding to the highest refresh rate, the timing controller 140 controls the display panel 110 to display the one frame of image at the highest refresh rate according to the corresponding signal, and the vertical blanking time corresponding to the one frame of image is the shortest vertical blanking time.

[0042] Therefore, when the vertical blanking time T2 of a certain frame of image is less than the shortest vertical blanking time, it means that the external host processor inputs a signal corresponding to the certain frame of image to the timing controller 140 at a frame rate lower than the highest refresh rate. This is because, in the present embodiment, no matter what frame rate the external host processor inputs a signal corresponding to one frame of image to the timing controller 140, the timing controller 140 drives the display panel 110 to display the one frame of image at the highest refresh rate within the active display time T3 of the one frame of image. That is, no matter what frame rate the external host processor inputs a signal corresponding to one frame of image to the timing controller 140, the active display time T3 of these images is the same.

[0043] The pixel clock signal generation unit 142 can receive the main clock signal CLK input by the external host processor corresponding to the current image. In a case where the clock frequency switching unit 141 determines that the vertical blanking time T2 is greater than or equal to the shortest vertical blanking time, the pixel clock signal generation unit 142 can receive the clock frequency down switching signal from the clock frequency switching unit 141. The pixel clock signal generation unit 142 generates a pixel clock signal having a frequency K times the frequency of the main clock signal CLK in response to the clock frequency down switching signal, where 0≤K<1. For example, K can be 1 / 2 or 1 / 4 or 1 / 8, or even 0.

[0044] Further, in the case that the external host processor inputs a signal corresponding to a frame image to the timing controller 140 at any frame rate, in order to ensure that the timing controller 140 drives the display panel 110 to display all images with the same effective display time T3, in the case that the clock frequency switching unit 141 determines that the vertical blanking time T2 of the current image is greater than or equal to the shortest vertical blanking time, the clock frequency switching unit 141 generates a clock frequency up switching signal before the effective display time T31 of the next image; the pixel clock signal generating unit 142 can receive the clock frequency up switching signal from the clock frequency switching unit 141, and generate a pixel clock signal with a frequency of the frequency of the main clock signal CLK in response to the clock frequency up switching signal. That is, the frequency of the pixel clock signal generated by the pixel clock signal generating unit 142 within the effective display time of a frame image is the same as the frequency of the main clock signal CLK, while the frequency of the pixel clock signal generated by the pixel clock signal generating unit 142 in the remaining time (for example, the vertical blanking time T1 and the vertical blanking time T2) of a frame image other than the effective display time is lower than the frequency of the main clock signal CLK, so that the power consumption of the timing controller 140 can be effectively reduced.

[0045] The image processing unit 143 can generate the scan control signal SCTRL, the data control signal DCTRL and the output image data ODAT of the current image based on the control signal CTRL (the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the enable signal DE, etc.) corresponding to the current image input by the external host processor and the pixel clock signal with a frequency of the frequency of the main clock signal CLK provided by the pixel clock signal generating unit 142.

[0046] Figure 4 is a flowchart of a processing method of image data according to an embodiment of the present application.

[0047] Referring to Figure 4 In step S410, the main clock signal and the control signal of the current image are received from the external host processor.

[0048] In particular, referring to Figure 3 The clock frequency switching unit 141 can receive the main clock signal CLK and the control signal CTRL (in particular, the horizontal synchronization signal Hsync and the enable signal DE in the control signal CTRL) corresponding to the current image from the external host processor.

[0049] In step S420, it is determined according to the control signal that the vertical blanking time of the current image is greater than or equal to the shortest vertical blanking time.

[0050] In particular, referring to Figure 3The clock frequency switching unit 141 determines the vertical blanking time T2 of the current image based on the host processor inputted master clock signal CLK and control signal CTRL corresponding to the current image. The clock frequency switching unit 141 can compare the vertical blanking time T2 with the minimum vertical blanking time, thereby determining whether the vertical blanking time T2 is greater than the minimum vertical blanking time.

[0051] In step S430, the clock frequency down switching signal is generated after the effective display end time of the current image.

[0052] In detail, with reference to both Figure 3 The clock frequency switching unit 141 can generate the clock frequency down switching signal after the effective display end time T32 of the current image corresponding to the current image in the case that it determines that the vertical blanking time T2 is greater than or equal to the minimum vertical blanking time.

[0053] In step S440, the pixel clock signal with the frequency of K times of the frequency of the master clock signal is generated in response to the clock frequency down switching signal, where 0≤K<1.

[0054] In detail, with reference to both Figure 3 The pixel clock signal generating unit 142 can receive the master clock signal CLK corresponding to the current image inputted by the external host processor. In the case that the clock frequency switching unit 141 determines that the vertical blanking time T2 is greater than or equal to the minimum vertical blanking time, the pixel clock signal generating unit 142 can receive the clock frequency down switching signal from the clock frequency switching unit 141. The pixel clock signal generating unit 142 generates the pixel clock signal with the frequency of K times of the frequency of the master clock signal CLK in response to the clock frequency down switching signal, where 0≤K<1. For example, K can be 1 / 2 or 1 / 4 or 1 / 8, or even 0.

[0055] Of course, as another embodiment, the clock frequency switching unit 141 can generate the clock frequency keeping signal in the case that it determines that the vertical blanking time T2 is equal to the minimum vertical blanking time. The pixel clock signal generating unit 142 can receive the clock frequency keeping signal from the clock frequency switching unit 141, and generate the pixel clock signal with the frequency of the master clock signal in response to the clock frequency keeping signal.

[0056] Further, as another embodiment, in the case that the external host processor inputs a signal corresponding to one frame of image to the timing controller 140 at any frame rate, in order to ensure that the timing controller 140 drives the display panel 110 to display all images with the same effective display time T3, in the case that the clock frequency switching unit 141 determines that the vertical back porch time T2 of the current image is greater than or equal to the shortest vertical back porch time, the clock frequency switching unit 141 generates a clock frequency up switching signal before the effective display time T31 of the next image; the pixel clock signal generating unit 142 can receive the clock frequency up switching signal from the clock frequency switching unit 141, and generate a pixel clock signal with a frequency of the frequency of the main clock signal CLK in response to the clock frequency up switching signal.

[0057] That is, the frequency of the pixel clock signal generated by the pixel clock signal generating unit 142 within the effective display time of one frame of image is the same as the frequency of the main clock signal CLK, while the frequency of the pixel clock signal generated by the pixel clock signal generating unit 142 in the remaining time (e.g. the vertical back porch time T2 and the vertical back porch time T1) other than the effective display time of one frame of image is lower than the frequency of the main clock signal CLK, so that the power consumption of the timing controller 140 can be effectively reduced.

[0058] Further, in the case that the external host processor inputs a signal corresponding to one frame of image to the timing controller 140 at any frame rate, in order to ensure that the timing controller 140 drives the display panel 110 to display all images with the same effective display time T3, in the case that the clock frequency switching unit 141 determines that the vertical back porch time T2 of the current image is greater than or equal to the shortest vertical back porch time, the clock frequency switching unit 141 generates a clock frequency up switching signal before the effective display time T31 of the next image; the pixel clock signal generating unit 142 can receive the clock frequency up switching signal from the clock frequency switching unit 141, and generate a pixel clock signal with a frequency of the frequency of the main clock signal CLK in response to the clock frequency up switching signal. Figure 4 After the step S440 shown in the figure, the image data processing method according to the embodiment of the present application can further comprise: receiving input pixel data of the current image from the external host processor; generating scan control signal, data control signal and output pixel data of the current image according to the control signal, the input pixel data and the pixel clock signal with a frequency of the frequency of the main clock signal. Specifically, continuing to refer to the figure, the image processing unit 143 can generate scan control signal SCTRL, data control signal DCTRL and output image data ODAT of the current image based on the control signal CTRL (vertical synchronization signal Vsync, horizontal synchronization signal Hsync, enable signal DE, etc.) corresponding to the current image input by the external host processor and the pixel clock signal with a frequency of the frequency of the main clock signal CLK provided by the pixel clock signal generating unit 142. Figure 3 , the image processing unit 143 can generate scan control signal SCTRL, data control signal DCTRL and output image data ODAT of the current image based on the control signal CTRL (vertical synchronization signal Vsync, horizontal synchronization signal Hsync, enable signal DE, etc.) corresponding to the current image input by the external host processor and the pixel clock signal with a frequency of the frequency of the main clock signal CLK provided by the pixel clock signal generating unit 142.

[0059] In summary, the timing controller according to the embodiment of the present application generates a pixel clock signal with the same frequency as the frequency of the main clock signal within the effective display time of one frame of image, while generates a pixel clock signal with a frequency lower than the frequency of the main clock signal in the remaining time (e.g. the vertical back porch time and the vertical back porch time) other than the effective display time of one frame of image, so that the power consumption of the timing controller can be effectively reduced.

[0060] The specific embodiments of the present application have been described above in detail, although a number of modifications and variations thereto will be readily apparent to those skilled in the art. It is to be understood that the principles of the present application can be applied to other embodiments without departing from the spirit and scope of the present application as defined by the claims and their equivalents.

Claims

1. A timing controller, characterized in that, The timing controller receives the master clock signal and control signal of the current image from an external host processor, wherein the timing controller includes: A clock frequency switching unit is used to receive the control signal and, based on the control signal, generate a clock frequency switching signal after the effective display end time of the current image when it is determined that the vertical down blanking time of the current image is greater than the shortest vertical down blanking time. A pixel clock signal generation unit is configured to receive the master clock signal, and when the vertical down blanking time of the current image is greater than the shortest vertical down blanking time, receive the clock frequency down switching signal, and generate a pixel clock signal with a frequency that is K times the frequency of the master clock signal in response to the clock frequency down switching signal, wherein 0 ≤ K < 1.

2. The timing controller according to claim 1, characterized in that, The clock frequency switching unit is also used to generate a clock frequency switching signal before the effective display start time of the next image when the vertical down blanking time of the current image is greater than the shortest vertical down blanking time. The pixel clock signal generation unit is further configured to receive the clock frequency switching signal when the vertical down blanking time of the current image is greater than the shortest vertical down blanking time, and generate a pixel clock signal with the frequency of the master clock signal in response to the clock frequency switching signal.

3. The timing controller according to claim 1 or 2, characterized in that, The clock frequency switching unit is also used to generate a clock frequency hold signal according to the control signal when the vertical down blanking time of the current image is equal to the shortest vertical down blanking time. The pixel clock signal generation unit is further configured to receive the clock frequency hold signal when the vertical down blanking time of the current image is equal to the shortest vertical down blanking time, and generate a pixel clock signal with the frequency of the master clock signal in response to the clock frequency hold signal.

4. The timing controller according to claim 1 or 2, characterized in that, It also receives input pixel data of the current image from the external host processor, wherein the timing controller further includes: The image processing unit is configured to generate a scan control signal, a data control signal, and output pixel data for the current image based on the control signal, the input pixel data, and a pixel clock signal having the frequency of the master clock signal.

5. The timing controller according to claim 1, characterized in that, The K is 1 / 2, 1 / 4, 1 / 8, or 0.

6. A display device, characterized in that, Includes the timing controller as described in any one of claims 1 to 5.

7. A method for processing image data, characterized in that, The processing method includes: Receive the master clock signal and control signal of the current image from the external host processor; Based on the control signal, it is determined that the vertical down-blinding time of the current image is greater than the shortest vertical down-blinding time; A switching signal at a clock frequency is generated after the effective display end time of the current image; In response to the switching signal at the clock frequency, a pixel clock signal with a frequency that is K times the frequency of the master clock signal is generated, where 0 ≤ K < 1.

8. The processing method according to claim 7, characterized in that, The processing method further includes: If the vertical down blanking time of the current image is greater than the shortest vertical down blanking time, a clock frequency switching signal is generated before the effective display start time of the next image; A pixel clock signal with the frequency of the master clock signal is generated in response to the clock frequency switching signal.

9. The processing method according to claim 7 or 8, characterized in that, The processing method further includes: Based on the control signal, the vertical down blanking time of the current image is determined to be equal to the shortest vertical down blanking time, and a clock frequency hold signal is generated; In response to the clock frequency hold signal, a pixel clock signal with the frequency of the master clock signal is generated.

10. The processing method according to claim 7 or 8, characterized in that, The processing method further includes: Receive the input pixel data of the current image from the external host processor; The current image's scan control signal, data control signal, and output pixel data are generated based on the control signal, the input pixel data, and a pixel clock signal having the frequency of the master clock signal.

Images