Pixel circuit, display panel and driving method of pixel circuit

Abstract

The application relates to a pixel circuit, a display panel and a driving method of the pixel circuit, which comprises a driving transistor, a threshold compensation module, a first reset module and a compensation module. A first end of the compensation module is connected with a target node, and a second end of the compensation module is used for receiving a target signal. The target node comprises at least one of an intermediate node of the threshold compensation module and an intermediate node of the first reset module, and the target signal comprises a first target signal and a second target signal. In a blanking stage, the electric potential of the first target signal received by the second end of the compensation module is higher than the electric potential of the second target signal received by the second end of the compensation module in a holding stage. The pixel circuit can improve the display performance of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel circuit, a display panel, and a driving method for the pixel circuit. Background Technology

[0002] Display technology, as an important component of the information industry, has played a vital role in the development of information technology. With the advancement of display technology, display panels of various types, such as organic light-emitting diode (OLED) displays, have been widely adopted.

[0003] Currently, the display performance of the display panel is poor. Summary of the Invention

[0004] Therefore, it is necessary to provide a pixel circuit, a display panel, and a driving method for the pixel circuit, with the aim of improving the display performance of the display panel.

[0005] In a first aspect, embodiments of this application provide a pixel circuit, the pixel circuit comprising:

[0006] Drive transistors;

[0007] A threshold compensation module, wherein a first terminal of the threshold compensation module is connected to the first terminal of the driving transistor, a second terminal of the threshold compensation module is connected to the gate of the driving transistor, and a control terminal of the threshold compensation module is used to receive a first scan signal;

[0008] A first reset module, wherein a first terminal of the first reset module is connected to the gate of the driving transistor, a second terminal of the first reset module is used to receive a first reset signal, and a control terminal of the first reset module is used to receive a second scan signal;

[0009] A compensation module, wherein a first end of the compensation module is connected to a target node, and a second end of the compensation module is used to receive a target signal; wherein the target node includes at least one of the intermediate node of the threshold compensation module and the intermediate node of the first reset module, and the target signal includes a first target signal and a second target signal;

[0010] In the blanking phase, the potential of the first target signal received at the second terminal of the compensation module is higher than the potential of the second target signal received at the second terminal of the compensation module during the holding phase.

[0011] Secondly, embodiments of this application also provide a display panel, which includes the pixel circuit provided in the first aspect.

[0012] Thirdly, embodiments of this application also provide a driving method for a pixel circuit, applied to the pixel circuit provided in the first aspect; the method includes:

[0013] During the blanking phase, a first target signal is provided to the second end of the compensation module;

[0014] During the holding phase, a second target signal is provided to the second end of the compensation module;

[0015] Wherein, the potential of the first target signal is higher than the potential of the second target signal.

[0016] The pixel circuit provided in this application includes a driving transistor, a threshold compensation module, a first reset module, and a compensation module. The first terminal of the threshold compensation module is connected to the first electrode of the driving transistor, and the second terminal of the threshold compensation module is connected to the gate of the driving transistor. The control terminal of the threshold compensation module is used to receive a first scan signal. The first terminal of the first reset module is connected to the gate of the driving transistor, and the second terminal of the first reset module is used to receive a first reset signal. The control terminal of the first reset module is used to receive a second scan signal. The first terminal of the compensation module is connected to at least one of the intermediate nodes of the threshold compensation module and the first reset module. In this application, during the blanking phase, the pixel circuit controls the second terminal of the compensation module to receive a first target signal with a higher potential. During the holding phase, the second terminal of the compensation module receives a second target signal with a lower potential. This can raise the potential of the intermediate nodes of the threshold compensation module and / or the first reset module during the holding phase, preventing leakage from the gate of the driving transistor to the intermediate nodes of the threshold compensation module and the first reset module during the holding phase. This stabilizes the gate potential of the driving transistor, avoids flickering on the display panel, and improves the display performance of the display panel. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure of a pixel circuit in related technologies;

[0018] Figure 2 A schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application;

[0019] Figure 3 A schematic diagram of another pixel circuit structure provided in an embodiment of this application;

[0020] Figure 4 A schematic diagram of another pixel circuit provided in an embodiment of this application;

[0021] Figure 5 A schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0022] Figure 6 A graph showing the ratio of the potential of a target signal to the display brightness value is provided in an embodiment of this application.

[0023] Figure 7 Another diagram showing the ratio of the potential of a target signal to the display brightness value provided in an embodiment of this application;

[0024] Figure 8 A schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0025] Figure 9 A schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0026] Figure 10 A schematic flowchart illustrating a pixel circuit driving method provided in an embodiment of this application;

[0027] Figure 11 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0028] Figure 12 A schematic diagram of the structure of the electronic device provided in the embodiments of this application.

[0029] Explanation of reference numerals in the attached figures: 11-threshold compensation module, 12-first reset module, 13-compensation module, 14-data writing module, 15-bias adjustment module, 16-second reset module, 17-first light emission control module, 18-second light emission control module. Detailed Implementation

[0030] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0033] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0034] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0035] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0036] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0037] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0038] As described in the background section, display panels in related technologies are prone to flickering when displaying at low frequencies. The inventors discovered the cause of this phenomenon; please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of the pixel circuit structure in the related technology. After the first reset process and data writing process in the refresh phase of the pixel circuit are completed, the scan signal SP1 and scan signal SP2 will switch from a low level state to a high level state, thereby coupling the potential of nodes N6 and N5 to high. In the subsequent blanking phase and holding phase, since the potential of nodes N6 and N5 is coupled to high, nodes N6 and N5 will leak current to node N1, i.e., the gate of driving transistor M3, causing the gate potential of driving transistor M3 to rise. As the holding phase continues, the brightness of the display panel will gradually decrease, resulting in the problem of flickering of the display panel.

[0039] Based on the aforementioned technical problems, the inventors discovered that the flickering phenomenon of the display panel can be improved by setting a compensation module at nodes N6 and / or N5. Based on this, the inventors further developed the technical solution of the embodiments of this application. Specifically, the pixel circuit provided in the embodiments of this application includes: a driving transistor; a threshold compensation module, the first end of which is connected to the first electrode of the driving transistor, the second end of which is connected to the gate of the driving transistor, and the control terminal of which is used to receive a first scan signal; a first reset module, the first end of which is connected to the gate of the driving transistor, the second end of which is used to receive a first reset signal, and the control terminal of which is used to receive a second scan signal; and a compensation module, the first end of which is connected to a target node, and the second end of which is used to receive a target signal; wherein the target node includes at least one of the intermediate nodes of the threshold compensation module and the intermediate nodes of the first reset module, and the target signal includes a first target signal and a second target signal; wherein, during the blanking phase, the potential of the first target signal received by the second end of the compensation module is higher than the potential of the second target signal received by the second end of the compensation module during the holding phase. By adopting the above technical solution, by setting a compensation module at the intermediate node of the threshold compensation module and / or the intermediate node of the first reset module in the pixel circuit, the potential of the first end of the compensation module can be raised during the blanking phase and the potential of the first end of the compensation module can be lowered during the holding phase, thereby avoiding leakage current from the intermediate node of the threshold compensation module and the intermediate node of the first reset module to the driving transistor, thus improving the flickering phenomenon of the display panel.

[0040] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] In one exemplary embodiment, please refer to Figure 2 This application provides a pixel circuit, which includes: a driving transistor T1, a threshold compensation module 11, a first reset module 12, and a compensation module 13.

[0042] The first terminal of the threshold compensation module 11 is connected to the first terminal of the driving transistor, and the second terminal of the threshold compensation module 11 is connected to the gate of the driving transistor. The control terminal of the threshold compensation module 11 is used to receive the first scan signal S1. The first terminal of the first reset module 12 is connected to the gate of the driving transistor T1, and the second terminal of the first reset module 12 is used to receive the first reset signal Vref1. The control terminal of the first reset module 12 is used to receive the second scan signal S2. The first terminal of the compensation module 13 is connected to the target node, and the second terminal of the compensation module 13 is used to receive the target signal SX. The target node includes at least one of the intermediate node N5 of the threshold compensation module 11 and the intermediate node N6 of the first reset module 12. The target signal SX includes a first target signal and a second target signal. During the blanking phase, the potential of the first target signal received by the second terminal of the compensation module 13 is higher than the potential of the second target signal received by the second terminal of the compensation module 13 during the holding phase.

[0043] In this embodiment, an LTPS type pixel circuit and a P-type transistor in the pixel circuit are used as examples for explanation. The pixel circuit of this application has a refresh stage, a blanking stage, and a holding stage. In the refresh stage, the first reset module 12 is turned on so that the first reset signal Vref1 resets the gate of the driving transistor T1. After that, the first reset module 12 is turned off, and the threshold compensation module 11 is turned on to perform threshold compensation on the gate of the driving transistor T1. It can be understood that after the first reset process and the threshold compensation process are completed, the second scan signal S2 and the first scan signal S1 will switch from low level to high level respectively to turn off the first reset module 12 and the threshold compensation module 11 respectively. When the second scan signal S2 switches from low level to high level, it will couple the potential of the intermediate node N6 of the first reset module 12 to high. Similarly, when the first scan signal S1 switches from low level to high level, it will couple the potential of the intermediate node N5 of the threshold compensation module 11 to high. Because the duration of the refresh phase in the pixel circuit is longer than the duration of the blanking phase, and the duration of the hold phase is longer than the duration of the refresh phase, when the potentials of the intermediate node N6 of the first reset module 12 and the intermediate node N5 of the threshold compensation module 11 are coupled high, leakage to the gate of the driving transistor T1 will mainly occur during the hold phase. In one example, the duration of the blanking phase is less than one-twentieth of the duration of the refresh phase, and the duration of the hold phase is greater than or equal to ten times the duration of the refresh phase.

[0044] Therefore, in this application, a compensation module 13 is provided at the intermediate node N5 of the threshold compensation module 11 and / or the intermediate node N6 of the first reset module 12. The compensation module 13 can be a capacitor. During the blanking phase of the pixel circuit, the potential of the intermediate node N5 and / or the intermediate node N6 is temporarily raised by the compensation module 13. Then, during the main leakage current phase of the pixel circuit, i.e., the holding phase, the potential of the intermediate node N5 of the threshold compensation module 11 and / or the intermediate node N6 of the first reset module 12 is lowered by the compensation module 13. This can prevent the intermediate nodes N5 and N6 from leaking current to the gate of the driving transistor T1, thus preventing the gate potential of the driving transistor T1 from continuously rising with the leakage current and thereby preventing the display panel from flickering.

[0045] The pixel circuit provided in this application includes a driving transistor, a threshold compensation module, a first reset module, and a compensation module. The first terminal of the threshold compensation module is connected to the first electrode of the driving transistor, and the second terminal of the threshold compensation module is connected to the gate of the driving transistor. The control terminal of the threshold compensation module is used to receive a first scan signal. The first terminal of the first reset module is connected to the gate of the driving transistor, and the second terminal of the first reset module is used to receive a first reset signal. The control terminal of the first reset module is used to receive a second scan signal. The first terminal of the compensation module is connected to at least one of the intermediate nodes of the threshold compensation module and the first reset module. In this application, during the blanking phase, the pixel circuit controls the second terminal of the compensation module to receive a first target signal with a higher potential. During the holding phase, the second terminal of the compensation module receives a second target signal with a lower potential. This can raise the potential of the intermediate nodes of the threshold compensation module and / or the first reset module during the holding phase, preventing leakage from the gate of the driving transistor to the intermediate nodes of the threshold compensation module and the first reset module during the holding phase. This stabilizes the gate potential of the driving transistor, avoids flickering on the display panel, and improves the display performance of the display panel.

[0046] In an exemplary embodiment, when the voltage difference between the gate voltage of the driving transistor T1 and the voltage of the first reset signal is greater than a preset threshold, the target node includes the intermediate node of the threshold compensation module or the intermediate node of the first reset module.

[0047] In applications, during the design phase of pixel circuits, relevant technical personnel will pre-determine the magnitudes of the scanning signals, reset signals, light emission control signals, data signals, etc., that the pixel circuits need to use. Therefore, during the design phase of pixel circuits, relevant technical personnel can determine how to design the compensation module 13 in the pixel circuits based on the magnitudes of the above signals.

[0048] In one example, a technician can determine how to design the compensation module 13 in the pixel circuit according to the formula Vn1-Vref1>1 / n*(VGH-VGL), where Vn1 is the gate voltage of the driving transistor, and the value of Vn1 is mainly determined by Vdata-Vth, where Vdata is the data signal, Vth is the threshold voltage of the driving transistor T1, Vref1 is the first reset signal, VGH is the high-level signal, VGL is the low-level signal, and 1 / n*(VGH-VGL) is the preset threshold, 0<1 / n<1. In application, the value of 1 / n can be determined by the technician as needed, as long as 0<1 / n<1 is satisfied.

[0049] When the voltage difference between the gate voltage Vn1 of the driving transistor T1 and the first reset signal Vref1 is greater than a preset threshold 1 / n*(VGH-VGL), the compensation module 13 can be set only at the intermediate node N5 of the threshold compensation module or the intermediate node N6 of the first reset module. This is because when the voltage difference between the gate voltage of the driving transistor T1 and the first reset signal is greater than the preset threshold, it indicates that the potential of the first reset signal Vref1 may be low. After the first reset process ends, the intermediate node N5 of the threshold compensation module will not be coupled very high. If the compensation module 13 is set at both the intermediate node N5 of the threshold compensation module and the intermediate node N6 of the first reset module, the potential of the intermediate node N6 of the first reset module will be lowered, and leakage may occur from the gate of the driving transistor T1 to the intermediate nodes N5 and N6. At this time, as the holding phase continues, the gate potential of the driving transistor T1 gradually decreases, the brightness of the light-emitting element gradually increases, and the display panel will also flicker. Therefore, in this application, when the voltage difference between the gate voltage of the driving transistor T1 and the voltage of the first reset signal is greater than a preset threshold, a compensation module 13 is set only at the intermediate node N5 of the threshold compensation module or the intermediate node N6 of the first reset module to alleviate the possible leakage of the gate of the driving transistor T1 to the intermediate node N5 and the intermediate node N6.

[0050] In one exemplary embodiment, please refer to Figure 3 and Figure 4 The compensation module 13 includes a first capacitor C1, the first end of which is connected to the target node, and the second end of which is used to receive the target signal SX; wherein the target node includes the intermediate node N5 of the threshold compensation module 11 or the intermediate node N6 of the first reset module 12.

[0051] In one example Figure 3 The diagram shows the pixel circuit when the target node is the intermediate node N6 of the first reset module. In another example, Figure 4This is a schematic diagram of the pixel circuit when the target node is the intermediate node N5 of the threshold compensation module. When the voltage difference between the gate voltage Vn1 of the driving transistor T1 and the first reset signal Vref1 is greater than the preset threshold 1 / n*(VGH-VGL), the first capacitor C1 can be set only at the intermediate node N5 of the threshold compensation module 11 or the intermediate node N6 of the first reset module 12 to pull down the potential of the intermediate node N5 or the intermediate node N6 during the holding phase, thereby avoiding leakage current from the intermediate node N5 or the intermediate node N6 to the gate of the driving transistor T1 and mitigating the possible leakage current from the gate of the driving transistor T1 to the intermediate nodes N5 and N6.

[0052] In an exemplary embodiment, when the voltage difference between the gate voltage of the driving transistor T1 and the voltage of the first reset signal Vref1 is less than or equal to a preset threshold, the target node includes the intermediate node of the threshold compensation module and the intermediate node of the first reset module.

[0053] It is understandable that when the voltage difference between the gate voltage Vn1 of the driving transistor T1 and the first reset signal Vref1 is less than or equal to the preset threshold 1 / n*(VGH-VGL), it indicates that the potential of the first reset signal Vref1 may be high. After the first reset process and the threshold compensation process are completed, the intermediate node N5 of the threshold compensation module and the intermediate node N6 of the first reset module will leak current to the gate of the driving transistor T1 due to high coupling. Therefore, the compensation module 13 can be set at the intermediate node N5 of the threshold compensation module 11 and the intermediate node N6 of the first reset module 12 at the same time.

[0054] In one exemplary embodiment, please refer to Figure 5 The compensation module includes a second capacitor C2 and a third capacitor C3. The target node includes an intermediate node N5 of the threshold compensation module 11 and an intermediate node N6 of the first reset module 12. The first end of the second capacitor C2 is connected to the intermediate node N5 of the threshold compensation module 11, and the second end of the second capacitor C2 is used to receive the target signal SX. The first end of the third capacitor C3 is connected to the intermediate node N6 of the first reset module 12, and the second end of the third capacitor C3 is used to receive the target signal SX.

[0055] In one example, when the voltage difference between the gate voltage Vn1 of the driving transistor T1 and the first reset signal Vref1 is less than or equal to a preset threshold 1 / n*(VGH-VGL), a second capacitor C2 can be set at the intermediate node N5 of the threshold compensation module 11, and a third capacitor C3 can be set at the intermediate node N6 of the first reset module 12. After the refresh phase ends, the potential of the intermediate node N5 is temporarily raised through the second capacitor C2 and the potential of the intermediate node N6 is temporarily raised through the third capacitor C3. Then, in the main leakage current phase of the pixel circuit, i.e., the holding phase, the potential of the intermediate node N5 is lowered through the second capacitor C2 and the potential of the intermediate node N6 is lowered through the third capacitor C3, so as to prevent the intermediate nodes N5 and N6 from leaking current to the gate of the driving transistor T1, thus preventing the gate potential of the driving transistor T1 from continuously rising with the leakage current, thereby preventing the display panel from flickering and improving the display performance of the display panel.

[0056] In an exemplary embodiment, the potential difference between the potential of the first target signal Va and the potential of the second target signal Vb is positively correlated with the display brightness value DBV of the pixel circuit.

[0057] In applications, as the Display Brightness Value (DBV) increases, the gate potential of the driving transistor T1 in the pixel circuit needs to be lower. It can be understood that the lower the gate potential of the driving transistor T1 in the pixel circuit, the easier it is for intermediate nodes N5 and N6 to leak current into the gate of the driving transistor T1, thus reducing the brightness of the display panel. Therefore, in this application, the higher the display brightness value DBV of the pixel circuit, the greater the potential difference (Va-Vb) between the potential of the first target signal Va and the potential of the second target signal Vb. Specifically, when the display brightness value DBV increases, the gate potential of the driving transistor T1 decreases, requiring a higher first target signal Va and a lower second target signal Vb; when the display brightness value DBV decreases, the gate potential of the driving transistor T1 increases, requiring a lower first target signal Va and a higher second target signal Vb.

[0058] In one exemplary embodiment, please refer to Figure 6 The potential of the first target signal Va is positively correlated with the display brightness value, while the potential of the second target signal Vb is negatively correlated with the display brightness value.

[0059] from Figure 6 As can be seen, the potential of the first target signal Va can be set to increase with the increase of the display brightness value, while the potential of the second target signal Vb can be set to decrease with the increase of the display brightness value, so as to ensure that the potential difference between the potential of the first target signal Va and the potential of the second target signal Vb is directly proportional to the display brightness value DBV of the pixel circuit.

[0060] In one exemplary embodiment, please refer to Figure 7 When the displayed brightness value DBV is less than the preset brightness threshold DBV~, the potential of the second target signal Vb is negatively correlated with the displayed brightness value. When the displayed brightness value is greater than or equal to the preset brightness threshold DBV~, the potential of the second target signal Vb remains unchanged. When the displayed brightness value DBV is greater than or equal to the preset brightness threshold DBV~, the rate of change of the potential of the first target signal Va is greater than the rate of change of the potential of the first target signal Va when the displayed brightness value DBV is less than the preset brightness threshold DBV~.

[0061] In another example, since the display panel's driver IC may not be able to provide excessively low voltage, the potentials of the first target signal Va and the second target signal Vb can change asynchronously. A preset brightness threshold DBV~ can be set. When the display brightness value DBV is less than the preset brightness threshold DBV~, the potential of the first target signal Va increases with the increase of the display brightness value, while the potential of the second target signal Vb decreases with the increase of the display brightness value, to ensure that the potential difference between the potentials of the first target signal Va and the second target signal Vb is proportional to the display brightness value DBV of the pixel circuit. When the display brightness value DBV is greater than or equal to the preset brightness threshold DBV~, the potential of the second target signal Vb can be kept constant, while the rate of change of the potential of the first target signal Va is increased, to maintain the proportional relationship between the potential difference between the potentials of the first target signal Va and the second target signal Vb and the display brightness value DBV of the pixel circuit.

[0062] In one exemplary embodiment, please continue to refer to Figures 2 to 5 The threshold compensation module 11 includes: a first threshold compensation transistor T2-1 and a second threshold compensation transistor T2-2.

[0063] The first terminal of the first threshold compensation transistor T2-1 is connected to the first terminal of the driving transistor T1, and the gate of the first threshold compensation transistor T2-1 is used to receive the first scan signal S1. The first terminal of the second threshold compensation transistor T2-2 is connected to the second terminal of the first threshold compensation transistor T2-1, and the second terminal of the second threshold compensation transistor T2-2 is connected to the gate of the driving transistor T1, and the gate of the second threshold compensation transistor T2-2 is used to receive the first scan signal S1. The intermediate node N5 of the threshold compensation module 11 is the second terminal of the first threshold compensation transistor T2-1.

[0064] In the application, the refresh stage of the pixel circuit may include a threshold compensation process. After the threshold compensation process is completed, the first scan signal S1 changes from low level to high level, which will couple the potential of the intermediate node N5 of the threshold compensation module 11 to high. By setting a compensation module 13 at the intermediate node N5 of the threshold compensation module 11, and by providing a first target signal Va to the second end of the compensation module 13 during the blanking stage and a second target signal Vb to the second end of the compensation module 13 during the holding stage, and controlling the potential difference between the potential of the first target signal Va and the potential of the second target signal Vb to be proportional to the display brightness value DBV of the pixel circuit, the leakage current from the intermediate node N5 of the threshold compensation module 11 to the gate of the driving transistor T1 can be suppressed. Moreover, regardless of the magnitude of the display brightness value DBV of the pixel circuit, the leakage current from the intermediate node N5 to the gate of the driving transistor T1 can be effectively suppressed, thereby improving the display performance of the display panel.

[0065] In one exemplary embodiment, please continue to refer to Figures 2 to 5 The first reset module 12 includes: a first A reset transistor T3-1 and a first B reset transistor T3-2.

[0066] The first terminal of the first reset transistor T3-1 is connected to the gate of the driving transistor T1. The gate of the first reset transistor T3-1 is used to receive the second scan signal S2. The first terminal of the first reset transistor T3-2 is connected to the second terminal of the first reset transistor T3-1. The second terminal of the first reset transistor T3-2 is used to receive the first reset signal Vref1, and the gate of the first reset transistor T3-2 is used to receive the second scan signal S2. The intermediate node N6 of the first reset module 12 is the second terminal of the first reset transistor T3-1.

[0067] The refresh phase of the pixel circuit may also include a first reset process. After the first reset process is completed, the second scan signal S2 changes from low level to high level, which will couple the potential of the intermediate node N6 of the first reset module 12 to high. By setting a compensation module 13 at the intermediate node N6 of the first reset module 12, and by providing a first target signal Va to the second end of the compensation module 13 during the blanking phase and a second target signal Vb to the second end of the compensation module 13 during the holding phase, and controlling the potential difference between the potential of the first target signal Va and the potential of the second target signal Vb to be proportional to the display brightness value DBV of the pixel circuit, the leakage current from the intermediate node N6 of the first reset module 12 to the gate of the driving transistor T1 can be suppressed. Moreover, regardless of the magnitude of the display brightness value DBV of the pixel circuit, the leakage current from the intermediate node N6 of the first reset module 12 to the gate of the driving transistor T1 can be effectively suppressed, thereby improving the display performance of the display panel.

[0068] In one exemplary embodiment, please refer to Figure 8 The pixel circuit also includes a data writing module 14.

[0069] The first terminal of the data writing module 14 is connected to the second terminal of the driving transistor T1, the second terminal of the data writing module 14 is used to receive the data signal Vdata, and the control terminal of the data writing module 14 is used to receive the first scan signal S1; wherein, during the refresh phase, the target signal also includes the data signal Vdata.

[0070] The data writing module 14 includes a data writing transistor T4, the first terminal of which is connected to the first terminal of the driving transistor T1, the second terminal of which is used to receive the data signal Vdata, and the gate of which is used to receive the first scan signal S1.

[0071] In one example, a new signal line can be added to the display panel to provide a first target signal Va to the second terminal of the compensation module 13 during the blanking phase and a second target signal Vb to the second terminal of the compensation module 13 during the holding phase. Alternatively, the data signal line in the display panel can be directly reused, controlling the data signal line to provide a data signal Vdata to the pixel circuit during the refresh phase, provide the first target signal Va to the second terminal of the compensation module 13 during the blanking phase, and provide the second target signal Vb to the second terminal of the compensation module 13 during the holding phase.

[0072] In one exemplary embodiment, please refer to Figure 9 The pixel circuit also includes a bias adjustment module 15, a second reset module 16, a first light emission control module 17, a second light emission control module 18, and a storage capacitor Cst.

[0073] The bias adjustment module 15 has the following components: a first terminal receiving a bias adjustment signal DHV, a second terminal connected to the first terminal of the driving transistor, and a control terminal receiving a third scan signal S3. The second reset module 16 has a first terminal receiving a second reset signal Vref2, a second terminal connected to the first terminal of the light-emitting element D, and a control terminal receiving the third scan signal S3. The first light-emitting control module 17 has a first terminal receiving a first power supply signal PVDD, a second terminal connected to the first terminal of the driving transistor T1, and a control terminal receiving a light-emitting control signal EM. The second light-emitting control module 18 has a first terminal connected to the second terminal of the driving transistor T1, a second terminal connected to the first terminal of the light-emitting element D, and a control terminal receiving the light-emitting control signal EM.

[0074] Specifically, the bias adjustment module 15 includes a bias adjustment transistor T5. The first terminal of the bias adjustment transistor T5 is used to receive the bias adjustment signal DHV. The second terminal of the bias adjustment transistor T5 is connected to the first terminal of the data writing transistor T4 and the first terminal of the driving transistor T1, respectively. The gate of the bias adjustment transistor T5 is used to receive the third scan signal S3. The second reset module 16 includes a second reset transistor 16. The first terminal of the second reset transistor 16 is used to receive the second reset signal Vref2. The second terminal of the second reset transistor 16 is connected to the first terminal of the light-emitting element D. The control terminal of the second reset transistor 16 is used to receive the third scan signal S3. The first light-emitting control module 17 includes a first light-emitting transistor T7. The first terminal of the first light-emitting transistor T7 is used to receive the first power supply signal PVDD. The second terminal of the first light-emitting transistor T7 is connected to the first terminal of the driving transistor T1. The gate of the first light-emitting transistor T7 is used to receive the light-emitting control signal EM, so that the first light-emitting transistor T7 turns on or off in response to the light-emitting control signal EM. The second light-emitting control module 18 includes a second light-emitting transistor T8. The first terminal of the second light-emitting transistor T8 is connected to the second terminal of the driving transistor T1. The second terminal of the second light-emitting transistor T8 is connected to the first terminal of the light-emitting element F. The gate of the second light-emitting transistor T8 is used to receive the light-emitting control signal EM so that the second light-emitting transistor T8 is turned on or off in response to the light-emitting control signal EM.

[0075] In one exemplary embodiment, please refer to Figure 10 This application provides a driving method for a pixel circuit, applied to a pixel circuit as described in any of the above embodiments; the driving method includes steps S1001 and S1002.

[0076] S1001: During the blanking phase, the first target signal is provided to the second end of the compensation module.

[0077] S1002: During the holding phase, a second target signal is provided to the second end of the compensation module.

[0078] In a detailed embodiment, please continue to refer to 9, taking as an example that the voltage difference between the gate voltage Vn1 of the driving transistor T1 in the pixel circuit and the first reset signal Vref1 is less than or equal to a preset threshold 1 / n*(VGH-VGL), that is, compensation modules 13 are set at the intermediate node N5 of the threshold compensation module 11 and the intermediate node N6 of the first reset module 12 in the pixel circuit.

[0079] The pixel circuit has a refresh phase, a blanking phase, and a holding phase. During the refresh phase, the first reset transistor T3-1 and the first reset transistor T3-2 are turned on so that the first reset signal Vref1 resets the gate of the driving transistor T1. After that, the first reset transistor T3-1 and the first reset transistor T3-2 are turned off, and the data writing transistor T4, the first threshold compensation transistor T2-1, and the second threshold compensation transistor T2-2 are turned on so as to write the data signal Vdata to the gate of the driving transistor T1. It is understandable that after the first reset process and data writing process in the brushing stage are completed, the second scan signal S2 and the first scan signal S1 will switch from low level to high level respectively, thereby turning off the first reset transistor T3-1, the first reset transistor T3-2, the first threshold compensation transistor T2-1, and the second threshold compensation transistor T2-2 respectively. When the second scan signal S2 switches from low level to high level, it will couple the potential of intermediate node N6 high. Similarly, when the first scan signal S1 switches from low level to high level, it will couple the potential of intermediate node N5 high. After the potentials of intermediate nodes N5 and N6 are coupled high, intermediate nodes N5 and N6 will leak current to the gate of driving transistor T1. Since the duration of the refresh stage in the pixel circuit is longer than the duration of the blanking stage, and the duration of the hold stage is longer than the duration of the refresh stage, this leakage phenomenon mainly occurs in the hold stage.

[0080] This application provides a first target signal Va to the second terminals of the second capacitor C2 and the third capacitor C3 during the blanking phase, and a second target signal Vb to the second terminals of the second capacitor C2 and the third capacitor C3 during the holding phase. This lowers the potential of intermediate nodes N5 and N6, preventing leakage of current from intermediate nodes N5 and N6 to the gate of the driving transistor T1. Furthermore, this application sets the potential difference between the first target signal Va and the second target signal Vb to be directly proportional to the display brightness value DBV of the pixel circuit, further ensuring that intermediate nodes N5 and N6 will not leak current to the gate of the driving transistor T1 regardless of the display brightness value DBV of the pixel circuit, thus further guaranteeing the display performance of the display panel.

[0081] Based on the same application concept, such as Figure 11 As shown, this application embodiment also provides a display panel 100, which includes a plurality of pixels 101. Each pixel 101 includes a light-emitting element and a pixel circuit as described in any of the above embodiments. Therefore, the display panel 100 also has the beneficial effects of the pixel circuit in the above embodiments. The similarities can be understood by referring to the explanation of the pixel circuit above, and will not be repeated below.

[0082] In one embodiment, such as Figure 12As shown, this application also provides a display device 200, which includes the display panel 100 in the above embodiments. Therefore, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiments. The similarities can be understood with reference to the explanation of the display panel 100 above, and will not be repeated below.

[0083] The display device 200 provided in this application embodiment can be a Figure 12 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0084] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: Drive transistors; A threshold compensation module, wherein a first terminal of the threshold compensation module is connected to the first electrode of the driving transistor, a second terminal of the threshold compensation module is connected to the gate of the driving transistor, and a control terminal of the threshold compensation module is used to receive a first scan signal; A first reset module, wherein a first terminal of the first reset module is connected to the gate of the driving transistor, a second terminal of the first reset module is used to receive a first reset signal, and a control terminal of the first reset module is used to receive a second scan signal; A compensation module, wherein a first end of the compensation module is connected to a target node, and a second end of the compensation module is used to receive a target signal; wherein the target node includes at least one of the intermediate node of the threshold compensation module and the intermediate node of the first reset module, and the target signal includes a first target signal and a second target signal; In the blanking phase, the potential of the first target signal received at the second terminal of the compensation module is higher than the potential of the second target signal received at the second terminal of the compensation module during the holding phase.

2. The pixel circuit according to claim 1, characterized in that, When the voltage difference between the gate voltage of the driving transistor and the voltage of the first reset signal is greater than a preset threshold, the target node includes the intermediate node of the threshold compensation module or the intermediate node of the first reset module.

3. The pixel circuit according to claim 1, characterized in that, The compensation module includes a first capacitor, a first end of which is connected to the target node, and a second end of which is used to receive the target signal; wherein, the target node includes an intermediate node of the threshold compensation module or an intermediate node of the first reset module.

4. The pixel circuit according to claim 1, characterized in that, When the voltage difference between the gate voltage of the driving transistor and the voltage of the first reset signal is less than or equal to a preset threshold, the target node includes the intermediate node of the threshold compensation module and the intermediate node of the first reset module.

5. The pixel circuit according to claim 1, characterized in that, The compensation module includes a second capacitor and a third capacitor, and the target node includes the intermediate node of the threshold compensation module and the intermediate node of the first reset module. The first end of the second capacitor is connected to the intermediate node of the threshold compensation module, and the second end of the second capacitor is used to receive the target signal. The first end of the third capacitor is connected to the intermediate node of the first reset module, and the second end of the third capacitor is used to receive the target signal.

6. The pixel circuit according to claim 1, characterized in that, The potential difference between the potential of the first target signal and the potential of the second target signal is positively correlated with the display brightness value of the pixel circuit.

7. The pixel circuit according to claim 6, characterized in that, The potential of the first target signal is positively correlated with the display brightness value, and the potential of the second target signal is negatively correlated with the display brightness value.

8. The pixel circuit according to claim 6, characterized in that, When the display brightness value is less than a preset brightness threshold, the potential of the second target signal is negatively correlated with the display brightness value; When the display brightness value is greater than or equal to a preset brightness threshold, the potential of the second target signal remains unchanged.

9. The pixel circuit according to claim 6, characterized in that, When the display brightness value is greater than or equal to a preset brightness threshold, the rate of change of the potential of the first target signal is greater than the rate of change of the potential of the first target signal when the display brightness value is less than the preset brightness threshold.

10. The pixel circuit according to claim 1, characterized in that, The threshold compensation module includes: A first threshold compensation transistor, wherein the first terminal of the first threshold compensation transistor is connected to the first terminal of the driving transistor, and the gate of the first threshold compensation transistor is used to receive a first scan signal; The second threshold compensation transistor has a first terminal connected to the second terminal of the first threshold compensation transistor, and the second terminal of the second threshold compensation transistor is connected to the gate of the driving transistor. The gate of the second threshold compensation transistor is used to receive the first scan signal. The intermediate node of the threshold compensation module is the second electrode of the first threshold compensation transistor.

11. The pixel circuit according to claim 1, characterized in that, The first reset module includes: A first reset transistor, the first terminal of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is used to receive a second scan signal; A first B reset transistor has its first terminal connected to the second terminal of the first A reset transistor. The second terminal of the first B reset transistor is used to receive a first reset signal, and the gate of the first B reset transistor is used to receive a second scan signal. The intermediate node of the first reset module is the second terminal of the first reset transistor A.

12. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: A data writing module, wherein a first terminal of the data writing module is connected to the second terminal of the driving transistor, the second terminal of the data writing module is used to receive a data signal, and the control terminal of the data writing module is used to receive the first scan signal; wherein, during the refresh phase, the target signal further includes the data signal.

13. The pixel circuit according to claim 12, characterized in that, The duration of the refresh phase is longer than the duration of the blanking phase, and the duration of the hold phase is longer than the duration of the refresh phase.

14. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 13.

15. A driving method for a pixel circuit, characterized in that, Applied to a pixel circuit as described in any one of claims 1 to 13; the method comprises: During the blanking phase, a first target signal is provided to the second end of the compensation module; During the holding phase, a second target signal is provided to the second end of the compensation module; Wherein, the potential of the first target signal is higher than the potential of the second target signal.

Images