In-memory computing circuit structure and data processing method applied thereto

Abstract

The application discloses an in-memory computing circuit structure and a data processing method applied to the same. The in-memory computing circuit structure comprises a data module with multiple rows and multiple columns of data, an operation module and a reference module with multiple rows and multiple columns of data. The data module comprises multiple rows of data units which can be connected in parallel, each data unit uniquely corresponds to an address of stored data. The reference module comprises multiple rows of reference units which can be connected in parallel, and the reference units and the data units are formed by the same standard units. In response to a received predetermined logic instruction, a current source is input to the data module and the reference module. The operation module outputs a logic result according to data voltage information input by the data module and reference voltage information input by the reference module, and executes the predetermined logic instruction according to the logic result. By the application, N-bit input logic can be realized without the aid of a median unit, the number of logic bits is linearly related to the number of rows of reference units in the reference module, and the operation is convenient and reliable.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of in-memory computing, and in particular to an in-memory computing circuit structure and a data processing method applied thereto. BACKGROUND

[0002] With the continuous reduction of semiconductor process size, the increase of leakage current and interconnection delay become the bottleneck of traditional CMOS memory, so finding a new generation of storage technology solution has become the focus of integrated circuit research. The resistive non-volatile memory is widely welcomed by the industry due to its near-zero static power consumption. The resistive non-volatile memory mainly includes resistive random access memory, phase change memory and magnetic memory, etc. Its main feature is to represent data by high and low resistance states of the device, for example, high resistance represents data 1 and low resistance represents data 0, so as to obtain negligible leakage current.

[0003] The resistive property of the resistive non-volatile memory also makes it have good in-memory computing expansion characteristics. By opening multiple word lines, the resistive device can be connected in parallel to realize cell coupling, and by setting multiple reference resistances, the original reading circuit can be used to realize Boolean logic operation. The combination of non-volatile memory and in-memory computing is expected to break through the bottleneck of traditional CMOS memory and Von Neumann architecture, and obtain better computing performance. However, many in-memory computing designs are currently in a relatively theoretical state, and the multi-level reference resistance greatly reduces the reliability of the operation. At the same time, in the existing parallel-resistor-configuration-reference-resistor in-memory computing scheme, the design of the reference resistance is relatively complicated, and many devices need to be connected in series and in parallel, or the resistance needs to be adjusted by transistors. These schemes make the reference module occupy a large area, and the resistance margin is small, and the reliability is poor. SUMMARY

[0004] Therefore, the present application provides an in-memory computing circuit structure and a data processing method applied thereto to solve at least one of the above problems.

[0005] According to a first aspect of the present application, an in-memory computing circuit structure is provided, which comprises a data module having multiple rows and multiple columns of data, an operation module, and a reference module having multiple rows and multiple columns of data; wherein the data module comprises multiple rows of data units that can be connected in parallel, each data unit uniquely corresponding to an address of a stored data; the reference module has multiple rows of reference units that can be connected in parallel, and the reference units and the data units are composed of the same standard units;

[0006] In response to the received predetermined logic instruction, a current source is input to the data module and the reference module to generate data voltage information and reference voltage information, respectively, wherein the predetermined logic instruction is a multiple-input address logic instruction or a single-input address logic instruction.

[0007] The operation module outputs a logic result according to the data voltage information input by the data module and the reference voltage information input by the reference module, and executes the predetermined logic instruction according to the logic result, wherein the reference voltage information includes high-resistance reference voltage information and low-resistance reference voltage information.

[0008] Preferably, at least one row of the plurality of rows of reference units includes a high-resistance unit and a low-resistance unit.

[0009] Specifically, the in-memory computing circuit structure can perform 1-N-bit input logic operations, and the in-memory computing circuit structure includes two sub-arrays and an operation module group above and below the two sub-arrays;

[0010] Each sub-array includes a reference module having N rows and N+1 columns of reference units and a data module having at least N+1 columns of data;

[0011] The operation module group includes N operation modules, each of which has an input port 1, an input port 2, and an input port 3;

[0012] Each column of data in the data module shares a group of operation modules;

[0013] The input port 1 of the N operation modules of the group of operation modules shared by each column of data is the data voltage information of the column of data, the input port 2 of the nth operation module of the group of operation modules is the reference voltage information generated by the nth column of reference units of the reference module, and the input port 3 of the nth operation module of the group of operation modules is the reference voltage information generated by the (n+1)th column of reference units of the reference module, wherein 1≤n≤N.

[0014] Further, the in-memory computing circuit structure further includes a switch unit connected to the data module and the reference module, respectively, and the switch unit is activated to access the current source to input the current source to the data module and the reference module.

[0015] According to a second aspect of the present application, a data processing method applied to the above in-memory computing circuit structure is provided, and the method includes:

[0016] receiving a predetermined logic instruction, wherein the predetermined logic instruction is a multiple-input address logic instruction or a single-input address logic instruction;

[0017] According to the predetermined logic instruction, corresponding column data in the data module and at least one row of reference cells in the reference module are selected respectively, the corresponding column data and the at least one row of reference cells each include a standard cell resistance, and the at least one row of reference cells includes a high-resistance cell and a low-resistance cell.

[0018] According to data voltage information of the corresponding column data and reference voltage information of the at least one reference cell, the operation module outputs a logic result, and the predetermined logic instruction is executed according to the logic result, wherein the reference voltage information includes high-resistance reference voltage information and low-resistance reference voltage information.

[0019] Preferably, the method includes pre-setting resistance state information of each standard cell resistance in each reference cell.

[0020] Further, after receiving the predetermined logic instruction, the method further includes:

[0021] According to current flowing into the corresponding column data, the corresponding column data outputs data voltage information.

[0022] According to current flowing into the at least one reference cell, the reference module outputs reference voltage information.

[0023] Specifically, according to the data voltage information of the corresponding column data and the reference voltage information of the at least one reference cell, the operation module outputs a logic result includes:

[0024] According to resistance state information of the corresponding column data, the data voltage information, resistance state information of the at least one reference cell and the reference voltage information, the operation module outputs a logic result.

[0025] According to a third aspect of the present application, an electronic device is provided, which includes a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor executes the program to implement the steps of the above method.

[0026] According to a fourth aspect of the present application, a computer readable storage medium is provided, which stores a computer program executable by a processor to implement the steps of the above method.

[0027] As can be seen from the above technical solutions, the in-memory computing circuit structure in the present technical solution can implement N-bit input logic without the aid of a median cell, and the number of logic bits is linearly related to the number of rows of reference cells in the reference module, and the operation is convenient and reliable. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative labor.

[0029] Figure 1 is a circuit schematic diagram of the in-memory computing circuit structure according to the embodiment of the present application;

[0030] Figure 2 is an example diagram of the in-memory computing circuit array structure according to the embodiment of the present application;

[0031] Figure 3 is a schematic diagram of the operation module group used in the in-memory computing circuit structure according to the embodiment of the present application; Figure 2

[0032] Figure 4A Figure 4B Figure 4C is a circuit schematic diagram of the in-memory computing circuit structure when the input logic is 2 bits according to the embodiment of the present application;

[0033] Figure 5A Figure 5B Figure 5C is a circuit schematic diagram of the in-memory computing circuit structure when the input logic is 3 bits according to the embodiment of the present application;

[0034] Figure 6 is an example diagram of the circuit array when the highest execution input logic is 3 bits according to the embodiment of the present application;

[0035] Figure 7 is a schematic diagram of the operation module group composed of 3 operation modules according to the embodiment of the present application;

[0036] Figure 8 is a flowchart of the data processing method applied to the in-memory computing circuit structure according to the embodiment of the present application;

[0037] Figure 9 is a schematic block diagram of the system structure of the electronic device 600 according to the embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present application.​​​​​

[0039] In view of the current resistor device parallel-configuration reference resistance type in-memory computing scheme, the reference resistance design is complicated, a large number of device series-parallel connection is required, or a transistor is used to adjust the resistance, which leads to a large area occupied by the reference resistance module, a small resistance margin, and poor reliability. Based on this, the embodiment of the present application provides an in-memory computing circuit structure, which does not require a median reference resistance and does not require an adjusting transistor. The standard cell resistance parallel connection with the same data cell structure, process, etc. can realize the in-memory computing function. The standard cell resistance is a unit manufactured by the same semiconductor and device process, which is composed of a gating transistor and a resistor device. The resistor device can realize the switching between the high resistance state and the low resistance state by the electrical method. In a chip, the standard cell resistance has the same high and low resistance characteristics, that is, the high resistance of all standard cell resistances is the same, and the low resistance is also the same. The circuit is simple to realize, small in area, high in expansibility, and high in reliability. The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0040] Figure 1 is a circuit schematic diagram of the in-memory computing circuit structure according to the embodiment of the present application, as Figure 1 shown, the in-memory computing circuit structure includes a data module with multiple rows and multiple columns of data, an operation module, and a reference module with multiple rows and multiple columns of data. The data module includes multiple rows of data cells that can be connected in parallel, each data cell uniquely corresponding to an address of stored data; the reference module includes multiple rows of reference cells that can be connected in parallel, wherein the reference cells are composed of standard cell resistances that are the same as the data cell structure, process, etc., without special design and process, and wherein at least one row of reference cells in the multiple rows of reference cells includes high resistance cells (devices in high resistance state) and low resistance cells (devices in low resistance state). As Figure 1 shown, the first row of reference cells includes high resistance cells and low resistance cells. The resistance state information of the resistor device in each reference cell can be set in advance.

[0041] Referring to Figure 1The in-memory computing circuit structure shown operates as follows: First, the in-memory computing circuit receives a predetermined logic instruction, which includes at least the address and logic type of the operation data. Then, in response to the address of the operation data in the predetermined logic instruction, the data unit at the corresponding address in the data module is activated, and a current source is input to the data unit. Simultaneously, in response to the logic type in the predetermined logic instruction, the corresponding reference unit in the reference module is activated, and a current source is input to the reference module. The arithmetic module outputs a logic result based on the data voltage information input from the data module and the reference voltage information input from the reference module. The reference voltage information includes: high-resistance reference voltage information generated by the high-resistance unit column and low-resistance reference voltage information generated by the low-resistance unit column.

[0042] In this practical operation, the predetermined logic instructions may include: multi-input address logic instructions or single-input address logic instructions. Multi-input address logic instructions are logic instructions with 2 to N input addresses, where N is the number of reference cell rows in the reference module, and N≥2.

[0043] Specifically, such as Figure 1 As shown, the left side is a data module with 2^k rows, which can represent two resistance states: high and low (H / L). The high resistance state (HRs) is defined as data 1, and the low resistance state (LRs) as data 0. The right side is the reference module, where R... 0,0 For HRs, R 0,1 For LRs, all are fixed values; R i,0 =R i,1 (1≤i≤N-1), the resistance state is fixed according to the operation performed; the middle is the operation module. After the signal SAE changes from 0 to 1, Q is the read data and QB is the inverse of Q.

[0044] The arithmetic module consists of an analog voltage adder and a comparator. The analog voltage adder can realize V IN+ =2V data , and V IN- =V refH +V refL ; Comparator for V IN+ and V IN- Compare, if V IN+ >V IN- If Q is 1 and QB is 0; if V IN+ <V IN- If Q = 0, then QB = 1. Figure 1 This demonstrates a specific implementation of the arithmetic module. Signals SAE, SA0, SA1, and SA2 are initially all 0. Step 1: Signal SAE changes from 0 to 1, signal SA0 changes from 0 to 1, V... IN+ =V data VIN- = V refH ; Step 2: signal SA0 changes from 1 to 0, signal SA1 changes from 0 to 1, V IN+ = 2V data , V IN- = V refH + V refL ; Step 3: signal SA2 changes from 0 to 1, comparator works, Q and QB get results; Step 4: signals SAE, SA0, SA1 and SA2 all return to initial state.

[0045] When performing a read operation (corresponding to the single-input address logical instruction described above), WL i (0≤i≤2^k-1) are activated for one row, WL ref,0 activates R 0,0 and R 0,1 , Q is the read-out selected data and QB is the read-out inverted selected data.

[0046] When performing an M (2≤M≤N) -input logical operation (corresponding to the multiple-input address logical instruction described above), WL i (0≤i≤2^k-1) are activated for M rows, WL ref,0 ~ WL ref,M-1 activates R i,0 and R i,1 , 0≤i≤M-1.

[0047] Specifically, for the logical proposition "all the selected M-bit data are data 1", R i,0 and R i,1 (1≤i≤M-1) are all set as HRs, Q is 1 then the proposition is true, and Q is 0 then the proposition is false.

[0048] For the logical proposition "at least m-bit data 1 (2≤m≤M-1) in the selected M-bit data", R i,0 and R i,1 (1≤i≤m-1) are set as HRs, R i,0 and R i,1 (m≤i≤M-1) are set as LRs, Q is 1 then the proposition is true, and Q is 0 then the proposition is false.

[0049] For the logical proposition "at least 1-bit data 1 in the selected M-bit data", R i,0 and R i,1 (1≤i≤M-1) are all set as LRs, Q is 1 then the proposition is true, and Q is 0 then the proposition is false.

[0050] In one embodiment, the in-memory computing circuit structure can perform 1-N bit input logic operation, and the in-memory computing circuit structure comprises: two sub-arrays and an operation module group, wherein each sub-array comprises: a data module with N+1 columns of data units, and a reference module with N rows and N+1 columns of reference units, each column of data in the data module sharing a group of N operation modules.

[0051] Figure 2 is an example diagram of the in-memory computing circuit array structure according to an embodiment of the present application, as shown in Figure 2 The smallest array that can perform N-bit input logic operation is composed of two sub-arrays and an operation module group, each sub-array has at least N+1 columns of data and N rows and N+1 columns of reference units, each column of data shares a group of N operation modules, each operation module includes three input ports, namely data voltage input port 1, low resistance reference voltage information input port 2, and high resistance reference voltage information input port 3 (hereinafter referred to as input port 1, input port 2 and input port 3, respectively). For an operation module group shared by a column of data, the input port 1 of the N operation modules in the operation module group inputs the data voltage information of the column of data, the input port 2 of the nth (1≤n≤N) operation module in the N operation modules is used to input the reference voltage information generated by the nth column of reference units in the reference module, and the input port 3 of the nth (1≤n≤N) operation module in the N operation modules is used to input the reference voltage information generated by the nth+1 column of reference units in the reference module.

[0052] Figure 2 TG 0,i (0≤i≤N), TG D0,i (0≤i≤N), TG R1,i (0≤i≤N), TG R0,i (0≤i≤N), TG D1,i (0≤i≤N), TG 1,i (0≤i≤N) are switch units. When the switch units are activated, the current source is connected, and the current source is input to the data module and the reference module. In this embodiment, considering that the reference module performs all N-bit input logic operations (at least n ones in N-bit input, n is 0-N), the reference module is set to have N rows of reference units; in actual application, if the reference module does not need to perform all input logic operations, the reference module can be set to have less than N rows of reference units. The data module has more columns of data than the reference module has rows of reference units.

[0053] Figure 3 is Figure 2 is a schematic diagram of the operation module group used in Figure 3The illustrated set of operation modules share a column of data.

[0054] For the reference module, the configuration is as follows, R 0,i,j = R 1,i,j (0≤i≤N-1, 0≤j≤N), R 0,i,j = LR (0≤i≤N-1, 0≤j≤i), R 0,i,j = HR (0≤i≤N-1, i+1≤j≤N).

[0055] When performing a read operation on the upper subarray, TG 0,i (0≤i≤N), TG D0,i (0≤i≤N), TG R0,0 , TG R0,1 are activated, WL i (0≤i≤2^k-1) are activated, WL ref0,0 activate R 0,0,0 and R 0,0,1 (i.e., the first row of reference cells), Q 0,i (0≤i≤N) are the values of the selected data from each column of the upper subarray, Q 1,i (0≤i≤N) are the complements of the selected data from each column of the upper subarray.

[0056] When performing an M (2≤M≤N) input logical operation on the upper subarray, TG 0,i (0≤i≤N), TG D0,i (0≤i≤N), TG R0,i (0≤i≤M+1), TG 1,i (0≤i≤M+1) are activated, WL i (0≤i≤2^k-1) are activated, WL ref0,i activate R 0,i,j (0≤i≤M-1, 0≤j≤M), S i (0≤i≤M-1) are activated, Q i,j (0≤i≤2M-1, 0≤j≤N) are the results of the complete logical operation on the selected data from each column of the upper subarray.

[0057] When performing a read operation on the lower subarray, TG 1,i (0≤i≤N), TG D1,i (0≤i≤N), TG R1,0 , TG R1,1 are activated, WL i (2^k≤i≤2^(k+1)-1) are activated, WL ref1,0 activate R 1,0,0 and R 1,0,1 , Q 0,i (0≤i≤N) are the values of the selected data from each column of the lower subarray, Q1,i (0≤i≤N) is the inverse of the selected data of each column of the upper subarray.

[0058] When performing the M (2≤M≤N) input logic operation of the lower subarray, TG 1,i (0≤i≤N), TG D1,i (0≤i≤N), TG R1,i (0≤i≤M+1), TG 0,i (0≤i≤M+1) is activated, WL i (2^k≤i≤2^(k+1)-1) is activated M rows, WL ref1,i R 1,i,j (0≤i≤M-1, 0≤j≤M), S i (0≤i≤M-1) is activated, Q i,j (0≤i≤2M-1, 0≤j≤N) is the result of the full logic operation of the selected data of each column of the lower subarray.

[0059] As can be seen from the above description, the in-memory computing circuit structure provided in the embodiments of the present application can implement N-bit input logic without the aid of a median unit, and the number of logic bits is linearly related to the number of reference unit rows in the reference module, and the operation is convenient and reliable.

[0060] In order to better understand the present application, the following describes the circuit array example structure in the embodiments of the present application with reference to the accompanying drawings. Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 5A 、 Figure 5B 、 Figure 5C and Figure 6 In this example, N=3, k=9, and read operation, 2-bit input logic (see Figure 4A 、 Figure 4B 、 Figure 4C ) and 3-bit input logic (see Figure 5A 、 Figure 5B 、 Figure 5C ) are demonstrated.

[0061] (I) 2-bit input logic

[0062] As shown in Figure 4A , when performing read operation, WL i (0≤i≤511) is activated one row, WL ref,0 R 0,0 (HRs) and R 0,1 (LRs) are activated, current source I data flows through the selected data unit to generate voltage V data , and current source I refH flows through R 0,0 to generate voltage V refHCurrent source I refL Flowing through R 0,1 Generated voltage V refL V IN+ =2V data V IN- =V refH +V refL For a single data point, V data Either because the data bit has high impedance and is equal to V refH Either because the data bit has low impedance and is equal to V refL For two-bit data, since the data bits can have three cases: HH / HL / LL, V data There are also three corresponding situations.

[0063] If the selected data cell is in a high-resistance state HRs, then V data =V refH V IN+ =2V refH >V refH +V refL =V IN- Q reads 1. If the selected data cell is in a low-resistance state LRs, then V data =V refL V IN+ =2V refL <V refH +V refL =V IN- Q reads 0.

[0064] like Figure 4B , Figure 4C As shown, when performing a 2-input logic operation, WL i (0≤i≤511) 2 rows are activated, WL ref,0 With WL ref,1 Activate R 0,0 (HRs), R 0,1 (LRs), R 1,0 With R 1,1 .

[0065] like Figure 4B As shown, when performing a 2-input AND / NAND operation, R 1,0 With R 1,1 Configured as HRs. Current source I data The current flows through the two selected parallel data cells, generating a voltage V. data Current source I refH Flowing through R 0,0 With R 1,0 Generated voltage V refH This is the voltage generated by HRs connected in parallel, hereinafter referred to as V. HH Current source IrefL Flowing through R 0,1 With R 1,1 Generated voltage V refL This is the voltage generated by LRs in parallel with HRs, hereinafter referred to as V. LH V IN+ =2V data V IN- =V HH +V LH If both data units are HRs, then V data =V HH V IN+ =2V HH >V HH +V LH =V IN- Q reads 1, QB reads 0. If the two data units are 1 HRs and 1 LRs respectively, then V data =V LH V IN+ =2V LH <V HH +V LH =V IN- Q reads 0, QB reads 1. If both data units are LRs, then V data =V LL V IN+ =2V LL <V HH +V LH =V IN- Q reads 0, and QB reads 1. Thus, Q implements a 2-input AND logic, and QB implements a 2-input AND NOT logic.

[0066] like Figure 4C As shown, when executing a 2-input OR / OR NOT operation logic, R 1,0 With R 1,1 Configured as LRs. Current source I data The current flows through the two selected parallel data cells, generating a voltage V. data Current source I refH Flowing through R 0,0 With R 1,0 Generated voltage V refH This is the voltage generated by LRs in parallel with HRs, hereinafter referred to as V. LH Current source I refL Flowing through R 0,1 With R 1,1 Generated voltage V refL This is the voltage generated by parallel LRs, hereinafter referred to as V. LL V IN+ =2V data V IN- =VLH +V LL If both data units are HRs, then V data =V HH V IN+ =2V HH >V LH +V LL =V IN- Q reads 1, QB reads 0. If the two data units are 1 HRs and 1 LRs respectively, then V data =V LH V IN+ =2V LH >V LH +V LL =VIN-, Q reads 1, QB reads 0. If both data units are LRs, then V data =V LL V IN+ =2V LL <V LH +V LL =V IN- Q reads 0, and QB reads 1. Thus, Q implements a 2-input OR logic, and QB implements a 2-input NOR logic.

[0067] (II) 3-bit input logic

[0068] like Figure 5A , Figure 5B , Figure 5C As shown, when performing a 3-input logic operation, WL i (0≤i≤511) 3 rows are activated, WL ref,0 WL ref,1 With WL ref,2 Activate R 0,0 (HRs), R 1,0 R 2,0 R 0,1 (LRs), R 1,1 With R 2,1 .

[0069] like Figure 5A As shown, when performing a 3-input AND / NAND operation, R 1,0 R 2,0 R 1,1 With R 2,1 Configured as HRs. Current source I data The current flows through the selected three parallel data cells, generating a voltage V. data Current source I refH Flowing through R 0,0 R 1,0 With R 2,0 Generated voltage V refHThis is the voltage generated by HRs connected in parallel, hereinafter referred to as V. HHH Current source I refL Flowing through R 0,1 R 1,1 With R 2,1 Generated voltage V refL This is the voltage generated by LRs in parallel with HRs, hereinafter referred to as V. LHH V IN+ =2V data V IN- =V HHH +V LHH If all 3 data units are HRs, then V data =V HHH V IN+ =2V HHH >V HHH +V LHH =V IN- Q reads 1, QB reads 0. If the 3-bit data units are 2 bits HRs and 1 bit LRs respectively, then V data =V LHH V IN+ =2V LHH <V HHH +V LHH =V IN- Q reads 0, QB reads 1. If the 3 data units are 1 HRs and 2 LRs respectively, or all 3 data units are LRs, then V data <V LHH V IN+ <2V LHH <V HHH +V LHH =V IN- Q reads 0, and QB reads 1. Thus, Q implements a 3-input AND logic, and QB implements a 3-input NOT logic.

[0070] like Figure 5B As shown, when executing the 3-input large number / large number NOT operation logic, R 1,0 With R 1,1 Configured as HRs, R 2,0 With R 2,1 Configured as LRs. Current source I data The current flows through the selected three parallel data cells, generating a voltage V. data Current source I refH Flowing through R 0,0 R 1,0 With R 2,0 Generated voltage V refH This is the voltage generated by LRs in parallel with HRs, hereinafter referred to as V. LHH Current source IrefL Flowing through R 0,1 R 1,1 With R 2,1 Generated voltage V refL This is the voltage generated by LRs in parallel and HRs in parallel, hereinafter referred to as V. LLH V IN+ =2V data V IN- =V LHH +V LLH If all 3 data units are HRs, then V data =V HHH V IN+ =2V HHH >V LHH +V LLH =V IN- Q reads 1, QB reads 0. If the 3-bit data units are 2 bits HRs and 1 bit LRs respectively, then V data =V LHH V IN+ =2V LHH >V LHH +V LLH =V IN- Q reads 1, QB reads 0. If the 3 data units are 1 HR bit and 2 LR bits respectively, then V data =V LLH V IN+ =2V LLH <V LHH +V LLH =V IN- Q reads 0, QB reads 1. If all 3 data units are LRs, then V data =V LLL V IN+ =2V LLL <V LHH +V LLH =V IN- Q reads 0, and QB reads 1. Thus, Q implements 3-input large number logic, and QB implements 3-input large number NOT logic.

[0071] like Figure 5C As shown, when executing 3-input OR / OR NOT operation logic, R 1,0 R 2,0 R 1,1 With R 2,1 Configured as LRs. Current source I data The current flows through the selected three parallel data cells, generating a voltage V. data Current source I refH Flowing through R 0,0 R 1,0 With R 2,0Generated voltage V refH This is the voltage generated by LRs in parallel and HRs in parallel, hereinafter referred to as V. LLH Current source I refL Flowing through R 0,1 R 1,1 With R 2,1 Generated voltage V refL This is the voltage generated by the parallel connection of LRs, hereinafter referred to as V. LLL V IN+ =2V data V IN- =V LLH +V LLL If all three data units are HRs, or if they are two HRs and one LRs respectively, then V data >V LLH V IN+ >2V LLH >V LLH +V LLL =V IN- Q reads 1, QB reads 0. If the 3 data units are 1 HR bit and 2 LR bits respectively, then V data =V LLH V IN+ =2V LLH >V LLH +V LLL =V IN- Q reads 1, QB reads 0. If all 3 data units are LRs, then V data =V LLL V IN+ =2V LLL <V LLH +V LLL =V IN- Q reads 0, and QB reads 1. Thus, Q implements a 3-input OR logic, and QB implements a 3-input NOR logic.

[0072] See Figure 6 As shown, in this example, the smallest array that performs up to 3-bit input logic operations consists of two subarrays, one above the other. Each subarray has 4 columns of data and 3 rows of reference cells. Each column of data shares a set of reference cells. Figure 7 The diagram shows a computation module group consisting of three computation modules.

[0073] The reference module configuration is as follows, R 0,i,j =R 1,i,j (0≤i≤2,0≤j≤3), R 0,i,j =LRs(0≤i≤2, 0≤j≤i), R 0,i,j =HRs(0≤i≤2, i+1≤j≤3).

[0074] When performing a read operation on the upper subarray, TG 0,i (0≤i≤3), TG D0,i (0≤i≤3), TG R0,0 , TG R0,1 activated, WL i (0≤i≤511) rows are activated, WL ref0,0 activated R 0,0,0 and R 0,0,1 , Q 0,i (0≤i≤3) are the values of the selected data of each column of the upper subarray, Q 1,i (0≤i≤3) are the inverse of the values of the selected data of each column of the upper subarray.

[0075] When performing a 2-input logic operation on the upper subarray, TG 0,i (0≤i≤3), TG D0,i (0≤i≤3), TG R0,i (0≤i≤3), TG 1,i activated, WL i (0≤i≤511) rows are activated, WL ref0,i activated R 0,i,j (0≤i≤1, 0≤j≤2), S i (0≤i≤1) are activated, Q i,j (0≤i≤3, 0≤j≤3) are the OR / NOR, AND / NAND (or NOR, NAND) operation results of the selected data of each column of the upper subarray, respectively.

[0076] When performing a 3-input logic operation on the upper subarray, TG 0,i (0≤i≤3), TG D0,i (0≤i≤3), TG R0,i (0≤i≤4), TG 1,i activated, WL i (0≤i≤511) rows are activated, WL ref0,i activated R 0,i,j (0≤i≤2, 0≤j≤3), S i (0≤i≤2) are activated, Q i,j (0≤i≤5, 0≤i≤3) are the OR / NOR, MAJ / NMAJ, AND / NAND (or NOR, NAND) operation results of the selected data of each column of the upper subarray, respectively.

[0077] When performing a read operation on the lower subarray, TG 1,i (0≤i≤3), TG D1,i (0≤i≤3), TG R1,0 , TG R1,1Activate, WL i Activate 2 rows, WL ref1,0 Activate R 1,0,0 Activate R 1,0,1 , Q 0,i (0≤i≤3) is the value of the selected data of each column of the lower subarray, Q 1,i (0≤i≤3) is the inverse of the selected data of each column of the lower subarray.

[0078] TG 1,i (0≤i≤3), TG D1,i (0≤i≤3), TG R1,i (0≤i≤3), TG 0,i (0≤i≤3) is activated, WL i (512≤i≤1023) is activated 2 rows, WL ref1,i Activate R 1,i,j (0≤i≤1, 0≤j≤2), S i (0≤i≤1) is activated, Q i,j (0≤i≤3, 0≤j≤3) are respectively the results of OR / NOR, AND / NAND operations of the selected data of each column of the lower subarray.

[0079] TG 1,i (0≤i≤3), TG D1,i (0≤i≤3), TG R1,i (0≤i≤4), TG 0,i (0≤i≤4) is activated, WL i (512≤i≤1023) is activated 3 rows, WL ref1,i Activate R 1,i,j (0≤i≤2, 0≤j≤3), S i (0≤i≤2) is activated, Q i,j (0≤i≤5, 0≤i≤3) are respectively the results of OR / NOR, MAJ / NMAJ, AND / NAND operations of the selected data of each column of the lower subarray.

[0080] As can be seen from the above description, the embodiment of the application realizes logic operation through two reference voltages, avoids the use of median resistance, requires a small number of reference cells, has high reliability, and has strong scalability.

[0081] Based on similar inventive concepts, the embodiment of the application also provides a data processing method applied to the above-mentioned in-memory computing circuit structure.

[0082] Figure 8 is a flowchart of the data processing method, as Figure 8 shown, the method comprises:

[0083] In step 801, a predetermined logic instruction is received, wherein the predetermined logic instruction is a multi-input address logic instruction or a single-input address logic instruction.

[0084] In step 802, corresponding column data in a data module and at least one row of reference cells in a reference module are selected according to the predetermined logic instruction, wherein the corresponding column data and the at least one row of reference cells each include standard cell resistances, and the at least one row of reference cells includes high-resistance cells and low-resistance cells.

[0085] In an embodiment, resistance state information of the standard cell resistances in each reference cell can be preset.

[0086] In step 803, a logic result is output by the operation module according to data voltage information of the corresponding column data and reference voltage information of the at least one reference cell, and the predetermined logic instruction is executed according to the logic result, wherein the reference voltage information includes high-resistance reference voltage information and low-resistance reference voltage information.

[0087] Specifically, the corresponding column data outputs data voltage information according to a current flowing into the corresponding column data, and the reference module outputs reference voltage information according to a current flowing into the at least one reference cell.

[0088] In actual operation, the operation module can output a logic result according to resistance state information of the corresponding column data, the data voltage information, resistance state information of the at least one reference cell, and the reference voltage information.

[0089] By selecting corresponding column data in a data module and at least one row of reference cells in a reference module according to a received predetermined logic instruction, and then outputting a logic result by the operation module according to data voltage information of the corresponding column data and reference voltage information of the at least one reference cell, and executing the predetermined logic instruction according to the logic result, the in-memory computing circuit structure in the embodiment can implement N-bit input logic without the aid of a median cell, and the number of logic bits is linearly related to the number of rows of reference cells in the reference module, which is convenient to operate and has high reliability.

[0090] The specific execution process of each step can be referred to the description in the above embodiments, which will not be repeated here.

[0091] The embodiment also provides an electronic device, which can be a desktop computer, a tablet computer, a mobile terminal, and the like, but is not limited thereto. In the embodiment, the electronic device can be implemented by referring to the above method embodiments and the in-memory computing circuit structure embodiments, the contents of which are incorporated herein, and the repeated parts will not be repeated here.

[0092] Figure 9 is a schematic block diagram of a system configuration of an electronic device 600 according to an embodiment of the present application. As shown, the electronic device 600 can include a central processor 100 and a memory 140; the memory 140 is coupled to the central processor 100. It is worth noting that this diagram is exemplary; other types of structures can also be used to supplement or replace this structure to implement telecommunication functions or other functions. Figure 9

[0093] In an embodiment, the data processing function can be integrated into the central processor 100. The central processor 100 can be configured to perform the following controls:

[0094] receiving a predetermined logic instruction, wherein the predetermined logic instruction is a multi-input address logic instruction or a single-input address logic instruction.

[0095] selecting corresponding column data in a data module and at least one row of reference cells in a reference module according to the predetermined logic instruction, respectively, wherein the corresponding column data and the at least one row of reference cells each include a standard cell resistance, and the at least one row of reference cells includes a high-resistance cell and a low-resistance cell.

[0096] outputting a logic result by the operation module according to data voltage information of the corresponding column data and reference voltage information of the at least one reference cell, wherein the reference voltage information includes high-resistance reference voltage information and low-resistance reference voltage information, and executing the predetermined logic instruction according to the logic result.

[0097] As can be seen from the above description, the electronic device provided by the embodiment of the present application can select corresponding column data in a data module and at least one row of reference cells in a reference module according to a received predetermined logic instruction, and then output a logic result by the operation module according to data voltage information of the corresponding column data and reference voltage information of the at least one reference cell, and execute the predetermined logic instruction according to the logic result. The in-memory computing circuit structure in the embodiment of the present application can achieve N-bit input logic without the aid of a median cell, and the number of logic bits is linearly related to the number of rows of reference cells in the reference module, which is convenient to operate and has high reliability.

[0098] In another embodiment, the in-memory computing circuit structure can be configured separately from the central processor 100, for example, the in-memory computing circuit structure can be configured as a chip connected to the central processor 100 to achieve the data processing function through the control of the central processor.

[0099] As shown in FIG. 6, the electronic device 600 can include a central processor 100 and a memory 140; the memory 140 is coupled to the central processor 100. It is worth noting that this diagram is exemplary; other types of structures can also be used to supplement or replace this structure to implement telecommunication functions or other functions. Figure 9 ​As shown, the electronic device 600 can also include a communication module 110, an input unit 120, an audio processing unit 130, a display 160, a power supply 170. Notably, the electronic device 600 does not necessarily have to include all of the components shown in Figure 9 FIG. 1; moreover, the electronic device 600 can include components not shown in Figure 9 FIG. 1, which can be found in the prior art.

[0100] As shown, the central processing unit 100, which is sometimes referred to as a controller or operating control, can include a microprocessor or other processor device and / or logic device, which receives input and controls the operation of the various components of the electronic device 600. Figure 1

[0101] The memory 140, for example, can be one or more of a buffer, a flash memory, a hard drive, a removable media, a volatile memory, a non-volatile memory, or other suitable device. Information relating to failures can be stored, in addition to programs for executing the information. The central processing unit 100 can execute the programs stored in the memory 140 to achieve information storage or processing, etc.

[0102] The input unit 120 provides input to the central processing unit 100. The input unit 120 is, for example, a key or touch input device. The power supply 170 is used to provide power to the electronic device 600. The display 160 is used to display display objects such as images and text. The display can be, for example, an LCD display, but is not limited thereto.

[0103] The memory 140 can be a solid state memory, such as a read only memory (ROM), a random access memory (RAM), a SIM card, etc. It can also be a memory that retains information even when power is off, can be selectively erased, and is provided with more data, examples of which are sometimes referred to as EPROM, etc. The memory 140 can also be some other type of device. The memory 140 includes a buffer memory 141 (sometimes referred to as a buffer). The memory 140 can include an application / function storage section 142 for storing application programs and function programs or for storing a flow for operating the electronic device 600 by the central processing unit 100.

[0104] The memory 140 can also include a data storage section 143 for storing data such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. A driver program storage section 144 of the memory 140 can include various driver programs of the electronic device for a communication function and / or for performing other functions of the electronic device (such as a messaging application, an address book application, etc.). ​

[0105] The communication module 110 is a transmitter / receiver 110 that transmits and receives signals via an antenna 111. The communication module (transmitter / receiver) 110 is coupled to the central processor 100 to provide input signals and receive output signals, as is the case with conventional mobile communication terminals.

[0106] Based on different communication technologies, a plurality of communication modules 110, such as a cellular network module, a Bluetooth module, and / or a wireless LAN module, can be provided in the same electronic device. The communication module (transmitter / receiver) 110 is also coupled to a speaker 131 and a microphone 132 via an audio processor 130 to provide audio output via the speaker 131 and receive audio input from the microphone 132, thereby implementing the usual telecommunication functions. The audio processor 130 can include any suitable buffers, decoders, amplifiers, etc. In addition, the audio processor 130 is coupled to the central processor 100, thereby enabling recording on the local device via the microphone 132 and playing stored sounds on the local device via the speaker 131.

[0107] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the data processing method.

[0108] In conclusion, the embodiment of the present application provides an in-memory computing circuit structure and a data processing method applied to the same. The in-memory computing circuit structure can implement N-bit input logic without the aid of a median unit, and the number of logic bits is linearly related to the number of reference unit rows in the reference module, which is convenient to operate and has high reliability.

[0109] The preferred embodiments of the application have been described above with reference to the accompanying drawings. Many features and advantages of the embodiments are apparent from the detailed specification, and it is therefore intended by the appended claims to cover all such features and advantages of the embodiments within their true spirit and scope. Further, since numerous modifications and changes can be made to the preferred embodiments of the application by those having ordinary skill in the art, it is intended that all such modifications and changes be covered by the claims.

[0110] Those skilled in the art will appreciate that embodiments of the present application can be devised for use with either a system, method, or computer program product. Accordingly, the embodiments of the present application are intended to embrace all such permutations, combinations, and variations that fall within the scope of the appended claims. Specifically, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment containing both software and hardware aspects.

[0111] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart Figure 1 one or more functions specified in the flowchart or multiple flows and / or blocks. Figure 1 one or more functions specified in the flowchart or multiple flows and / or blocks.

[0112] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device that implements the functions specified in the flowchart Figure 1 one or more functions specified in the flowchart or multiple flows and / or blocks. Figure 1 one or more functions specified in the flowchart or multiple flows and / or blocks.

[0113] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart Figure 1 one or more functions specified in the flowchart or multiple flows and / or blocks. ​ one or more functions specified in the flowchart or multiple flows and / or blocks.

[0114] The principles and implementation manners of the present application are described in the specific embodiments, and the above embodiment descriptions are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges can be changed, and the above description should not be understood as the limitation of the present application.

Claims

1. An in-memory computing circuit structure, characterized by, The in-memory computing circuit structure comprises a data module having multiple rows and multiple columns of data, an operation module, and a reference module having multiple rows and multiple columns of data; wherein the data module comprises multiple rows of data units that can be connected in parallel, each data unit uniquely corresponding to an address storing data; the reference module has multiple rows of reference units that can be connected in parallel, the reference units and the data units being composed of the same standard units; In response to a received predetermined logic instruction, a current source is input to the data module and the reference module to generate data voltage information and reference voltage information, respectively, wherein the predetermined logic instruction is a multiple-input address logic instruction or a single-input address logic instruction; The operation module outputs a logic result according to the data voltage information input by the data module and the reference voltage information input by the reference module, and executes the predetermined logic instruction according to the logic result, wherein the reference voltage information comprises high-resistance reference voltage information and low-resistance reference voltage information; The in-memory computing circuit structure can perform 1-N-bit input logic operations, and comprises two sub-arrays and an operation module group above and below; Each sub-array comprises a reference module having N rows and N+1 columns of reference units, and a data module having at least N+1 columns of data; The operation module group comprises N operation modules, each having an input port 1, an input port 2, and an input port 3; Each column of data in the data module shares a group of operation module groups; The input port 1 of the N operation modules of each group of operation module groups shared by each column of data is the data voltage information of the column of data, the input port 2 of the nth operation module of the group of operation module groups is the reference voltage information generated by the nth column of the reference module, and the input port 3 of the nth operation module of the group of operation module groups is the reference voltage information generated by the (n+1)th column of the reference module, wherein 1≤n≤N.

2. The computing-in-memory circuitry structure of claim 1, wherein, At least one row of the multiple rows of reference units comprises a high-resistance unit and a low-resistance unit.

3. The computing-in-memory circuitry structure of claim 1, wherein, The in-memory computing circuit structure further comprises a switch unit connected to the data module and the reference module, respectively, which, when activated, accesses the current source to input the current source to the data module and the reference module.

4. A data processing method applied to the in-memory computing circuit structure of any one of claims 1 to 3, characterized in that, The method comprises: receiving a predetermined logic instruction, wherein the predetermined logic instruction is a multiple-input address logic instruction or a single-input address logic instruction; selecting corresponding column data in the data module and at least one row of reference units in the reference module according to the predetermined logic instruction, wherein the corresponding column data and the at least one row of reference units each comprise a standard unit resistance, and the at least one row of reference units comprises a high-resistance unit and a low-resistance unit; outputting a logic result by the operation module according to data voltage information of the corresponding column data and reference voltage information of the at least one reference unit, and executing the predetermined logic instruction according to the logic result, wherein the reference voltage information comprises high-resistance reference voltage information and low-resistance reference voltage information.

5. The data processing method of an in-memory computing circuit structure according to claim 4, characterized by, The method comprises: pre-setting resistance state information of each standard unit resistance in each reference unit.

6. The data processing method of an in-memory computing circuit structure according to claim 4, wherein, After receiving the predetermined logic instruction, the method further comprises: According to the current flowing into the corresponding column data, the corresponding column data outputs data voltage information; According to the current flowing into the at least one reference cell, the reference module outputs reference voltage information.

7. The data processing method of an in-memory computing circuit structure according to claim 6, wherein, According to the data voltage information of the corresponding column data and the reference voltage information of the at least one reference cell, the operation module outputs a logic result comprising: According to the resistance state information of the corresponding column data, the data voltage information, the resistance state information of the at least one reference cell and the reference voltage information, the operation module outputs a logic result.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the steps of the method of any one of claims 4 to 7 when executing the program.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program implements the steps of the method of any one of claims 4 to 7 when executed by the processor.

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