Memory device for outputting data and method of operating the same

Abstract

The invention relates to a memory device for outputting data and a method of operating the memory device. The memory device includes a cache latch group including a plurality of cache latches arranged in sequence, in which a plurality of odd-numbered cache latches and a plurality of even-numbered cache latches included in the plurality of cache latches are alternately arranged. The memory device also includes a sense amplifier configured to be alternately coupled to the plurality of odd-numbered cache latches through the first bit output line group and to the plurality of even-numbered cache latches through the second bit output line group. The memory device also includes a bit output line selection circuit configured to alternately couple the sense amplifier to the first bit output line group and the second bit output line group in response to a bit output line selection signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0099813 filed on July 31, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to a semiconductor device, and more particularly, to a memory device for outputting read data to the outside of the memory device and a method of operating the memory device. Background Art

[0004] Memory devices may be devices that store data, and they may be classified as volatile memory devices or nonvolatile memory devices.

[0005] The memory device may perform a read operation of reading data stored in the memory cell. In addition, the memory device may perform a data output operation of outputting the read data to an external device. For example, the read data may be stored in a cache latch, and the data stored in the cache latch may be output to a bit output line. A sense amplifier may sense data based on a voltage difference between bit output lines, and may output the sensed data to a data input / output line.

[0006] On the other hand, in the process of outputting data, the bit output line may be developed for a certain time to increase the voltage difference. After the sense amplifier senses the voltage difference, the bit output line may maintain a voltage level corresponding to the precharge voltage according to the precharge operation. Summary of the invention

[0007] The embodiment of the present disclosure relates to a memory device. The memory device may include: a cache latch group including a plurality of cache latches arranged in sequence, wherein a plurality of odd cache latches and a plurality of even cache latches included in the plurality of cache latches are arranged alternately; a sense amplifier configured to be alternately connected to the plurality of odd cache latches through a first bit output line group and to the plurality of even cache latches through a second bit output line group; and a bit output line selection circuit configured to alternately connect the sense amplifier to the first bit output line group and the second bit output line group in response to a bit output line selection signal.

[0008] Embodiments of the present disclosure relate to another memory device. The memory device may include: a plurality of odd cache latches configured to output data to a first bit output line group; a plurality of even cache latches configured to output data to a second bit output line group, wherein each even cache latch in the plurality of even cache latches is arranged alternately with each odd cache latch in the plurality of odd cache latches; a sense amplifier configured to be alternately connected to the first bit output line group and the second bit output line group and configured to output data obtained by sensing and amplifying a voltage difference of the connected first bit output line group or the connected second bit output line group to a data input / output line; a first precharge circuit configured to precharge the first bit output line group while the sense amplifier is connected to the second bit output line group; and a second precharge circuit configured to precharge the second bit output line group while the sense amplifier is connected to the first bit output line group.

[0009] Embodiments of the present disclosure may provide a method for operating a memory device. The method may include: connecting an odd cache latch to a first bit output line group in response to a first column selection signal; and connecting the first bit output line group to a sense amplifier in response to a first bit output line selection signal; sensing a voltage difference of the first bit output line group through the sense amplifier in response to a strobe signal; outputting first data obtained based on sensing the voltage difference of the first bit output line group to a data input / output line; activating a precharge operation on the first bit output line group; connecting an even cache latch to a second bit output line group in response to a second column selection signal; connecting the second bit output line group to the sense amplifier in response to a second bit output line selection signal; sensing a voltage difference of the second bit output line group through the sense amplifier in response to a strobe signal; outputting second data obtained based on sensing the voltage difference of the second bit output line group to the data input / output line; and stopping the precharge operation on the first bit output line group. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram illustrating an example of a memory device outputting data according to an embodiment of the present disclosure.

[0012] Figure 3 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0013] Figure 4 is a diagram illustrating a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are provided as examples to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0015] Various embodiments of the present disclosure are directed to a memory device capable of increasing a time for performing a precharge operation on a bit output line and a method of operating the memory device.

[0016] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0017] Reference Figure 1 , the memory device 100 may include a cache latch group 110 , a sense amplifier (senseamp) 120 , a bit output line selection circuit 130 , a first precharge circuit 141 , and a second precharge circuit 142 .

[0018] The cache latch group 110 may include a plurality of cache latches CL1 to CL8 that are sequentially arranged.

[0019] The plurality of cache latches CL1 to CL8 may temporarily store data read from memory cells.

[0020] In an embodiment, the plurality of cache latches CL1 to CL8 may include a plurality of odd cache latches CL1, CL3, CL5 and CL7 and a plurality of even cache latches CL2, CL4, CL6 and CL8. The plurality of odd cache latches CL1, CL3, CL5 and CL7 and the plurality of even cache latches CL2, CL4, CL6 and CL8 may be arranged alternately.

[0021] In an embodiment, the plurality of odd cache latches CL1, CL3, CL5, and CL7 may be latches arranged at odd positions among the plurality of cache latches CL1 to CL8. The plurality of odd cache latches CL1, CL3, CL5, and CL7 may be coupled to the first bit output line group. The plurality of odd cache latches CL1, CL3, CL5, and CL7 may output stored data to the first bit output line group.

[0022] The first bit output line group may include a first bit output line BOL1 and a first bar bit output line BOLb1.

[0023] In an embodiment, the first bit output line group may be coupled to an odd cache latch selected from among a plurality of odd cache latches CL1, CL3, CL5, and CL7 in response to a corresponding one of column selection signals CS1 to CS8. For example, when the column selection signal CS1 for selecting the first cache latch CL1 is input, the first bit output line group may be coupled to the first cache latch CL1. The remaining odd cache latches CL3, CL5, and CL7 may be coupled to the first bit output line group in the same manner as the first cache latch CL1.

[0024] In an embodiment, the plurality of even cache latches CL2, CL4, CL6, and CL8 may be latches arranged at even positions among the plurality of cache latches CL1 to CL8. The plurality of even cache latches CL2, CL4, CL6, and CL8 may be coupled to the second bit output line group.

[0025] The second bit output line group may include a second bit output line BOL2 and a second bar bit output line BOLb2.

[0026] In an embodiment, the second bit output line group may be coupled to an even cache latch selected from among a plurality of even cache latches CL2, CL4, CL6, and CL8 in response to a corresponding one of column selection signals CS1 to CS8. For example, when the column selection signal CS2 for selecting the second cache latch CL2 is input, the second bit output line group may be coupled to the second cache latch CL2. The remaining even cache latches CL4, CL6, and CL8 may be coupled to the second bit output line group in the same manner as the second cache latch CL2.

[0027] In an embodiment, a plurality of odd cache latches CL1, CL3, CL5 and CL7 and a plurality of even cache latches CL2, CL4, CL6 and CL8 may be selected in sequence in the order in which they are arranged. For example, in response to column selection signals CS1 to CS8, the cache latches may be selected in sequence in the order of the first cache latch CL1 to the eighth cache latch CL8.

[0028] On the other hand, although Figure 1 , the number of cache latches is described as 8, but the present disclosure is not limited thereto. For example, the number of cache latches may be set to be less than 8 or greater than 8.

[0029] The sense amplifier 120 may be coupled to the plurality of odd cache latches CL1, CL3, CL5, and CL7 through a first bit output line group, or may be coupled to the plurality of even cache latches CL2, CL4, CL6, and CL8 through a second bit output line group.

[0030] The sense amplifier 120 may output data obtained by sensing and amplifying the voltage difference of the first bit output line group or the second bit output line group to the data input / output line DL in response to the strobe signal IOSTB. For example, when the sense amplifier 120 is connected to the first bit output line group, the sense amplifier 120 may output first data obtained by sensing and amplifying the voltage difference of the first bit output line group in response to the strobe signal IOSTB. When the sense amplifier 120 is connected to the second bit output line group, the sense amplifier 120 may output second data obtained by sensing and amplifying the voltage difference of the second bit output line group in response to the strobe signal IOSTB.

[0031] In an embodiment, the sense amplifier 120 may alternately sense a voltage difference of a first bit output line group and a voltage difference of a second bit output line group.

[0032] The bit output line selection circuit 130 may connect the sense amplifier 120 to the first bit output line group when the first bit output line selection signal SEL1 is activated. Further, the bit output line selection circuit 130 may connect the sense amplifier 120 to the second bit output line group when the second bit output line selection signal SEL2 is activated. In this way, the sense amplifier may be alternately connected to the first bit output line group or the second bit output line group depending on which of the first bit output line selection signal SEL1 or the second bit output line selection signal SEL2 is activated.

[0033] In an embodiment, the bit output line selection circuit 130 may alternately couple the sense amplifier 120 to the first bit output line group and the second bit output line group in response to the bit output line selection signals SEL1 and SEL2 .

[0034] After sensing the voltage difference of the first bit output line group, the first precharge circuit 141 may precharge the first bit output line group in response to a first precharge signal.

[0035] In an embodiment, the first precharge circuit 141 may start precharging the first bit output line group after outputting the first data in response to the strobe signal IOSTB.

[0036] In an embodiment, when the sense amplifier 120 is coupled to the second bit output line group, the first precharge circuit 141 may additionally precharge the first bit output line group.

[0037] After sensing the voltage difference of the second bit output line group, the second precharge circuit 142 may precharge the second bit output line group in response to a second precharge signal.

[0038] In an embodiment, the second precharge circuit 142 may start precharging the second bit output line group after outputting the second data in response to the strobe signal IOSTB.

[0039] In an embodiment, when the sense amplifier 120 is coupled to the first bit output line group, the second precharge circuit 142 may additionally precharge the second bit output line group.

[0040] Figure 2 is a diagram showing an example of a memory device outputting data according to an embodiment of the present disclosure. Figure 2 In the example of outputting the data stored in the first to fourth cache latches CL1 to CL4 for convenience of description, the description of the first to fourth cache latches CL1 to CL4 can be applied to the fifth to eighth cache latches CL5 to CL8 in the same manner.

[0041] Reference Figure 2 , at time T0, the first column selection signal CS1 may be activated. Therefore, the first cache latch CL1 may be coupled to the first bit output line group.

[0042] Further, the first bit output line selection signal SEL1 may be activated. Therefore, the sense amplifier 120 may be coupled to the first cache latch CL1 through the first bit output line group.

[0043] The first bit output line group may be developed for a certain period of time. The development operation (Develop Operation, DVL) may be an operation of increasing the voltage difference between the first bit output line BOL1 and the first inverted bit output line BOLb1. The development operation (DVL) for the first bit output line group may be performed when the first column selection signal CS1 is activated.

[0044] At time T1 , the first column selection signal CS1 may be deactivated.

[0045] Further, the strobe signal IOSTB may be activated. Therefore, the sense amplifier 120 may sense the voltage difference of the developed first bit output line group. The sense amplifier 120 may output the first data DATA1 to the data input / output line DL based on the sensed voltage difference.

[0046] In addition, the first precharge signal PRE1 may be turned to a low level. The first precharge circuit 141 may start precharging the first bit output line group in response to the first precharge signal PRE1. For example, the first precharge circuit 141 may apply a preset precharge voltage to the first bit output line BOL1 and the first inverted bit output line BOLb1. The first bit output line BOL1 and the first inverted bit output line BOLb1 may be precharged to a voltage level corresponding to the precharge voltage.

[0047] At time T2, the second column selection signal CS2 may be activated. Thus, the second cache latch CL2 may be coupled to the second bit output line group.

[0048] Furthermore, the first bit output line selection signal SEL1 may be inactivated and the second bit output line selection signal SEL2 may be activated. Therefore, the sense amplifier 120 may be separated from the first bit output line group and coupled to the second cache latch CL2 through the second bit output line group.

[0049] The second bit output line group may be expanded for a certain period of time. The voltage difference between the second bit output line BOL2 and the second inverted bit output line BOLb2 may increase. The expansion operation (DVL) for the second bit output line group may be performed while the second column selection signal CS2 is activated.

[0050] In addition, when the sense amplifier 120 is connected to the second bit output line group, the first precharge circuit 141 can additionally precharge the first bit output line group. That is, because the first bit output line group is disconnected from the sense amplifier 120, the first bit output line group can continue to be precharged. Therefore, the time for precharging the first bit output line group can be increased, and the sensing margin corresponding to the voltage difference of the first bit output line group can be improved.

[0051] At time T3 , the second column select signal CS2 may be inactivated.

[0052] Further, the strobe signal IOSTB may be activated. Therefore, the sense amplifier 120 may sense the voltage difference of the developed second bit output line group. The sense amplifier 120 may output the second data DATA2 to the data input / output line DL based on the sensed voltage difference.

[0053] In addition, the second precharge signal PRE2 may be turned into a low level. The second precharge circuit 142 may start precharging the second bit output line group in response to the second precharge signal PRE2. For example, the second precharge circuit 142 may apply a preset precharge voltage to the second bit output line BOL2 and the second inverted bit output line BOLb2. The second bit output line BOL2 and the second inverted bit output line BOLb2 may be precharged to a voltage level corresponding to the precharge voltage.

[0054] At time T4, the first precharge signal PRE1 may be turned to a high level. Therefore, the first precharge circuit 141 may stop supplying the precharge voltage to the first bit output line group.

[0055] The third column selection signal CS3 may be activated. Therefore, the third cache latch CL3 may be coupled to the first bit output line group.

[0056] Furthermore, the second bit output line selection signal SEL2 may be inactivated and the first bit output line selection signal SEL1 may be activated. Therefore, the sense amplifier 120 may be separated from the second bit output line group and coupled to the third cache latch CL3 through the first bit output line group.

[0057] The first bit output line group may be expanded for a certain period of time. The voltage difference between the first bit output line BOL1 and the first inverted bit output line BOLb1 may increase. The expansion operation (DVL) for the first bit output line group may be performed while the third column selection signal CS3 is activated.

[0058] In addition, when the sense amplifier 120 is connected to the first bit output line group, the second precharge circuit 142 can additionally precharge the second bit output line group. That is, because the second bit output line group is disconnected from the sense amplifier 120, the second bit output line group can continue to be precharged. Therefore, the time for precharging the second bit output line group can be increased, and the sensing margin corresponding to the voltage difference of the second bit output line group can be improved.

[0059] At time T5 , the third column select signal CS3 may be inactivated.

[0060] Further, the strobe signal IOSTB may be activated. Therefore, the sense amplifier 120 may sense the voltage difference of the developed first bit output line group. The sense amplifier 120 may output the third data DATA3 to the data input / output line DL based on the sensed voltage difference.

[0061] In addition, the first precharge signal PRE1 may be turned to a low level. The first precharge circuit 141 may start precharging the first bit output line group in response to the first precharge signal PRE1. For example, the first precharge circuit 141 may apply a preset precharge voltage to the first bit output line BOL1 and the first inverted bit output line BOLb1. The first bit output line BOL1 and the first inverted bit output line BOLb1 may be precharged to a voltage level corresponding to the precharge voltage.

[0062] At time T6, the second precharge signal PRE2 may be turned to a high level. Thus, the second precharge circuit 142 may stop supplying the precharge voltage to the second bit output line group.

[0063] The fourth column selection signal CS4 may be activated. Therefore, the fourth cache latch CL4 may be coupled to the second bit output line group.

[0064] Furthermore, the first bit output line selection signal SEL1 may be inactivated and the second bit output line selection signal SEL2 may be activated. Therefore, the sense amplifier 120 may be separated from the first bit output line group and coupled to the fourth cache latch CL4 through the second bit output line group.

[0065] The second bit output line group may be expanded for a certain period of time. The voltage difference between the second bit output line BOL2 and the second inverted bit output line BOLb2 may increase. The expansion operation (DVL) for the second bit output line group may be performed while the fourth column selection signal CS4 is activated.

[0066] In addition, when the sense amplifier 120 is connected to the second bit output line group, the first precharge circuit 141 can additionally precharge the first bit output line group. That is, because the first bit output line group is disconnected from the sense amplifier 120, the first bit output line group can continue to be precharged.

[0067] At time T7 , the fourth column select signal CS4 may be inactivated.

[0068] Further, the strobe signal IOSTB may be activated. Therefore, the sense amplifier 120 may sense the voltage difference of the developed second bit output line group. The sense amplifier 120 may output the fourth data DATA4 to the data input / output line DL based on the sensed voltage difference.

[0069] In addition, the second precharge signal PRE2 may be turned into a low level. The second precharge circuit 142 may start precharging the second bit output line group in response to the second precharge signal PRE2. For example, the second precharge circuit 142 may apply a preset precharge voltage to the second bit output line BOL2 and the second inverted bit output line BOLb2. The second bit output line BOL2 and the second inverted bit output line BOLb2 may be precharged to a voltage level corresponding to the precharge voltage.

[0070] At time T8, the first precharge signal PRE1 may be turned to a high level. Therefore, the first precharge circuit 141 may stop supplying the precharge voltage to the first bit output line group.

[0071] Furthermore, the second-bit output line selection signal SEL2 may be inactivated, and the first-bit output line selection signal SEL1 may be activated.

[0072] In addition, when the sense amplifier 120 is connected to the first bit output line group, the second precharge circuit 142 can additionally precharge the second bit output line group. That is, because the second bit output line group is disconnected from the sense amplifier 120, the second bit output line group can continue to be precharged.

[0073] Figure 3 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0074] Figure 3 The method shown can be accomplished, for example, by Figure 1 The memory device shown is used for execution.

[0075] Reference Figure 3 , in step S301, the memory device 100 may couple the odd cache latches to the first bit output line group in response to a first column selection signal.

[0076] In step S303 , the memory device 100 may couple the first bit output line group to the sense amplifier 120 in response to the first bit output line selection signal.

[0077] In step S305 , the memory device 100 may sense a voltage difference of the first bit output line group through the sense amplifier 120 in response to the strobe signal IOSTB.

[0078] In step S307 , the memory device 100 may output first data obtained based on the voltage difference of the first bit output line group to the data input / output line DL.

[0079] In step S309 , the memory device 100 may activate a precharge operation on the first bit output line group.

[0080] Here, the memory device 100 may apply a precharge voltage to the first bit output line group.

[0081] In step S311 , the memory device 100 may couple the even-numbered cache latches to the second bit output line group in response to the second column selection signal.

[0082] In step S313, the memory device 100 may couple the second bit output line group to the sense amplifier 120 in response to the second bit output line selection signal. In an embodiment, the sense amplifier 120 is separated from the first bit output line group when coupled to the second bit output line group. Further, the sense amplifier 120 is separated from the second bit output line group when coupled to the first bit output line group.

[0083] In step S315 , the memory device 100 may sense a voltage difference of the second bit output line group through the sense amplifier 120 in response to the strobe signal IOSTB.

[0084] In step S317 , the memory device 100 may output second data obtained based on the voltage difference of the second bit output line group to the data input / output line DL.

[0085] In step S319 , the memory device 100 may stop the precharge operation on the first bit output line group.

[0086] Here, the memory device 100 may stop supplying the precharge voltage to the first bit output line group before inactivating the second bit output line selection signal.

[0087] Figure 4 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0088] Reference Figure 4 , the memory device 1000 may include a memory cell array 1100 , a peripheral circuit 1200 , and a control logic 1300 .

[0089] The memory cell array 1100 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be coupled to a row decoder 1210 through row lines RL. The plurality of memory blocks BLK1 to BLKz may be coupled to a page buffer group 1230 through bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells storing data. Each of the memory cells may store one or more data bits.

[0090] The peripheral circuit 1200 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLm or release the applied voltages under the control of the control logic 1300 .

[0091] The peripheral circuit 1200 may include a row decoder 1210 , a voltage generator 1220 , a page buffer group 1230 , a column decoder 1240 , an input / output circuit 1250 , and a sensing circuit 1260 .

[0092] The row decoder 1210 may decode the row address RADD received from the control logic 1300. The row decoder 1210 selects at least one of the memory blocks BLK1 to BLKz according to the decoded address. Further, the row decoder 1210 may select at least one word line of the selected memory block according to the decoded address so as to apply the voltage generated by the voltage generator 1220 to the at least one word line.

[0093] The voltage generator 1220 may generate various operation voltages Vop such as a read voltage, a program voltage, a verification voltage, and a pass voltage using an external power supply voltage supplied to the memory device 1000 .

[0094] The page buffer group 1230 may include a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm may temporarily store data received through the plurality of bit lines BL1 to BLm in response to a page buffer control signal PBSIGNALS. For example, the plurality of page buffers PB1 to PBm may temporarily store result values ​​obtained by sensing a voltage or current of the bit lines BL1 to BLm through a read operation. In this case, each of the plurality of page buffers PB1 to PBm may include a cache latch configured to temporarily store data. The cache latch may be Figure 1 Any one of the plurality of cache latches CL1 to CL8 shown.

[0095] In an embodiment, the plurality of page buffers PB1 to PBm may include a plurality of odd page buffers and a plurality of even page buffers. The plurality of odd page buffers may be page buffers arranged at odd positions and may be connected to the first bit output line among the bit output lines BOL. The plurality of even page buffers may be page buffers arranged at even positions and may be connected to the second bit output line among the bit output lines BOL.

[0096] The column decoder 1240 may transfer data between the page buffer group 1230 and the input / output circuit 1250 in response to the column address CADD.

[0097] In an embodiment, the column decoder 1240 may include a signal generator 1241, a sense amplifier 1242, a bit output line selection circuit 1243, and a precharge circuit group 1244. The sense amplifier 1242, the bit output line selection circuit 1243, and the precharge circuit group 1244 may correspond to Figure 1The sense amplifier 120, the bit output line selection circuit 130, the first precharge circuit 141 and the second precharge circuit 142.

[0098] The signal generator 1241 can generate a column selection signal CS <m:0>, for selecting a page buffer to output data from among the plurality of page buffers PB1 to PBm in response to the column address CADD. Therefore, the page buffer selected from among the plurality of page buffers PB1 to PBm may be connected to the bit output line BOL. The bit output line BOL may include the above reference Figure 1 Describe the first bit output line group and the second bit output line group.

[0099] Further, the signal generator 1241 may generate a strobe signal IOSTB for instructing the sense amplifier 1242 to sense the voltage difference of the bit output line BOL. The sense amplifier 1242 may sense the voltage difference of the bit output line BOL in response to the strobe signal.

[0100] In addition, the signal generator 1241 may generate a bit output line selection signal SEL for selecting the bit output line BOL connected to the sense amplifier 1242. The bit output line selection circuit 1243 may connect the bit output line BOL selected in response to the bit output line selection signal SEL to the sense amplifier 1242. In an embodiment, the bit output line selection circuit 1243 may alternately connect the sense amplifier 1242 to the first bit output line and the second bit output line among the bit output lines BOL.

[0101] Moreover, the signal generator 1241 may generate a precharge signal PRE indicating that the bit output line BOL is precharged. The precharge circuit group 1244 may precharge the bit output line BOL in response to the precharge signal PRE. In an embodiment, the first precharge circuit included in the precharge circuit group 1244 may precharge the first bit output line while the sense amplifier 1242 is coupled to the second bit output line. Further, the second precharge circuit included in the precharge circuit group 1244 may precharge the second bit output line while the sense amplifier 1242 is coupled to the first bit output line.

[0102] The input / output circuit 1250 may transfer a command CMD and an address ADD received from an external memory controller (not shown) to the control logic 1300 , or may exchange data DATA with the column decoder 1240 .

[0103] During a verification operation, the sensing circuit 1260 may generate a reference current in response to an enable bit signal VRYBIT, and may compare a sensing voltage VPB received from the page buffer group 1230 with a reference voltage generated by the reference current, and then output a pass signal PASS or a fail signal FAIL.

[0104] The control logic 1300 may control the peripheral circuit 1200 by outputting an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit signal VRYBIT in response to a command CMD and an address ADDR. In addition, the control logic 1300 may determine whether the verification operation is passed or failed in response to a pass signal PASS or a fail signal FAIL. The control logic 1300 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 1300 may be a control logic circuit according to an algorithm operation and / or a processor that executes a control logic code.

[0105] Teachings of the present disclosure include a memory device having improved sensing margin corresponding to a voltage difference between bit output lines and a method of operating the memory device.

Claims

1. A memory device, comprising: A cache latch group, comprising a plurality of cache latches arranged in sequence, wherein a plurality of odd-numbered cache latches and a plurality of even-numbered cache latches included in the plurality of cache latches are arranged alternately; a sense amplifier alternately coupled to the plurality of odd cache latches via a first bit output line group and to the plurality of even cache latches via a second bit output line group; and The bit output line selection circuit alternately connects the sense amplifier to the first bit output line group and the second bit output line group in response to a bit output line selection signal.

2. The memory device according to claim 1, wherein: The memory device enables: The first bit output line group is coupled to an odd cache latch selected from among the plurality of odd cache latches in response to a column selection signal, and The second bit output line group is coupled to an even cache latch selected from the plurality of even cache latches in response to the column selection signal.

3. The memory device according to claim 2, wherein: The plurality of odd-numbered cache latches and the plurality of even-numbered cache latches are sequentially selected in an arrangement order.

4. The memory device according to claim 1, wherein: The sense amplifier outputs data obtained by sensing and amplifying a voltage difference of the first bit output line group or the second bit output line group to a data input / output line in response to a strobe signal.

5. The memory device according to claim 4, wherein: The sense amplifier alternately senses a voltage difference of the first bit output line group and a voltage difference of the second bit output line group.

6. The memory device of claim 5, further comprising: a first precharge circuit that precharges the first bit output line group after sensing a voltage difference of the first bit output line group in response to the strobe signal; as well as The second precharge circuit precharges the second bit output line group after sensing a voltage difference of the second bit output line group in response to the strobe signal.

7. The memory device according to claim 6, wherein: The first precharge circuit also precharges the first bit output line group while the sense amplifier is coupled to the second bit output line group, and The second precharge circuit also precharges the second bit output line group while the sense amplifier is coupled to the first bit output line group.

8. A memory device comprising: a plurality of odd-numbered cache latches for outputting data to a first bit output line group; a plurality of even cache latches, outputting the data to a second bit output line group, each of the plurality of even cache latches being arranged alternately with each of the plurality of odd cache latches; a sense amplifier alternately connected to the first bit output line group and the second bit output line group, and outputting data obtained by sensing and amplifying a voltage difference of the connected first bit output line group or the connected second bit output line group to a data input / output line; a first precharge circuit for precharging the first bit output line group while the sense amplifier is coupled to the second bit output line group; as well as A second precharge circuit precharges the second bit output line group while the sense amplifier is coupled to the first bit output line group.

9. The memory device of claim 8, further comprising: The bit output line selection circuit connects the sense amplifier to the first bit output line group while a first bit output line selection signal is activated, and connects the sense amplifier to the second bit output line group while a second bit output line selection signal is activated.

10. The memory device according to claim 9, wherein: The sense amplifier, when connected to the first bit output line group, outputs first data obtained by sensing and amplifying a voltage difference of the first bit output line group in response to a strobe signal.

11. The memory device according to claim 10, wherein: The first precharge circuit starts precharging the first bit output line group after outputting the first data in response to the strobe signal.

12. The memory device according to claim 9, wherein: The sense amplifier, when connected to the second bit output line group, outputs second data obtained by sensing and amplifying a voltage difference of the second bit output line group in response to a strobe signal.

13. The memory device according to claim 12, wherein: The second precharge circuit starts precharging the second bit output line group after outputting the second data in response to the strobe signal.

14. A method of operating a memory device, comprising: coupling the odd cache latches to a first bit output line group in response to a first column select signal; coupling the first bit output line group to a sense amplifier in response to a first bit output line selection signal; In response to a strobe signal, sensing a voltage difference of the first bit output line group through the sense amplifier; outputting first data obtained based on sensing a voltage difference of the first bit output line group to a data input / output line; activating a precharge operation on the first bit output line group; coupling the even cache latches to a second set of bit output lines in response to a second column select signal; coupling the second bit output line group to the sense amplifier in response to a second bit output line selection signal; In response to the strobe signal, sensing a voltage difference of the second bit output line group through the sense amplifier; outputting second data obtained based on sensing a voltage difference of the second bit output line group to the data input / output line; and The precharge operation on the first bit output line group is stopped.

15. The method according to claim 14, wherein: Activating the precharge operation includes: A precharge voltage is applied to the first bit output line group.

16. The method according to claim 15, wherein: Stopping the pre-charging operation includes: Before the second bit output line selection signal is inactivated, supply of the precharge voltage to the first bit output line group is stopped.

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