Hybrid memory chip, and memory system and computing device comprising hybrid memory chip

Abstract

The invention provides a hybrid memory chip, a memory system comprising the hybrid memory chip and a computing device. The hybrid memory chip includes: a plurality of dynamic random access memory (DRAM) arrays; a plurality of sense amplifier arrays adjacent to the plurality of dynamic random access memory arrays; and a plurality of static random access memory (SRAM) arrays adjacent to the plurality of dynamic random access memory arrays or the plurality of sense amplifier arrays, and each of the plurality of static random access memory (SRAM) arrays is respectively adjacent to one of the plurality of sense amplifier arrays. The plurality of sense amplifier arrays are configured to perform access operations between the plurality of dynamic random access memory arrays and the plurality of static random access memory arrays.

Description

Technical Field

[0001] The present invention relates to a memory chip and a memory system and a computing device including the memory chip, and more particularly, to a hybrid memory chip and a memory system and a computing device including the hybrid memory chip. Background Art

[0002] In reality, a memory system is a hierarchical structure consisting of multiple storage devices with different capacities, costs, and access times. Figure 1 As shown, a small, fast cache memory C102 (e.g., static random access memory (SRAM)) integrated into a processor chip C104 with a central processing unit (CPU) C100 serves as a staging area for a subset of data and instructions stored in a relatively slow main memory C106. The main memory C106 is used to temporarily store data stored on large, slow disks.

[0003] On the other hand, the system bus C110 is used to transfer data between storage devices at different levels (e.g., cache memory C102 and main memory C106). As the CPU C100 and the storage devices process more data, the data transfer speed via the system bus C110 becomes insufficient and has become the bottleneck of the entire computing system. No matter how fast the CPU can work, the CPU will be limited by the transfer speed allowed by the system bus.

[0004] As a frequently accessed storage device, the main memory C106 (e.g., dynamic random access memory (DRAM)) includes a memory array / core circuit C112 and peripheral circuits (e.g., an address decoder, an instruction decoder, a word line driver C114, a sense amplifier array C116, and other devices). Each memory cell in the memory array C112 is addressed at the intersection of a bit line BL and a word line WL. The word line WL extends along a first direction to the word line driver C114, and the bit line BL can extend along a second direction to the sense amplifier array C116, and the data stored in the memory cell can be read out by the sense amplifier in the sense amplifier array C116.

[0005] On the other hand, storage memory plays a key role in high performance computing (HPC) and artificial intelligence (AI) applications. It is crucial to provide efficient and fast storage memory for HPC and AI. Summary of the invention

[0006] In one aspect of the present disclosure, a hybrid memory chip is provided. The hybrid memory chip includes: a plurality of dynamic random access memory arrays; a plurality of sense amplifier arrays adjacent to the plurality of dynamic random access memory arrays; and a plurality of static random access memory arrays adjacent to the plurality of dynamic random access memory arrays or the plurality of sense amplifier arrays, and each of the plurality of static random access memory arrays is respectively adjacent to one of the plurality of sense amplifier arrays, wherein the plurality of sense amplifier arrays are configured to perform access operations between the plurality of dynamic random access memory arrays and the plurality of static random access memory arrays.

[0007] In some embodiments, the bit lines across the plurality of dynamic random access memory arrays extend through the plurality of sense amplifier arrays and the plurality of static random access memory arrays. The plurality of static random access memory arrays are configured to be written with data stored in the plurality of dynamic random access memory arrays through the bit lines, or the plurality of dynamic random access memory arrays are configured to be written with data stored in the plurality of static random access memory arrays through the bit lines.

[0008] In some embodiments, the hybrid memory chip further includes: a word line driver adjacent to the multiple dynamic random access memory arrays, the multiple sense amplifier arrays and the multiple static random access memory arrays, wherein word lines spanning the multiple dynamic random access memory arrays and the multiple static random access memory arrays extend to the word line driver.

[0009] In some embodiments, the plurality of dynamic random access memory arrays, the plurality of static random access memory arrays, the plurality of sense amplifier arrays, and the word line driver are configured to perform a copy operation that copies data stored in a single cell of one of the plurality of dynamic random access memory arrays to a single cell of one of the plurality of static random access memory arrays, or copies data stored in a single cell of one of the plurality of static random access memory arrays to a single cell of one of the plurality of dynamic random access memory arrays.

[0010] In some embodiments, the plurality of dynamic random access memory arrays, the plurality of static random access memory arrays, the plurality of sense amplifier arrays, and the word line driver are configured to perform a copy operation, wherein the copy operation copies a series of data stored in a plurality of cells of one of the plurality of dynamic random access memory arrays to a plurality of cells of one of the plurality of static random access memory arrays, or copies a series of data stored in a plurality of cells of one of the plurality of static random access memory arrays to a plurality of cells of one of the plurality of dynamic random access memory arrays.

[0011] In some embodiments, during the copy operation, a series of data stored in a column of cells of one of the plurality of dynamic random access memory arrays is copied to a column of cells of one of the plurality of static random access memory arrays, or during the copy operation, a series of data stored in a column of cells of one of the plurality of static random access memory arrays is copied to a column of cells of one of the plurality of dynamic random access memory arrays.

[0012] In some embodiments, two adjacent dynamic random access memory arrays among the multiple dynamic random access memory arrays are spaced apart from each other, and one sense amplifier array among the multiple sense amplifier arrays and one static random access memory array among the multiple static random access memory arrays are arranged between the two adjacent dynamic random access memory arrays.

[0013] In some embodiments, two adjacent dynamic random access memory arrays among the multiple dynamic random access memory arrays are spaced apart from each other, and one sense amplifier array among the multiple sense amplifier arrays and two static random access memory arrays among the multiple static random access memory arrays are arranged between the two adjacent dynamic random access memory arrays.

[0014] In some embodiments, each of the plurality of sense amplifier arrays is sandwiched between two SRAM arrays of the plurality of SRAM arrays.

[0015] In another aspect of the present disclosure, a memory system is provided. The memory system includes: a first primary memory, integrated with a central processing unit in a processor chip, and including a first static random access memory array; a second primary memory, located outside the processor chip and including a second static random access memory array; and a main memory, including a dynamic random access memory array and integrated with the second primary memory in a hybrid memory chip.

[0016] In some embodiments, the second primary memory is configured to store data provided from the main memory, and is configured to enable data transfer between the second primary memory and the main memory without using an external bus extending between the processor chip and the hybrid memory chip.

[0017] In some embodiments, the second SRAM array of the second primary memory is disposed in the hybrid memory chip adjacent to a sense amplifier array surrounding the DRAM array of the main memory.

[0018] In some embodiments, a bit line across the DRAM array of the main memory extends through the sense amplifier array and the second SRAM array of the second primary memory.

[0019] In another aspect of the present disclosure, a computing device is provided, comprising: a processor chip integrating a central processing unit and a first primary memory, wherein the first primary memory comprises a first static random access memory array; and a hybrid memory chip connected to the processor chip via an external bus, wherein a second primary memory and a main memory are integrated into the hybrid memory chip, wherein the second primary memory comprises a second static random access memory array, and the main memory is formed by a dynamic random access memory array.

[0020] In some embodiments, the second primary memory is configured to store data provided from the main memory, and is configured to enable data transfer between the second primary memory and the main memory without using the external bus.

[0021] In order to make the above content easier to understand, several embodiments are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0023] Figure 1 is a schematic diagram showing a portion of a conventional memory system.

[0024] Figure 2 is a schematic diagram showing a memory array surrounded by word line decoders and sense amplifiers in a conventional memory system.

[0025] Figure 3A is a schematic diagram showing a portion of a memory system according to some embodiments of the present disclosure, and Figure 3BThe configuration of the DRAM array and the SRAM array in the hybrid memory chip of the memory system and the data transmission between the two are schematically illustrated.

[0026] Figure 4A is a schematic diagram showing a hybrid memory chip according to some embodiments of the present disclosure, and Figure 4B The configuration of the DRAM array and the SRAM array in the hybrid memory chip of the memory system and the data transmission between the two are schematically illustrated. DETAILED DESCRIPTION

[0027] Embodiments of the present disclosure provide a solution for overcoming the memory bottleneck caused by slow data transfer on a system bus.

[0028] Figure 3A is a schematic diagram showing a portion of a memory system 10 according to some embodiments of the present disclosure.

[0029] Memory System 10( Figure 3A 100 . The primary memory 102 (also referred to as primary memory 102a) is a hierarchical structure based on the speed, cost and capacity of each memory device therein. This hierarchical structure is essentially used to configure the memory devices in a manner that minimizes data access time, thereby improving the performance of the computing device. At the top of the memory hierarchy, the primary memory 102 (e.g., SRAM) has the highest speed and can store a small amount of data and instructions that are most frequently used. The first portion of the primary memory 102 (also referred to as primary memory 102a) can be integrated with the CPU 100 in the processor chip 104, which can be provided by an application specific integrated chip (ASIC). In this way, communication between the primary memory 102a and the CPU 100 can be efficiently implemented by the internal routing of the processor chip 104. In addition, as will be described in more detail, the second portion of the primary memory 102 (also referred to as primary memory 102b) is integrated with the main memory 106 (e.g., DRAM) in a hybrid memory chip 108 to avoid the need to use inter-chip communication to achieve data transmission between the two.

[0030] The data and instructions temporarily stored by the primary memory 102 are provided by the main memory 106. Compared with the primary memory 102, the main memory 106 has a larger storage capacity and is generally slower. In the case where both the primary memory 102 and the main memory 106 are volatile memories, the primary memory 102 is provided by static random access memory (SRAM) and the main memory 106 is provided by dynamic random access memory (DRAM). In other words, the hybrid memory chip 108 including both the main memory 106 and the primary memory 102b integrates DRAM and SRAM.

[0031] Since the primary memory 102b and the main memory 106 are configured in the same chip, the primary memory 102b can communicate with the slower main memory 106 via an in-chip data path that is much shorter than an inter-chip data path. Therefore, data transfer between the primary memory 102 and the slower main memory 106 can be achieved with the shortest delay. On the other hand, the primary memory 102b in the hybrid memory chip 108 can communicate with the primary memory 102a in the processor chip 104 via an inter-chip data path provided by the external bus 110. Nevertheless, since frequent communication with the slow main memory 106 is no longer implemented via the external bus 110, the speed of inter-chip communication performed via the external bus 110 can be effectively increased.

[0032] In order to more effectively utilize the chip area, the primary memory 102b is integrated with the main memory 106 in a specific manner. Specifically, the DRAM providing the main memory 106 includes a DRAM array 112, and includes peripheral circuits disposed around the DRAM array 112 and configured to control the reading and writing of cells in the DRAM array 112. In addition to the word line drivers 114 disposed next to one of the DRAM arrays 112, respectively, a sense amplifier array 116 is disposed next to each DRAM array 112. The word lines WL crossing the DRAM array 112 may extend along the column direction to reach the word line drivers 114, and the bit lines BL crossing the DRAM array 112 may extend along the row direction to the sense amplifier array 116. Since both the cells of the SRAM array 118 and the cells of the sense amplifier array 116 constituting the primary memory 102b use latch circuits as the main architecture, the SRAM array 118 and the sense amplifier array 116 may be highly similar to each other in terms of circuit and layout design. Based on this similarity, the primary memory 102 b is placed adjacent to the sense amplifier array 116 to reduce area penalty.

[0033] More specifically, since the SRAM array 118 and the sense amplifier array 116 are highly similar to each other in terms of circuit and layout, the SRAM array 118 and the sense amplifier array 116 can be placed in cells having similar or even the same size and can have similar pattern densities. As a result, no large isolation region is required to separate the SRAM array 118 and the sense amplifier array 116. In certain cases, the SRAM array 118 can even be adjacent to the sense amplifier array 116 without an isolation region existing between the SRAM array 118 and the sense amplifier array 116.

[0034] In some embodiments, each sense amplifier array 116 may be disposed along a side of one of the DRAM arrays 112, and the bit lines BL crossing the DRAM array 112 extend through the sense amplifier array 116, so that data stored in the DRAM array 112 can be read out from the bit lines BL by the sense amplifier array 116. In addition, the SRAM array 118 may be in lateral contact with a corresponding one of the DRAM arrays 112 and one of the sense amplifier arrays 116, respectively, and the bit lines BL may further extend through the SRAM array 118. Based on this configuration, data stored in the SRAM array 118 can also be read out from the bit lines BL by the sense amplifier array 116. That is, the sense amplifier array 116 can be shared by the DRAM array 112 and the SRAM array 118.

[0035] Furthermore, since the bit lines BL extend across both the DRAM array 112 and the SRAM array 118, writing to both the DRAM array 112 and the SRAM array 118 can be achieved through the bit lines BL. Thus, data stored in the DRAM array 112 can be sensed from the bit lines BL by the sense amplifier array 116, and can also be written to the SRAM array 118 through the bit lines BL. Or conversely, data stored in the SRAM array 118 can be read from the bit lines BL by the sense amplifier array 116, and can also be written to the DRAM array 112 through the bit lines BL. Such data transfer from the DRAM array 112 to the SRAM array 118 (and vice versa) is achieved in the hybrid memory chip 108, and inter-chip data transfer via the external bus 110 is avoided. Therefore, as described above, frequent communication with the relatively slow main memory 106 is no longer achieved through the inter-chip path provided by the external bus 110, and thus the speed of inter-chip communication via the external bus 110 can be effectively increased.

[0036] Although not shown, additional word lines may extend across the SRAM array 118 and enable column selection during reading and writing of the SRAM array 118. In some embodiments, the word line driver 114 is extended to be shared by both the DRAM array 112 and the SRAM array 118. In these embodiments, the word line driver 114 may extend further along the SRAM array 118, and additional word lines across the SRAM array 118 may extend to the word line driver 114 in the column direction.

[0037] According to some embodiments, each SRAM array 118 has approximately the same capacity as the adjacent sense amplifier array 116. The term "capacity" used herein refers to the cell count and may further indicate the array size. For example, each DRAM array 112 has 512 rows of cells and is connected to 16 input / output pins. Therefore, each DRAM array 112 may require 8k bit line sense amplifiers. The sense amplifier arrays 116 located at opposite sides of each DRAM array 112 may include 4k bit line sense amplifiers, respectively. Similarly, the SRAM arrays 118 located at opposite sides of each DRAM array 112 may include 4k SRAM cells, respectively. Figure 3B As further shown, based on the similarity between the SRAM array 118 and the sense amplifier array 116, the SRAM array 118 can be described as an extension of the sense amplifier array 116. In an example where 4K bit line sense amplifier arrays 116 are arranged along one side of the adjacent DRAM array 112, another 4K SRAM cells are placed adjacent to the 4K bit line sense amplifiers as an extension of the bit line sense amplifiers.

[0038] During a copy operation to transfer single-bit metadata from one of the DRAM arrays 112 to one of the SRAM arrays 118, data stored in a selected cell in the DRAM array 112 is read in response to the selection of a row address and a column address of the DRAM array 112. That is, a cell located at the intersection of a selected word line WL and a selected bit line BL is read by a bit line sense amplifier connected to the selected bit line BL. Thereafter, in response to the selection of a column address of the SRAM array 118, this data is written to a cell located at the intersection of a selected word line WL of the SRAM array 118 and a selected bit line BL shared by the DRAM array 112 and the SRAM array 118. In this way, data stored in a selected cell of the DRAM array 112 is copied to a selected cell in the SRAM array 118. In a similar manner, a copy operation may be performed to transfer single-bit metadata from one of the SRAM arrays 118 to one of the DRAM arrays 112.

[0039] In addition to single-bit transfer, multi-bit transfer can also be achieved in a single copy operation from one of the DRAM arrays 112 to one of the SRAM arrays 118 (or vice versa). For example, a series of data (data pattern) stored in a column of cells in the DRAM array 112 can be read in response to the selection of multiple row addresses and one column address of the DRAM array 112. That is, the column of cells located at the intersection of the selected word line WL and the selected bit line BL is sensed by the bit line sense amplifier connected to the selected bit line BL. Thereafter, in response to the selection of the column address of the SRAM array 118, this series of data is written to a column of cells located at the intersection of the selected word line WL of the SRAM array 118 and the selected bit line BL shared by the DRAM array 112 and the SRAM array 118. In this way, a series of data stored in a selected column of cells in the DRAM array 112 is copied to a selected column of cells in the SRAM array 118. In a similar manner, a copy operation may be performed to transfer a series of data from one of the SRAM arrays 118 to one of the DRAM arrays 112. In a particular case, a series of data stored in multiple columns of cells in one of the DRAM arrays 112 may be copied to selected multiple columns of cells in the corresponding SRAM array 118.

[0040] like Figure 3B Schematically illustrated, for single-bit transfer or multi-bit transfer, data transfer between each of the DRAM arrays 112 and the adjacent SRAM array 118 may pass through the sense amplifier array 116 shared by the DRAM array 112 and the SRAM array 118 along the intra-chip path P1. On the other hand, data transfer between each of the SRAM arrays 118 and the adjacent DRAM array 112 may pass through the sense amplifier array 116 shared by the SRAM array 118 and the DRAM array 112 along the intra-chip path P2. For example, 8K bits (4K on each side) may be copied from the DRAM array 112 and two sense amplifier arrays 116 to the corresponding adjacent SRAM array 118, or 8K bits (4K on each side) may be copied from the SRAM array 118 to the corresponding sense amplifier array 116 and the DRAM array 112 at the same time. When the number of row addresses is 512, the copy (COPY) speed is increased by 512 times.

[0041] Specifically, in order to execute the copy instruction, the word line WL is selected according to the selected column address (e.g., the column address "RAn" and the column segment address "RAsec"), and the one or more bit lines BL are selected according to the one or more row addresses "CAn". When an instruction to copy data from the SRAM array 118 to the DRAM array 112 ("S2D copy instruction") is given, the data stored in the selected SRAM cells of the SRAM array 118 are simultaneously written to the corresponding bit line sense amplifiers according to the given column address and the given column segment address. For example, based on the given column address RAn and the column segment address RAsec, an S2D copy instruction corresponding to the column RAn and the column segment address RAsec can be issued to simultaneously write 8K bits from the two SRAM arrays 118 to their corresponding sense amplifier arrays 116 and DRAM arrays 112.

[0042] On the other hand, when a command to copy data from the DRAM array 112 to the SRAM array 118 ("D2S copy command") is given, the data read from the DRAM array 112 to the bit line sense amplifier is simultaneously written to one or more corresponding SRAM cells of the SRAM array 118 based on a given column address and a given column segment address. For example, based on a given column address RAn and a given column segment address RAsec, a D2S copy command corresponding to the column address RAn and the column segment address RAsec may be issued to simultaneously write 8K bits from the DRAM array 112 and the sense amplifier array 116 to their corresponding two SRAM arrays 118.

[0043] Under the specified SRAM timing standard, any SRAM cell in the hybrid memory chip 108 can be accessed using the row address, column segment address, and column address. In addition, under the specified DRAM timing standard, any DRAM cell in the hybrid memory chip 108 can be accessed using the row address, column segment address, and column address. In addition, the DRAM array 112 and the SRAM array 118 in the hybrid memory chip 108 can share input / output pins, or have different sets of input / output pins.

[0044] Compared to data transfer via the external bus 110, data transfer via the copy operation within the hybrid memory chip 108 is much faster and consumes much less power because one copy operation can replace multiple repeated reads and writes via the external bus 110. In some embodiments, data transfer between the main memory 106 and the primary memory 102b within the hybrid memory chip 108 is approximately 400 times faster and consumes approximately 100 times less power than transferring data between the main memory and the primary memory using an external bus.

[0045] In reference Figure 3Aand Figure 3B In the illustrated embodiment, the sense amplifier array 116 and the SRAM array 118 in the hybrid memory chip 108 may have approximately the same capacity. In an alternative embodiment, in the hybrid memory chip 108, the SRAM array 118 is larger in capacity than the sense amplifier array 116.

[0046] Figure 4A 1 is a schematic diagram showing a hybrid memory chip 108' according to some embodiments of the present disclosure. The hybrid memory chip 108' is similar to the reference Figure 3A and Figure 3B The hybrid memory chip 108 is described, but the hybrid memory chip 108' has more SRAM arrays 118. For example, in the hybrid memory chip 108', the capacity of the SRAM array 118 may be approximately twice the capacity of the sense amplifier array 116. Specifically, along a single side of each DRAM array 112 in the hybrid memory chip 108', one of the sense amplifier arrays 116 may be disposed between a pair of SRAM arrays 118, and each of the sense amplifier arrays 116 may be in contact with the adjacent DRAM array 112 via the SRAM array 118 on the opposite side. Since each sense amplifier array 116 and each SRAM array 118 are substantially the same as each other in capacity, the total capacity of the SRAM array 118 may be approximately twice the total capacity of the sense amplifier array 116.

[0047] In an example where each DRAM array 112 has 512 rows of cells and is connected to 16 input / output pins, the sense amplifier arrays 116 may include 4k sense amplifiers, respectively. Similarly, the SRAM arrays 118 may include 4k SRAM cells, respectively. That is, at a single side of each DRAM array 112, there may be 4k sense amplifiers and 8k SRAM cells.

[0048] like Figure 4B As further shown, based on the similarity between the SRAM array 118 and the sense amplifier array 116, the SRAM array 118 can be described as an extension of the sense amplifier array 116. In an example where 4K bit line sense amplifier arrays 116 are arranged along one side of the adjacent DRAM array 112, 8K SRAM cells are placed on the opposite side of the 4K bit line sense amplifiers as an extension of the bit line sense amplifiers.

[0049] Based on the high similarity in circuit and layout between the sense amplifier arrays 116 and the SRAM arrays 118, a large isolation region between each SRAM array 118 and the adjacent sense amplifier arrays 116 may not be required. In a specific case, the SRAM arrays 118 are adjacent to the sense amplifier arrays 116, and no isolation region exists between the SRAM arrays 118 and the sense amplifier arrays 116.

[0050] Since the bit lines BL that cross the DRAM array 112 extend through the SRAM array 118 and the sense amplifier array 116, the sense amplifier array 116 can also be shared by the DRAM array 112 and the SRAM array 118 for read operations. In addition, data stored in the DRAM array 112 can be read from the bit lines BL by the sense amplifiers and then written to the SRAM array 118 without traveling through the inter-chip path provided by the external bus 110. Similarly, data stored in the SRAM array 118 can be read from the bit lines BL by the sense amplifiers and then written to the DRAM array 112 without traveling through the inter-chip path provided by the external bus 110.

[0051] In some embodiments, a single-bit data transfer may be implemented in a copy operation from one of the DRAM arrays 112 to one of the SRAM arrays 118 (or vice versa). In other embodiments, a multi-bit data transfer may be implemented in a copy operation from one of the DRAM arrays 112 to one of the SRAM arrays 118 (or vice versa). Figure 4B Schematically, for single-bit transfer or multi-bit transfer, data from each of the DRAM arrays 112 can be copied to the adjacent SRAM array 118 via the intra-chip path P1. On the other hand, data from each of the SRAM arrays 118 can be copied to the adjacent DRAM array 112 via the intra-chip path P2.

[0052] Since there are additional word lines (not shown) extending across the SRAM array 118 to enable column selection during operation of the SRAM array 118, the word line driver 114 can be extended to be shared by both the DRAM array 112 and the SRAM array 118. In some embodiments, the word line driver 114 can be further extended along the SRAM array 118, and the additional word lines across the SRAM array 118 can be extended to the word line driver 114 along the column direction.

[0053] Although not specifically shown, the hybrid memory chip 108' may also be used in a memory system in which another portion of the primary memory of the memory system is external to the hybrid memory chip 108' and communicates with the hybrid memory chip 108' via an external bus. It should be noted that such a memory system may also be applied to a memory system having a primary memory of at least one memory cell. Figure 3A In the computing device described.

[0054] In the event that data must be written from the processor chip 104 to the DRAM array 112 of the hybrid memory chip, the data may be written to the SRAM array 118 of the hybrid memory chip without waiting for any refresh / latency of the DRAM array 112, and then the written data may be transferred from the SRAM array 118 of the hybrid memory chip to the DRAM array 112. Thus, the processor chip 104 does not have to wait for a refresh / latency cycle of the DRAM array 112.

[0055] In some embodiments, in reference to Figure 3A and Figure 3B The memory system 10 described herein or in reference to Figure 4A and Figure 4B In the described memory system, the primary memory 102 may have different levels of SRAM, such as 3 or more levels of SRAM. Compared with the SRAM at the higher level, the SRAM at the lower level may occupy a larger chip area. In order to free up more chip area from the processor chip 104, the SRAM at the lower level may be integrated with the main memory 106 in the hybrid memory chip 108 / 108'. For example, when the first level and the second level of SRAM are integrated into the processor chip 104 as the primary memory 102a, the third level of SRAM is integrated into the hybrid memory chip 108 / 108' as the primary memory 102b.

[0056] In addition, although not shown in the figure, Figure 3A , Figure 3B The memory system 10 including the hybrid memory chip 108 is described and referenced Figure 4A , Figure 4B The illustrated memory system 10 including the hybrid memory chip 108 ′ may include lower level memories, such as non-volatile memory and / or a hard disk.

[0057] As described above, the present disclosure provides a solution to overcome the memory bottleneck caused by slow data transfer along the system bus. Traditionally, the primary memory (e.g., SRAM) is embedded in the processor chip, while the slower main memory (e.g., DRAM) is formed in another chip. Therefore, the data transfer between the primary memory and the slower main memory must pass through the inter-chip data path provided by the external bus, resulting in considerable write / read delays. According to an embodiment of the present disclosure, a portion of the primary memory is integrated with the main memory in a hybrid memory chip (i.e., DRAM and SRAM can be integrated into a single semiconductor chip), which significantly reduces the delay and power consumption of the data transfer between the primary memory and the main memory. Therefore, the access operation (read or write operation) between DRAM and SRAM can be efficient. In addition, since the SRAM cell and the sense amplifier used to read / write the DRAM cell are highly similar in layout, circuit and pattern density, the primary memory (e.g., SRAM) can be integrated with the main memory (e.g., DRAM) with minimal area loss. In addition, the peripheral circuits around the DRAM cell can be shared with the SRAM cell.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hybrid memory chip, comprising: multiple dynamic random access memory arrays; a plurality of sense amplifier arrays adjacent to the plurality of dynamic random access memory arrays; as well as a plurality of static random access memory arrays adjacent to the plurality of dynamic random access memory arrays or the plurality of sense amplifier arrays, and each of the plurality of static random access memory arrays is adjacent to one of the plurality of sense amplifier arrays, The plurality of sense amplifier arrays are configured to perform access operations between the plurality of dynamic random access memory arrays and the plurality of static random access memory arrays.

2. The hybrid memory chip according to claim 1, wherein bit lines spanning the plurality of dynamic random access memory arrays extend through the plurality of sense amplifier arrays and the plurality of static random access memory arrays, The plurality of static random access memory arrays are configured to be written with data stored in the plurality of dynamic random access memory arrays via the bit lines, or the plurality of dynamic random access memory arrays are configured to be written with data stored in the plurality of static random access memory arrays via the bit lines.

3. The hybrid memory chip according to claim 1, further comprising: A word line driver is adjacent to the plurality of dynamic random access memory arrays, the plurality of sense amplifier arrays, and the plurality of static random access memory arrays, wherein a word line spanning the plurality of dynamic random access memory arrays and the plurality of static random access memory arrays extends to the word line driver.

4. The hybrid memory chip according to claim 3, wherein the plurality of dynamic random access memory arrays, the plurality of static random access memory arrays, the plurality of sense amplifier arrays and the word line driver are configured to perform a copy operation, wherein the copy operation copies data stored in a single cell of one of the plurality of dynamic random access memory arrays to a single cell of one of the plurality of static random access memory arrays, or copies data stored in a single cell of one of the plurality of static random access memory arrays to a single cell of one of the plurality of dynamic random access memory arrays.

5. The hybrid memory chip according to claim 3, wherein the plurality of dynamic random access memory arrays, the plurality of static random access memory arrays, the plurality of sense amplifier arrays and the word line driver are configured to perform a copy operation, wherein the copy operation copies a series of data stored in a plurality of cells of one of the plurality of dynamic random access memory arrays to a plurality of cells of one of the plurality of static random access memory arrays, or copies a series of data stored in a plurality of cells of one of the plurality of static random access memory arrays to a plurality of cells of one of the plurality of dynamic random access memory arrays.

6. The hybrid memory chip of claim 5 , wherein during the copy operation, a series of data stored in a column of cells of one of the plurality of dynamic random access memory arrays is copied to a column of cells of one of the plurality of static random access memory arrays, or during the copy operation, a series of data stored in a column of cells of one of the plurality of static random access memory arrays is copied to a column of cells of one of the plurality of dynamic random access memory arrays.

7. The hybrid memory chip according to claim 1, wherein two adjacent dynamic random access memory arrays among the multiple dynamic random access memory arrays are spaced apart from each other, and one sense amplifier array among the multiple sense amplifier arrays and one static random access memory array among the multiple static random access memory arrays are arranged between the two adjacent dynamic random access memory arrays.

8. The hybrid memory chip according to claim 1, wherein two adjacent dynamic random access memory arrays among the plurality of dynamic random access memory arrays are spaced apart from each other, and one sense amplifier array among the plurality of sense amplifier arrays and two static random access memory arrays among the plurality of static random access memory arrays are arranged between the two adjacent dynamic random access memory arrays. 9 . The hybrid memory chip of claim 8 , wherein each of the plurality of sense amplifier arrays is sandwiched between two SRAM arrays of the plurality of SRAM arrays.

10. A memory system comprising: A first primary memory is integrated into the processor chip together with the central processing unit and includes a first static random access memory array; a second primary memory located external to the processor chip and comprising a second static random access memory array; as well as The main memory includes a dynamic random access memory array and is integrated with the second primary memory in a hybrid memory chip.

11. The memory system of claim 10, wherein the second primary memory is configured to store data provided from the main memory, and is configured to enable data transfer between the second primary memory and the main memory without using an external bus extending between the processor chip and the hybrid memory chip.

12. The memory system of claim 10, wherein the second SRAM array of the second primary memory is disposed in the hybrid memory chip adjacent to a sense amplifier array surrounding the DRAM array of the main memory.

13. The memory system of claim 12, wherein a bit line spanning the DRAM array of the main memory extends through the sense amplifier array and the second SRAM array of the second primary memory.

14. A computing device comprising: A processor chip integrating a central processing unit and a first primary memory, wherein the first primary memory comprises a first static random access memory array; as well as A hybrid memory chip is connected to the processor chip via an external bus, wherein a second primary memory and a main memory are integrated in the hybrid memory chip, the second primary memory includes a second static random access memory array, and the main memory is formed by a dynamic random access memory array.

15. The computing device of claim 14, wherein the second primary memory is configured to store data provided from the main memory, and is configured to enable data transfer between the second primary memory and the main memory without using the external bus.

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