Multi-level signaling in memory with wide system interface

Abstract

The invention relates to multi-level signaling in memory with a wide system interface. Techniques are provided herein that use multi-level signaling to increase the speed of data transmission across a larger number of channels in a memory device. This multi-level signaling may be configured to increase data transmission speed without increasing data transmission frequency and / or transmit power of communicated data. An example of the multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of data bits.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with application date of July 23, 2018, application number 201880045340.2, and invention name “Multi-level signaling in a memory with a wide system interface”.

[0003] Cross Reference

[0004] This patent application claims priority to PCT Application No. PCT / US2018 / 043311, filed by Hollis et al. on July 23, 2018, entitled “Multi-Level Signaling in Memory with Wide System Interface,” which claims priority to U.S. Patent Application No. 15 / 854,600, filed by Hollis et al. on December 26, 2017, entitled “Multi-Level Signaling in Memory with Wide System Interface,” which claims priority to U.S. Provisional Patent Application No. 62 / 542,160, filed by Hollis et al. on August 7, 2017, entitled “Multi-Level Signaling in Memory with Wide System Interface,” each of which is assigned to its assignee, and the entire contents of each of which are expressly incorporated herein by reference.

[0005] The technical field relates to multi-level signaling in memories with wide system interfaces. Background Art

[0006] The following relates generally to multi-level signaling using memory devices and more particularly to multi-level signaling in memory devices that include a wide system interface.

[0007] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, which are usually represented by a logical "1" or a logical "0". In other systems, more than two states can be stored. To access the stored information, a component of the electronic device can read or sense the stored state in the memory device. To store information, a component of the electronic device can write or program the state into the memory device.

[0008] There are many types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for an extended period of time even without an external power source. Volatile memory devices (e.g., DRAM) can lose their stored state over time unless they are periodically refreshed by an external power source. FeRAM can use a device architecture similar to volatile memory, but may have non-volatile properties due to the use of ferroelectric capacitors as storage devices. Therefore, FeRAM devices may have improved performance compared to other non-volatile and volatile memory devices.

[0009] Generally speaking, improving memory devices may include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Summary of the invention

[0010] An apparatus is described. The apparatus may include a memory cell array, a controller configured to control access to the memory cell array, an interposer operably coupling the memory cell array and the controller, the interposer including a plurality of channels between the memory cell array and the controller, and a receiver configured to decode a multi-level signal modulated using a first modulation scheme having at least three levels communicated across at least one channel of the interposer.

[0011] A method is described. The method may include identifying, by a controller of a memory device, information to be written to a memory cell array; generating, by the controller, a multi-level signal modulated using a first modulation scheme having at least three levels representing a plurality of bits of the identified information; and transmitting, by the controller, the multi-level signal to the memory cell array across an interpolator comprising a plurality of channels.

[0012] Another apparatus is described. The apparatus may include a memory cell array; an interposer operably coupled to the memory cell array, the interposer including a plurality of channels; and a controller operably coupled to the interposer. The controller may be configured to: identify information to be written to the memory cell array; generate a multi-level signal modulated using a first modulation scheme having at least three levels representing a plurality of bits of the identified information; and transmit the multi-level signal across the interposer to the memory cell array.

[0013] Another apparatus is described. The apparatus may include means for identifying information to be written to a memory cell array; means for generating a multi-level signal modulated using a first modulation scheme having at least three levels representing a plurality of bits of the identified information; and means for transmitting the multi-level signal to the memory cell array across an interpolator comprising a plurality of channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 An example of a memory device supporting multi-level signaling in a memory with a wide system interface according to an embodiment of the present invention is described.

[0015] Figure 2 An example of an eye diagram supporting multi-level signaling in a memory with a wide system interface according to an embodiment of the present invention is illustrated.

[0016] Figure 3 An example of a transmission circuit supporting multi-level signaling in a memory with a wide system interface according to an embodiment of the present invention is described.

[0017] Figure 4 An example of a receiver supporting multi-level signaling in a memory with a wide system interface according to an embodiment of the present invention is described.

[0018] Figure 5 An example of a memory device supporting multi-level signaling in a memory with a wide system interface according to an embodiment of the present invention is described.

[0019] Figure 6 A block diagram of an apparatus supporting multi-level signaling in a memory with a wide system interface according to an embodiment of the present invention is shown.

[0020] Figure 7 A block diagram illustrates a system including a memory controller that supports multi-level signaling in a memory with a wide system interface in accordance with an embodiment of the present invention.

[0021] Figure 8 A method for multi-level signaling in a memory with a wide system interface according to an embodiment of the present invention is described. DETAILED DESCRIPTION

[0022] Some memory devices may use wide communication channels between connected devices (e.g., a memory cell array and a processor) to communicate data (e.g., high bandwidth memory (HBM)). In some cases, these wide communication channels include a large number of resistive channels. Because each channel is resistive, as the data transfer frequency increases, the power required to transfer the data increases in a nonlinear manner with respect to the frequency. Such characteristics may result in a practical upper frequency limit that can be used to transmit data through a resistive channel at a given amount of transmit power.

[0023] Techniques for increasing data transfer speeds across a larger number of channels in a memory device using multi-level signaling are provided herein. Such multi-level signaling can be configured to increase data transfer speeds without increasing data transfer frequency and / or transmit power of the communicated data. An example of a multi-level signaling scheme can be pulse amplitude modulation (PAM), such as PAM4 or PAM8. Each unique symbol of a multi-level signal can be configured to represent multiple data bits.

[0024] The features of the present invention introduced above are further described below in the context of the content of the memory device.Then, a specific example is described for the memory device supporting the multi-level signaling in the memory with a wide system interface.These and other features of the present invention are further described and described with reference to the equipment diagram, system diagram and flow chart relevant to the multi-level signaling.

[0025] Figure 1 An example memory device 100 according to various examples of the present invention is illustrated. The memory device 100 may also be referred to as an electronic memory device. The memory device 100 may be configured to utilize multi-level signaling to communicate data between various components of the memory device 100. Some examples of multi-level signaling may include PAM signaling, such as PAM4 signaling, PAM8 signaling, etc. The memory device 100 may include a memory cell array 105, a controller 110, a plurality of channels 115, a signaling interface 120, other components, or a combination thereof.

[0026] The memory device 100 can use multi-level signaling to increase the amount of information transmitted using a given bandwidth of frequency resources. In binary signaling, two symbols (e.g., two voltage levels) of a signal are used to represent at most two logic states (e.g., logic state '0' or logic state '1'). In multi-level signaling, a larger symbol library can be used to represent data. Each symbol can represent more than two logic states (e.g., logic states with multiple bits). For example, if a signal is capable of having four unique symbols, the signal can be used to represent at most four logic states (e.g., '00', '01', '10', and '11'). Therefore, multiple data bits can be compressed into a single symbol, thereby increasing the amount of data communicated using a given bandwidth.

[0027] In some cases of multi-level signaling, the amplitude of the signal can be used to generate different symbols. For example, the first amplitude level can represent '00', the second amplitude level can represent '01', the third amplitude level can represent '10', and the fourth amplitude level can represent '11'. One disadvantage of some multi-level signaling schemes is that the symbols can be separated by a voltage smaller than the symbols in the binary signaling scheme. Smaller voltage separation can make the multi-level signaling scheme more prone to errors caused by noise or other aspects. However, the voltage separation of the symbols in the multi-level signaling scheme can be extended by increasing the peak-to-peak transmission power of the transmitted signal. However, in some cases, this increase of peak-to-peak transmission power can be attributed to fixed power supply voltage, fixed signal power requirements or other factors but is impossible or difficult. Therefore, to implement multi-level signaling, when compared with the binary signaling scheme, the transmitter can use more power and / or the receiver can be prone to increase the error rate.

[0028] A multi-level signal (sometimes referred to as a multi-symbol signal) may be a signal modulated using a modulation scheme that includes three or more unique symbols to represent data (e.g., two or more data bits). A multi-level signal may be an example of an M-ary signal modulated using a modulation scheme, where M is greater than or equal to 3, where M represents the number of possible unique symbols, levels, or conditions in the modulation scheme. In some examples, a multi-level signal or a multi-level modulation scheme may be referred to as a non-binary signal or a non-binary modulation scheme. Examples of multi-level (or M-ary) modulation schemes associated with multi-level signals may include, but are not limited to, pulse amplitude modulation (e.g., PAM4, PAM8), quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others.

[0029] A binary level signal (sometimes referred to as a binary symbol signal) may be a signal modulated using a modulation scheme that includes two unique symbols to represent one data bit. The binary level signal may be an example of an M-ary modulation scheme, where M is less than or equal to 2. Examples of binary level modulation schemes associated with the binary level signal include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, PAM2, and / or others.

[0030] Each memory cell of the memory cell array 105 can be programmed to store a different state. For example, each memory cell can be programmed to store two or more logic states (e.g., logic '0', logic '1', logic '00', logic '01', logic '10', logic '11', etc.). The memory cell can store a charge representing the programmable state in a capacitor; for example, a charged and uncharged capacitor can represent two logic states, respectively. The memory cells of the memory cell array 105 can use any number of storage media, including DRAM, FeRAM, PCM, or other types of memory cells. A DRAM memory cell can include a capacitor having a dielectric material as an insulating material. For example, the dielectric material can have linear or paraelectric polarization properties and a ferroelectric memory cell can include a capacitor having a ferroelectric material as an insulating material. In an example where the storage medium includes FeRAM, different charge levels of the ferroelectric capacitor can represent different logic states.

[0031] The memory cell array 105 may be or include a three-dimensional (3D) array in which multiple two-dimensional (2D) arrays or multiple memory cells are stacked on top of each other. This configuration may increase the number of memory cells that may be formed on a single wafer or substrate compared to a 2D array. This in turn may reduce production costs or increase the performance of the memory array, or both. Each level of the array may be aligned or positioned so that the memory cells may be approximately aligned with each other across each level, thereby forming a stack of memory cells.

[0032] In some examples, the memory cell array 105 may include memory cells, word lines, digit lines, and sensing components. In some examples, the memory cell array 105 may include plate lines (e.g., in the case of FeRAM). The memory cells of the memory cell array 105 may include selection components and logic storage components, such as a capacitor including a first plate, a cell plate, a second plate, and a cell bottom. The cell plate and the cell bottom may be capacitively coupled by an insulating material (e.g., a dielectric, ferroelectric, or PCM material) positioned therebetween.

[0033] Memory cells of the memory cell array 105 may be accessed using various combinations of word lines, digit lines, and / or plate lines (e.g., during a read operation, a write operation, or other operation). In some cases, some memory cells may share access lines (e.g., digit lines, word lines, plate lines) with other memory cells. For example, memory cells in the same column may share a digit line, memory cells in the same row may share a word line, and memory cells in the same section, block, stack, or multiple stacks may share a plate line. As described above, various states may be stored by charging or discharging the capacitors of the memory cells.

[0034] The stored state of the capacitor of the memory cell can be read or sensed by operating various elements. The capacitor can be in electronic communication with the digit line. The capacitor can be isolated from the digit line when the selection component is deactivated, and the capacitor can be connected to the digit line when the selection component is activated (e.g., by a word line). Activating the selection component can be referred to as selecting the memory cell. In some cases, the selection component can be a transistor and its operation can be controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than the threshold magnitude of the transistor. The word line can activate the selection component; for example, a voltage applied to the transistor gate of the word line can connect the capacitor of the memory cell to the digit line.

[0035] In some examples, the voltage change of the digit line may depend on its intrinsic capacitance. That is, as charge flows through the digit line, some finite charge may be stored in the digit line and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance may depend on physical properties, including the size of the digit line. The digit line may connect many memory cells of the memory cell array 105, so the digit line may have a length that results in a non-negligible capacitance (e.g., on the order of a few picofarads (pF)). The resulting voltage of the digit line may then be compared to a reference voltage (e.g., the voltage of the reference line) by a sensing component in order to determine the stored logic state in the memory cell. Other sensing processes may be used.

[0036] The sensing component may include various transistors or amplifiers to detect and amplify the difference in the signal, which may be referred to as latching. The sensing component may include a sense amplifier that receives and compares the voltage of the digital line to a reference line (which may be a reference voltage). The sense amplifier output may be driven to a higher (e.g., positive) or lower (e.g., negative or ground) supply voltage based on the comparison. For example, if the digital line has a higher voltage than the reference line, the sense amplifier output may be driven to the positive supply voltage.

[0037] In some cases, the sense amplifier may drive the digit line to a supply voltage. The sensing component may then latch the output of the sense amplifier and / or the voltage of the digit line, which may be used to determine the stored state (e.g., logic, '1') in the memory cell. Alternatively, for example, if the digit line has a higher voltage than the reference line, the sense amplifier output may be driven to a negative or ground voltage. The sensing component may similarly latch the sense amplifier output to determine the stored state (e.g., logic '0') in the memory cell. The latched logic state of the memory cell may then be output, for example, by a column decoder.

[0038] To write to a memory cell, a voltage may be applied across the capacitor of the memory cell. Various methods may be used to write to a memory cell. In one example, a selection component may be activated by a word line so as to electrically connect the capacitor to a digit line. A voltage may be applied across the capacitor by controlling the voltage of a cell plate (e.g., by a plate line) and a cell bottom (e.g., by a digit line). To write a logic '0', the cell plate may be high (e.g., the voltage level may be increased above a predetermined voltage (which is a "high" voltage)). That is, a positive voltage may be applied to the plate line, and the cell bottom may be low (e.g., a virtual ground or a negative voltage applied to the digit line). The reverse process may be performed to write a logic '1', where the cell plate may be low and the cell bottom may be high.

[0039] The controller 110 may control the operation (e.g., reading, writing, rewriting, refreshing, discharging, etc.) of the memory cells in the memory cell array 105 through various components (e.g., row decoders, column decoders, and sensing components). In some cases, one or more of the row decoders, column decoders, and sensing components may be co-located with the controller 110. The controller 110 may generate row and column address signals in order to activate the desired word lines and digit lines. In other examples, the controller 110 may generate and control various voltages or currents used during the operation of the memory device 100. For example, the controller 110 may apply a discharge voltage to a word line or digit line after accessing one or more memory cells. In general, the amplitude, shape, or duration of the applied voltage or current discussed herein may be adjusted or varied and may be different for the various operations discussed when operating the memory device 100. In addition, one, multiple, or all memory cells within the memory cell array 105 may be accessed simultaneously. For example, multiple memory cells or all memory cells of the memory cell array 105 may be accessed simultaneously during a reset operation, where multiple memory cells or all memory cells may be set to a single logic state (eg, logic "0").

[0040] Each of the plurality of channels 115 may be configured to couple the memory cell array 105 and the controller 110. In some examples, each of the plurality of channels 115 may be referred to as a plurality of branches. In some memory devices, the data transfer speed between the memory device and a host device (e.g., a personal computer or other computing device) may be limited by the data rate transmitted across the plurality of channels 115. In some examples, the memory device 100 may include a larger number of high resistance channels. By increasing the number of channels, the amount of data transmitted in the memory device 100 may be increased without increasing the data transfer speed. In some examples, the plurality of channels 115 may be referred to as a wide system interface. Each of the plurality of channels 115 may be part of an interposer positioned between the memory cell array 105 and the controller 110. In some examples, one or more of the channels 115 may be unidirectional, and in other examples, one or more of the channels 115 may be bidirectional.

[0041] In some examples, at least some (and in some cases, each) signaling interface 120 can generate and / or decode signals communicated using multiple channels 115. A signaling interface 120 can be associated with each component coupled to multiple channels 115. The signaling interface 120 can be configured to generate and / or decode multi-level signals, binary signals, or both (e.g., simultaneously). Each signaling interface 120 can include a driver 125 and a receiver 130. In some examples, each driver 125 can be referred to as a multi-drop driver.

[0042] Each driver 125 may be configured to generate a multi-level signal based on a logic state including a plurality of bits. For example, the driver 125 may use a PAM4 signaling technique (or other types of multi-level signaling techniques) to generate a signal having an amplitude corresponding to the logic state. The driver 125 may be configured to receive data using a single input line. In some cases, the driver 125 may include a first input line for a first data bit (e.g., a most significant bit), a second input line for a second data bit (e.g., a least significant bit). In some circumstances, the driver 125 may be configured to generate a binary level signal (e.g., an NRZ signal). In some cases, the driver 125 may use single-ended signaling to generate a multi-level signal. In such cases, the multi-level signal may be transmitted without differential.

[0043] Each receiver 130 may be configured to determine a logic state represented by a sign of a multi-level signal received using a plurality of channels 115. In some cases, the receiver 130 may determine the amplitude of the received multi-level signal. Based on the determined amplitude, the receiver 130 may determine the logic state represented by the multi-level signal. The receiver 130 may be configured to output data using a single output line. In some cases, the receiver 130 may include a first output line for a first data bit (e.g., a most significant bit), a second output line for a second data bit (e.g., a least significant bit). In some circumstances, the receiver 130 may be configured to decode a binary level signal (e.g., an NRZ signal). For example, each of the receivers 130 may be coupled to a transmitter (not illustrated) via a plurality of channels 115. Each of the channels 115 may be configured to output data comprising a plurality of bits, and the controller 110 may be configured to determine an output impedance offset between the data outputs. One or more transistors (e.g., not separately illustrated) may be configured to adjust the resistance level of one or more of the plurality of channels 115. This adjustment may be based at least in part on the determined output impedance offset.

[0044] In some cases, each of the signaling interfaces 120 may be configured to selectively generate and / or decode different types of signals (e.g., NRZ signals, PAM4 signals, PAM8 signals, etc.). Different types of signals may be used based on the operating environment of the memory device 100. For example, binary signaling may use less power than multi-level signaling and may be used when power consumption drives performance considerations. Other performance factors that may be used to determine which type of signaling should be used may include clock considerations, data strobe (DQS) considerations, circuit capabilities, bandwidth considerations, jitter considerations, or a combination thereof. In some cases, the controller 110 may be configured to select the signal type, and the signaling interface 120 may be configured to implement the selection based on instructions received from the controller 110. In some cases, each of the signaling interfaces 120 may be configured to implement encoding functions, such as error detection procedures, error correction procedures, data bus inversion procedures, or a combination thereof.

[0045] In some cases, the signaling interface 120 may be configured to communicate multi-level signals and binary signals simultaneously. In such cases, the signaling interface 120 may include more than one set of drivers 125 and receivers 130. For example, the signaling interface 120 may be configured to communicate a first set of data (e.g., control signals) using a first set of channels 115 using binary level signals while communicating a second set of data (e.g., user information) using a second set of channels 115 using multi-level signals.

[0046] Figure 2An example of an eye diagram 200 representing a multi-level signal according to various embodiments of the present invention is illustrated. Eye diagram 200 can be used to indicate signal quality in high-speed transmission and can represent four symbols of the signal (e.g., '00', '01', '10', or '11'). In some examples, each of the four symbols can be represented by a different voltage amplitude (e.g., amplitudes 205-a, 205-b, 205-c, 205-d). In other examples, eye diagram 200 can represent a PAM4 signal, which can be used in a memory device (e.g., as shown in FIG. 1 ). Figure 1 The eye diagram 200 may be used to provide a visual indication of the health of the signal integrity and may indicate the noise margin of the data signal. The noise margin may, for example, refer to the amount by which the signal exceeds the ideal boundary of the amplitude 205.

[0047] To generate the eye diagram 200, an oscilloscope or other computing device may sample a digital signal according to a sampling period 210 (e.g., a unit time interval or bit period). The sampling period 210 may be defined by a clock associated with the transmission of the measured signal. In some examples, the oscilloscope or other computing device may measure the voltage level of the signal during the sampling period 210 to form a trace 215. Noise and other factors may cause the trace 215 to be measured from a signal derived from a set of ideal step functions. By overlaying multiple traces 215, various characteristics about the measured signal may be determined. For example, the eye diagram 200 may be used to identify several characteristics of a communication signal, such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof. A closed eye may indicate noise and / or unpredictable signals or other problems.

[0048] In some examples, the eye diagram 200 may indicate a width 220. The width 220 of the eye in the eye diagram 200 may be used to indicate the timing synchronization of the measured signal or the jitter effect of the measured signal. In some examples, comparing the width 220 to the sampling period 210 may provide an SNR measurement of the measured signal. Each eye in the eye diagram may have a unique width based on the characteristics of the measured signal. Various encoding and decoding techniques may be used to modify the width 220 of the measured signal.

[0049] In other examples, the eye diagram 200 may indicate a sampling time 225 (e.g., an ideal sampling time) for determining the value of the logic state represented by the symbol of the measured signal. For example, determining the correct time to sample data of the measured signal (e.g., timing synchronization) may be important to minimize error rates in signal detection. For example, if a computing device samples a signal during a transition time (e.g., rise time 230 or fall time 235), errors may be introduced into the data represented by the symbol of the signal by the decoder. Various encoding and decoding techniques may be used to modify the ideal sampling time 225 of the measured signal.

[0050] Eye diagram 200 may be used to identify rise time 230 and / or fall time 235 of transition from first amplitude 205 to second amplitude 205. The slope of trace 215 during rise time 230 or fall time 235 may indicate, among other things, the sensitivity of the signal to timing errors. For example, the steeper the slope of trace 215 (e.g., the smaller rise time 230 and / or fall time 235), the more ideal the transition between amplitudes 205. Various encoding and decoding techniques may be used to modify the rise time 230 and / or fall time 235 of the measured signal.

[0051] In some examples, the eye diagram 200 can be used to identify the amount of jitter 240 in the measured signal. Jitter 240 can refer to timing errors caused by misalignment of rise and fall times. Jitter 240 occurs when a rising edge or a falling edge occurs at a different time than the ideal time defined by the data clock. Jitter 240 can be caused by signal reflections, inter-symbol interference, crosstalk, process-voltage-temperature (PVT) variations, random jitter, additive noise, or a combination thereof. Various encoding and decoding techniques can be used to modify the jitter 240 of the measured signal. In some cases, the jitter 240 can be different for each signal level or each eye.

[0052] In other examples, the eye diagram 200 may indicate an eye opening 245, which may represent a peak-to-peak voltage difference between various amplitudes 205. The eye opening 245 may be related to a voltage tolerance for distinguishing between different amplitudes 205 of the measured signal. The smaller the tolerance, the more difficult it may be to distinguish between adjacent amplitudes, and more errors may be introduced due to noise. In some cases, a receiver of the signal (e.g., such as a reference Figure 1 Receiver 130 described above may compare the signal to one or more threshold voltages positioned between various amplitudes 205. In other cases, the larger the eye opening 245, the less likely it is that noise will cause one or more voltage thresholds to be erroneously met. Eye opening 245 may be used to indicate the amount of additive noise in the measured signal and may be used to determine the SNR of the measured signal. Various encoding and decoding techniques may be used to modify the eye opening 245 of the measured signal. In some cases, the eye opening 245 may be different for each eye. In such cases, the eyes of the multi-level signal may not be the same.

[0053] In other examples, the eye diagram 200 may indicate distortion 250. Distortion 250 may represent overshoot and / or undershoot of the measured signal due to noise or interruptions in the signal path. As the signal settles from an old amplitude (e.g., amplitude 205-c) to a new amplitude (e.g., amplitude 205-b), the signal may exceed and / or fall below the new amplitude level. In some examples, distortion 250 may be caused by such overshoot and / or undershoot and may be caused by additive noise in the signal or interruptions in the signal path. Each eye in the eye diagram may have a unique opening based on the characteristics of the measured signal. Various encoding and decoding techniques may be used to modify the distortion 250 of the measured signal. In some cases, the distortion 250 may be different for each signal level or each eye.

[0054] Figure 2 The locations of the characteristics of the eye diagram 200 shown in FIG. 2 are for illustrative purposes only. Characteristics such as width 220, sampling time 225, rise time 230, fall time 235, jitter 240, eye opening 245, and / or distortion 250 may be shown in FIG. Figure 2 The EM field may appear in other parts of the eye diagram 200 not explicitly indicated in FIG.

[0055] Figure 3 An example of a transmit circuit 300 according to various embodiments of the present invention is described. The transmit circuit 300 can be configured to generate a multi-level signal or a binary level signal based on one or more data bits. The transmit circuit 300 can be as shown in FIG. Figure 1 An example of driver 125 is depicted. Transmit circuit 300 may include driver 315, first-in, first-out (FIFO) element 330, multiplexer 335, and pre-driver 340.

[0056] The driver 315 may include a pull-up circuit 305 and a pull-down circuit 310. The transmit circuit 300 may be configured to output signals to a plurality of channels (eg, reference channels) based on logic states received from the memory core 325. Figure 1 In some examples, the transmit circuit 300 can be coupled to a memory core 325, which can be as described in reference Figure 1 An example of a controller 110 or a memory cell array 105 of memory cells is depicted.

[0057] In some examples, the transmit circuit 300 may operate based on data received from the memory core 325. In some examples, the identified data may include one or more bits of information. In other examples, the transmit circuit 300 or the memory controller may identify a desired amplitude level based on the identified data. The transmit circuit 300 or the memory controller may identify a current amplitude level of an output signal of the transmit circuit 300, and in some examples, the transmit circuit 300 or the memory controller may determine a set of instructions for causing the pull-up circuit 305 and / or the pull-down circuit 310 to transition from the current amplitude level of the output signal to the desired amplitude level. Additionally or alternatively, for example, the instructions may include characteristics of a gate voltage (e.g., an amplitude of the gate voltage, a timing of the gate voltage, and / or a pattern of gate voltage activation) to be applied to one or more switching components that couple the output 320 of the driver 315 to two or more voltage sources. The instructions may be configured to cause the output signal to be "pulled up" or "pulled down" to a desired amplitude level.

[0058] In some examples, the memory core 325 can be coupled to a FIFO component 330. For example, data transmitted from the memory core 325 can be routed through the FIFO component 330. The FIFO component 330 can, for example, organize and / or manipulate the data transmitted from the memory core 325. In some examples, the FIFO component 330 can manipulate and / or organize the data according to time and priority. Thus, the FIFO component 330 can process data on a first-come, first-served basis. In some examples, the FIFO component 330 can utilize a memory controller (e.g., as described in reference to Figure 1 In other examples, FIFO component 330 may utilize separate clocks for read and write operations.

[0059] In other examples, data transmitted from the memory core 325 and passing through the FIFO component 330 may be multiplexed via a multiplexer 335. The multiplexer 335 may be coupled to both the memory core 325 and the FIFO component 330. In some examples, the multiplexer 335 may select one of several input signals received from the FIFO component 330. After selecting the input signal, the multiplexer 335 may forward the signal to the pre-driver 340. For example, the pre-driver 340 may be coupled to the multiplexer 335 and may utilize a bias circuit to generate a low power signal. In some examples, the signal generated via the pre-driver 340 may be transmitted to the pull-up circuit 305 and / or the pull-down circuit 310. In some cases, the pre-driver 340 may include one or more inverters connected to the output of the multiplexer 335 to generate a gate signal for the switching component of the driver 315.

[0060] The pull-up circuit 305 can be configured to bias the output signal of the driver 315 from a first amplitude to a second amplitude greater than the first amplitude. Figure 2 If the output signal is first amplitude 205-b as described above, then the pull-up circuit 305 can be used to convert the output signal to either amplitude 205-c or 205-d. The pull-up circuit 305 can be coupled to the first voltage source using one or more switching components (e.g., transistors). The first voltage source can have a voltage greater than the second voltage source associated with the pull-down circuit 310.

[0061] The pull-down circuit 310 can be configured to bias the output signal of the driver 315 from a first amplitude to a second amplitude that is smaller than the first amplitude. For example, if the output signal has a reference Figure 2 If the output signal is at the first amplitude 205-b described above, then the pull-down circuit 310 can be used to convert the output signal to the amplitude 205-a. The pull-down circuit 310 can be coupled to a second voltage source using one or more switching components (e.g., transistors). The second voltage source can have a voltage less than the first voltage source associated with the pull-up circuit 305. In some cases, the pull-down circuit 310 selectively couples the output of the driver 315 with ground or a virtual ground.

[0062] In some cases, the design of the pull-up circuit 305 and / or the pull-down circuit 310 may affect the image quality as shown by the eye diagram (e.g., as shown in FIG. Figure 2 For example, the design of the pull-up circuit 305 and / or the pull-down circuit 310 may affect the eye width (e.g., as shown in FIG. Figure 2 width 220 as described), eye opening (e.g., as described in reference Figure 2 eye opening 245), distortion (e.g., as described in reference Figure 2 Distortion 250 described), jitter (e.g., as described in reference Figure 2 jitter 240 described herein), amplitude, location, other characteristics, or a combination thereof.

[0063] In some cases, the transmit circuit 300 can be configured to selectively generate a binary signal (e.g., NRZ signaling) or a multi-level signal (e.g., PAM4 or PAM8). In other examples, the transmit circuit 300 can be configured to adjust the transmit power of the output signal of the driver 315. Additionally or alternatively, for example, the transmit circuit 300 or a memory controller (e.g., as described in reference Figure 1 The controller 110 described herein may be configured to select one or more channels or one or more groups of channels to communicate the output signal to another component of the memory device.

[0064] Figure 4An example of a receiver 400 according to various embodiments of the present invention is described. The receiver 400 may be configured to receive and / or decode a multi-level signal or a binary level signal. For example, the receiver 400 of a connected component (e.g., the memory cell array 105 or the controller 110 of the memory device 100) may receive a signal using one or more channels (e.g., the channel 115). The receiver 400 may be configured to output one or more data bits based on the received signal. The receiver 400 may include one or more comparators 405 and a decoder 410. The receiver 400 may be a reference Figure 1 An example of a receiver 130 is described.

[0065] The one or more comparators 405 may be configured to compare the received signal with one or more reference voltages 415. The number of comparators 405 may be related to the number of symbols (e.g., amplitude levels) that can be represented in the received signal. For example, if the received signal is a multi-level signal (e.g., a PAM4 signal) configured to have four symbols, the receiver 400 may include three comparators 405-a, 405-b, 405-c and three reference voltages 415-a, 415-b, 415-c.

[0066] Each comparator 405 may output a signal based on whether the received signal is greater than or less than a reference voltage 415. In other words, the comparator 405 may determine whether the received signal satisfies a voltage threshold defined by the comparator 405 and its associated reference voltage 415. For example, the comparator 405 may output a high voltage if the received signal is greater than the associated reference voltage 415 and the comparator 405 may output a low voltage if the received signal is less than the associated reference voltage 415 (or vice versa). The decoder 410 may receive the output of the comparator 405. The reference voltage 415 may be selected to distinguish between expected amplitude levels of the received signal. For example, the reference voltage 415 may be selected to be between two amplitude levels (e.g., amplitudes 205-a and 205-b) within the eye opening 245 of the eye in the eye diagram.

[0067] Decoder 410 may be configured to determine the logic state represented by the sign of the received signal based on the output of comparator 405. A combination of the outputs of comparator 405 may be used to determine the amplitude of the received signal. In some cases, decoder 410 may be an example of a lookup table that indexes the output of comparator 405 to the logic state of the received signal.

[0068] In some examples, if the received signal is less than all of the reference voltages 415, the decoder 410 may determine that a logic state of “00” is represented by the sign of the received signal. If the received signal is greater than one of the reference voltages 415 but less than both of the reference voltages 415, the decoder 410 may determine that a logic state of “01” is represented by the sign of the received signal. If the received signal is greater than both of the reference voltages 415 but less than one of the reference voltages 415, the decoder 410 may determine that a logic state of “10” is represented by the sign of the received signal. If the received signal is greater than all of the reference voltages 415, the decoder 410 may determine that a logic state of “11” is represented by the sign of the received signal. It should be appreciated that the mapping of logic states to amplitudes may be modified based on design choice.

[0069] In some cases, the receiver 400 may be configured to selectively decode binary signals (e.g., NRZ signaling) or multi-level signals (e.g., PAM4 or PAM8). In some cases, the receiver 400 or a connected component may be configured to select one or more channels or one or more channel groups to listen to a received signal from another component of the memory device.

[0070] Figure 5 An example of a memory device 500 according to various embodiments of the invention is described. The memory device 500 may be an example of a high bandwidth memory (HBM) device. The memory device 500 may be configured to provide more data transfer bandwidth per power unit used in the memory device 500. The memory device 500 may include a memory cell array 505, a processor 510, and an interposer 515. The memory device 500 may be a reference Figure 1 An example of a memory device 100 is described.

[0071] Memory cell array 505 may be an example of a 3D memory array. Array 505 may include multiple memory cell stacks 520, each stack 520 being an example of a 2D memory array. Memory cell array 505 may also include a substrate 525 coupling array 505 and interposer 515. One or more through silicon vias (TSVs) (not shown) may be used to couple memory cell stacks 520 and substrate 525. Memory cell array 505 may be a reference Figure 1 An example of a memory cell array 105 is depicted. The memory cell array 505 may be an example of DRAM technology, FeRAM technology, or PCM technology.

[0072] The substrate 525 may be configured as an input / output (I / O) device for the memory cell array 505. In some cases, the substrate 525 may be configured as a memory controller for the memory cell array 505 that accesses various memory cells using row decoders, column decoders, word lines, digit lines, other components, or a combination thereof. In some cases, the substrate 525 may be configured to buffer data communicated to and from the memory cell array 505. The substrate 525 may include a signaling interface (e.g., reference 1 to FIG. 1 ). Figure 1 The signaling interface 120 is described to communicate data across the interposer 515 using binary signaling and / or multi-level signaling.

[0073] Processor 510 may be configured to perform any functions required by the host device. In some cases, processor 510 may be an example of a graphics processing unit (GPU) in a graphics device. In some cases, processor 510 may be an example of a central processing unit (CPU). In some cases, processor 510 may include a memory controller (e.g., reference Figure 1 The processor 510 may include a signaling interface (e.g., reference Figure 1 The signaling interface 120 described above can be used to communicate data across the interposer 515 using binary signaling and / or multi-level signaling. The processor 510 and the array 505 can be coupled to the interposer using micropillars 540.

[0074] The interposer 515 is configured to provide a wide communication channel between connected components (e.g., the array 505, the processor 510, and / or the package substrate 535). The interposer 515 may include a plurality of high resistance channels 530 for communicating between devices. In some cases, the channels 530 may be completely independent of each other. Some channels 530 may be unidirectional and some channels 530 may be bidirectional. The array 505 and / or the processor 510 may select different combinations or groups of channels to communicate data.

[0075] Interposer 515 can provide a wide communication channel by providing a large number of channels 530 to connect components. In some cases, channel 530 can be a thin trace of a connector, thereby making each individual channel lossy. Since each channel 530 is resistive, the power required to transmit data increases in a nonlinear manner relative to the frequency as the frequency of transmitting data increases. Such characteristics can bring a practical upper frequency limit, which can be used to transmit data through channel 530 at a given amount of transmit power. To increase the amount of data transmitted in a given amount of time, interposer 515 can include a very high number of channels 530. Thus, the bus of memory device 500 can be wider than other DRAM memories, such as DDR4 (double data rate fourth generation synchronous dynamic random access memory) or GDDR5 (double data rate type fifth generation synchronous graphic random access memory). In some cases, memory cell array 505 can have two 128-bit channels per stack 520. Therefore, if array 505 has four stacks 520, processor 510 will have a memory bus with a width of 4096 bits. In comparison, some GDDR memories may have only sixteen 32-bit channels of a memory bus having a total width of 512 bits. Interposer 515 may be formed of a first material (e.g., silicon) that is different from a second material forming package substrate 535. Interposer 515 and package substrate may be coupled to other components using one or more solder balls 545, 550.

[0076] Multi-level signaling (e.g., PAM4) can be used in conjunction with memory device 500 (e.g., HBM device) to increase data transfer speed without increasing data transfer frequency. As the frequency of data communicated across interposer 515 increases, the power required to transmit the data increases. This is due to the lossy nature of channel 530. Multi-level signaling can be configured to increase the data rate of data communicated across interposer 515 without increasing the frequency and / or transmit power of the data.

[0077] The memory device 500 may be configured to select various types of signaling that may be used based on the context. For example, in some contexts (e.g., control signaling), the memory device 500 may wish to use binary signaling (e.g., NRZ signaling), and in other contexts (e.g., user data), the memory device may wish to use multi-level signaling (e.g., PAM4, PAM8, etc.).

[0078] Various components of the memory device 500 may include a signaling interface capable of communicating using binary signaling and / or multi-level signaling. For example, the processor 510 and / or the substrate 525 may include a signaling interface, such as reference Figure 1 The signaling interface 120 is described.

[0079] The memory device 500 may be configured to perform a number of access operations (e.g., a read operation or a write operation) on the array 505. For a write operation, the processor 510 may identify information to be written to the memory cell array 505. The processor 510 may generate a multi-level signal modulated using a first modulation scheme having at least three levels using a signaling interface (or a driver of a signaling interface) based on the identified information. The multi-level signal may represent more than one bit of the identified information. The processor 510 may transmit the multi-level signal to the memory cell array 505 using a plurality of channels 530 of the interpolator 515.

[0080] The substrate 525 may receive and decode the multi-level signal using a signaling interface (or a receiver of a signaling interface). The substrate 525 may determine the amplitude of the received multi-level signal. For example, the substrate 525 may use one or more comparators to compare the received multi-level signal with one or more voltage thresholds. Based on whether the voltage threshold is met, the comparator may output a specific signal. The substrate 525 may (for example, using a decoder) determine a plurality of bits represented by the amplitude of the multi-level signal based on the output of the comparator. The substrate 525 may identify one or more memory cells to store a plurality of bits. The substrate 525 may write a plurality of bits to one or more memory cells of the array 505.

[0081] For a read operation, processor 510 may identify some information stored on array 505 that it wishes to use for one of its operations. Processor 510 may transmit a signal (e.g., a binary level signal or a multi-level signal) to array 505 to request the identified information. Base 525 may identify one or more memory cells that currently store the identified information. Base 525 may use a reference Figure 1 The described process reads one or more data bits from the identified cell or cells.

[0082] The substrate 525 can generate a multi-level signal modulated using a first modulation scheme having at least three levels using a signaling interface (or a driver of a signaling interface) based on one or more data bits read from a memory cell. The substrate 525 can transmit the multi-level signal to the processor 510 using a plurality of channels 530 of the interpolator 515.

[0083] The processor 510 may receive and decode the multi-level signal using a signaling interface (or a receiver of a signaling interface). The processor 510 may determine the amplitude of the received multi-level signal. For example, the processor 510 may use one or more comparators to compare the received multi-level signal with one or more voltage thresholds. Based on whether the voltage threshold is met, the comparator may output a specific signal. The processor 510 may (e.g., using a decoder) determine a plurality of bits represented by the amplitude of the multi-level signal based on the output of the comparator.

[0084] Figure 6A block diagram 600 is shown of a signaling component 615 that supports multi-level signaling in a memory with a wide system interface in accordance with an embodiment of the present invention. The signaling component 615 may be referenced Figure 1 Components of signaling interface 120 are described.

[0085] At least some of the signaling component 615 and / or its various subcomponents may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions of at least some of the signaling component 615 and / or its various subcomponents may be performed by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present invention. At least some of the signaling component 615 and / or its various subcomponents may be physically located at various locations, including portions that are distributed so that functions are implemented by one or more physical devices at different physical locations. In some examples, at least some of the signaling component 615 and / or its various subcomponents may be separate and distinct components according to various embodiments of the present invention. In other examples, at least some of the signaling component 615 and / or its various subcomponents may be combined with one or more other hardware components, including but not limited to an I / O component, a transceiver, a network server, another computing device, one or more other components described in the present invention, or a combination thereof according to various embodiments of the present invention.

[0086] Signaling component 615 may include bias component 620, timing component 625, information manager 630, multi-level signal generator 635, cell manager 640, and binary signal generator 645. Each of these components may communicate directly with each other or indirectly (eg, via one or more buses).

[0087] The information manager 630 may identify information to be written to the memory cell array through the controller of the memory device.

[0088] The multi-level signal generator 635 may: generate, through a controller, a multi-level signal modulated using a first modulation scheme having at least three levels representing a set of bits of identified information; transmit, through the controller, the multi-level signal to a memory cell array across an interpolator comprising a set of channels; and determine, through the memory cell array, whether an amplitude of the multi-level signal satisfies one or more thresholds.

[0089] The cell manager 640 may identify the set of bits represented by the multilevel signal and write the set of bits represented by the multilevel signal to one or more memory cells of the memory cell array through the memory cell array based on a threshold number of one or more thresholds satisfied by the multilevel signal.

[0090] The binary signal generator 645 may transmit a binary level signal simultaneously with a multi-level signal to the memory cell array across the interposer through the controller.

[0091] Figure 7 A diagram of a system 700 including a device 705 supporting multi-level signaling in a memory having a wide system interface according to an embodiment of the present invention is shown. The device 705 may be as described above (e.g., with reference to Figure 1 ) or include components of controller 110. Device 705 may include components for two-way voice and data communications, including components for transmitting and receiving communications, including signaling components 715, memory unit 720, basic input / output system (BIOS) components 725, processor 730, I / O controller 735, and peripheral components 740. These components may communicate electronically via one or more buses, such as bus 710.

[0092] Memory cell 720 may store information as described herein (ie, in the form of logic states).

[0093] BIOS component 725 is a software component including BIOS operating as firmware that can initialize and run various hardware components. BIOS component 725 can also manage the data flow between the processor and various other components (e.g., peripheral components, input / output control components, etc.). BIOS component 725 can include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0094] The processor 730 may include an intelligent hardware device (e.g., a general purpose processor, a DSP, a central processing unit (CPU), a microcontroller, an ASIC, an FPGA, a programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some cases, the processor 730 may be configured to operate a memory array using a memory controller. In other cases, the memory controller may be integrated into the processor 730. The processor 730 may be configured to execute computer readable instructions stored in a memory to perform various functions (e.g., functions or tasks that support multi-level signaling in a memory with a wide system interface).

[0095] I / O controller 735 can manage input signals and output signals of device 705. I / O controller 735 can also manage interface devices that are not integrated into device 705. In some cases, I / O controller 735 can represent a physical connection or port to an external interface device. In some cases, I / O controller 735 can utilize an operating system, such as or another known operating system. In other cases, I / O controller 735 may represent or interact with a modem, keyboard, mouse, touch screen, or similar device. In some cases, I / O controller 735 may be implemented as part of a processor. In some cases, a user may interact with device 705 via I / O controller 735 or via hardware components controlled by I / O controller 735.

[0096] Peripheral components 740 may include any input or output device or interface for such a device. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot.

[0097] Input 745 may represent a device or signal external to device 705 that provides input to device 705 or a component of device 705. This may include a user interface or an interface with other devices or between other devices. In some cases, input 745 may be managed by I / O controller 735 and may interact with device 705 via peripheral components 740.

[0098] Output 750 may also represent a device or signal external to device 705 that is configured to receive output from device 705 or any of the components of device 705. Examples of output 750 may include a display, an audio speaker, a printing device, another processor or printed circuit board, etc. In some cases, output 750 may be a peripheral element that interfaces with device 705 via peripheral component 740. In some cases, output 750 may be managed by I / O controller 735.

[0099] The components of device 705 may include circuits designed to carry out their functions. This may include various circuit elements configured to carry out the functions described herein, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements. Device 705 may be a computer, server, laptop, notebook, tablet, mobile phone, wearable electronic device, personal electronic device, or the like. Or device 705 may be part or aspect of such a device.

[0100] In one embodiment, device 705 or system 700 may include: a memory cell array; a controller configured to control access to the memory cell array; an interposer that operably couples the memory cell array and the controller, the interposer including a plurality of channels between the memory cell array and the controller; and a receiver configured to decode a multi-level signal modulated using a first modulation scheme having at least three levels communicated across at least one channel of the interposer.

[0101] Some examples of the device 705 or system 700 described above may also include a driver configured to generate a multi-level signal transmitted across at least one channel of the interpolator based at least in part on the plurality of information bits.

[0102] In some examples of the device 705 or system 700 described above, the driver may be configured to encode data using Gray encoding or data bus inversion, or both.

[0103] In some examples of the device 705 or system 700 described above, the receiver further includes a plurality of comparators, each comparator configured to compare the multi-level signal to a voltage threshold.

[0104] In some examples of the apparatus 705 or system 700 described above, the receiver further includes a decoder configured to determine a plurality of bits represented by the multi-level signal based at least in part on information received from a set of the plurality of comparators.

[0105] Some examples of the device 705 or system 700 described above may also include multiple bits of information that may be represented by the amplitude of the multi-level signal.

[0106] In some examples of the apparatus 705 or system 700 described above, a multi-level signal may be encoded with information using a PAM scheme.

[0107] In some examples of the apparatus 705 or system 700 described above, a controller transmits a multi-level signal to the memory cell array across a subset of the plurality of channels of the interposer.

[0108] In some examples of the apparatus 705 or system 700 described above, the controller transmits the multi-level signal using a unidirectional channel of the interpolator.

[0109] In some examples of the apparatus 705 or system 700 described above, the memory cell array transmits multi-level signals to the controller across a subset of the plurality of channels of the interposer.

[0110] Some examples of the device 705 or system 700 described above may also include a substrate formed of a first material, wherein the interposer may be formed of a second material different from the first material. In some examples of the device 705 or system 700 described above, the second material may be silicon.

[0111]

[0066] Some examples of the device 705 or system 700 described above may also include a second memory cell array stacked on top of the memory cell array, where the second memory cell array may be operably coupled with the controller through an interposer.

[0112] Some examples of the device 705 or system 700 described above may also include an input / output device coupled with the memory cell array and the interposer, where the input / output device may be configured to buffer information communicated with the memory cell array.

[0113] Figure 8 1 shows a flow chart illustrating a method 800 for multi-level signaling in a memory with a wide system interface according to an embodiment of the present invention. The operations of the method 800 may be implemented by the controller 110 or its components as described herein. For example, the method 800 may be implemented by the controller 110 or its components as described in reference to Figure 7 The described signaling components perform the operations of method 800. In some examples, controller 110 may execute a set of codes to control functional elements of the device to perform the functions described below. Additionally or alternatively, controller 110 may use dedicated hardware to perform aspects of the functions described below.

[0114] In some cases, the method may also include identifying information to be written to a memory cell array by a controller of a memory device. In some cases, the method may also include generating, by a controller, a multi-level signal modulated by a first modulation scheme having at least three levels representing a plurality of bits of the identified information. In some cases, the method may also include transmitting the multi-level signal to the memory cell array across an interpolator comprising a plurality of channels by a controller. In some cases, the method may also include determining, by a memory cell array, whether the amplitude of the multi-level signal satisfies one or more thresholds. In some cases, the method may also include identifying, by a memory cell array, a plurality of bits represented by the multi-level signal, at least in part based on a threshold number of one or more thresholds satisfied by the multi-level signal. In some cases, the method may also include writing, by a memory cell array, a plurality of bits represented by the multi-level signal to one or more memory cells of the memory cell array. In some cases, the method may also include transmitting, by a controller, a binary level signal and a multi-level signal simultaneously to the memory cell array across an interpolator.

[0115] At block 805, the controller 110 may identify information to be written to the memory cell array via a controller of the memory device. The operations of block 805 may be performed according to the methods described herein. In a specific example, the information may be written to the memory cell array as described in reference to FIG. Figure 7 The described information manager performs aspects of the operations of block 805 .

[0116] At block 810, the controller 110 may generate, by the controller, a multi-level signal modulated using a first modulation scheme having at least three levels representing a plurality of bits of the identified information. The operation of block 810 may be performed according to the method described herein. In a specific example, the multi-level signal may be modulated by a first modulation scheme having at least three levels representing a plurality of bits of the identified information. Figure 7 The multi-level signal generator described performs aspects of the operations of block 810 .

[0117] At block 815, the controller 110 may transmit the multi-level signal to the memory cell array across the interposer including the plurality of channels via the controller. The operation of block 815 may be performed according to the method described herein. In a specific example, the operation may be performed as described in reference to Figure 7 The multi-level signal generator described performs aspects of the operations of block 815 .

[0118] A method is described. The method may include: identifying, by a controller of a memory device, information to be written to a memory cell array; generating, by the controller, a multi-level signal modulated using a first modulation scheme having at least three levels representing a plurality of bits of the identified information; and transmitting, by the controller, the multi-level signal to the memory cell array across an interposer comprising a plurality of channels.

[0119] Method 800 may be implemented by an apparatus that may include: means for identifying, by a controller of a memory device, information to be written to a memory cell array; means for generating, by the controller, a multi-level signal modulated using a first modulation scheme having at least three levels representing a plurality of bits of the identified information; and means for transmitting, by the controller, the multi-level signal to the memory cell array across an interposer comprising a plurality of channels.

[0120] In some cases, the apparatus may further include means for determining, by the memory cell array, whether an amplitude of the multi-level signal satisfies one or more thresholds.

[0121] In some cases, the apparatus may further include means for identifying, by the array of memory cells, a plurality of bits represented by the multilevel signal based at least in part on a threshold number of one or more thresholds satisfied by the multilevel signal.

[0122] In some cases, the apparatus may further include means for writing, through the memory cell array, a plurality of bits represented by the multi-level signal to one or more memory cells of the memory cell array.

[0123] In some cases, the apparatus may further include means for transmitting, by the controller, the binary level signal simultaneously with the multi-level signal to the memory cell array across the interposer.

[0124] Method 800 may be implemented by another device, which may include: a processor; a memory in electronic communication with the processor; and instructions stored in the memory. The instructions are operable to cause the processor to: identify, by a controller of the memory device, information to be written to a memory cell array; generate, by the controller, a multi-level signal modulated using a first modulation scheme having at least three levels representing a plurality of bits of the identified information; and transmit, by the controller, the multi-level signal to the memory cell array across an interpolator comprising a plurality of channels.

[0125] Method 800 may be implemented by a non-transitory computer-readable medium that may include instructions operable to cause a processor to: identify, by a controller of a memory device, information to be written to a memory cell array; generate, by the controller, a multi-level signal modulated using a first modulation scheme having at least three levels representing a plurality of bits of the identified information; and transmit, by the controller, the multi-level signal to the memory cell array across an interpolator comprising a plurality of channels.

[0126] Some examples of the method 800 , apparatus, and non-transitory computer-readable media described above may further include a process, feature, means, or instruction for determining, by a memory cell array, whether an amplitude of a multi-level signal satisfies one or more thresholds.

[0127] Some examples of the method 800, apparatus, and non-transitory computer-readable media described above may further include processes, features, means, or instructions for identifying, through a memory cell array, a plurality of bits represented by a multi-level signal based at least in part on a threshold number of one or more thresholds that the multi-level signal may satisfy.

[0128] Some examples of the method 800, apparatus, and non-transitory computer-readable media described above may further include processes, features, means, or instructions for writing, through a memory cell array, a plurality of bits represented by a multi-level signal to one or more memory cells of a memory cell array.

[0129] Some examples of the method 800, apparatus, and non-transitory computer-readable media described above may further include processes, features, means, or instructions for transmitting, by a controller, a binary level signal and a multi-level signal simultaneously to the memory cell array across an interposer.

[0130] In one embodiment, a device or system may include: a memory cell array; an interposer operably coupled to the memory cell array, the interposer including a plurality of channels; a controller operably coupled to the interposer, the controller configured to: identify information to be written to the memory cell array; generate a multi-level signal modulated using a first modulation scheme having at least three levels representing a plurality of bits of the identified information; and transmit the multi-level signal to the memory cell array across the interposer.

[0131] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified so that other implementations are possible. Furthermore, two or more embodiments from the methods may be combined.

[0132] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have various bit widths.

[0133] As used herein, the term "virtual ground" refers to a node of a circuit that is maintained at a voltage of approximately zero volts (0V) but is not directly connected to ground. Thus, the voltage of the virtual ground may temporarily fluctuate and return to approximately 0V in a steady state. Virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and a resistor. Other implementations are also possible. "Virtual ground" or "virtual ground" means connecting to approximately 0V.

[0134] The terms "electronic communication" and "coupling" refer to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components or may include intermediate components. Components in electronic communication may be actively exchanging electrons or signals (e.g., in an energized circuit) or may not be actively exchanging electrons or signals (e.g., in a de-energized circuit), but may be configured and operable to exchange electrons or signals after energizing the circuit. By way of example, two components that are physically connected via a switch (e.g., a transistor) are in electronic communication regardless of the state of the switch (i.e., open or closed).

[0135] As used herein, the term "substantially" means that the modified property (eg, a verb or adjective modified by the term substantially) is not necessarily absolute, but is close enough to achieve the advantage of the property.

[0136] As used herein, the term "electrode" may refer to a conductor, and in some cases may be employed as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, a line, a conductive wire, a conductive layer, or the like that provides a conductive path between elements or components of the memory device 100.

[0137] As used herein, the term "photolithography" may refer to a process of patterning using a photoresist material and exposing such material using electromagnetic radiation. For example, a photoresist material may be formed on a substrate material by, for example, spin coating the photoresist on the substrate material. A pattern may be created in the photoresist by exposing the photoresist to radiation. For example, the pattern may be defined by a photomask that spatially depicts the locations where the radiation exposes the photoresist. For example, the exposed photoresist areas may then be removed by a chemical treatment, leaving behind the desired pattern. In some cases, the exposed areas may be maintained and the unexposed areas may be removed.

[0138] Chalcogenide materials may be materials or alloys including at least one of the elements S, Se, and Te. The phase change materials discussed herein may be chalcogenide materials. Chalcogenide materials may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-A s, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, T e-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-B i-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. As used herein, chemical composition designations connected by hyphens indicate elements included in a particular compound or alloy and are intended to represent all ideal proportions involving the indicated elements. For example, Ge-Te may include Ge x Te y , where x and y may be any positive integer. Other examples of variable resistance materials may include binary metal oxide materials or mixed valence oxides including two or more metals (e.g., transition metals, alkaline earth metals, and / or rare earth metals). Embodiments are not limited to one or more specific variable resistance materials associated with the memory element of the memory cell. For example, other examples of variable resistance materials may be used to form the memory element and may include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, etc.

[0139] The term "isolation" refers to a relationship between components where electrons cannot currently flow between them; if there is an open circuit between components, they are isolated from each other. For example, two components that are physically connected by a switch can be isolated from each other when the switch is open.

[0140] As used herein, the term "short" refers to a relationship between components in which a conductive path is established between the components via activation of a single intermediate component between the two components. For example, a first component shorted to a second component may exchange electrons with the second component when a switch between the two components is closed. Thus, shorting may be a dynamic operation that enables the flow of charge between components (or lines) in electronic communication.

[0141] The devices discussed herein, including memory device 100, may be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0142] The transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0143] The descriptions set forth herein and the accompanying drawings describe example configurations and do not represent all examples that may be implemented or within the scope of the claims. The term "example" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples". The embodiments include specific details for the purpose of providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0144] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. When only the first reference label is used in the specification, the description may apply to any of the similar components with the same first reference label, regardless of the second reference label.

[0145] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0146] The various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0147] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the function may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of the software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or any combination of these. The features of the implementation functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations. Moreover, as used herein, included in the claims, such as a list of items (e.g., a list of items starting with a phrase such as "at least one of" or "one or more of"), the "or" used indicates a list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a conditional closed set. For example, without departing from the scope of the present invention, the example steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0148] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media that can be accessed by a general or special purpose computer. By way of example but not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage device or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general or special purpose computer or a general or special purpose processor. Moreover, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0149] The description herein is provided to enable one skilled in the art to make or use the invention. Various modifications of the invention will be readily apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but should be in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a memory cell array; a controller configured to control operation of memory cells in the memory cell array; a signaling interface coupled to the memory cell array and configured to generate a signal modulated using a first modulation scheme based at least in part on logic states read from the memory cell array; and A receiver is configured to determine the logic state represented by the signal modulated using the first modulation scheme communicated across at least one channel of a plurality of channels between the memory cell array and the controller.

2. The apparatus according to claim 1, further comprising: An interposer is operatively coupled to the memory cell array and the controller, wherein the interposer includes the plurality of channels between the memory cell array and the controller.

3. The apparatus according to claim 1, further comprising: A substrate is coupled to the controller via a second plurality of channels.

4. The device according to claim 1, wherein the signaling interface comprises: A driver is coupled to the controller and configured to generate the signal.

5. The device of claim 4, wherein the driver comprises: a pull-up circuit configured to increase the amplitude of the signal; and A pull-down circuit is configured to reduce the amplitude of the signal.

6. The apparatus of claim 1, wherein: The signal communicated across the at least one channel comprises a multi-level signal; and The at least one channel comprises a unidirectional channel.

7. The apparatus of claim 1, wherein the receiver comprises: One or more comparators, each comparator configured to compare the signal to a corresponding reference voltage of one or more reference voltages.

8. The apparatus of claim 7, wherein the receiver further comprises: A decoder is configured to determine the logic state represented by the signal based at least in part on a respective output of each comparator of the one or more comparators.

9. The apparatus of claim 1, wherein the first modulation scheme comprises a non-return-to-zero (NRZ) scheme, a unipolar coding scheme, a bipolar coding scheme, a Manchester coding scheme, a two-level pulse amplitude modulation (PAM) scheme, a four-level PAM scheme, an eight-level PAM scheme, a quadrature amplitude modulation (QAM) scheme, quadrature phase shift keying, or a combination thereof.

10. A method comprising: identifying, by a controller of the memory device, information to be written to the memory cell array; generating, by the controller, a signal representing a plurality of bits of identified information, wherein the signal is modulated using a first modulation scheme; and The signal is transmitted to the memory cell array by the controller across at least one channel of a plurality of channels between the controller and the memory cell array.

11. The method according to claim 10, further comprising: receiving data from the memory cell array via a transmit circuit based at least in part on transmitting the signal; and Instructions are determined by the controller including adjustments to the amplitude of the signal.

12. The method according to claim 11, further comprising: The signal is biased via a pull-up circuit to increase the amplitude of the signal based at least in part on the instruction.

13. The method according to claim 11, further comprising: The signal is biased via a pull-down circuit to reduce the amplitude of the signal based at least in part on the instruction.

14. The method according to claim 10, further comprising: comparing the signal to one or more voltage thresholds via the memory cell array; identifying, by the memory cell array, the plurality of bits represented by the signal based at least in part on comparing the signal to the one or more voltage thresholds; and The plurality of bits represented by the signal are written through the memory cell array to one or more memory cells of the memory cell array.

15. An apparatus comprising: a memory cell array; and a controller coupled to the memory cell array and configured to cause the apparatus to: identifying information to be written to the memory cell array; generating a signal representing a plurality of bits of identified information, wherein the signal is modulated using a first modulation scheme; and The signal is transmitted to the memory cell array across at least one channel of a plurality of channels between the controller and the memory cell array.

16. The apparatus of claim 15, wherein the controller is further configured to cause the apparatus to: receiving data from the array of memory cells based at least in part on transmitting the signal; and Instructions are determined that include adjusting an amplitude of an output signal based at least in part on the received data.

17. The apparatus of claim 16, wherein the controller is further configured to cause the apparatus to: The output signal is biased based at least in part on the command to increase or decrease the amplitude of the output signal.

18. The apparatus of claim 15, wherein the controller is further configured to cause the apparatus to: comparing the signal to one or more voltage thresholds; identifying the plurality of bits represented by the signal based at least in part on comparing the signal to the one or more voltage thresholds; and The plurality of bits represented by the signal are written to one or more memory cells of the memory cell array.

19. The apparatus of claim 15, wherein: The signal communicated across the at least one channel comprises a multi-level signal; and The at least one channel comprises a unidirectional channel.

20. The apparatus of claim 15, wherein the first modulation scheme comprises a non-return-to-zero (NRZ) scheme, a unipolar coding scheme, a bipolar coding scheme, a Manchester coding scheme, a two-level pulse amplitude modulation (PAM) scheme, a four-level PAM scheme, an eight-level PAM scheme, a quadrature amplitude modulation (QAM) scheme, quadrature phase shift keying, or a combination thereof.

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