Partial programming block fill operations

Abstract

The invention relates to partial programming block fill operations. Apparatuses and methods are provided for programming a partially programmed block with padding. An example apparatus may include a controller configured to program a first number of word lines in a block of word lines in a memory cell array, where the first number of word lines is less than a total number of word lines in the block; and programming a second number of word lines of the array of memory cells, where the second number of word lines is programmed with padding, and where the second number of word lines is different from the first number of word lines, and the total number of word lines in the block includes the first and second numbers of word lines.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 531,091, filed on August 7, 2023, the contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to partially programmed blocks, and more particularly, to apparatus and methods for programming partially programmed blocks with padding. Background Art

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data, and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can provide permanent data by retaining stored data when not powered, and can include NAND flash memory, NOR flash memory, phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), etc.

[0005] Memory devices may be combined together to form a solid-state drive (SSD). An SSD may include nonvolatile memory (e.g., NAND flash memory and / or NOR flash memory), and / or may include volatile memory (e.g., DRAM and / or SRAM), as well as various other types of nonvolatile and volatile memory. For example, a flash memory device may include a memory cell that stores data in a charge storage structure such as a floating gate, and may be used as nonvolatile memory for a wide range of electronic applications. Flash memory devices typically use a single-transistor memory cell that allows for high memory density, high reliability, and low power consumption.

[0006] SSDs can be used to replace hard disk drives as the primary storage capacity of a computer because solid-state drives can have advantages over hard disk drives in terms of performance, size, weight, ruggedness, operating temperature range, and power consumption. For example, when compared to magnetic disk drives, SSDs can have superior performance due to their lack of moving parts, which can avoid seek times, latencies, and other electromechanical delays associated with magnetic disk drives.

[0007] Memories are used as volatile and nonvolatile data storage devices for a wide range of electronic applications. Nonvolatile memories can be used, for example, in personal computers, portable memory sticks, digital cameras, cellular phones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged in an array, where the array is used in a memory device.

[0008] Memory cells in an array architecture can be programmed to a desired state. For example, charge can be placed on or removed from a charge storage structure (e.g., a floating gate) of a memory cell to program the cell to a specific state. For example, a single level (memory) cell (SLC) can be programmed to one of two different states, each state representing a different number of data values, such as 1 or 0. Some flash memory cells can be programmed to one of more than two states corresponding to different specific data values, such as 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, or 1110. Such cells may be referred to as multi-state memory cells, multi-unit cells, or multi-level (memory) cells (MLC). MLCs can provide higher density memory without increasing the number of memory cells because each cell can be programmed to a state corresponding to more than one number (eg, more than one bit of data). Summary of the invention

[0009] One aspect of the present disclosure relates to an apparatus for filling a partially programmed block, comprising: a memory cell array; a controller coupled to the memory cell array, and the controller is configured to: program a first number of word lines in a word line block in the memory cell array, wherein the first number of word lines is less than the total number of word lines in the block; and program a second number of word lines of the memory cell array, wherein the second number of word lines is programmed with filling, and wherein the second number of word lines is different from the first number of word lines, and the total number of word lines in the block includes the first and second numbers of word lines.

[0010] Another aspect of the present disclosure relates to an apparatus for filling a partially programmed block, comprising: a memory cell array; a controller coupled to the memory cell array, and the controller is configured to: program a first number of word lines in a word line block in the memory cell array with valid data using a programming operation in a four-level cell (QLC) mode, wherein the first number of word lines is less than the total number of word lines in the block; and program a second number of word lines in the word line block in the memory cell array with filling, wherein when the first number of word lines in the block are programmed, the second number of word lines are not programmed.

[0011] Another aspect of the present disclosure relates to a method for filling a partially programmed block, comprising: programming a first number of word lines in a word line block in a memory cell array, wherein the first number of word lines is less than the total number of word lines in the block; and programming a second number of word lines in the word line block, wherein the second number of word lines is programmed with filling, and wherein the second number of word lines is different from the first number of word lines, and the total number of word lines in the block includes the first and second numbers of word lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram of a device in the form of a computing system including at least one memory system, according to several embodiments of the present disclosure.

[0013] Figure 2 A schematic diagram illustrating a portion of a non-volatile memory array according to several embodiments of the present disclosure.

[0014] Figure 3A A table indicating data stored in a word line when a partially programmed block is filled according to an embodiment of the present disclosure is described.

[0015] Figure 3B A table indicating data stored in a word line when a partially programmed block is filled according to an embodiment of the present disclosure is described.

[0016] Figure 4 is a flow chart of a method for operating a controller configured to populate a partially programmed block, according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] The present disclosure provides an apparatus and method for programming a partially programmed block with padding. An example apparatus may include a controller configured to: program a first number of word lines in a word line block in a memory cell array, wherein the first number of word lines is less than the total number of word lines in the block; and program a second number of word lines of the memory cell array, wherein the second number of word lines is programmed with padding, and wherein the second number of word lines is different from the first number of word lines, and the total number of word lines in the block includes the first and second numbers of word lines.

[0018] While the memory device is being programmed, a read command for data located in a partially programmed block (e.g., a block in which a portion of a word line is programmed and a portion of a word line is not programmed in an erased state) may be received. During a read operation, the threshold voltages of memory cells in the partially programmed block may be different from the threshold voltages of memory cells in the fully programmed block due to back pattern effects. When the same pass voltage is applied to word lines that are not sensed in the partially programmed block and in the fully programmed block, the word lines sensed in the partially programmed block may have a lower threshold voltage than the word lines sensed in the fully programmed block due to the partially programmed block experiencing a different string current than the fully programmed block.

[0019] In several embodiments, the lower threshold voltage in the partially programmed block can also be attributed to capacitive coupling between programmed and unprogrammed word lines and lateral charge migration between programmed and unprogrammed word lines.

[0020] In several embodiments, when a programming operation on a partially programmed block is completed or interrupted, the remaining unprogrammed word lines in the partially programmed block may be programmed with fill. The fill may be random invalid data received from a host and / or generated by a controller on the memory device. The fill may program the previously unprogrammed word lines in the partially programmed block with data that may reduce the reduction in threshold voltage caused by back pattern effects, capacitive coupling, and / or lateral charge migration when reading data in the partially programmed block.

[0021] In several embodiments, the fill may be programmed using a process programming operation in a quad level cell (QLC) mode, which may be the same mode used to program valid data in a partially programmed block. The fill may also be programmed using a programming operation in a single level cell (SLC) mode, a multi-level cell (MLC) mode, and / or a three level cell (TLC) mode, where the mode is changed from the mode used to program valid data in a partially programmed block. Programming the fill using a process QPL programming operation and / or a programming operation in SLC, MLC, or TLC mode may allow the fill to occur in a shorter time than continuing to program the block with the fill using a normal QLC programming operation that includes both process and fine programming operations. Programming the fill using a process QLC programming operation may reduce the fill programming time by more than 70% when compared to filling using a normal QLC programming operation that includes both process and fine programming operations. Programming the fill using a TLC programming operation may reduce the fill programming time by more than 80% when compared to filling using a normal QLC programming operation that includes both process and fine programming operations. The programming time for programming a fill using an SLC programming operation may be 10 times faster than a fill using a normal QLC programming operation including both process and fine programming operations.

[0022] In the following detailed description of the present disclosure, reference is made to the accompanying drawings which form a part of the present disclosure and in which are shown by way of illustration how several embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it is understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the present disclosure.

[0023] As used herein, "a number of" something may refer to one or more of such things. For example, a number of memory cells may refer to one or more memory cells. Additionally, the designators "M" and "N" as used herein (especially with respect to reference numbers in the drawings) indicate that several embodiments of the present disclosure may include several of the particular features so indicated.

[0024] The figures herein follow a numbering convention, wherein the first or first few bits correspond to the figure number of the accompanying drawings and the remaining bits identify the elements or components in the accompanying drawings. Similar elements or components between different figures can be identified by using similar bits. The elements shown in various embodiments herein can be added, exchanged and / or eliminated to provide several additional embodiments of the present disclosure. In addition, the proportions and relative scales of the elements provided in the figures are intended to illustrate embodiments of the present disclosure and should not be considered as limiting.

[0025] Figure 11 is a block diagram of an apparatus in the form of a computing system 101 including at least one memory system 104 according to several embodiments of the present disclosure. As used herein, a memory system 104, a controller 108, or a memory device 110 may also be individually referred to as a "device". The memory system 104 may be, for example, a solid-state drive (SSD), and may include a host interface 106, a controller 108 (e.g., a processor and / or other control circuitry), and a number of memory devices 110-1, ..., 110-M (e.g., solid-state memory devices such as NAND flash memory devices that provide storage capacity for the memory system 104). In several embodiments, the controller 108, the memory devices 110-1 to 110-M, and / or the host interface 106 may be physically located on a single die or within a single package (e.g., a managed NAND application). Moreover, in several embodiments, the memory (e.g., the memory devices 110-1 to 110-M) may include a single memory device.

[0026] like Figure 1 , the controller 108 may be coupled to the host interface 106 and the memory devices 110-1, ..., 110-M via multiple channels, and may be used to transfer data between the memory system 104 and the host 102. The interface 106 may be in the form of a standardized interface. For example, when the memory system 104 is used for data storage in the computing system 100, the interface 106 may be a Serial Advanced Technology Attachment (SATA), a Peripheral Component Interconnect Express (PCIe), or a Universal Serial Bus (USB), among other connectors and interfaces. However, in general, the interface 106 may provide an interface for passing control, address, data, and other signals between the memory system 104 and a host 102 having a compatible receiver of the interface 106.

[0027] The host 102 may be a host system, such as a personal laptop computer, a desktop computer, a digital camera, a mobile phone, or a memory card reader, as well as various other types of hosts. The host 102 may include a system motherboard and / or a backplane, and may include several memory access devices, such as several processors.

[0028] Controller 108 may communicate with memory devices 110-1, ..., 110-M to control data read, write, and erase operations, among other operations. Controller 108 may include, for example, several components in the form of hardware and / or firmware (e.g., one or more integrated circuits), and / or software for controlling access to several memory devices 110-1, ..., 110-M and / or for facilitating data transfer between host 102 and memory devices 110-1, ..., 110-M. For example, in Figure 1In the example illustrated in FIG. 1 , the controller 108 includes an error correction code encoder / decoder component 114. However, the controller 108 may include various other components that are not illustrated so as not to obscure the embodiments of the present disclosure. Moreover, the component 114 may not be a component of the controller 108, and in some embodiments, for example, the component 114 may be a separate component.

[0029] For example, the error correction code encoder / decoder component 114 may be an LDPC encoder / decoder that may encode / decode user data transferred between the host 102 and the memory devices 110 - 1 , . . . , 110 -M.

[0030] Memory devices 110-1, ..., 110-M may include several arrays of memory cells. For example, the array may be a flash memory array having a NAND architecture. However, embodiments are not limited to a particular type of memory array or array architecture. Memory cells may, for example, be grouped into several blocks comprising several physical pages. Several blocks may be included in a plane of memory cells and the array may include several planes. As an example, a memory device may be configured to store 8KB (kilobytes) of user data per page, 128 pages of user data per block, 2048 blocks per plane, and 16 planes per device.

[0031] Figure 2 A schematic diagram illustrating a portion of a non-volatile memory array 200 according to several embodiments of the present disclosure. Figure 2 The embodiments of the present invention illustrate a NAND architecture non-volatile memory array, such as a NAND flash memory. However, the embodiments described herein are not limited to this example. Figure 2 , the memory array 200 includes access lines (e.g., word lines 205-1, ..., 205-N), and intersecting data lines (e.g., local bit lines 207-1, 207-2, 207-3, ..., 207-M). To facilitate addressing in a digital environment, the number of word lines 205-1, ..., 205-N and the number of local bit lines 207-1, 207-2, 207-3, ..., 207-M ​​can be some power of 2, such as 256 word lines times 4,096 bit lines.

[0032] The memory array 200 includes NAND strings 209-1, 209-2, 209-3, ..., 209-M. Each NAND string includes nonvolatile memory cells 211-1, ..., 211-N, each of which is communicatively coupled to a respective word line 205-1, ..., 205-N. Each NAND string (and its constituent memory cells) is also associated with a local bit line 207-1, 207-2, 207-3, ..., 207-M. The nonvolatile memory cells 211-1, ..., 211-N of each NAND string 209-1, 209-2, 209-3, ..., 209-M are connected in series source to drain between a source select gate (SGS) (e.g., a field effect transistor (FET)) 213 and a drain select gate (SGD) (e.g., a FET) 214. Each source select gate 213 is configured to selectively couple a respective NAND string to a common source 223 in response to a signal on a source select line 217 , while each drain select gate 214 is configured to selectively couple a respective NAND string to a respective bit line in response to a signal on a drain select line 215 .

[0033] like Figure 2 , the source of the source select gate 213 is connected to the common source line 223. The drain of the source select gate 213 is connected to the source of the memory cell 211-1 of the corresponding NAND string 209-1. The drain of the drain select gate 214 is connected to the bit line 207-1 of the corresponding NAND string 209-1 at the drain contact 221-1. The source of the drain select gate 214 is connected to the drain of the last memory cell 211-N (e.g., a floating gate transistor) of the corresponding NAND string 209-1.

[0034] In some embodiments, the construction of the nonvolatile memory cells 211-1, ..., 211-N includes a source, a drain, a charge storage structure such as a floating gate, and a control gate. The nonvolatile memory cells 211-1, ..., 211-N have their control gates coupled to word lines 205-1, ..., 205-N, respectively. A "column" of nonvolatile memory cells 211-1, ..., 211-N makes up a NAND string 209-1, 209-2, 209-3, ..., 209-M, and is coupled to a given local bit line 207-1, 207-2, 207-3, ..., 207-M, respectively. A "row" of nonvolatile memory cells is those memory cells that are commonly coupled to a given word line 205-1, ..., 205-N. The use of the terms "column" and "row" is not intended to imply a particular linear (e.g., vertical and / or horizontal) orientation of the nonvolatile memory cells. A NOR array architecture would be laid out similarly, differing only in that strings of memory cells would be coupled in parallel between select gates.

[0035] A subset of cells coupled to a selected word line (e.g., 205-1, ..., 205-N) can be programmed and / or read together as a page of memory cells. A programming operation (e.g., a write operation) can include applying a number of programming pulses (e.g., 16V to 20V) to a selected word line in order to increase the threshold voltage (Vt) of a selected cell coupled to the selected access line to a desired programming voltage level corresponding to a target (e.g., desired) state (e.g., charge storage state). States are equivalently referred to herein as "levels".

[0036] A read operation (which may also be referred to as a program verification operation) may include sensing a voltage and / or current change of a bit line coupled to a selected cell in order to determine the state of the selected cell. The state of a particular fractional-bit memory cell may not correspond directly to the data value of the particular memory cell, but rather the states of a group of memory cells including the particular memory cell together map to a data value having an integer number of bits. A read operation may include precharging the bit line and detecting a discharge when the selected cell begins to conduct.

[0037] Determining (e.g., detecting) the state of a selected cell may include providing a number of sense signals (e.g., read voltages) to a selected word line while providing a number of voltages (e.g., read pass voltages) to word lines coupled to unselected cells of the string sufficient to place the unselected cells in a conductive state that is independent of the threshold voltage of the unselected cells. The bit lines corresponding to the selected cells being read and / or verified may be detected to determine whether the selected cell is conductive in response to a particular sense signal applied to the selected word line. For example, the state of a selected cell may be determined by the word line voltage when the bit line current reaches a particular reference current associated with a particular state.

[0038] For example, the array may include single level cells (SLC) storing 1 bit per cell, multi level cells (MLC) storing 2 bits per cell, three level cells (TLC) storing three bits per cell, or quad level cells (QLC) storing 4 bits per cell. Embodiments are not limited to a particular type of memory cell.

[0039] The MLC may be a two-bit (e.g., four-state) memory cell, or each memory cell may store more than two data bits, including storing fractional data bits per memory cell. For example, the two-bit memory cells may be programmed to one of four states, e.g., P0, P1, P2, and P3, respectively. In operation, a number of memory cells (e.g., in a selected block) may be programmed so that they have a Vt level corresponding to any one of P0, P1, P2, or P3. As an example, state P0 may represent a stored data value such as binary "11". State P1 may represent a stored data value such as binary "10". State P2 may represent a stored data value such as binary "00". State P3 may represent a stored data value such as binary "01". However, embodiments are not limited to these data value correspondences.

[0040] TLC can be a three-bit (e.g., eight-state) memory cell, or each memory cell can store more than three data bits, including storing fractional data bits per memory cell. For example, the three-bit memory cells can be programmed to one of eight states, such as P0, P1, P2, P3, P4, P5, P6, or P7, respectively. In operation, a number of memory cells (e.g., in a selected block) can be programmed so that they have a Vt level corresponding to any one of P0, P1, P2, P3, P4, P5, P6, or P7. As an example, state P0 can represent a stored data value such as binary "111". State P1 can represent a stored data value such as binary "110". State P2 can represent a stored data value such as binary "101". State P3 can represent a stored data value such as binary "100". State P4 can represent a stored data value such as binary "011". State P5 may represent a stored data value of, for example, binary "010." State P6 may represent a stored data value of, for example, binary "001." State P7 may represent a stored data value of, for example, binary "000." However, embodiments are not limited to these data value correspondences.

[0041] QLCs may be four-bit (e.g., 16-state) memory cells, or each memory cell may store more than four data bits, including fractional data bits per memory cell. For example, four-bit memory cells may be individually programmed to one of 16 states, such as P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, or P15. In operation, a number of memory cells (e.g., in a selected block) may be programmed so that they have a Vt level corresponding to any one of P0, P1, P2, P3, P4, P5, P6, or P7. As an example, state P0 may represent a stored data value such as binary "1111". State P1 may represent a stored data value such as binary "1100". State P2 may represent a stored data value such as binary "1101". State P3 may represent a stored data value, such as binary “1100”. State P4 may represent a stored data value, such as binary “1011”. State P5 may represent a stored data value, such as binary “1010”. State P6 may represent a stored data value, such as binary “1001”. State P7 may represent a stored data value, such as binary “1000”. State P8 may represent a stored data value, such as binary “0111”. State P9 may represent a stored data value, such as binary “0110”. State P10 may represent a stored data value, such as binary “0101”. State P11 may represent a stored data value, such as binary “0100”. State P12 may represent a stored data value, such as binary “0011”. State P13 may represent a stored data value, such as binary “0010”. State P14 may represent a stored data value, such as binary “0001”. State P15 may represent, for example, a stored data value of binary “0000.” However, embodiments are not limited to these data value correspondences.

[0042] Figure 3AA table indicating data stored in a word line when a partially programmed block is filled according to an embodiment of the present disclosure is described. The table illustrates the type of data programmed to a partially programmed block when a partially programmed block is filled according to an embodiment of the present disclosure. When a programming operation is performed, the programming operation may end with a block that is not fully programmed, thereby generating a partially programmed block. Moreover, when a programming operation is performed, the programming operation may be interrupted or stopped before it is completed, thereby generating a partially programmed block. When reading data on a partially programmed block, the threshold voltage of a memory cell may be lower than the threshold voltage of a memory cell on a fully programmed block due to back pattern effects, capacitive coupling and / or lateral charge migration. Filling can be used to program memory cells on word lines that have not been programmed due to completion or interruption of a programming operation to reduce the drop in the threshold voltage in the memory cell due to back pattern effects, capacitive coupling and / or lateral charge migration when reading memory cells on a partially programmed block.

[0043] like Figure 3A As shown in , the programming operation may begin by programming valid data 340 to the memory cells coupled to word line 305-1. The programming operation may continue to program valid data 340 to the memory cells coupled to word lines 305-2 to 304-(T-1). Figure 3A , once a programming operation reaches word line 305-T and programs valid data 340 into memory cells coupled to word line 305-T, the programming operation may be completed, interrupted, or canceled, resulting in a partially programmed block.

[0044] Filling may be utilized to program memory cells that were not programmed during a programming operation to reduce the drop in threshold voltage due to back pattern effects, capacitive coupling, and / or lateral charge migration when reading memory cells on a partially programmed block. Since the programming operation is completed, interrupted, or canceled when valid data 340 is programmed to memory cells coupled to word line 305-T, memory cells coupled to word line 305-(T+1) have been programmed with process data 342 as part of the QLC programming operation performed on word lines 305-1 to 305-T, program filling may be initiated on memory cells coupled to word line 305-(T+2).

[0045] The memory cells coupled to word lines 305-(T+2) to 305-N may be programmed with fill 344. Fill 344 may be invalid random data. The random data may be received from a host coupled to the memory device and / or generated by a controller of the memory device. Fill 344 may be programmed using a process programming operation in QLC mode. Fill may also be performed using SLC, MLC, and / or TLC programming operations by switching from QLC mode to SLC, MLC, and / or TLC mode to perform a fill programming operation.

[0046] Figure 3B A table indicating data stored in a word line when a partially programmed block is filled according to an embodiment of the present disclosure is described. The table illustrates the type of data programmed into a partially programmed block when a partially programmed block is filled according to an embodiment of the present disclosure. When performing a programming operation, the programming operation may end without a portion of a word line of a block being fully programmed, thereby producing a partially programmed block. Moreover, when performing a programming operation, the programming operation may be interrupted or stopped before it is completed, resulting in a portion of a word line of a block being incompletely programmed, thereby producing a partially programmed block. Figure 3B In the embodiment of the present invention, the memory cells coupled to the word line 305-T are partially programmed, wherein a first portion of the memory cells are programmed with valid data and a second portion of the memory cells are programmed with process data (e.g., the programming operation on the second portion of the memory cells is not completed). When reading the data on the partially programmed block, the threshold voltage of the memory cells may be lower than the threshold voltage of the memory cells on the fully programmed block due to back pattern effects, capacitive coupling, and / or lateral charge migration. The memory cells on the word line that are not programmed due to the completion or interruption of the programming operation may be programmed with filling to reduce the drop in the threshold voltage in the memory cells due to back pattern effects, capacitive coupling, and / or lateral charge migration when reading the memory cells on the partially programmed block.

[0047] like Figure 3B As shown in , the programming operation may begin by programming valid data 340 to the memory cells coupled to word line 305-1. The programming operation may continue to program valid data 340 to the memory cells coupled to word lines 305-2 to 304-(T-1). Figure 3B , once the programming operation reaches word line 305-T and programs valid data 340 into a first portion of memory cells coupled to word line 305-T and programs process data 342 into a second portion of memory cells coupled to word line 305-T, the programming operation can be completed, interrupted, or canceled, thereby producing a partially programmed block.

[0048] Filling may be utilized to program memory cells that are not programmed during a programming operation to reduce a drop in threshold voltage due to back pattern effects, capacitive coupling, and / or lateral charge migration when reading memory cells on a partially programmed block. Since the programming operation is completed, interrupted, or canceled while programming memory cells coupled to word line 305-T, memory cells coupled to word line 305-T and a second portion of memory cells coupled to word line 305-(T+1) have been programmed with process data 342 as part of the QLC programming operation performed on word lines 305-1 to 305-T, program filling may begin on memory cells coupled to word line 305-(T+2).

[0049] The memory cells coupled to word lines 305-(T+2) to 305-N may be programmed with fill 344. Fill 344 may be invalid random data. The random data may be received from a host coupled to the memory device and / or generated by a controller of the memory device. Fill 344 may be programmed using a process programming operation in QLC mode. Fill may also be performed using SLC, MLC, and / or TLC programming operations by switching from QLC mode to SLC, MLC, and / or TLC mode to perform a fill programming operation.

[0050] Figure 4 is a flow chart of a method 450 for operating a controller configured to populate a partially programmed block, according to several embodiments of the present disclosure.

[0051] At 452, the method may include programming a first number of word lines in a word line block in an array of memory cells, wherein the first number of word lines is less than the total number of word lines in the block, as in Figure 3A and 3B As described in 305-1 to 305-T.

[0052] At 454, the method may include programming a second number of word lines in the word line block, wherein the second number of word lines is programmed with fill, and wherein the second number of word lines is a different word line than the first number of word lines, and the total number of word lines in the block includes the first and second numbers of word lines, as in Figure 3A and 3B This is described at 305-1 to 305-(T+2) to 305-N.

[0053] The method may include programming a first number of word lines in a first mode and programming a second number of word lines in a second mode. Programming the second number of word lines with fill may include using a process programming operation in a QLC mode, using a programming operation in an SLC mode, using a programming operation in an MLC mode, and / or using a programming operation in a TLC mode.

[0054] The method may include performing a sensing operation on one of the first number of word lines in the partially programmed block in response to the second number of word lines being programmed.The sensing operation on the partially programmed block uses a sensing voltage used in the sensing operation performed on the fully programmed block.

[0055] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or changes to the various embodiments of the present disclosure. It should be appreciated that the above description has been made in an illustrative and non-restrictive manner. After reviewing the above description, those skilled in the art will understand the combination of the above embodiments and other embodiments not explicitly described herein. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the attached claims and the full scope of equivalents to which such claims are entitled.

[0056] In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of simplifying the present disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure must use more features than those explicitly recited in each claim. Rather, as the appended claims reflect, the inventive subject matter lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. An apparatus for filling a partially programmed block, comprising: a memory cell array; a controller coupled to the memory cell array, the controller being configured to: programming a first number of word lines in a block of word lines in the memory cell array, wherein the first number of word lines is less than a total number of word lines in the block; and A second number of word lines of the memory cell array are programmed, wherein the second number of word lines are programmed with padding, and wherein the second number of word lines are different word lines than the first number of word lines, and the total number of word lines in the block includes the first and second numbers of word lines.

2. The apparatus of claim 1, wherein the first number of word lines are programmed with valid data and the second number of word lines are programmed with invalid data.

3. The apparatus of claim 1, wherein the block is a partially programmed block including the first number of word lines programmed with valid data and the second number of word lines programmed with invalid data.

4. The apparatus of claim 3, wherein the controller is configured to perform a sensing operation on one of the first number of word lines in the partially programmed block in response to the second number of word lines being programmed.

5. The apparatus of claim 1, wherein the controller is configured to program the first number of word lines using a programming operation in a first mode and to program the second number of word lines using a programming operation in a second mode. 6 . The apparatus of claim 1 , wherein the second number of word lines is programmed using a process programming operation in a four level cell (QLC) mode. 7 . The apparatus of claim 1 , wherein the second number of word lines is programmed using a programming operation in a single level cell (SLC) mode.

8. The apparatus of claim 1, wherein the second number of word lines is programmed using a programming operation in a multi-level cell (MLC) mode.

9. An apparatus for filling a partially programmed block, comprising: a memory cell array; a controller coupled to the memory cell array and configured to: programming a first number of word lines in a word line block in the memory cell array with valid data using a programming operation in a quad level cell (QLC) mode, wherein the first number of word lines is less than a total number of word lines in the block; and A second number of word lines in the word line block in the memory cell array are programmed with padding, wherein the second number of word lines are not programmed when the first number of word lines in the block are programmed.

10. The apparatus of claim 9, wherein the controller is configured to program the second number of word lines with fill using a process programming operation in QLC mode.

11. The apparatus of claim 9, wherein the controller is configured to switch modes prior to programming the second number of word lines.

12. The apparatus of claim 11, wherein the controller is configured to program the second number of word lines with fill using a program operation in a single level cell (SLC) mode.

13. The apparatus of claim 11, wherein the controller is configured to program the second number of word lines with fill using a programming operation in a multi-level cell (MLC) mode.

14. The apparatus of claim 11, wherein the controller is configured to program the second number of word lines with fill using a program operation in a three-level cell (TLC) mode.

15. A method for filling a partial programming block, comprising: programming a first number of word lines in a block of word lines in an array of memory cells, wherein the first number of word lines is less than a total number of word lines in the block; and A second number of word lines in the word line block are programmed, wherein the second number of word lines are programmed with padding, and wherein the second number of word lines are different word lines than the first number of word lines, and the total number of word lines in the block includes the first and second numbers of word lines.

16. The method of claim 15, further comprising programming the first number of word lines in a first mode and programming the second number of word lines in a second mode.

17. The method of claim 15, further comprising programming the second number of word lines using a process programming operation in a four level cell (QLC) mode.

18. The method of claim 15, further comprising programming the second number of word lines using a process programming operation in a single level cell (SLC) mode.

19. The method of any one of claims 15-18, further comprising performing a sensing operation on one of the first number of word lines in a partially programmed block in response to the second number of word lines being programmed. 20 . The method of claim 19 , wherein the sensing operation on the partially programmed block uses a sensing voltage used in a sensing operation performed on a fully programmed block.

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