Test method and circuit

Abstract

The invention relates to a test method and circuit, and the method comprises the steps: pre-writing preset data into a memory, carrying out the refreshing operation of the memory after the preset data is written, and waiting for a preset time length; controlling the data reader to respond to the read command, reading the preset data in the memory, compressing the read data into initial read data with a preset bit number, and outputting the initial read data; controlling a data selector to perform selection processing on the received initial read data according to a data selection signal containing address information of the target data, and generating target read data containing the target data; and judging whether the memory has defects or not according to a comparison result of the preset data and the target read-out data.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a testing method and circuit. Background Art

[0002] With the continuous development of integrated circuit technology, the market has higher and higher requirements for the performance and reliability of integrated circuit chips. Integrated circuit chips are generally subjected to various tests before leaving the factory to evaluate the performance of the integrated circuit chips and prevent unqualified chips from entering the market.

[0003] In the process of testing integrated circuit chips, it is necessary to write specific data patterns to create specific failure modes to implement specific functional tests. If the data of non-interesting bytes can be covered or hidden during the data reading process, and only the data of the bytes of interest are read, it can not only improve the efficiency of circuit design, but also avoid the adverse effects of the failure of non-interesting bytes on the data of the bytes of interest, thereby improving the efficiency and accuracy of circuit testing. Summary of the invention

[0004] Based on this, it is necessary to provide a testing method and circuit to address the technical problems in the above-mentioned background technology, which can at least avoid the data failure of non-interested bytes from having an adverse effect on the target read data used for testing, thereby improving the efficiency and accuracy of the test.

[0005] According to various embodiments of the present disclosure, a first aspect provides a testing method, including:

[0006] Pre-write preset data into the memory, perform a refresh operation on the memory after the preset data is written, and wait for a preset time;

[0007] Controlling the data reader to respond to a read command, read the preset data in the memory, and compress the read data into initial read data of preset bits and then output it;

[0008] Controlling a data selector to select and process received initial read data according to a data selection signal including address information of target data, thereby generating target read data including target data;

[0009] According to the comparison result between the preset data and the target read data, it is determined whether the memory has defects.

[0010] In the test method in the above embodiment, the data reader is controlled to read out the initial read data of a preset number of bits from the memory, and the read data is compressed into the initial read data of a preset number of bits and then output, thereby effectively improving the efficiency of data reading, and then the data selector is controlled to respond to the data selection signal containing the address information of the target data, select and process the received initial read data, generate target read data containing the target data, and cover or hide the data in the initial read data except for the data corresponding to the address information of the target data, and only read the data of the byte bits of interest from the memory, thereby avoiding the data failure of the byte bits of non-interest from causing adverse effects on the target read data used for testing, thereby improving the efficiency and accuracy of memory testing, and being able to meet the distribution pattern requirements of the target read data for specific function testing under specific failure modes, thereby improving the accuracy of specific function testing.

[0011] In some embodiments, the testing method also includes: determining the address information of the target data; generating a data selection signal based on the address information, thereby controlling the output of the initial read data corresponding to the address information of the target data according to the data selection signal, and controlling the masking or hiding of data in the initial read data except for the data corresponding to the address information of the target data.

[0012] In some embodiments, the target data is data that is at least partially surrounded by inverted data of the target data; the data selection signal includes an output signal set corresponding to the address bit of the target data; generating target read data including the target data includes: controlling the data of the corresponding address bit in the initial read data to always be output with equal value according to the output signal, so as to generate target read data including the target data, thereby avoiding output errors of the target data due to problems such as memory leakage, which affects the efficiency and accuracy of memory testing.

[0013] In some embodiments, pre-writing preset data into the memory includes:

[0014] Sequentially turn on the word lines one by one, and write the preset data into the storage unit corresponding to the word line until the preset data is written into the memory;

[0015] Controlling the data reader to read the data in the memory in response to the read command, including:

[0016] The word lines are turned on one by one in sequence, and the preset data in the storage unit corresponding to the word line is read to read the preset data in the memory. By writing and reading the preset data to the storage unit corresponding to the word line row by row, the data writing and reading efficiency can be improved.

[0017] A second aspect of an embodiment of the present disclosure provides a test circuit, including a data reader, a data selector and a judger. The data reader is connected to multiple storage bodies in a memory, and is used to respond to a read command, read the data in the memory, and compress the read data into initial read data of a preset number of bits and then output it; the data selector is connected to the data reader, and is used to receive and respond to a data selection signal containing address information of target data, select and process the received initial read data, and generate target read data containing target data; the judger is connected to the data selector, and is used to judge whether the memory has defects based on a comparison result of the preset data and the target read data.

[0018] In the test circuit in the above embodiment, since a data reader is used to read out a preset number of initial read data from a memory, and the read data is compressed into a preset number of initial read data and then output, the efficiency of data reading is effectively improved; a data selector is used to respond to a data selection signal containing address information of target data, select and process the received initial read data, generate target read data containing target data, and cover or hide the data in the initial read data except for the data corresponding to the address information of the target data, and only read out the data of the byte of interest from the memory, so as to avoid the data failure of the byte of non-interest causing adverse effects on the target read data used for testing, thereby improving the efficiency and accuracy of the test and meeting the distribution pattern requirements of the target read data for specific functional tests under specific failure modes.

[0019] In some embodiments, the test circuit further includes a data selection signal generator, which is connected to the data selector and is used to generate a data selection signal according to the acquired address information of the target data.

[0020] In some embodiments, the target data is data at least partially surrounded by inverted data of the target data.

[0021] In some embodiments, the data selector includes a logic circuit, which is configured as follows: a first input terminal is connected to an output terminal of the data reader, a second input terminal is connected to an output terminal of a data selection signal generator, and an output terminal is used to output target read data to the determiner.

[0022] In some embodiments, the logic circuit includes: an OR gate, which is set corresponding to the number of byte bits of the initial read data, and is configured such that a first input terminal is connected to an output terminal of a data reader to receive the initial read data corresponding to an address bit, a second input terminal is connected to an output terminal of a data selection signal generator to receive a corresponding data selection signal, and an output terminal is used to output target read data corresponding to the address bit to a judge, wherein the address information of the target data corresponds to a data selection signal received by the OR gate as a low-level signal.

[0023] In some embodiments, the data reader includes a word line data reader, a clock controller and a selection switch; the word line data reader is connected to multiple storage bodies in the memory, and is used to respond to a read command to read data on multiple enabled word lines when the word lines in each of the storage bodies are enabled, and then compress the read data into parallel data of the first bit number according to a preset compression method and output it; the clock controller is used to generate a multi-level data selection signal according to a preset clock signal, a read command, a compression mode enable signal and a compression mode control signal; the selection switch is connected to the clock controller and the word line data reader, and is used to compress the parallel data into initial read data of a preset bit number according to the multi-level data selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1-Figure 2 A schematic diagram showing the flow of the testing method in different embodiments of the present disclosure;

[0026] Figure 3-Figure 5 , Figure 7-Figure 8 A schematic diagram showing the circuit principles of the test circuit in different embodiments of the present disclosure;

[0027] Figure 6 A circuit diagram showing a logic circuit in a test circuit according to an embodiment of the present disclosure.

[0028] Description of reference numerals:

[0029] 100. Test circuit; 10. Data reader; 20. Data selector; 30. Data selection signal generator; 40. Judger; 21. Logic circuit; 11. Word line data reader; 12. Clock controller; 13. Selection switch. DETAILED DESCRIPTION

[0030] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. In addition, certain terms used throughout the specification and the claims that follow refer to specific elements. It will be understood by those skilled in the art that manufacturers may refer to elements by different names. This document does not intend to distinguish between elements with different names but the same functions. In the following description and embodiments, the terms "include" and "include" are open-ended and should therefore be interpreted as "include, but not limited to...". Similarly, the term "connect" is intended to express an indirect or direct electrical connection. Accordingly, if a device is connected to another device, the connection may be completed by a direct electrical connection or by an indirect electrical connection through other devices and connectors.

[0032] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0033] In some embodiments of the present disclosure, a test method is provided. In this embodiment, the test method is illustrated by using a processor to execute the test method. It is understandable that the processor can be located on a terminal or a server. The test method is used to generate judgment result information in a preset format, and the judgment result information includes result information of a memory test after writing preset data into the memory.

[0034] Based on this, the present disclosure provides a testing method, such as Figure 1 As shown, including:

[0035] Step S302: Preset data is written into the memory in advance, a refresh operation is performed on the memory after the preset data is written, and a preset time period is waited;

[0036] Step S304: Control the data reader to respond to the read command, read the preset data in the memory, and compress the read data into initial read data of a preset number of bits and then output it;

[0037] Step S306: controlling the data selector to select and process the received initial read data according to the data selection signal including the address information of the target data, and generating target read data including the target data;

[0038] Step S308: judging whether the memory has defects according to the comparison result between the preset data and the target read data.

[0039] By controlling the data reader to read out the initial read data of a preset number of bits from the memory, and compressing the read data into the initial read data of a preset number of bits and then outputting it, the efficiency of data reading is effectively improved; the data selector is controlled to respond to the data selection signal containing the address information of the target data, select and process the received initial read data, generate target read data containing the target data, and cover or hide the data in the initial read data except the data corresponding to the address information of the target data, and only read the data of the byte bits of interest from the memory, so as to avoid the data failure of the byte bits of non-interest from causing adverse effects on the target read data used for testing, thereby improving the efficiency and accuracy of memory testing, being able to meet the distribution pattern requirements of the target read data for specific function testing under specific failure modes, and improving the accuracy of specific function testing.

[0040] In some embodiments, Figure 2 As shown, the testing method of the present disclosure also includes:

[0041] Step S305: Determine the address information of the target data, and generate a data selection signal according to the address information.

[0042] Specifically, the target data may be data at least partially surrounded by inverted data of the target data; the data selection signal includes an output signal set corresponding to the address bit of the target data; and target read data including the target data is generated, including: according to the output signal, the data corresponding to the address bit in the initial read data is controlled to always be output with equal value, so as to generate target read data including the target data, so as to avoid output errors of the target data due to problems such as memory leakage, thereby affecting the efficiency and accuracy of the memory test.

[0043] Table 1

[0044] BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7 WL0 0 1 0 1 0 1 0 1 WL1 1 1 1 1 1 1 1 1 WL2 0 1 0 1 0 1 0 1 WL3 1 1 1 1 1 1 1 1 WL4 0 1 0 1 0 1 0 1 WL5 1 1 1 1 1 1 1 1 WL6 0 1 0 1 0 1 0 1 WL7 1 1 1 1 1 1 1 1

[0045] Since the target data is generally "0" or "1". For example, in order to test the leakage result of the storage cell storing "1" to the storage cell storing "0", after writing the data in Table 1 below into the memory, the tester only cares about the read data of the storage cell storing "0", but not the read data of the storage cell storing "1". As shown in Table 1, the target data can be set to "0", and the target data "0" is at least partially surrounded by the inverted data "1" of the target data; a data selection signal containing the address information of the storage cell storing "0" in Table 1 can be generated, so as to select and process the received initial read data in response to the data selection signal, and generate the target read data DATA_target containing the target data "0". Since the read data of the storage cell storing "1" is hidden or masked, even if an error or abnormality occurs therein, it does not affect the target read data DATA_target containing only the target data "0", thereby improving the efficiency and accuracy of the test.

[0046] Similarly, if it is necessary to write test data in a specific distribution pattern to the memory to perform a specific function test on the memory, the data selection signal Signal can be set according to the address information of the target data in the specific distribution pattern, and the received initial read data is selected and processed according to the data selection signal Signal to generate target read data DATA_target containing the target data, so as to cover or hide the data in the initial read data except the data corresponding to the address information of the target data, and only read the target data from the memory, so as to avoid the data failure of non-interested bytes causing adverse effects on the target read data DATA_target, and improve the accuracy of performing a specific function test on the memory in a specific failure mode. For example, in order to test the leakage current between adjacent word lines, after writing the test data in Table 2 into the memory, only the read data of the storage unit storing "0" is concerned, and the read data of the storage unit storing "1" is not concerned. The target data can be set to "0", and the target data "0" is at least partially surrounded by the inverted data "1" of the target data; a data selection signal can be provided based on the address information of the storage unit storing "0" in Table 2, so that the received initial read data can be selected and processed according to the data selection signal to generate the target read data DATA_target containing the target data "0".

[0047] Table 2

[0048] BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7 WL0 0 1 1 1 1 1 1 1 WL1 1 1 1 1 1 1 1 1 WL2 0 1 1 1 1 1 1 1 WL3 1 1 1 1 1 1 1 1 WL4 0 1 1 1 1 1 1 1 WL5 1 1 1 1 1 1 1 1 WL6 0 1 1 1 1 1 1 1 WL7 1 1 1 1 1 1 1 1

[0049] Table 3 shows another data format presenting a specific pattern, in which word lines WL0, word lines WL1, ..., word line WL7 connected to bit line BL0 are all written with 0, word lines WL0, word lines WL1, ..., word line WL7 connected to bit line BL1 are all written with 1, word lines WL0, word lines WL1, ..., word line WL7 connected to bit line BL2 are all written with 1, ..., and so on, word lines WL0, word lines WL1, ..., word line WL7 connected to bit line BL7 are all written with 1.

[0050] Table 3

[0051] BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7 WL0 0 1 1 1 1 1 1 1 WL1 0 1 1 1 1 1 1 1 WL2 0 1 1 1 1 1 1 1 WL3 0 1 1 1 1 1 1 1 WL4 0 1 1 1 1 1 1 1 WL5 0 1 1 1 1 1 1 1 WL6 0 1 1 1 1 1 1 1 WL7 0 1 1 1 1 1 1 1

[0052] It should be noted that the data arrangement patterns presented in Tables 1 to 3 only schematically illustrate partial forms of "the target data is at least partially surrounded by the inverted data of the target data", and the target data can be "1". Any deformation given by those skilled in the art without creative work should fall within the scope of protection of the present disclosure.

[0053] The Y-page write operation means that before each write operation is performed, a word line is turned on, all the corresponding storage cells on this word line are written sequentially, and then this word line is turned off, and then the next word line is turned on to write all the storage cells sequentially.

[0054] In some embodiments, pre-writing preset data into the memory may include sequentially turning on word lines one by one, and writing the preset data into the storage cells corresponding to the word lines, until the preset data is written into the memory. Exemplarily, sequentially turning on word lines one by one, and writing the preset data into the storage cells corresponding to the word lines can be implemented by performing a Y-page write operation to write data into the memory, that is, before each write operation is performed, the memory is controlled to turn on a word line and sequentially write data into the storage cells corresponding to the word line, then turn off the word line and turn on the next adjacent word line, and then sequentially write data into the storage cells corresponding to the word line, until the preset data is written into the memory.

[0055] In order to maintain its own data, DRAM must be refreshed at regular intervals. Therefore, after pre-writing preset data into the memory, it is also necessary to perform a refresh operation on the memory after the preset data is written, i.e., Auto Refresh (AR).

[0056] After performing the automatic refresh AR, the process also includes waiting for a preset time, which may be 1 second, for example. The preset time is a condition for causing leakage of the capacitor plate of the storage unit. In this way, the capacitor in the storage unit may be caused to leak as much as possible by waiting for the preset time, so as to detect the failed storage unit as much as possible.

[0057] The Y-Page read operation means that before each read operation is performed, a word line is turned on, all the corresponding storage cells on this word line are read sequentially, the word line is turned off, and then the next word line is turned on to read all the storage cells sequentially.

[0058] The control data reader responds to the read command to read the preset data in the memory, including: sequentially opening the word lines one by one, and reading the preset data in the storage cells corresponding to the word lines, so as to read the preset data in the memory. This step can be implemented by a Y-page read operation, that is, after the control memory opens a word line and sequentially reads the storage cells corresponding to the word line, closes the word line and opens the next adjacent word line. After the control data reader responds to the read command and sequentially reads the data on the storage cells corresponding to the multiple opened word lines, the read data is compressed into the initial read data of the preset number of bits and then output.

[0059] Data is written to the storage cell corresponding to the word line through the Y-page write operation, and after the refresh operation is performed, a preset time is waited to create a leakage condition. Therefore, after the data in the storage cell corresponding to the word line is read out by the Y-Page read operation, the performance of the memory can be tested by comparing the written preset data and the target read data.

[0060] In some embodiments, the target read data includes hidden data, and the data selection signal can be set to include a hidden signal set corresponding to the address bit of the hidden data; generating the target read data including the target data in step S306 also includes: controlling the data of the corresponding address bit in the initial read data to be outputted as equal value or outputted after inversion according to the hidden signal, so as to generate the target read data including the target data and the hidden data. Since the address information of the target data is already known, the identifier of the target data can be added to the target read data to facilitate identification of the target data in the target read data.

[0061] Please refer to Figure 3In some embodiments, a test circuit 100 is provided, including a data reader 10, a data selector 20 and a judge 40. The data reader 10 is connected to multiple memory banks in the memory, and is used to respond to a read command RD CMD when a word line in each memory bank is activated, read the data in the memory, and compress the read data into initial read data DATA_PARAB of a preset number of bits and then output it; the data selector 20 is connected to the data reader 10, and is used to receive and respond to a data selection signal Signal containing address information of target data, select and process the received initial read data DATA_PARAB, and generate target read data DATA_target containing target data; the judge 40 is connected to the data selector 20, and is used to judge whether the memory has a defect according to a comparison result between the preset data and the target read data DATA_target.

[0062] Please continue to refer to Figure 3 If the data reader 10 is connected to 16 memory banks in the memory, that is, memory bank 0, memory bank 1, ..., and memory bank 15, before executing the read command RD CMD, two word lines in each of the 16 memory banks are controlled first, and after a total of 32 word lines are activated, the data reader 10 is controlled to respond to the read command RD CMD to read the data on each activated word line, so as to compress the read data into parallel data of the first bit number, for example, 64 bits, and then output it according to a preset compression method, wherein each activated word line outputs 64 bits of data, and the 32 activated word lines output a total of 2048 bits of data. After the data reader 10 responds to the read command RD CMD to read the data on each activated word line, it compresses the read 2048 bits of data into initial read data DATA_PARAB of a preset bit number according to the preset compression method and then outputs it. Since the data reader 10 is used to read out the preset number of initial read data DATA_PARAB from the memory in parallel, the efficiency of data reading is effectively improved. Then, the data selector 20 is used to respond to the data selection signal containing the address information of the target data to select and process the received initial read data DATA_PARAB to generate the target read data DATA_target containing the target data, so as to cover or hide the data in the initial read data DATA_PARAB except the data corresponding to the address information of the target data, and only read out the data of the byte of interest from the memory, so as to avoid the data failure of the byte of non-interest causing adverse effects on the target read data DATA_target, thereby improving the efficiency and accuracy of the test and meeting the distribution pattern requirements of the target read data DATA_target for specific functional tests under specific failure modes.

[0063] Please continue to refer to Figure 3The judger 40 may include a processor and a storage unit (not shown). The storage unit may store preset data pre-written in the memory, so that after the processor obtains the target read data DATA_target, the target data in the target read data DATA_target is compared with the data of the corresponding address bit in the preset data. If the number of different bits exceeds a preset threshold, it indicates that the performance of the memory does not meet the test requirements. Otherwise, the memory passes the test.

[0064] Please refer to Figure 4 In some embodiments, the test circuit 100 further includes a data selection signal generator 30, which is connected to the data selector 20 and is used to generate a data selection signal Signal containing address information of the target data. The data selection signal generator 30 may include a terminal or an integrated circuit chip that supports programming, such as a laptop computer, a desktop computer, a tablet computer, or an industrial computer.

[0065] Please continue to refer to Figure 4 In some embodiments, the target data is data at least partially surrounded by the inverted data of the target data. Since the target data is generally "0" or "1". For example, in order to test the leakage result of the memory cell storing "1" to the memory cell storing "0", after writing the data in Table 1 below into the memory, the tester only cares about the read data of the memory cell storing "0" and does not care about the read data of the memory cell storing "1". Please refer to Figure 2 According to Table 1, the target data "0" can be set to "0", and the target data "0" is at least partially surrounded by the inverted data "1" of the target data; the data selection signal generator 30 can generate a data selection signal containing the address information of the storage unit storing "0" in Table 1, so that the data selector 20 receives and responds to the data selection signal, selects and processes the received initial read data, and generates the target read data DATA_target containing the target data "0". Since the read data of the storage unit storing "1" is hidden or masked, even if an error or abnormality occurs therein, it does not affect the target read data DATA_target containing only the target data "0", thereby improving the efficiency and accuracy of the test.

[0066] Please refer to Figure 5 In some embodiments, the data selector 20 includes a logic circuit 21, which is configured as follows: a first input terminal is connected to the output terminal of the data reader 10, a second input terminal is connected to the output terminal of the data selection signal generator 30, and an output terminal is used to output the target read data DATA_target.

[0067] Please refer to Figure 5 and Figure 6In some embodiments, the logic circuit 21 includes an OR gate set corresponding to the number of byte bits of the initial read data, for example, including OR gates OR0, OR gates OR1, ..., OR gates OR7, wherein the OR gate OR0 is configured as follows: a first input terminal is connected to the output terminal of the data reader 10 to receive the initial read data DATA_PARAB corresponding to the address bit, a second input terminal is connected to the output terminal of the data selection signal generator 30 to receive the corresponding data selection signal signal, and an output terminal is used to output the target read data DATA_target corresponding to the address bit, wherein the address information of the target data corresponds to the data selection signal received by the OR gate as a low-level signal, so that the corresponding OR gate always outputs the received target read data DATA_target of the corresponding address bit with the same value.

[0068] Please continue to refer to Figure 6 , the data pattern in Table 3 is used as an example to illustrate the implementation principle of the present disclosure, Figure 4 In which A0 represents the address information corresponding to the word line WL0, word line WL1, ..., word line WL7 connected to the bit line BL0, A1 represents the address information corresponding to the word line WL0, word line WL1, ..., word line WL7 connected to the bit line BL1, ..., A7 represents the address information corresponding to the word line WL0, word line WL1, ..., word line WL7 connected to the bit line BL7, by setting the data selection signal signal received by the OR gate OR0 to maintain a low level, and setting the data selection signal signal received by the OR gate OR1, OR2, ..., OR7 to maintain a high level, the data of the storage unit corresponding to the address information A0 is always read out as the target data, and the data of the storage unit corresponding to the address information A1, address information A2, ..., address information A7 is covered or hidden, so as to obtain the target read data DATA_target including the target data, avoid the data failure of non-interested bytes from causing adverse effects on the target read data DATA_target, and improve the efficiency and accuracy of the test.

[0069] Please refer to Figure 7In some embodiments, the data reader 10 includes a word line data reader 11, a clock controller 12 and a selection switch 13. The word line data reader 11 is connected to multiple storage bodies in the memory, and is used to respond to a read command RD CMD when the word lines in each storage body are activated, read the data on multiple activated word lines, and then compress the read data into parallel data Input_data of the first bit number according to a preset compression method and output it; the clock controller 12 is used to generate a multi-level data selection signal according to a preset clock signal CLK, the read command RD CMD, the compression mode enable signal TPARA and the compression mode control signal SET. The selection switch 13 is connected to the clock controller 12 and the word line data reader 11, and is used to compress the parallel data into the initial read data of the preset bit number according to the multi-level data selection signal.

[0070] Please refer to Figure 8 In some embodiments, the selection switch 13 includes a primary data selection subcircuit 131, a secondary data selection subcircuit 132, and a tertiary data selection subcircuit 133. The primary data selection subcircuit 131 is connected to the clock controller 12 and the word line data reader 11, and is used to sample the parallel data Input_data during the period when the primary data selection signal CLKST1 is in the first state, and intercept the parallel data Input_data during the period when the primary data selection signal CLKST1 is in the second state, so as to generate and output the serial data Output1 of the second bit number; the secondary data selection subcircuit 132 is connected to the clock controller 12 and the primary data selection subcircuit 131, and is used to sample the data provided by the primary data selection subcircuit 131 according to the secondary data selection signal CLKST2, so as to generate and output the serial data Output2 of the third bit number; the tertiary data selection subcircuit 133 is connected to the clock controller 12 and the secondary data selection subcircuit 132, and is used to sample the data provided by the secondary data selection subcircuit 132 according to the tertiary data selection signal CLKST3, so as to generate and output the initial read data DATA_PARAB of the preset bit number. This embodiment uses the selection switch 13 to compress the parallel data Input_data into the initial read data DATA_PARAB of a preset number of bits and then outputs it, thereby reducing the size of the test circuit, reducing the occupation of the data read port of the memory, and reducing the data read energy consumption.

[0071] Please continue to refer to Figure 8In some embodiments, the clock controller 12 includes a clock control unit 121 and a decoding unit 122. The clock control unit 121 is used to read the clock signal CLK and the read command RD according to the preset clock signal CLK and the read command RD. CMD, the compression mode enable signal TPARA and the compression mode control signal SET generate the initial data selection signal CLKS; the decoding unit 122 is connected to the clock control unit 121, and is used to generate the primary data selection signal CLKST1, the secondary data selection signal CLKST2 and the tertiary data selection signal CLKST3 according to the initial data selection signal CLKS, so as to control the low-power selection switch 13 to respond to the primary data selection signal CLKST1 to compress the first-digit parallel data Input_data into the second-digit (for example, 16-bit) serial data Output1, respond to the secondary data selection signal CLKST2 to compress the second-digit serial data Output1 into the third-digit (for example, 8-bit) serial data Output2, and respond to the tertiary data selection signal CLKST3 to compress the third-digit serial data Output2 into the preset number of initial read data DATA_PARAB, thereby reducing the volume of the test circuit 100, reducing the occupation of the data read port of the memory, and reducing the data read energy consumption.

[0072] As to how to compress data by using multi-level data selection signals and selection switch devices, conventional technical means in the art may be adopted and will not be described in detail here.

[0073] In some embodiments, a memory is provided, including a test circuit in any of the embodiments of the present disclosure. By using a data selector in response to a data selection signal containing address information of target data, the received initial read data is selected and processed to generate target read data containing target data, so as to cover or hide the data in the initial read data except for the data corresponding to the address information of the target data, and only read the data of the byte of interest from the memory, so as to avoid the data failure of the byte of non-interest causing adverse effects on the target read data used for testing, improve the efficiency and accuracy of the test, and meet the distribution pattern requirements of the target read data for specific functional tests under specific failure modes, so as to improve the accuracy of the memory test. While ensuring that the size of the memory is small and the energy consumption is low, the function of the memory is increased and the performance of the memory is improved.

[0074] The present disclosure also provides a testing device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the testing method in any of the above embodiments are implemented, and data of bytes of interest can be read out from the memory, thereby preventing data failure of bytes of non-interest from causing adverse effects on target read data used for testing, thereby improving the efficiency and accuracy of memory testing, and meeting the distribution pattern requirements of target read data for specific functional testing under specific failure modes, thereby improving the accuracy of specific functional testing.

[0075] The present disclosure also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the test method in any of the above embodiments are implemented, and data of bytes of interest can be read out from a memory to avoid adverse effects of data failure of bytes of non-interest on target read data used for testing, thereby improving the efficiency and accuracy of memory testing and meeting the distribution pattern requirements of target read data for specific function testing under specific failure modes, thereby improving the accuracy of specific function testing.

[0076] In one embodiment, a computer program product is provided, including a computer program, which, when executed by a processor, implements the steps of the test method in any of the above embodiments, can read data of bytes of interest from a memory, avoid data failure of bytes of non-interest from causing adverse effects on target read data used for testing, improve memory testing efficiency and accuracy, and at the same time, can meet the distribution pattern requirements of target read data for specific functional testing under specific failure modes, thereby improving the accuracy of specific functional testing.

[0077] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present disclosure can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0078] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present invention.

[0079] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A testing method, characterized in that: include: Pre-write preset data into the memory, perform a refresh operation on the memory after writing the preset data, and wait for a preset time; Controlling the data reader to read the preset data in the memory in response to a read command, and compressing the read data into initial read data of preset bits and then outputting the data; Controlling a data selector to select and process the received initial read data according to a data selection signal including address information of the target data, so as to generate target read data including the target data; According to the comparison result between the preset data and the target read data, it is determined whether the memory has a defect.

2. The testing method according to claim 1, characterized in that: Also includes: Determining address information of the target data; The data selection signal is generated according to the address information.

3. The testing method according to claim 2, characterized in that: The target data is data at least partially surrounded by inverted data of the target data; the data selection signal includes an output signal set corresponding to an address bit of the target data; generating target read data including the target data, comprising: The data equivalent output of the corresponding address bit in the initial read data is controlled according to the output signal to generate target read data including the target data.

4. The testing method according to claim 1, characterized in that: The step of pre-writing preset data into the memory comprises: Turning on the word lines one by one in sequence, and writing the preset data into the storage units corresponding to the word lines, until the preset data is written into the memory; The control data reader reads the preset data in the memory in response to the read command, including: The word lines are turned on one by one in sequence, and the preset data in the storage unit corresponding to the word line is read to read the preset data in the memory.

5. A test circuit, characterized in that: include: A data reader connected to a plurality of storage bodies in the memory, for responding to a read command, reading data in the memory, and compressing the read data into initial read data of a preset number of bits and then outputting the data; A data selector connected to the data reader, configured to receive and respond to a data selection signal containing address information of target data, select and process the received initial read data, and generate target read data containing the target data; A judger is connected to the data selector and is used to judge whether the memory has defects according to a comparison result between preset data and the target read data.

6. The test circuit according to claim 5, characterized in that: Also includes: A data selection signal generator is connected to the data selector and is used to generate the data selection signal according to the acquired address information of the target data.

7. The test circuit according to claim 6, characterized in that: The target data is data at least partially surrounded by inverted data of the target data.

8. The test circuit according to claim 6 or 7, characterized in that: The data selector comprises: The logic circuit is configured as follows: a first input terminal is connected to the output terminal of the data reader, a second input terminal is connected to the output terminal of the data selection signal generator, and an output terminal is used to output the target read data to the determiner.

9. The test circuit according to claim 8, characterized in that: The logic circuit comprises: An OR gate is set corresponding to the number of byte bits of the initial read data, and is configured such that a first input end is connected to an output end of the data reader to receive the initial read data corresponding to the address bit, a second input end is connected to an output end of the data selection signal generator to receive a corresponding data selection signal, and an output end is used to output the target read data corresponding to the address bit to the judger, wherein the address information of the target data corresponds to a data selection signal received by the OR gate which is a low-level signal.

10. The test circuit according to any one of claims 5 to 7, characterized in that: The data reader comprises: A word line data reader connected to a plurality of memory banks in the memory, for responding to a read command, when a word line in each of the memory banks is turned on, reading data on a plurality of turned-on word lines, compressing the read data into parallel data of a first digit according to a preset compression method, and then outputting the data; A clock controller, configured to generate a multi-level data selection signal according to a preset clock signal, the read command, a compression mode enable signal and a compression mode control signal; The selection switch is connected to the clock controller and the word line data reader, and is used to compress the parallel data into initial read data of a preset number of bits according to the multi-level data selection signal.

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