Storage test method and storage test device

Abstract

The present invention provides a storage test method and a storage test device, the storage test method comprising the following steps: setting the format of the original data to generate multiple pieces of original data; randomizing the original data to obtain test data, and writing the test data to the storage device; setting the retention time, placing the storage device at a constant temperature, and maintaining the retention time for at least a certain period of time; processing the test data in the reverse steps of the randomization process to obtain the recovered data; and comparing the recovered data with the original data, and when the recovered data and the original data are the same, continuing to test another piece of original data until multiple pieces of original data are traversed and tested. The present invention provides a storage test method and a storage test device, which can accurately evaluate the cache performance of a storage device.

Description

Technical Field

[0001] The present invention relates to the technical field of storage testing, and in particular to a storage testing method and storage testing equipment. Background Art

[0002] Cache is a temporary storage in a computer system, usually located inside the CPU or between the main memory and the CPU. Cache is used to store frequently accessed data and instructions in a computer system to improve the performance and response speed of the system. When the CPU needs to access data or instructions, it first checks whether the corresponding data or instructions already exist in the cache. If so, it can be read directly from the cache, avoiding the delay of reading data or instructions from the main memory. Therefore, the reliability of the cache is a particularly important indicator of storage devices and even computer systems.

[0003] Storage devices have a wide range of applications, and the working conditions that caches may face are also diverse. Therefore, it is difficult to fully predict the errors that may occur in the cache, and it is difficult to accurately evaluate the performance of the cache. Only based on the storage performance of the cache can we design a variety of storage logic algorithms for storage devices and even computer systems. In computer systems, the firmware configuration of storage devices is required to be able to develop hardware performance as much as possible while having high reliability and high read and write efficiency. Summary of the invention

[0004] The object of the present invention is to provide a storage testing method and a storage testing device, which can accurately evaluate the cache performance of a storage device.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a storage test method, comprising the following steps:

[0007] Setting the format of the original data to generate multiple pieces of the original data;

[0008] Randomizing the original data to obtain test data, and writing the test data into a storage device;

[0009] Setting a holding time, placing the storage device at a constant temperature, and maintaining the storage device for at least the holding time;

[0010] Process the test data according to the reverse steps of the randomization process to obtain restored data; and

[0011] The restored data is compared with the original data. When the restored data is the same as the original data, another piece of the original data is tested until multiple pieces of the original data are tested.

[0012] In one embodiment of the present invention, the step of obtaining the original data includes:

[0013] Setting the number of bits of the original data;

[0014] Set first type of data, second type of data and third type of data, in the first type of data, two adjacent bit data are opposite, in the second type of data, two bit data separated by one bit are opposite, in the third type of data, two bit data separated by two bits are opposite; and

[0015] At least one type of data is selected from the first type of data, the second type of data and the third type of data and mixed to obtain the original data.

[0016] In one embodiment of the present invention, the step of randomizing the original data includes:

[0017] Setting reference data, wherein the reference data is preset data or random data, wherein the number of bits of the reference data is the same as the number of bits of the original data;

[0018] inverting the original data to obtain first intermediate data; and

[0019] The first intermediate data and the reference data are subjected to an XOR process, and test data is obtained according to an output value of the XOR process.

[0020] In one embodiment of the present invention, the step of obtaining the test data by XOR processing includes:

[0021] Comparing the same bit of the first intermediate data and the reference data in sequence according to the order of the bits, if the comparison result is the same, outputting the first value at the bit of the current order, if the comparison result is different, outputting the second value at the bit of the current order; and

[0022] The output values ​​are sorted in order of bits to generate the test data.

[0023] In one embodiment of the present invention, the step of processing the test data according to the reverse step of the randomization process includes:

[0024] Sequentially XORing the reference data and the test data at the same bit position in the order of the bit positions to obtain second intermediate data; and

[0025] The second intermediate data is inverted to obtain restored data.

[0026] In one embodiment of the present invention, the step of placing the storage device at a constant temperature includes:

[0027] Setting a first temperature and a second temperature, wherein the first temperature is lower than the second temperature and higher than normal temperature;

[0028] Placing the storage device in a temperature box and increasing the temperature of the temperature box in a stepwise manner until the temperature of the temperature box increases from a first temperature to a second temperature; and

[0029] The temperature of the incubator is maintained at the second temperature until the comparison between the original data and the restored data is completed, and the temperature of the incubator is initialized to the first temperature.

[0030] In one embodiment of the present invention, in the step of writing the test data into the storage device, the test data is written into a buffer of the storage device and fills up the buffer.

[0031] In one embodiment of the present invention, before writing the test data, the buffer capacity of the storage device is acquired, and when writing the test data, the data volume of the test is set to the buffer capacity.

[0032] The present invention provides a storage test device, comprising:

[0033] A data generation module, used for generating a plurality of pieces of original data according to a preset format of the original data at the beginning of the test;

[0034] A data configuration module, used for randomizing the original data to obtain test data;

[0035] A data writing module, used for writing the test data into the storage device;

[0036] A data recovery module, configured to process the test data according to the reverse steps of the randomization process to obtain recovery data after the storage device has been placed at a constant temperature for at least a retention time;

[0037] a comparison module, used to compare the restored data with the original data and output a comparison result; and

[0038] The loop control module is used to continue testing another piece of the original data when the restored data is the same as the original data, until multiple pieces of the original data are traversed and tested.

[0039] In one embodiment of the present invention, the storage testing device further includes:

[0040] a temperature chamber to allow the storage device to be placed therein; and

[0041] A temperature control module is used to adjust the temperature of the incubator. The temperature control module controls the initialization temperature of the incubator to be a first temperature. The temperature control module controls the constant temperature placement temperature of the storage device to be a second temperature. The first temperature is less than the second temperature, and the first temperature is higher than normal temperature. The temperature control module uses a step-by-step temperature increase to adjust the temperature.

[0042] As described above, the present invention provides a storage test method and storage test device, which can detect the cache capacity of a flash memory device. The present invention can detect simple bit flips, short circuits or open circuits of the read-write cache, and can also detect multi-bit flips, address-data cross-coupling conditions, and the data retention capacity of the read-write cache. The present invention not only has high test accuracy, but is also applicable to various storage devices and has a wide range of test objects.

[0043] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0045] Figure 1 It is a schematic diagram of the structure of a storage test device in one embodiment of the present invention.

[0046] Figure 2 FIG. 4 is a schematic diagram of the structure of a storage device in an embodiment of the present invention.

[0047] Figure 3 The figure is a flow chart of a storage test method in one embodiment of the present invention.

[0048] Figure 4 FIG. 1 is a flow chart of step S100 in an embodiment of the present invention.

[0049] Figure 5 FIG. 1 is a flow chart of step S200 in an embodiment of the present invention.

[0050] Figure 6 FIG. 1 is a flow chart of step S230 in an embodiment of the present invention.

[0051] Figure 7 FIG. 4 is a flow chart of step S400 in an embodiment of the present invention.

[0052] In the figure: 10, storage test equipment; 20, host; 21, data generation module; 22, data configuration module; 23, data writing module; 24, data recovery module; 25, comparison module; 26, cycle control module; 27, temperature control module; 30, temperature box; 40, storage device; 41, main controller; 42, cache chip; 43, flash memory chip; 50, timer. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] See also Figure 1 and Figure 2 As shown, the machine to be tested of the storage device test device 10 provided by the present invention is a storage device 40, wherein the storage device 40 uses flash memory as a storage medium, and may be an embedded memory (embedded Multi Media Card, eMMC) or a universal flash storage (UFS), etc. In this embodiment, the storage device 40 may be an SM flash card, a CF card, a Multi Media Card (Multi Media Card, MMC), a Secure Digital Card (Secure Digital Card, SD card), a memory stick, a micro hard disk, etc. And the machine to be tested may also be a digital device loaded with the storage device 40. The storage device 40 includes a main controller 41, a cache chip 42, and a flash memory chip 43. The main controller 41 receives instructions and data from the host computer, and completes writing or reading data according to the instructions of the host computer. The main controller 41 is electrically connected to the cache chip 42 and the flash memory chip 43, and the cache chip 42 and the flash memory chip 43 are electrically connected. The cache chip 42 stores system temporary data, and the flash memory chip 43 stores user data. Before writing data to the flash memory chip 43, the data is stored in the cache chip 42. The storage device 40 not only responds to the host computer instructions, but also has multiple processes such as scanning self-checking, garbage collection and data backup, data reconstruction, etc. inside the storage device 40. Therefore, the cache chip 42 is called very frequently.

[0055] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, the storage test device 10 includes a host 20 and an incubator 30. The incubator 30 is used to accommodate a storage device 40. The present invention does not limit the number of storage devices 40 in the incubator 30. The host 20 includes a data generation module 21, a data configuration module 22, a data writing module 23, a data recovery module 24, a comparison module 25, a circulation control module 26 and a temperature control module 27. In the present invention, the data generation module 21 is used to generate multiple pieces of original data according to a preset format of the original data at the beginning of the test. The data configuration module 22 is used to randomly process the original data to obtain test data. The data writing module 23 is used to write test data to the storage device 40. After the constant temperature placement time of the storage device 40 reaches at least the holding time, the data recovery module 24 processes the test data according to the reverse steps of the randomization process to obtain the recovered data. The comparison module 25 compares the recovered data with the original data and outputs the comparison result. According to the comparison result, when the restored data and the original data are the same, the loop control module 26 restarts the test step and continues to test another piece of original data until multiple pieces of original data are traversed and tested. In this embodiment, the temperature control module 27 is electrically connected to the incubator 30 and is used to adjust the temperature of the incubator 30. The temperature control module 27 controls the initialization temperature of the incubator 30 to be a first temperature, and the temperature control module 27 controls the constant temperature placement temperature of the storage device 40 to be a second temperature, the first temperature is less than the second temperature, and the first temperature is higher than the normal temperature.

[0056] See also Figures 1 to 3 As shown, the present invention provides a storage test method, which includes steps S100 to S500.

[0057] Step S100: setting the format of the original data to generate multiple pieces of original data.

[0058] Step S200: randomize the original data to obtain test data, and write the test data to the storage device.

[0059] Step S300: Set a retention time, place the storage device at a constant temperature, and keep it for at least the retention time.

[0060] Step S400: Process the test data according to the reverse steps of the randomization process to obtain restored data.

[0061] Step S500: Compare the restored data with the original data. When the restored data and the original data are the same, continue to test another piece of original data until multiple pieces of original data are traversed and tested.

[0062] See also Figures 1 to 3As shown, in one embodiment of the present invention, in step S100, the storage device 40 is placed in the incubator 30. After the storage device 40 is placed in the incubator 30, the test starts. Specifically, the host 20 can generate an indication signal for the start of the test. The temperature control module 27 receives the indication signal for the start of the test, and under the regulation of the temperature control module 27, the temperature inside the incubator 30 is adjusted to a first temperature. In this embodiment, the first temperature is higher than normal temperature, for example, 60°C. The normal temperature in the present invention is the room temperature of the test environment, for example, 25°C. Then the data generation module 21 starts to generate multiple pieces of raw data.

[0063] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S100, a test firmware is set, and the test firmware includes a rule for generating raw data. In this embodiment, the rule for generating raw data is to mix one or more preset data types to generate raw data. The preset data type is set by a tester and input into the host 20. In this embodiment, the preset data type includes a first type of data, a second type of data, and a third type of data. The step of generating raw data includes step S100 including steps S110 to S130.

[0064] Step S110: Set the number of bits of the original data.

[0065] Step S120: setting model data of multiple preset data types.

[0066] Step S130: Mix at least one preset data type to obtain original data.

[0067] See also Figures 1 to 4As shown, in one embodiment of the present invention, in step S110, the original data is binary data. In this embodiment, for example, the original data is set to binary data of 8-bit data, such as 00000000. In step S120, multiple preset data types are set. Specifically, the first type of data, the second type of data and the third type of data are set. Among them, in the first type of data, the two adjacent bit data are opposite. For example, the first type of data is 01 or 10. In the second type of data, the two bit data separated by one bit are opposite. For example, the second type of data is 001, 011, 100, 110. In the third type of data, the two bit data separated by two bits are opposite. For example, the third type of data is 0001, 0111, 0011, 0101, 1000, 1010, 1100, 1110. It should be noted that the step of setting the original data in the present invention can improve the discrete balance degree of data distribution, thereby simulating the working conditions faced by the cache chip 42 as much as possible, and improving the test pressure faced by the cache chip 42. In other embodiments of the present invention, the generation rule of the original data can also be adjusted to generate multiple preset data types. In step S130, at least one type of data is selected from the first type of data, the second type of data and the third type of data to mix and obtain the original data. In this embodiment, the preset data types are mixed until the number of bits of the original data reaches the preset number of bits, thereby obtaining the original data. In the step of mixing data, the preset data types mixed can be of the same type or of different types. For example, if the original number of bits is 8, four first type of data can be selected to mix, and the original data obtained is 01010101, 10101010. For example, two third type of data can be selected to mix, 01011000, 11101100, etc. For example, two second type of data and one first type of data can be selected to mix, 00101110.

[0068] See also Figures 1 to 4As shown, it should be noted that in the present invention, in step S100, the number of original data is preset, for example, 6. The data generation module 21 generates original data until the number of original data reaches the preset number. In the step of generating the preset data type, the number of bits of the first type of data, the second type of data and the third type of data is different. Specifically, the first type of data is two bits, the second type of data is three bits, and the third type of data is four bits. The mixed preset data type can be the same as the initial preset data type. For example, two first type of data are mixed to obtain 0101, and the third type of data can also have 0101. The multiple original data finally generated are random. Although the data is generated in different ways, it is also possible to obtain the same data. In this embodiment, the generated original data is not adjusted and is directly used in step S200 to simulate the actual use environment of the cache chip 42 as much as possible. The same original data can be included in the multiple original data generated. In other embodiments of the present invention, in step S100, the same original data in the multiple original data are deleted to ensure that the data in the multiple original data do not overlap, thereby increasing the number of test data of the cache chip 42. After deleting the same original data, new original data are continuously generated according to the data generation rule to ensure that the number of generated original data meets the preset number. It should also be noted that in the step of mixing data, the generation rule of the original data is measured with a preset data type as a unit, for example, two third-type data are selected to be mixed, 01011000, data 0101 is a unit, and data 1000 is a unit.

[0069] See also Figures 1 to 3 and Figure 5 As shown, in one embodiment of the present invention, in step S200, the steps of randomizing the original data include steps S210 to S240.

[0070] Step S210: setting reference data, where the reference data is preset data or random data, wherein the number of bits of the reference data is the same as the number of bits of the original data.

[0071] Step S220: invert the original data to obtain first intermediate data.

[0072] Step S230: XOR the first intermediate data and the reference data, and obtain test data according to an output value of the XOR processing.

[0073] Step S240: configure the cache capacity and cache address of the storage device, and write test data to the storage device.

[0074] See also Figures 1 to 3 , Figure 5 and Figure 6As shown, in one embodiment of the present invention, in step S210, the reference data is preset data, and for example, is 11111111. In another embodiment of the present invention, the reference data may be randomly generated data. In the step of testing an original data, no matter the reference data, preset data or random data, after determining the value of the reference data, the value of the reference data will no longer be changed in this round of testing. In step S220, the data on all bits of the original data are inverted. For example, if the original data is 01010101, the first intermediate data obtained after inversion is 10101010. Step S230 includes steps S231 to S234.

[0075] Step S231 : Compare the same bits of the first intermediate data and the reference data in sequence according to the order of the bits.

[0076] Step S232: If the comparison result is the same, output the first value at the bit position in the current sequence.

[0077] Step S233: If the comparison result is different, output a second value at the bit position in the current sequence.

[0078] Step S234: Sort the output values ​​in order of bits to generate test data.

[0079] See also Figures 1 to 3 , Figure 5 and Figure 6As shown, in one embodiment of the present invention, in step S231, the bits of the first intermediate data and the bits of the reference data can be sorted in order from right to left. Compare the values ​​on the first bit of the first intermediate data and the reference data. If the values ​​are the same, step S232 is executed, and the data configuration module 22 outputs a first value for the first bit, and the first value is, for example, 0. If the values ​​are different, step S233 is executed, and the data configuration module 22 outputs a second value for the first bit, and the second value is, for example, 1. In this embodiment, the first value and the second value are opposite binary data. The first intermediate data and the reference data are sequentially compared in order from right to left until the comparison and value output of all bits are completed. According to the output value of the data configuration module 22, and sorted in the order of the bits, the test data is obtained. For example, the first intermediate data is 10101010, and the reference data is set to 11111111, then the generated test data is 01010101. If the reference data is 10001000, then the generated test data is 01100110. In step S240, in the present invention, the cache capacity of the cache chip 42 is obtained. The data writing module 23 writes test data to the cache chip 42 multiple times according to the cache capacity, and the total amount of the written test data is the cache capacity of the cache chip 42. In this embodiment, multiple test data are written to the cache chip 42 until the cache chip 42 is full. The storage address of the test data is obtained to facilitate subsequent reading of the test data.

[0080] See also Figures 1 to 3 , Figure 5 and Figure 6 As shown, in one embodiment of the present invention, in step S300, the storage test device 10 includes a timer 50. The timer 50 stores the holding time, wherein the holding time is, for example, 30 minutes. After the data writing module 23 completes the writing of the test data, the host 20 generates a temperature control signal, and the temperature control module 27 completes the temperature control of the temperature box 30, and the temperature of the temperature box 30 is stepped to the second temperature. The second temperature is, for example, 120°C. The temperature rise gradient of the step temperature rise is, for example, 15°C every 5 minutes. After the temperature box 30 is heated to the second temperature, the temperature control module 27 feeds back a start timing signal to the timer 50, thereby starting the timer 50. The timer 50 starts timing from zero. When the timer 50 reaches the holding time, the timer 50 feeds back a data recovery start signal to the data recovery module 24, and the data recovery module 24 starts to execute step S400. Wherein, when the timer 50 feeds back a data recovery start signal to the data recovery module 24, the timing data of the timer 50 is cleared.

[0081] See also Figures 1 to 3 and Figure 7As shown, in one embodiment of the present invention, in step S400, the step of acquiring recovery data includes step S410 and step S420.

[0082] Step S410: XOR the reference data and the test data in the same bit order in sequence to obtain second intermediate data.

[0083] Step S420: invert the second intermediate data to obtain restored data.

[0084] See also Figures 1 to 3 and Figure 7 As shown, in one embodiment of the present invention, in step S410, test data is read from the cache chip 42. The data of the same bit position of the reference data and the test data are compared. If the data are the same, a first value is output, and if the data are different, a second value is output. For example, the read test data is 01010101, and the reference data is 11111111, then the output second intermediate data is 10101010. In step S420, the second intermediate data is inverted. Specifically, all bit data of the second intermediate data are inverted. For example, if the second intermediate data is 10101010, then the restored data is 01010101. In this embodiment, the reference data used in step S410 and step S200 are the same data.

[0085] See also Figures 1 to 3As shown, in one embodiment of the present invention, in step S500, the restored data and the original data are compared in bytes. If the restored data and the original data are inconsistent, it means that the reliability of the cache chip 42 is not up to standard, the test is terminated directly, and the current product can be used as a waste or an object for further study. In this embodiment, if the restored data and the original data are consistent, the comparison module 25 feeds back a loop start signal to the loop control module 26. Under the loop start signal, the loop control module 26 sends a second temperature control signal to the temperature control module 27, and the temperature control module 27 adjusts the temperature of the temperature box 30 from the second temperature to the first temperature. In this embodiment, under the second temperature control signal, the temperature of the temperature box 30 is cooled from, for example, 120°C to, for example, 60°C. And the loop control module 26 continues to read another original data in the new cycle, and re-executes steps S100 to S500. The number of original data and the number of cycles are stored in the loop control module 26. When the number of cycles exceeds the original number, the test is stopped. In this embodiment, an array can be set to store the original data, and the original data can be sorted, and the original data can be tested in sequence according to the sequence number. In the first cycle, while the original data is generated, the number of original data is stored in the loop control module 26, and the number of cycles is initialized to 1. When the recovered data and the original data are compared, and the recovered data and the original data are the same, a new test cycle is started, and the number of cycles is increased by one. At the end of the second to last test cycle, the number of cycles is equal to the number of original data. At the end of the last test cycle, when the recovered data and the original data are compared, and the recovered data and the original data are the same, the number of cycles is increased by one. At this time, the number of cycles is greater than the number of original data, and the test is stopped. In the present invention, when all the original data pass the test, the test reliability of the cache chip 42 meets the standard.

[0086] The present invention provides a storage test method, which includes the following steps: setting the format of original data and generating multiple pieces of the original data. Randomizing the original data to obtain test data, and writing the test data to a storage device. Setting a retention time, placing the storage device at a constant temperature, and at least continuing the retention time. Processing the test data according to the reverse steps of the randomization process to obtain recovery data. Comparing the recovery data with the original data, when the recovery data is the same as the original data, continuing to test another piece of the original data until multiple pieces of the original data are traversed and tested. The present invention can detect the cache capacity of a flash memory device. The present invention can detect simple bit flips, short circuits or open circuits of a read-write cache, and can also detect multi-bit flips, address-data cross-coupling conditions, and the data retention capacity of a read-write cache. The present invention not only has high test accuracy, but is also applicable to various storage devices and has a wide range of test objects.

[0087] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A storage test method, characterized in that: The following steps are involved: Setting the format of the original data, wherein the number of bits of the original data is set, and setting the first type of data, the second type of data and the third type of data, wherein in the first type of data, two adjacent bit data are opposite, in the second type of data, two bit data separated by one bit are opposite, and in the third type of data, two bit data separated by two bits are opposite, and at least one type of data is selected from the first type of data, the second type of data and the third type of data and mixed to generate a plurality of pieces of the original data; The original data is randomly processed, wherein reference data is set, the reference data is preset data or random data, wherein the number of bits of the reference data is the same as the number of bits of the original data, the original data is inverted to obtain first intermediate data, the first intermediate data and the reference data are XOR-processed, test data is obtained according to an output value of the XOR processing, and the test data is written to a storage device; Setting a holding time, placing the storage device at a constant temperature, and maintaining the storage device for at least the holding time; Process the test data according to the reverse steps of the randomization process to obtain restored data; as well as The restored data is compared with the original data. When the restored data is the same as the original data, another piece of the original data is tested until multiple pieces of the original data are tested.

2. A storage test method according to claim 1, characterized in that: The steps of obtaining the test data by XOR processing include: Comparing the same bit of the first intermediate data and the reference data in sequence according to the order of the bits, if the comparison result is the same, outputting the first value at the bit of the current order, if the comparison result is different, outputting the second value at the bit of the current order; and The output values ​​are sorted in order of bits to generate the test data.

3. A storage test method according to claim 1, characterized in that: The step of processing the test data in the reverse order of the randomization process comprises: Sequentially XORing the reference data and the test data at the same bit position in the order of the bit positions to obtain second intermediate data; and The second intermediate data is inverted to obtain restored data.

4. A storage test method according to claim 1, characterized in that: The step of placing the storage device at a constant temperature comprises: Setting a first temperature and a second temperature, wherein the first temperature is lower than the second temperature and higher than normal temperature; Placing the storage device in a temperature box and increasing the temperature of the temperature box in a stepwise manner until the temperature of the temperature box increases from a first temperature to a second temperature; and The temperature of the incubator is maintained at the second temperature until the comparison between the original data and the restored data is completed, and the temperature of the incubator is initialized to the first temperature.

5. A storage test method according to claim 1, characterized in that: In the step of writing the test data into the storage device, the test data is written into a buffer of the storage device and fills up the buffer.

6. A storage test method according to claim 1, characterized in that: Before writing the test data, the buffer capacity of the storage device is obtained, and when writing the test data, the data volume of the test is set to the buffer capacity.

7. A storage test device, characterized in that: include: A data generation module, configured to set the format of the original data at the beginning of the test, wherein the number of bits of the original data is set, and first-category data, second-category data, and third-category data are set, wherein two adjacent bit data of the first-category data are opposite, and two bit data of the second-category data are opposite with one bit interval, and two bit data of the third-category data are opposite with two bits interval, and at least one type of data is selected from the first-category data, the second-category data, and the third-category data to mix, and generate a plurality of pieces of the original data; A data configuration module, for randomly processing the original data, wherein reference data is set, the reference data is preset data or random data, the number of bits of the reference data is the same as the number of bits of the original data, the original data is inverted to obtain first intermediate data, the first intermediate data and the reference data are XOR-processed, and test data is obtained according to an output value of the XOR processing; A data writing module, used for writing the test data into the storage device; A data recovery module, configured to process the test data according to the reverse steps of the randomization process to obtain recovery data after the storage device has been placed at a constant temperature for at least a retention time; A comparison module, used for comparing the restored data with the original data, and outputting a comparison result; as well as The loop control module is used to continue testing another piece of the original data when the restored data is the same as the original data, until multiple pieces of the original data are traversed and tested.

8. The storage test device according to claim 7, characterized in that: The storage test device also includes: a temperature chamber to allow the storage device to be placed therein; and A temperature control module is used to adjust the temperature of the incubator. The temperature control module controls the initialization temperature of the incubator to be a first temperature. The temperature control module controls the constant temperature placement temperature of the storage device to be a second temperature. The first temperature is less than the second temperature, and the first temperature is higher than normal temperature. The temperature control module uses a step-by-step temperature increase to adjust the temperature.

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