Read voltage overdrive in read recovery

Abstract

Devices, systems, and methods for applying read voltage overdrive in read recovery are described. One example apparatus may include an array of memory cells and a controller coupled to the array of memory cells, where the controller is configured to apply a pass voltage to a word line in the array of memory cells, apply a read voltage to the word line, and apply a read voltage to the word line. And overdrive applying a read voltage greater than the read voltage and less than or equal to the pass voltage to the word line.

Description

Technical Field

[0001] The present disclosure relates generally to memory devices, and more particularly, to apparatus, methods, and systems for applying a read voltage overdrive in read recovery. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data, and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered, and may include NAND flash memory, NOR flash memory, phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), among others.

[0003] Memory devices may be combined together to form a solid state drive (SSD). An SSD may include nonvolatile memory (e.g., NAND flash memory and / or NOR flash memory), and / or may include volatile memory (e.g., DRAM and / or SRAM), as well as various other types of nonvolatile and volatile memory. For example, a flash memory device may include memory cells that store data in a charge storage structure (e.g., a floating gate), and may be used as nonvolatile memory for a wide range of electronic applications. Flash memory devices typically use single-transistor memory cells that allow for high memory density, high reliability, and low power consumption.

[0004] SSDs can be used to replace hard disk drives as the primary storage volume of a computer because solid-state drives may have advantages over hard disk drives in terms of performance, size, weight, ruggedness, operating temperature range, and power consumption. For example, compared to magnetic disk drives, SSDs may have superior performance because they have no moving parts (which avoids seek times, latencies, and other electromechanical delays associated with magnetic disk drives).

[0005] Memories are used as volatile and nonvolatile data storage devices for a wide range of electronic applications. For example, nonvolatile memories can be used in personal computers, portable memory sticks, digital cameras, cellular phones, portable music players (e.g., MP3 players), movie players, and other electronic devices. Memory cells can be arranged in arrays, which are used in memory devices.

[0006] Memory cells in an array architecture can be programmed to a desired state. For example, charge can be placed on or removed from a charge storage structure (e.g., a floating gate) of a memory cell to program the cell to a specific state. For example, a single level cell (SLC) can be programmed to one of two different states, each state representing a different number of data values, such as 1 or 0. Some flash memory cells can be programmed to one of more than two states corresponding to different specific data values ​​(e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, or 1110). Such cells may be referred to as multi-state memory cells, multi-unit cells, or multi-level cells (MLC). MLCs can provide higher density memory without increasing the number of memory cells because each cell can be programmed to a state corresponding to more than one number (e.g., more than one data bit). Summary of the invention

[0007] One aspect of the present disclosure relates to an apparatus for read voltage overdrive in read recovery, comprising: a memory cell array; and a controller coupled to the memory cell array, wherein the controller is configured to: apply a pass voltage to a word line in the memory cell array; apply a read voltage to the word line; and apply a read voltage overdrive greater than the read voltage and less than or equal to the pass voltage to the word line.

[0008] Another aspect of the present disclosure relates to an apparatus for read voltage overdrive in read recovery, comprising: a nonvolatile memory cell array; and a controller coupled to the nonvolatile memory cell array, wherein the controller is configured to: apply a read voltage to a word line in the nonvolatile memory array; identify a number of errors in response to applying the read voltage to the word line; and apply a read voltage overdrive to the word line that is greater than the read voltage and greater than a highest read voltage applied to the word line in response to the number of errors exceeding a threshold number of errors.

[0009] Yet another aspect of the present disclosure relates to a method for read voltage overdrive in read recovery, comprising: applying a pass voltage to a word line in a memory cell array; applying a first read voltage to the word line; applying a read voltage overdrive equal to the pass voltage to the word line; and applying a second read voltage to the word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a device in the form of a computing system including at least one memory system according to some embodiments of the present disclosure.

[0011] Figure 2 Schematic diagram illustrating a portion of a non-volatile memory array according to several embodiments of the present disclosure.

[0012] Figure 3 is a graph of voltage applied to a word line over time according to several embodiments of the present disclosure.

[0013] Figure 4 is a graph of voltage applied to a word line over time according to several embodiments of the present disclosure.

[0014] Figure 5 is a graph of voltage applied to a word line mapped to a polysilicon channel trap over time according to several embodiments of the present disclosure.

[0015] Figure 6 is a flow chart of a method for applying a read voltage overdrive according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Provided herein are apparatus, systems, and methods for applying a read voltage overdrive in read recovery. In several embodiments of the present disclosure, an apparatus may include a memory cell array and a controller coupled to the memory cell array, wherein the controller is configured to apply a pass voltage to a word line in the memory cell array, apply a read voltage to the word line, and apply a read voltage overdrive greater than the read voltage and less than or equal to the pass voltage to the word line. The read voltage overdrive may be applied prior to a subsequent read voltage to recapture electrons within a channel to reduce voltage drop and / or read window budget loss.

[0017] Polysilicon is commonly used as a channel material in 3D-Nand flash products. Electron traps within a polysilicon channel (e.g., a poly channel) or at a polysilicon interface (e.g., a poly interface) may affect the read window budget. In a three-level cell (TLC) and / or a four-level cell (QLC) read sequence, the read voltage applied to the word line during the read operation may act as a read voltage underdrive. These read voltages may cause de-trapping of electrons, which may result in voltage drops and / or read window budget losses.

[0018] Read voltage overdrive has been used in read operations to help word line stabilization and obtain read time margin. For example, in existing methods, the read voltage overdrive trim in read recovery is the same as the read voltage overdrive trim in normal read operation. However, in several embodiments of the present disclosure, a strong read voltage overdrive that is significantly greater than the read voltage overdrive trim used in normal read operation is used in read recovery to recover the read window budget loss. During read recovery in TLC and QLC read sequences, an expanded read voltage overdrive and an expanded precharge time can be used in all reads.

[0019] In the following detailed description of the present disclosure, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of illustration several implementations of how the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it is understood that other embodiments may be utilized and process changes, electrical changes, and / or structural changes may be made without departing from the scope of the present disclosure.

[0020] As used herein, "a number" of something may refer to one or more of such things. For example, a number of word lines may refer to one or more word lines. Additionally, designators such as "M" and "N" as used herein, particularly with respect to reference numerals in the drawings, indicate that a number of the particular features so designated may be included in several embodiments of the present disclosure.

[0021] The figures herein follow a numbering convention in which the first digit or the first few digits correspond to the figure number of the accompanying drawing and the remaining digits identify the elements or components in the accompanying drawings. Similar elements or components between different figures can be identified by using similar numbers. As will be appreciated, the elements shown in various embodiments herein can be added, exchanged and / or deleted in order to provide several additional embodiments of the present disclosure. In addition, the proportions and relative dimensions of the elements provided in the figures are intended to illustrate various embodiments of the present disclosure and are not used in a limiting sense.

[0022] Figure 11 is a block diagram of an apparatus in the form of a computing system 101 including at least one memory system 104 according to several embodiments of the present disclosure. As used herein, a memory system 104, a controller 108, or a memory device 110 may also be individually considered to be a "device". For example, the memory system 104 may be a solid state drive (SSD), and may include a host interface 106, a controller 108 (e.g., a processor and / or other control circuitry), and a number of memory devices 110-1, ..., 110-M that provide storage volumes for the memory system 104, for example, solid-state memory devices such as NAND flash memory devices. In several embodiments, the controller 108, the memory devices 110-1, ..., 110-M, and / or the host interface 106 may be physically located on a single die or within a single package (e.g., a managed NAND application). Moreover, in several embodiments, the memory (e.g., the memory devices 110-1, ..., 110-M) may include a single memory device.

[0023] like Figure 1 , the controller 108 may be coupled to the host interface 106 and the memory devices 110-1, ..., 110-M via a plurality of channels and may be used to transfer data between the memory system 104 and the host 102. The host interface 106 may be in the form of a standardized interface. For example, when the memory system 104 is used for data storage in a computing system, the host interface 106 may be a Serial Advanced Technology Attachment (SATA), a Peripheral Component Interconnect Express (PCIe), or a Universal Serial Bus (USB), among other connectors and interfaces. However, in general, the host interface 106 may provide an interface for passing control, address, data, and other signals between the memory system 104 and a host 102 having a compatible acceptor for the host interface 106.

[0024] The host 102 may be a host system, such as a personal laptop computer, a desktop computer, a digital camera, a mobile phone, or a memory card reader, as well as various other types of hosts. The host 102 may include a system motherboard and / or a backplane and may include a plurality of memory access devices, such as a plurality of processors.

[0025] Controller 108 may communicate with memory devices 110-1, ..., 110-M to control data read, write, and erase operations, among other operations. Controller 108 may include, for example, a number of components in the form of hardware and / or firmware (e.g., one or more integrated circuits) and / or software for controlling access to the number of memory devices 110-1, ..., 110-M and / or for facilitating data transfer between host 102 and memory devices 110-1, ..., 110-M. For example, in Figure 1In the example illustrated in FIG. 1 , the controller 108 includes an error correction code encoder / decoder component 114. However, the controller 108 may include various other components that are not illustrated so as not to obscure the embodiments of the present disclosure. Moreover, in some embodiments, the component 114 may not be a component of the controller 108, for example, the component 114 may be a separate component.

[0026] For example, the ECC encoder / decoder component 114 may be an LDPC encoder / decoder that may encode / decode user data transmitted between the host 102 and the memory devices 110 - 1 , . . . , 110 -M.

[0027] Memory devices 110-1, ..., 110-M may include several arrays of memory cells. For example, the array may be a flash array having a NAND architecture. However, embodiments are not limited to a particular type of memory array or array architecture. For example, memory cells may be grouped into several blocks including several physical pages. Several blocks may be included in a plane of memory cells and the array may include several planes. As an example, a memory device may be configured to store 8KB (kilobytes) of user data per page, 128 pages of user data per block, 2048 blocks per plane, and 16 planes per device.

[0028] Figure 2 A schematic diagram illustrating a portion of a non-volatile memory array 200 according to several embodiments of the present disclosure. Figure 2 The embodiment of the present invention describes a NAND architecture non-volatile memory array, such as a NAND flash memory. However, the embodiments described herein are not limited to this example. Figure 2 , the memory array 200 includes access lines (e.g., word lines 205-1, ..., 205-N) and intersecting data lines (e.g., local bit lines 207-1, 207-2, 207-3, ..., 207-M). For ease of addressing in a digital environment, the number of word lines 205-1, ..., 205-N and the number of local bit lines 207-1, 207-2, 207-3, ..., 207-M ​​can be some power of 2, such as 256 word lines times 4,096 bit lines.

[0029] The memory array 200 includes NAND strings 209-1, 209-2, 209-3, ..., 209-M. Each NAND string includes non-volatile memory cells 211-1, ..., 211-N, each of which is communicatively coupled to a respective word line 205-1, ..., 205-N. Each NAND string (and its constituent memory cells) is also associated with a local bit line 207-1, 207-2, 207-3, ..., 207-M. The non-volatile memory cells 211-1, ..., 211-N of each NAND string 209-1, 209-2, 209-3, ..., 209-M are connected source to drain in series between a source select gate (SGS) (e.g., field effect transistor (FET) 213) and a drain select gate (SGD) (e.g., FET 214). Each source select gate 213 is configured to selectively couple a respective NAND string to a common source 223 in response to a signal on a source select line 217 , while each drain select gate 214 is configured to selectively couple a respective NAND string to a respective bit line in response to a signal on a drain select line 215 .

[0030] like Figure 2 , the source of the source select gate 213 is connected to the common source line 223. The drain of the source select gate 213 is connected to the source of the memory cell 211-1 of the corresponding NAND string 209-1. The drain of the drain select gate 214 is connected to the bit line 207-1 of the corresponding NAND string 209-1 at the drain contact 221-1. The source of the drain select gate 214 is connected to the drain of the last memory cell 211-N (e.g., a floating gate transistor) of the corresponding NAND string 209-1.

[0031] In several embodiments, the construction of the nonvolatile memory cells 211-1, ..., 211-N includes a source, a drain, a charge storage structure (e.g., a floating gate), and a control gate. The nonvolatile memory cells 211-1, ..., 211-N have their control gates coupled to word lines 205-1, ..., 205-N, respectively. The "columns" of nonvolatile memory cells 211-1, ..., 211-N make up NAND strings 209-1, 209-2, 209-3, ..., 209-M, and are coupled to given local bit lines 207-1, 207-2, 207-3, ..., 207-M, respectively. The "rows" of nonvolatile memory cells are those memory cells that are typically coupled to a given word line 205-1, ..., 205-N. The use of the terms "column" and "row" is not meant to imply a particular linear (eg, vertical and / or horizontal) orientation of the nonvolatile memory cells. A NOR array architecture would be laid out similarly, except that strings of memory cells would be coupled in parallel between select gates.

[0032] A subset of cells coupled to a selected word line (e.g., 205-1, ..., 2105-N) can be programmed and / or read together as a page of memory cells. A programming operation (e.g., a write operation) can include applying a number of programming pulses (e.g., 16V to 20V) to a selected word line in order to increase the threshold voltage (Vt) of a selected cell coupled to that selected access line to a desired programming voltage level corresponding to a target (e.g., desired) state (e.g., charge storage state). States are equivalently referred to herein as "levels".

[0033] A read operation (which may also be referred to as a program verify operation) may include sensing a voltage and / or current change of a bit line coupled to a selected cell in order to determine the state of the selected cell. The state of a particular fractional-bit memory cell may not directly correspond to a data value for that particular memory cell, but rather the states of a group of memory cells including that particular memory cell together map to a data value having an integer number of bits. A read operation may include precharging a bit line and detecting a discharge when the selected cell begins to conduct.

[0034] Determining (e.g., detecting) the state of a selected cell may include providing a number of sense signals (e.g., read voltages) to a selected word line while providing a number of voltages (e.g., read pass voltages) to word lines coupled to unselected cells of the string sufficient to place the unselected cells in a conductive state independent of the threshold voltages of the unselected cells. The bit line corresponding to the selected cell being read and / or verified may be detected to determine whether the selected cell is conductive in response to a particular sense signal applied to the selected word line. For example, the state of a selected cell may be determined by a word line voltage at which the bit line current reaches a particular reference current associated with a particular state.

[0035] MLCs may be two-bit (e.g., four-state) memory cells, or store more than two data bits per memory cell, including storing fractional data bits per memory cell. For example, a two-bit memory cell may be programmed to one of four states, such as P0, P1, P2, and P3. In operation, for example, a number of memory cells in a selected block may be programmed so that they have Vt levels corresponding to P0, P1, P2, or P3. As an example, state P0 may represent a stored data value such as binary "11". State P1 may represent a stored data value such as binary "10". State P2 may represent a stored data value such as binary "00". State P3 may represent a stored data value such as binary "01". However, embodiments are not limited to these data value correspondences.

[0036] Figure 33 is a graph of voltages applied to a word line over time according to several embodiments of the present disclosure. During a read operation, a read pass voltage (e.g., a pass voltage) is applied to the word line at 330. A read voltage overdrive is applied at 334 and the time required to apply the read voltage overdrive is illustrated at 332. The overdrive time (t od ) 332 may begin when the read voltage overdrive begins ramping after applying a read voltage (e.g., read voltage 331) until the read voltage overdrive has stabilized to reach the next read voltage in the read sequence. At 331, a read voltage may be applied between the pass voltage and the read voltage overdrive.

[0037] In the case where the word line contains three-level cells (TLC) and / or four-level cells (QLC), the read voltage on the word line may appear as a read voltage underdrive. These read voltages may cause detrapping of electrons, which may result in voltage drop and / or read window budget loss.

[0038] An expanded read voltage overdrive may be applied to perform read recovery on a word line including TLC and / or QLC. For example, read recovery may include read retry, soft bit read, and / or correction read. When a number of errors are identified, read recovery may be initiated after applying a read voltage to the word line and / or a read voltage overdrive may be applied to the word line.

[0039] By applying a read voltage overdrive, the traps can be refilled with electrons. For TLC, the read window budget can be increased by more than 50 millivolts (mV) by applying a read voltage overdrive. By applying a read voltage overdrive to QLC, the read window budget can be increased by more than 190 mV.

[0040] The read voltage overdrive may be greater than the read voltage. In some examples, the read voltage overdrive may be equal to the pass voltage to ensure that the read voltage overdrive is greater than the sixteenth voltage state of the QLC. In several embodiments, the read voltage overdrive may be greater than the highest read voltage applied to the word line.

[0041] Fine tuning settings other than read voltage overdrive may be changed in response to identifying a number of errors and / or initiating read recovery. For example, the precharge time may be increased as a change to the fine tuning settings. Since a higher voltage is applied to the word line for the read voltage overdrive, it may take longer for the voltage to ramp up to the read voltage overdrive and ramp down from the read voltage overdrive. The precharge time may be increased accordingly to include longer ramp up and ramp down times. For example, if the word line includes TLC, the precharge time may be increased to greater than 2 microseconds. When the word line includes QLC, the precharge time may be increased to greater than 5 microseconds. The precharge time for a word line including QLC may be greater than the precharge time for a word line including TLC because QLC has more levels.

[0042] Figure 4 is a graph of voltage applied to a word line over time according to several embodiments of the present disclosure. Figure 4 The voltages applied to the word lines in a read operation (e.g., a forward read sequence) are illustrated. For example, a first read voltage (e.g., a lower page read voltage) is applied at 431-1, a second read voltage (e.g., an upper page read voltage) is applied at 431-2, and a third read voltage (e.g., an additional page read voltage) is applied at 431-3. The read sequence can include any number of read voltages applied to the word lines.

[0043] A read voltage overdrive, which may be the same as a pass voltage, may be applied between read voltages. For example, a pass voltage may be applied at 430-1, then a first read voltage (e.g., a lower page read voltage) may be applied at 431-1, then a pass voltage may be applied at 430-2, then a second read voltage (e.g., an upper page read voltage) may be applied at 431-2, then a pass voltage may be applied at 430-3, and then a third read voltage (e.g., an additional page read voltage) may be applied at 431-3. A read sequence may include any number of read voltages applied to a word line, wherein a pass voltage is applied to the word line between each of the read voltages in the read sequence.

[0044] The pass voltage may be used as a read voltage overdrive because the pass voltage is greater than the highest read voltage applied to the word line. Thus, the pass voltage may be used as a read voltage overdrive to ensure that the read voltage overdrive is sufficient to recover the read window budget loss. However, in several embodiments, the read voltage overdrive may not need to be as high as the pass voltage to recover the read window budget loss and in some instances, a read voltage overdrive greater than the pass voltage may cause read disturbance. Thus, the read voltage overdrive during the recovery operation may be greater than the highest read voltage applied to the word line and equal to or less than the pass voltage applied to the word line.

[0045] A read voltage overdrive may also be applied to the reverse read sequence. For example, an additional page read voltage may be applied, a read voltage overdrive may be applied, an upper page read voltage may be applied, a read voltage overdrive may be applied, and a lower page read voltage may be applied.

[0046] Figure 5 is a graph of voltage applied to a word line mapped to a polysilicon channel 552 including wells 554-1, 554-2, 554-3, 554-4, 554-5, 554-6, 554-7, 554-8, 554-9, and 554-10 over time according to several embodiments of the present disclosure.

[0047] Polysilicon is commonly used as a channel material in 3D-Nand flash products. Traps 554-1, ..., 554-10 within the polysilicon channel 552 or at the polysilicon interface may affect the read window budget. In a three-level cell (TLC) and / or four-level cell (QLC) read sequence, the previous read voltage on the word line may act as a read voltage underdrive. These previous read voltages may cause de-trapping of electrons, which may result in voltage drops and read window budget losses.

[0048] like Figure 5 As illustrated in FIG. 5 , a pass voltage may be applied to a word line at 530. A first read voltage may be applied to a word line at 531-1. A read voltage overdrive may be applied to a word line at 534. A second read voltage may be applied to a word line at 531-2.

[0049] In response to applying a first read voltage to the word line at 531-1, traps 554-1, 544-2, and 554-3 may be decaptured. Due to the application of the first read voltage at 531-1, there are no electrons or fewer electrons in the polysilicon channel 552. A read voltage overdrive is applied to the word line at 534, and traps 544-4, 544-5, and 554-7 are refilled with electrons. In several embodiments, several traps may remain unfilled even after the read voltage overdrive is applied. For example, trap 554-6 may remain unfilled, but may have been refilled if a larger read voltage overdrive has been applied. For example, trap 554-6 may have been refilled if the read voltage overdrive is equal to the pass voltage applied at 530. In response to applying a second read voltage to the word line at 531 - 2 , the traps 554 - 8 , 554 - 9 , and 554 - 10 may be de-trapped, leaving no or fewer electrons in the polysilicon channel 552 due to the second read voltage.

[0050] Figure 6 6 is a flow chart of a method 660 for applying a read voltage overdrive according to several embodiments of the present disclosure. At block 662, the method 660 may include applying a pass voltage to a word line in a memory cell array, such as Figure 3 330 of them and Figure 5 Applying a pass voltage to the word line may place unselected cells in a conducting state.

[0051] At block 664, method 660 may include applying a first read voltage to the word line, such as Figure 5 The method 660 may further include de-trapping electrons in response to applying a first read voltage to the word line. Thus, when the first read voltage is applied to the word line, the read window budget may be reduced.

[0052] At block 666, method 660 may include applying a read voltage overdrive equal to the pass voltage to the word line, such as Figure 3 334 of them and Figure 5 The method 660 may further include stabilizing the word line when a read voltage overdrive is applied to the word line. In some examples, the precharge time may be increased in response to applying the read voltage overdrive.

[0053] At block 668, method 660 may include applying a second read voltage to the word line, such as Figure 5 In response to applying the second read voltage to the word line, electron de-trapping and read window budget loss may occur again.

[0054] Although specific embodiments have been illustrated and described herein, it will be apparent to those of ordinary skill in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of the various embodiments of the present disclosure. It should be understood that the above description has been made in an illustrative manner, not a restrictive manner. Upon reviewing the above description, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those of skill in the art. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the appended claims together with the full scope of equivalents authorized by such claims.

[0055] In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of simplifying the present disclosure. This disclosure method should not be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure must use more features than those explicitly stated in each claim. On the contrary, as reflected in the appended claims, the inventive subject matter lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim itself as a separate embodiment.

Claims

1. A device for overdriving a read voltage in read recovery, comprising: A memory cell array (200); and A controller (108) coupled to the memory cell array, wherein the controller is configured to: applying a pass voltage to word lines (205-1, ..., 205-N) in the memory cell array; applying a read voltage to the word line; and A read voltage overdrive greater than the read voltage and less than or equal to the pass voltage is applied to the word line. 2 . The apparatus of claim 1 , wherein the controller is configured to apply the read voltage overdrive to perform read recovery.

3. The apparatus of claim 2, wherein the read recovery comprises at least one of a read retry, a soft bit read, or a correction read.

4. The apparatus of claim 1, wherein the word lines comprise three-level cells (TLCs).

5. The apparatus of claim 4, wherein the controller is configured to increase a read window budget by greater than 50 mV in response to applying the read voltage overdrive to the TLC.

6. The apparatus of claim 1, wherein the word lines comprise quad level cells (QLCs).

7. The apparatus of claim 6, wherein the controller is configured to increase a read window budget by greater than 190 mV in response to applying the read voltage overdrive to the QLC.

8. A device for overdriving a read voltage in read recovery, comprising: A non-volatile memory cell array (200); and A controller (108) coupled to the array of non-volatile memory cells, wherein the controller is configured to: applying a read voltage to word lines (205-1, ..., 205-N) in the nonvolatile memory array; identifying a number of errors in response to applying the read voltage to the word line; and A read voltage overdrive greater than the read voltage and greater than a highest read voltage applied to the word line is applied to the word line in response to the number of errors exceeding a threshold number of errors.

9. The apparatus of claim 8, wherein the apparatus is a three-dimensional NAND (3D NAND) device.

10. The apparatus of claim 9, wherein the 3D NAND device comprises a polysilicon (poly) channel trap.

11. The apparatus of claim 10, wherein the applied read voltage causes de-trapping of electrons in the polysilicon channel traps.

12. The apparatus of claim 8, wherein the controller is configured to change a trim setting in response to the number of errors exceeding the threshold number of errors.

13. The apparatus of claim 12, wherein the controller is configured to change a trim setting by increasing a precharge time. 14 . The apparatus of claim 13 , wherein in response to the word line comprising a three-level cell (TLC), the precharge time is greater than 2 μsec.

15. The apparatus of claim 13, wherein in response to the word line comprising a quad level cell (QLC), the precharge time is greater than 5 microseconds.

16. A method for overdriving a read voltage in read recovery, comprising: applying a pass voltage to word lines (205-1, ..., 205-N) in a memory cell array (200); applying a first read voltage to the word line; applying a read voltage overdrive equal to the pass voltage to the word line; and A second read voltage is applied to the word line.

17. The method of claim 16, further comprising detrapping electrons induced in response to applying the first read voltage to the word line.

18. The method of claim 16, further comprising reducing a read window budget in response to applying the first read voltage to the word line.

19. The method of claim 16, further comprising stabilizing the word line in response to applying the read voltage overdrive.

20. The method of claim 16, further comprising increasing a precharge time in response to applying the read voltage overdrive.

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