Word line ramp rate monitor for early detection of defect activation

Abstract

Methods and systems are disclosed for a word line ramp rate monitor for early detection of defect activation. A memory access to a word line is initiated. Based on the applied ramping voltage, a ramping rate of the word line is determined. In response to determining that the ramp rate satisfies a defect condition, a memory access operation is aborted.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to wordline ramp rate monitors for early detection of defect activation in memory subsystems. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure provides a method comprising: initiating a memory access operation for a word line; determining a ramp rate for the word line based on an applied ramping voltage; and causing the memory access operation to be aborted in response to determining that the ramp rate satisfies a defect condition.

[0004] In another aspect, the present disclosure further provides a system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations comprising: initiating a memory access operation for a word line; applying a ramp voltage to the word line; enabling a counter in response to a first voltage detector sensing that the ramp voltage is at a first voltage level; disabling the counter in response to a second voltage detector sensing that the ramp voltage is at a second voltage level; and causing the memory access operation to be terminated in response to determining that the value of the counter satisfies a criterion.

[0005] In yet another aspect, the present disclosure further provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: initiating a memory access operation for a word line; determining a ramp rate for the word line based on an applied ramp voltage; and in response to determining that the ramp rate satisfies a defect condition, causing the memory access operation to be aborted. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2A is a graph of two programming pulses with different ramp rates according to some embodiments of the present disclosure.

[0009] Figure 2B The determination of a ramp rate during a memory access operation according to some embodiments of the present disclosure is schematically illustrated.

[0010] Figure 3 is a flow chart of an example method of detecting a defect condition on a word line according to some embodiments of the present disclosure.

[0011] Figure 4 is a flow chart of another example method of detecting a defect condition on a word line according to some embodiments of the present disclosure.

[0012] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure are directed to a word line (WL) ramp rate monitor for early detection of defect activation in a memory subsystem. The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0014] The memory subsystem may include a high density non-volatile memory device where data retention is required when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of nonvolatile memory devices are described. A nonvolatile memory device is a package of one or more dies. Each die may include one or more planes. For some types of nonvolatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. Each block includes a set of pages. Each page consists of a group of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more binary bits of information and have various logical states related to the number of bits stored. The logical state can be represented by a binary value such as "0" and "1" or a combination of such values.

[0015] A memory device may consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are formed on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may have an associated row of memory cells in a memory device and is used together with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of a memory cell. Hereinafter, a block refers to a unit of a memory device for storing data, and may include a group of memory cells, a word line group, a word line, or an individual memory cell. One or more blocks may be grouped together to form a separate partition (e.g., a plane) of a memory device so as to allow parallel operations on each plane. A memory device may include a circuit system for performing concurrent memory page accesses of two or more memory planes. For example, a memory device may include a plurality of access line driver circuits and power circuits that may be shared by the planes of a memory device to facilitate concurrent access of pages containing different page types of two or more memory planes. For ease of description, these circuits may generally be referred to as independent plane driver circuits. Depending on the storage architecture employed, data may be stored across memory planes (i.e., in stripes). Thus, one request to read a segment of data (e.g., corresponding to one or more data addresses) may result in read operations being performed on two or more of the memory planes of the memory device.

[0016] The memory subsystem further includes a memory subsystem controller that can communicate with the memory devices to perform memory access operations such as reading data, writing data, or erasing data at the memory devices and other such operations. Figure 1The memory subsystem controller is described in more detail. The operations may be performed in response to an access request (e.g., a write command, a read command) sent by a host system to the memory subsystem so as to store data on a memory device of the memory subsystem and read data from a memory device of the memory subsystem. As specified by the host request, the data to be read or written is referred to as "host data" hereinafter. The host request may include logical address information (e.g., a logical block address (LBA), a namespace) for the host data, which is a location that the host system associates with the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata together with the host data is referred to as "payload" hereinafter. The operation may be further initiated by the memory subsystem as a media management operation, which may include performing, for example, a write operation, a read operation, or an erase operation on the host data stored on the memory device. For example, the memory subsystem may rewrite previously written host data from a location on the memory device to the same location or a new location as part of a write refresh operation. In another example, the media management operation may include rereading the host data stored on the memory device as part of a read refresh operation. During memory access operations, such as programming operations, a high voltage may be generated by a charge pump and applied to a regulator. A charge pump is a circuit that can increase or decrease the voltage applied to a word line to reach a target voltage level during a memory access operation. A regulator (sometimes referred to as a voltage regulator) is a circuit that maintains a stable and regulated voltage level within a memory device. The high voltage may be applied, for example, during a programming pulse and / or a program verification operation.

[0017] As described above, a nonvolatile memory device may include several individual blocks, each of which references a set of one or more word lines used to access the memory cells of the block. Over time, as memory access operations, including programming operations, read operations, and erase operations, are repeatedly performed on the blocks of the memory device, certain defects may be generated. For example, an electrical short may be generated between two adjacent word lines. For example, when a certain voltage, such as a programming voltage, is applied to one of these word lines, a current is generated, and at least a portion of the current may flow through the electrical short and onto an adjacent word line. This defect may be referred to as a word line to word line short. As another example, an electrical short may be formed between a word line and a pillar (e.g., a conductive trace), and may be referred to as a word line to pillar short. This portion of current may be referred to as a "leakage current". This leakage current may affect the logic value programmed into or read from the memory cell connected to the associated word line, thereby causing errors on the memory device. In addition, word line to word line and / or word line to pillar shorts may cause charge pump and / or regulator crashes. In the case of a wordline to wordline short and / or a wordline to pillar short, the charge pump and / or regulator cannot maintain the high voltage applied during the memory access operation. That is, once the wordline to wordline or wordline to pillar short defect is in effect, the short will sink current from the pump and / or regulator, which in turn will not be able to maintain the target voltage. As a result, the bias along the string may be impaired, which may result in permanent data loss.

[0018] The memory subsystem may employ an error detection / correction engine capable of detecting and correcting a certain number of errors. Such a detection / correction engine may use an error correction code (ECC) to detect and / or correct errors. An ECC failure occurs when the detection / correction engine cannot correct an error within the data being read. This may be referred to as an uncorrectable ECC error (UECC error). Certain physical defects, including a wordline to wordline short or a wordline to pillar short, are considered UECC errors, and in response to detecting such an error, the memory subsystem may retire the corresponding block and / or wordline so that it is not used to store the advancing data. In addition, in a multi-plane device, a defect in a block in one plane may also affect a block in an adjacent plane, even if the adjacent plane does not have the defect. In addition to wordline to wordline shorts, other defects on the memory device are also possible.

[0019] When this UECC error occurs when data is written to a memory device during a programming operation, all or a portion of the data may be improperly stored on the memory device. In addition, once the data being written is removed from any associated buffer, the data may be permanently lost. Some conventional memory subsystems attempt to detect defects on memory devices, but with limited success. For example, some systems monitor the operation of a charge pump that is configured to raise or lower the voltage applied to the word line of the memory device during a memory access operation. When there is a word line to word line short (and / or a word line to pillar short) on the memory device, the work required for the charge pump to reach the desired voltage level (e.g., programming voltage) may be more difficult due to leakage current flowing across the short circuit. The system can detect this overwork and conclude that there is a word line to word line short (and / or a word line to pillar short) on the memory device. Such detection methods typically require the voltage of the word line to reach a target voltage value (or nearly reach the target voltage value), and / or include a long observation phase. In these cases, in the case of a defect, the voltage of the word line will be high enough to cause unrecoverable interference on the already programmed word line. Furthermore, in multi-plane devices, the charge pump is typically shared by multiple planes. Therefore, even if any over-operation of the charge pump is detected, it is not immediately known which specific plane has a defect that caused the over-operation of the charge pump. Therefore, the system must perform a separate operation to test each individual plane of the memory device to identify the specific plane with the defect. This results in additional delays in detecting defects and reduced bandwidth for performing other operations.

[0020] Aspects of the present disclosure address the above and other defects by detecting defects (e.g., caused by leaky word lines) based on measurements of the rate of change of a voltage signal applied to a given word line during a memory access operation (e.g., a program, read, or erase operation). The measurement of the rate of change may be referred to as the ramp rate of the voltage signal. Irreversible defects may be preceded by a change in the resistance-capacitance (RC) of the word line. Therefore, the ramp rate has a linear relationship with the RC of the word line. During a memory access operation, the voltage on the accessed word line transitions from an initial voltage level (e.g., a standby voltage level) to a target voltage level (e.g., an access voltage level). The rate at which the voltage level changes as it transitions from one level to another may be referred to as the ramp rate. For example, if Figure 2B As shown, the ramp rate can be depicted in graphical form as the slope of the leading edge of the programming pulses 231, 230.

[0021] In one embodiment, a voltage detector may be used to estimate the ramp rate. The voltage detector may continuously monitor the supply voltage of the memory device and may detect whether the supply voltage exceeds a threshold level. Based on the detected voltage, the voltage detector may trigger an action. The memory subsystem may include two voltage detectors that may detect a specific voltage level applied to a word line as part of a memory access operation. The first voltage detector may detect a first voltage level and the second voltage may detect a second voltage level. Upon detecting the first voltage level, the first voltage detector may immediately enable (i.e., start) a counter. The counter is connected to a clock and counts clock cycles while enabled. Upon detecting the second voltage level, the second voltage detector may immediately disable (i.e., stop) the counter. Thus, the counter counts the number of clock cycles between the applied voltages from the first voltage level to the second voltage level. That is, the counter value corresponds to the time it takes for the voltage to change from the first voltage level to the second voltage level. In addition, the counter value is related to the ramp rate. The ramp rate is the rate of change of the voltage level when it changes from the first voltage level to the second voltage level. The rate of change may be calculated as the difference in voltage divided by the measurement time represented by the counter value.

[0022] In some embodiments, the counter value may be compared to a predetermined threshold to determine whether the corresponding word line is leaking, approaching a leaking state, or not leaking. In other embodiments, the ramp rate may be compared to a predetermined ramp rate threshold to determine whether the corresponding word line is leaking, approaching a leaking state, or not leaking. A leaking word line is a word line that is affected by a word line to word line or a word line to a pillar short circuit. Therefore, the voltage applied to the leaking word line may result in a leakage current. If the word line leaks, the memory access operation may be suspended, and the block associated with the leaking word line may be retired. Suspending the memory access operation based on the ramp rate may prevent the voltage supplied to the word line from reaching the high voltage stage of the memory access operation. Therefore, suspending the memory access operation at the ramp stage level may avoid pump and / or regulator collapse. If the word line is approaching a leaking state, the memory access operation may continue. In some embodiments, the memory subsystem controller may perform preventive actions because the word line is approaching a leaking state. In other embodiments, the memory subsystem controller may mark the approaching leaking state for the host to take preventive actions. Preventive actions may include, for example, copying previously programmed data from blocks associated with the leaking word line to good blocks, and / or retiring blocks associated with the leaking word line. The retired blocks may no longer be trusted to be programmed with host or system data. In some embodiments, an indication of the retired blocks may be stored in a list. If the word line is not leaking, memory access operations may continue.

[0023] Advantages of the present disclosure include improved memory device performance and reliability. Embodiments of the present disclosure provide for early detection of defective word lines before reaching the high voltage level of a memory access operation, for example, during the ramp phase of a memory access operation. This avoids transmitting the high voltage level to the damaged string bias, and thus avoids irreversible defects that lead to permanent data loss. In addition, detecting leaking and / or near-leaking word lines reduces current consumption. By detecting and addressing leaking and near-leaking word lines before reaching the high voltage level of a programming operation, the overall performance and reliability of the memory device is improved without any undue delay penalty.

[0024] Figure 1 An example computing system 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0026] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), a device supporting the Internet of Things (IoT), an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0028] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses, for example, the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0029] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may additionally utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, for example, a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC) may store multiple bits per cell. In some embodiments, each memory device 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), name spaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0039] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local media controller 135) on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] The memory subsystem 110 includes a ramp rate monitoring component 113 that can detect a leaking WL or a WL that is close to leaking based on the ramp rate of the memory access operation. In some embodiments, the memory subsystem controller 115 includes at least a portion of the ramp rate monitoring component 113. In some embodiments, the ramp rate monitoring component 113 is part of the host system 120, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the ramp rate monitoring component 113 and is configured to perform the functionality described herein.

[0041] The ramp rate monitoring component 113 can monitor memory access operations performed on the memory devices 130, 140. The ramp rate monitoring component 113 can identify the initiation of memory access operations such as read operations, write operations, erase operations, and / or refresh operations. It should be noted that the ramp rate monitoring component 113 can identify other memory access operations that are not listed.

[0042] The memory access operation may include a ramp phase, in which a voltage is applied to activate a word line to gradually increase the voltage from a lower voltage level to a target voltage level. The ramp rate monitoring component 113 may use two voltage detectors to determine the ramp rate of the applied ramp voltage. One voltage detector may sense when the applied voltage reaches a first voltage level, and a second voltage detector may sense when the applied voltage reaches a second voltage level. The amount of time it takes for the voltage level to ramp up from the first level to the second level represents the ramp rate. The first voltage detector may enable a counter when the applied voltage reaches the first voltage level, and the second voltage detector may disable the counter when the applied voltage reaches the second voltage level. While enabled, the counter counts the number of clock cycles. In some embodiments, the ramp rate monitoring component 113 may compare the value of the counter with a predetermined counter threshold to determine whether the word line is a leaky word line, a healthy word line (i.e., not leaking), or something in between (i.e., close to leaking).

[0043] The ramp rate monitoring component 113 may compare the value of the counter (representing the number of clock cycles) with the leakage WL counter threshold. If the counter value exceeds the leakage WL counter threshold, the ramp rate monitoring component 113 may determine that the word line is leaking. The leakage WL indicates the activation of a defect. Therefore, the ramp rate monitoring component 113 may suspend the memory access operation during the ramp phase, thereby avoiding applying a high voltage to the leakage WL. The ramp rate monitoring component 113 may also retire the blocks associated with the leakage WL. Retiring the blocks associated with the leakage WL may include adding an indication of the retired blocks to a leakage block list. The blocks listed in the leakage block list may no longer be used to store data.

[0044] The ramp rate monitoring component 113 may compare the value of the counter (representing the number of clock cycles) with the counter WL threshold value close to leakage. If the counter value does not exceed the leakage WL counter threshold value but exceeds the close leakage counter WL counter threshold value, the ramp rate monitoring component 113 may determine that the word line is close to leakage. Close to the leakage counter WL threshold value may indicate that the WL may have leakage, but it has not yet reached a defective state. The ramp rate monitoring component 113 may allow the memory access operation to continue, but may retire the block associated with the close leakage WL. This avoids future memory access operations that will be performed on the close leakage WL. Retiring the block associated with the close leakage WL may include adding an indication of the retired block to the leakage block list. The blocks listed in the leakage block list may no longer be used to store data. If the counter value does not exceed the leakage WL or the close leakage WL counter threshold value, the ramp rate monitoring component 113 may allow the memory access operation to continue.

[0045] In some embodiments, the local media controller 135 may compare the value of the counter with a predetermined counter threshold. If the value of the counter exceeds the predetermined counter threshold for the leaking WL, the local media controller 135 may send a signal to the ramp rate monitoring component 113. Upon receiving the signal, the ramp rate monitoring component 113 may then immediately cause the memory access operation to be suspended, and may cause the block associated with the leaking WL to be retired. If the value of the counter exceeds the predetermined counter threshold for the near-leaking WL, the local media controller 135 may send a different signal to the ramp rate monitoring component 113. Upon receiving the signal, the ramp rate monitoring component 113 may immediately cause the block associated with the near-leaking WL to be retired.

[0046] In some embodiments, the ramp rate monitoring component 113 can calculate the ramp rate of the WL based on the counter value. The ramp rate can be the difference between the second voltage level and the first voltage level divided by the time it takes for the voltage level to transition from the first voltage level to the second voltage level. The time can be represented by the counter value. The ramp rate monitoring component 113 can compare the ramp rate with a predetermined ramp rate threshold to determine whether the word line is a leaky word line, a healthy word line (i.e., not leaking), or something in between (i.e., close to leaking).

[0047] The ramp rate monitoring component 113 may compare the ramp rate to a leakage WL ramp rate threshold. If the ramp rate is less than the leakage WL ramp rate threshold, the ramp rate monitoring component 113 may determine that the word line is leaking. Therefore, the ramp rate monitoring component 113 may suspend the memory access operation during the ramp phase, thus avoiding applying a high voltage to the leakage WL. The ramp rate monitoring component 113 may also retire the block associated with the leakage WL.

[0048] The ramp rate monitoring component 113 may compare the ramp rate to a near-leakage ramp rate WL threshold. If the ramp rate is greater than or equal to the leakage WL ramp rate threshold but less than the near-leakage WL ramp rate threshold, the ramp rate monitoring component 113 may determine that the word line is near leakage. Near-leakage ramp rate WL threshold may indicate that the WL may have leakage, but it has not yet reached a defective state. The ramp rate monitoring component 113 may allow the memory access operation to continue, but may retire the block associated with the near-leakage WL. If the ramp rate exceeds both the leakage WL or the near-leakage WL ramp rate threshold, the ramp rate monitoring component 113 may allow the memory access operation to continue.

[0049] The predetermined threshold may be determined during manufacture and / or characterization of the memory device. The first level detected by the first voltage detector and the second level detected by the second voltage detector may be determined during manufacture and / or characterization. That is, these values ​​(the predetermined threshold, and / or the first and second voltage levels) may be parameters that may be adjusted and / or fine-tuned during manufacture and / or characterization of the memory device. The predetermined threshold may be related to the voltage level of the first voltage detector and the voltage level of the second voltage detector.

[0050] The voltage detector may be placed within the memory devices 130, 140. In some embodiments, the voltage detector may be placed at the output of the regulator. In other embodiments, the voltage detector may be placed at the global line driver (sometimes called a word line driver, which is responsible for driving the voltage signal of the word line).

[0051] The voltage detector may enable or disable a counter configured to count clock cycles. The clock may operate within the corresponding memory device 130, 140 and / or within the memory subsystem 110. In some embodiments, the clock frequency may be adjusted (e.g., during the manufacture and / or characterization of the memory device). The frequency of the clock represents the number of clock cycles that occur within a certain time period. A higher frequency clock may result in a more accurate ramp rate determination. For example, a frequency of one cycle per 30 nanoseconds may result in a counter value of 34 for a leaking WL, while a frequency of one cycle per 15 nanoseconds may result in a counter value of 69 for the same leaking WL. The frequency of the clock, the predetermined threshold voltage value used to determine whether the WL is leaking or close to leaking, and the voltage level detected by the voltage detector are related and may be set during the manufacture and / or characterization of the memory device.

[0052] Figure 2A 2 is a voltage-time graph 200 showing voltage levels of two programming pulses 230, 231 with different ramp rates according to some embodiments of the present disclosure. The y-axis of the graph 200 is the voltage level 220, and the x-axis of the graph 200 is time 210. The programming pulse 231 shows the voltage level during a programming operation applied to a non-leakage WL. The programming pulse 230 shows the voltage level during a programming operation applied to a leakage WL. Due to the leakage current, more voltage is applied to the leakage WL in order to achieve the same voltage level. Therefore, the amount of time it takes for the voltage to reach a certain level on the leakage WL is greater than that on the non-leakage WL.

[0053] The voltage level changes shown in the area labeled 240 represent the ramp-up phase of the memory access operation. The ramp-up phase is a gradual increase in voltage levels in the initial phase of a memory access operation, such as a programming operation. It should be noted that the voltage-time graph 200 is provided as an illustrative example, and embodiments of the present disclosure may be applied to program verification pulses of a programming operation, an erase operation, and / or other memory access operations.

[0054] Figure 2B Schematically illustrates the determination of a ramp rate during a memory access operation according to some embodiments of the present disclosure. Voltage-time graph 250 illustrates the ramp-up phase of a programming operation (ie, graph 250 is Figure 2A The y-axis of the graph 250 is the voltage level 220, and the x-axis of the graph 250 is the time 210. Figure 2A , a programming pulse 231 shows a voltage level during a programming operation on a non-leakage WL, and a programming pulse 230 shows a voltage level during a programming operation on a leakage WL.

[0055] Two voltage detectors (not shown) may be connected to the memory device (eg, Figure 1 1 260). The first voltage detector may detect a voltage at voltage level 1 260, and the second voltage detector may detect a voltage at voltage level 2 262. Voltage level 1 261 and / or voltage level 2 262 may be determined during manufacturing and / or characterization of the memory device.

[0056] Clock 275 is shown operatively coupled to a memory device (eg, Figure 1 260 ) of the memory devices 130, 140). Counter 280A shows a counter operating in conjunction with programming pulse 230. Counter 280B shows a counter operating in conjunction with programming pulse 231. Thus, counter 280A is enabled when the first voltage detector detects programming pulse 230 at level 1 260, and is disabled when the second voltage detector detects programming pulse 230 at level 2 262. Similarly, counter 280B is enabled when the first voltage detector detects programming pulse 231 at level 1 260, and is disabled when the second voltage detector detects programming pulse 231 at level 2 262.

[0057] Clock count 282A represents the number of clock cycles counted when counter 280A is enabled, and clock count 282B represents the number of clock cycles counted when counter 280B is enabled. In some embodiments, to determine whether programming pulses 230, 231 are leaking, near leaking, or healthy, the ramp rate monitor component 113 may compare clock counts 282A, B to counter thresholds. The counter thresholds may be, for example, a leaking WL counter threshold and a near leaking WL counter threshold. In the illustrative example, clock count 282A exceeds the leaking WL counter threshold, and thus the word line on which programming pulse 230 operates is determined to be leaking. Therefore, when the applied voltage reaches a high voltage level (e.g., shown as Figure 2A Before the high point on the voltage-time graph 200 of Figure 1 The ramp rate monitoring component 113 may suspend the programming operation during the ramp phase. The ramp rate monitoring component 113 may also retire the blocks associated with the WL.

[0058] In this illustrative example, clock count 282B does not exceed the leakage WL counter threshold, and thus the word line on which programming pulse 231 operates is determined to be non-leaking. Therefore, the programming operation can proceed. In some embodiments, clock count 282B can be compared to a near leakage WL counter threshold. If clock count 282B exceeds the additional near leakage WL counter threshold (but is less than or equal to the leakage WL counter threshold), the programming operation associated with programming pulse 231 can proceed, however the block associated with the WL can be retired.

[0059] In some embodiments, the ramp rate monitor component 113 may determine the ramp rate of the programming pulses 230, 231. To determine the ramp rate, the ramp rate monitor component 113 may divide the voltage level difference between the voltage level 2 262 and the voltage level 1 260 by the clock counter value. For example, to determine the ramp rate of the programming pulse 230, the ramp rate monitor component 113 may determine the voltage level 2 262 minus the voltage level 1 260. The ramp rate monitor component 113 may then divide the difference (voltage level 2 262 minus voltage level 1 260) by the clock counter value, clock counter 282A, to determine the ramp rate of the programming pulse 230. The ramp rate monitor component 113 may compare the ramp rate of the programming pulse 230 to a leakage WL ramp rate threshold. In this illustrative example, the ramp rate of the programming pulse 230 is less than the leakage WL ramp rate threshold, and therefore the ramp rate monitor component 113 may determine that the word line on which the programming pulse 230 operates is leaking. As described above, the ramp rate monitoring component 113 can suspend the programming operation during the ramping phase and can optionally retire the block associated with the WL on which the programming pulse 230 operates.

[0060] As another example, to determine the ramp rate of the programming pulse 231, the ramp rate monitoring component 113 may determine the voltage level 2 262 minus the voltage level 1 260. The ramp rate monitoring component 113 may then divide the difference (voltage level 2 262 minus voltage level 1 260) by the clock counter value, clock counter 282B, to determine the ramp rate of the programming pulse 231. The ramp rate monitor component 113 may compare the ramp rate of the programming pulse 231 to a leakage WL ramp rate threshold. In this illustrative example, the ramp rate of the programming pulse 231 is less than the leakage WL ramp rate threshold, and thus the ramp rate monitoring component 113 may determine that the word line on which the programming pulse 231 operates is not leaking. The ramp rate monitoring component 113 may allow the programming operation to proceed.

[0061] In some embodiments, the ramp rate may be compared to a near-leakage WL ramp rate threshold. If the ramp rate of the programming pulse 231 is less than the near-leakage WL ramp rate threshold (but greater than or equal to the leakage WL ramp rate threshold), the ramp rate monitoring component 113 may determine that the WL on which the programming pulse 231 operates is near leakage. The programming operation associated with the programming pulse 231 may continue, however, the block associated with the WL may be retired.

[0062] Figure 3 is a flow chart of an example method 300 of detecting a defect condition on a word line according to some embodiments of the present disclosure. The method 300 may be performed by a processing logic that may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The slope rate monitoring component 113 is executed. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0063] At operation 310, processing logic initiates a memory access operation for a word line. The memory access may be a program operation, a sense operation (ie, a read operation), an erase operation, a refresh operation, or any other memory access operation. The memory access operation may cause a voltage to be applied to the word line.

[0064] At operation 320, processing logic determines a ramp rate for the word line based on the applied ramp voltage. The ramp rate represents the rate at which a voltage level changes as it transitions from one level to another, such as during a ramp phase of a memory access operation. In some embodiments, processing logic may determine the ramp rate by causing a ramp voltage to be applied to the word line. For example, the ramp voltage may correspond to a programming pulse or a programming verification pulse during a programming operation. In response to determining that the ramp voltage reaches a first voltage level, processing logic may enable a counter. The counter may correspond to a clock. Once enabled, the counter may count clock cycles of the clock. In response to determining that the ramp voltage reaches a second voltage level, processing logic may disable the counter. Once disabled, the counter stops counting clock cycles. In some embodiments, the value of the counter may be stored (e.g., Figure 1 The local memory 119 of the memory 119 is used. The counter value may represent the time taken for the applied ramp to transition from the first voltage level to the second voltage. The counter value may be used to calculate the ramp rate. The ramp rate may be the difference between the second counter value and the first counter value divided by the counter value. Thus, the higher the counter value, the lower the ramp rate.

[0065] In some embodiments, to determine that the ramp voltage reaches a first voltage level, the processing logic may sense that the ramp voltage crosses the first voltage level via a first voltage detector. Similarly, to determine that the ramp voltage reaches a second voltage level, the processing logic may sense that the ramp voltage crosses the second voltage level via a second voltage detector.

[0066] At operation 330, processing logic determines whether the ramp rate satisfies a defect condition. If the ramp rate is less than a threshold (e.g., a leaky WL ramp rate threshold), then the defect condition is satisfied. In response to determining that the ramp rate satisfies the defect condition (i.e., the ramp rate indicates a leaky WL), the method proceeds to operation 340. At operation 340, processing logic may cause the memory access operation to be aborted (i.e., prevent the memory access operation from proceeding). In some embodiments, processing logic may cause the block associated with the word line to be retired. In some embodiments, processing logic may add an indicator of the word line to a leaky block list that stores indicators of blocks associated with leaky WLs that are no longer in use.

[0067] In response to determining that the ramp rate does not satisfy the defect condition, the method proceeds to operation 350. At operation 350, processing logic determines whether the ramp rate satisfies a second defect condition. If the ramp rate is less than a second threshold (e.g., close to a leaky WL ramp rate threshold), the second defect condition is satisfied. The second threshold may be greater than the first threshold. That is, the first threshold may indicate a leaky word line, while the second threshold may indicate that the word line is approaching a leaky word line state (or close to leaking). In response to determining that the ramp rate satisfies the second defect condition, the method proceeds to operation 360. In response to determining that the ramp rate does not satisfy the second defect condition, the method proceeds to operation 370. At operation 370, processing logic may enable the memory access operation to continue.

[0068] At operation 360, processing logic has determined that the ramp rate does not satisfy the defect condition but does satisfy the second defect condition. That is, the ramp rate is between the leak WL ramp rate threshold and the near leak WL ramp rate threshold. Therefore, at operation 360, processing logic may cause the block associated with the word line to be retired. Retiring the block associated with the near leak WL may include adding an indicator of the block to the near leak block list. In some embodiments, retiring the block associated with the near leak WL may include blocking future program operations while still enabling future read operations. For example, when selecting a location to store data, the memory subsystem controller 115 may determine not to use a block on the near leak block list. In some embodiments, the leak block list and the near leak block list may store indications of the leak WL and the near leak WL (respectively), and when selecting a location to store data, the memory subsystem controller 115 may determine not to use a location accessible to a WL on the leak block list and / or the near leak block list. Data already stored in a location accessible to the near leak WL (i.e., a block on the near leak block list) may remain there, however after the current memory access operation is performed, the location accessible to the near leak WL (i.e., a block on the near leak block list) may no longer be used to program data. Data already stored in a location accessible to the near leak WL (i.e., a block on the near leak block list) may still be read. Once the data stored in the location accessible to the near leak WL is invalid or no longer needed, the block associated with the near leak WL may be fully retired (i.e., no longer used). After causing the block associated with the near leak WL to retire, the method may proceed to operation 370. At operation 370, processing may enable the memory access operation to continue.

[0069] In some embodiments, the defect condition may be a pass / fail determination. Thus, if the ramp rate is less than or equal to a leaky WL ramp rate threshold, the processing logic may determine that the WL fails, i.e., the WL leaks. Similarly, if the ramp rate is greater than a leaky WL ramp rate threshold, the processing logic may determine that the WL passes, i.e., the WL does not leak. In some embodiments, the processing logic may determine that the WL passes in response to determining that the ramp rate is greater than a near leaky WL ramp rate threshold.

[0070] Figure 4 4 is a flow chart of another example method 400 for detecting a defect condition on a word line according to some embodiments of the present disclosure. The method 400 may be performed by a processing logic that may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The slope rate monitoring component 113 is executed. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0071] At operation 410, processing logic initiates a memory access operation for a word line. The memory access may be a program operation, a sense operation (ie, a read operation), an erase operation, a refresh operation, or any other memory access operation. The memory access operation may cause a voltage to be applied to the word line.

[0072] At operation 420, processing logic applies a ramp voltage to the word line. At operation 430, in response to the first voltage detector sensing the ramp voltage, processing logic may enable a counter. The counter may correspond to a clock. Once enabled, the counter may count clock cycles of the clock. At operation 440, in response to the second voltage detector sensing the ramp voltage, processing logic may disable the counter. Once disabled, the counter stops counting clock cycles. In some embodiments, the value of the counter may be stored (e.g., Figure 1 The counter value may represent the time it takes for the applied ramp to transition from the first voltage level to the second voltage.

[0073] At operation 450, processing logic may determine whether the value of the counter satisfies a criterion. Processing logic may determine that the value of the counter satisfies the criterion in response to determining that the value of the counter exceeds a threshold value (e.g., a leaky WL counter threshold value). If the value of the counter satisfies the criterion (i.e., the counter value is greater than the leaky WL counter threshold value), the method proceeds to operation 460. If not, the method proceeds to operation 470. At operation 460, processing logic may cause the memory access to be aborted (i.e., prevent the memory access operation from proceeding). In some embodiments, processing logic may cause the block associated with the word line to be retired. In some embodiments, processing logic may add an indicator of the block associated with the word line to a leaky block list, which stores indicators of blocks that are no longer in use.

[0074] At operation 470, processing logic has determined that the value of the counter does not satisfy a criterion (i.e., is less than or equal to a threshold value, such as a leaky WL counter threshold value). At operation 470, processing logic determines whether the value of the counter satisfies a second criterion. If the value of the counter is greater than a second threshold value (e.g., close to a leaky WL counter threshold value), the second criterion is satisfied. The second threshold value may be less than the first threshold value. That is, the first threshold value may indicate a leaky word line, while the second threshold value may indicate that the word line is approaching a leaky word line state (or close to leaking). In response to determining that the value of the counter satisfies the second criterion, the method proceeds to operation 480. In response to determining that the value of the counter does not satisfy the second criterion, the method proceeds to operation 490. At operation 490, processing logic may enable the memory access operation to proceed.

[0075] At operation 480, processing logic has determined that the value of the counter does not satisfy the criterion, but does satisfy the second criterion. That is, the value of the counter is less than or equal to the threshold (e.g., the leaky WL counter threshold) but greater than the second threshold (e.g., the near leaky WL counter threshold). Therefore, at operation 480, processing logic may cause the block associated with the word line to be retired. Retiring the block associated with the near leaky WL may include adding an indicator of the block to a near leaky block list. After causing the block associated with the near leaky WL to retire, the method may proceed to operation 490. At operation 490, the processing logic may enable memory access operations to continue.

[0076] In some embodiments, the defect condition may be a pass / fail determination. Thus, if the value of the counter is greater than the leaky WL counter threshold, the processing logic may determine that the WL failed, i.e., the WL leaked. Similarly, if the value of the counter is less than or equal to the leaky WL counter threshold, the processing logic may determine that the WL passed, i.e., the WL did not leak. In some embodiments, the processing logic may determine that the WL passed in response to determining that the value of the counter is less than the near leaky WL counter threshold.

[0077] Figure 5An example machine of computer system 500 is shown, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, computer system 500 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 A host system (eg, a memory subsystem 110) of Figure 1 host system 120), or can be used to perform operations of the controller (for example, to execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0078] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be construed to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0079] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518 that communicate with each other via a bus 530.

[0080] The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 may further include a network interface device 508 to communicate over a network 520.

[0081] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution by the computer system 500, with the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0082] In one embodiment, the instructions 526 include instructions for implementing a corresponding memory access monitoring component (eg, Figure 1 The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0083] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. In this article, and generally, an algorithm is conceived to be a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven to be convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0084] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) numbers within a computer system's registers and memories into other data similarly represented as physical numbers within a computer system's memories or registers or other such information storage systems.

[0085] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is connected to a computer system bus.

[0086] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0087] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory component, etc.

[0088] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method comprising: Initiating a memory access operation for a word line; determining a ramp rate of the word line based on the applied ramp voltage; as well as In response to determining that the ramp rate satisfies a defect condition, the memory access operation is caused to be aborted. 2 . The method of claim 1 , wherein the defect condition is satisfied in response to determining that the ramp rate is less than a threshold value.

3. The method according to claim 1, further comprising: In response to determining that the ramp rate satisfies one of the defect condition or a second defect condition, a block associated with the word line is caused to be retired. 4 . The method of claim 1 , wherein the applied ramp voltage corresponds to a program pulse or a program verification pulse of a program operation.

5. The method of claim 1 , wherein determining the ramp rate of the word line comprises: causing a ramp voltage to be applied to the word line; responsive to determining that the ramped voltage of the word line reaches a first voltage level, enabling a counter; in response to determining that the ramped voltage of the word line reaches a second voltage level, disabling the counter; as well as The ramp rate is determined based on the value of the counter.

6. The method of claim 5, wherein determining that the ramped voltage of the word line reaches the first voltage level comprises: The ramped voltage is sensed by a first voltage detector to cross the first voltage level. The method of claim 5 , wherein the counter is associated with a clock, the counter counting clock cycles of the clock.

8. A system comprising: Memory device; as well as a processing device operatively coupled to the memory device to perform operations including: Initiating a memory access operation for a word line; applying a ramp voltage to the word line; enabling a counter in response to the first voltage detector sensing that the ramped voltage is at a first voltage level; in response to the second voltage detector sensing that the ramp voltage is at a second voltage level, disabling the counter; as well as Responsive to determining that the value of the counter satisfies a criterion, the memory access operation is caused to abort.

9. The system of claim 8, wherein the value of the counter satisfies the criterion in response to determining that the value of the counter exceeds a threshold.

10. The system of claim 8, further comprising: Responsive to determining that the value of the counter satisfies the criterion or a second criterion, causing the block associated with the word line to be retired.

11. The system of claim 8, wherein the ramped voltage corresponds to a ramp phase of one of a program pulse or a program verify pulse of a programming operation.

12. The system of claim 8, wherein the ramped voltage corresponds to a ramp phase of an erase operation.

13. The system of claim 11, wherein the counter is associated with a clock, the counter counting clock cycles of the clock.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: Initiating a memory access operation for a word line; determining a ramp rate for the word line based on the applied ramp voltage; and In response to determining that the ramp rate satisfies a defect condition, the memory access operation is caused to be aborted.

15. The non-transitory computer-readable storage medium of claim 14, wherein the defect condition is satisfied in response to determining that the ramp rate is less than a threshold value.

16. The non-transitory computer-readable storage medium of claim 14, wherein the operations further comprise: In response to determining that the ramp rate satisfies the defect condition or a second defect condition, a block associated with the word line is caused to be retired.

17. The non-transitory computer-readable storage medium of claim 14, wherein the applied ramp voltage corresponds to a program pulse or a program verify pulse of a program operation.

18. The non-transitory computer readable storage medium of claim 14, wherein to determine the ramp rate of the word line, the operations further comprise: causing a ramp voltage to be applied to the word line; responsive to determining that the ramped voltage of the word line reaches a first voltage level, enabling a counter; in response to determining that the ramped voltage of the word line reaches a second voltage level, disabling the counter; as well as The ramp rate is determined based on the value of the counter.

19. The non-transitory computer-readable storage medium of claim 18, wherein the operations further comprise: The ramped voltage is sensed by a first voltage detector to cross the first voltage level.

20. The non-transitory computer-readable storage medium of claim 18, wherein the counter is associated with a clock, the counter counting clock cycles of the clock.

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