Methods for forming floating gates

Abstract

This application discloses a method for forming a floating gate, comprising: providing a substrate, the substrate having a device forming region including a first region and a second region, the first region being used to form a flash memory cell device, the second region being used to form a logic device, a first trench being formed in the first region, a second trench being formed in the second region, a floating gate dielectric layer and a first etch stop layer being sequentially formed on the substrate in the first region excluding the first trench, and a gate dielectric layer and a second etch stop layer being sequentially formed on the substrate in the second region excluding the second trench, the thickness of the first etch stop layer being greater than the thickness of the second etch stop layer; forming an isolation dielectric layer that fills the first trench and the second trench while exposing the first etch stop layer and covering the second etch stop layer; removing the first etch stop layer and forming a third trench in the region of the first etch stop layer; and forming a floating gate in the third trench.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for forming a floating gate. Background Technology

[0002] Memory using non-volatile memory (NVM) technology is currently widely used in electronic products with storage functions such as smartphones, tablets, digital cameras, and universal serial bus flash disks (USB flash drives, or "U disks" for short).

[0003] In NVM memory, flash memory is characterized by high transfer efficiency and low cost. Flash memory wafers typically integrate memory arrays composed of flash memory cells and peripheral circuits composed of logic devices. During flash memory fabrication, a common industry practice is to fabricate the cell active area (CAA) and the peripheral active area (PAA) of the peripheral circuitry separately, using two sets of photomasks. To allow for deeper shallow trench isolation (STI) structures in the PAA to ensure isolation of high-voltage devices, the STI structure of the CAA is usually made slightly shallower to facilitate STI structure filling during flash memory cell miniaturization.

[0004] refer to Figure 1 It shows a cross-sectional view of the trenches formed by etching the PAA region during the fabrication process of a flash memory device provided in the related art; Reference Figure 2 It shows a cross-sectional view of the formation of floating gate (FG) trenches during the fabrication process of a flash memory device provided in the related art. For example, as shown... Figure 1 and Figure 2 As shown, after etching the isolation layer trench of CAA101, photoresist 301 is covered on the substrate 110 using a photomask to expose the area to be etched in PAA102, and then the isolation layer trench is etched. After the PAA102 is etched, the trench formed by the etching is filled by growing an isolation dielectric layer 124, and then the isolation dielectric layer 124 is planarized by a planarization process until the etch barrier layer 120 is exposed. Photoresist 302 is covered on PAA102 using a photomask, and then the etch barrier layer 120 of CAA101 (the gate dielectric layer 123 is below the etch barrier layer 120) is removed to form the trench of the floating gate.

[0005] It is not difficult to see that in the process of manufacturing flash memory devices provided by related technologies, when removing the etch barrier layer of CAA, photoresist needs to be covered on PAA with a photomask to protect the etch barrier layer of PAA. This requires an extra photolithography step and the design of an extra photomask, making the process more complex. Summary of the Invention

[0006] This application provides a method for forming a floating gate, which can solve the problem of complex process caused by the need to use a photomask to shield the PAA area to protect the etch stop layer after filling the CAA and PAA with isolation layers in the flash memory manufacturing process provided in the related art. The method includes:

[0007] A substrate is provided, wherein the substrate has a first region and a second region for forming devices, the first region is used to form a flash memory cell device, the second region is used to form a logic device, a first trench is formed in the first region, a second trench is formed in the second region, a floating gate dielectric layer and a first etch barrier layer are sequentially formed on the substrate in the first region excluding the first trench, and a gate dielectric layer and a second etch barrier layer are sequentially formed on the substrate in the second region excluding the second trench, wherein the thickness of the first etch barrier layer is greater than the thickness of the second etch barrier layer.

[0008] An isolation dielectric layer is formed, which fills the first trench and the second trench while exposing the first etch barrier layer and covering the second etch barrier layer.

[0009] Remove the first etch barrier layer and form a third trench in the region of the first etch barrier layer;

[0010] A floating gate is formed in the third trench.

[0011] In some embodiments, the first etch barrier layer and the second etch barrier layer comprise silicon nitride layers.

[0012] In some embodiments, the depth of the second trench is greater than the depth of the first trench.

[0013] In some embodiments, removing the first etch barrier layer includes:

[0014] The first etching barrier layer is removed by a wet etching process.

[0015] In some embodiments, forming a floating gate in the third trench includes:

[0016] Forming the first polycrystalline silicon layer;

[0017] The first polysilicon layer is planarized until the second etch barrier layer is exposed, and the first polysilicon layer outside the third trench is removed, with the first polysilicon layer inside the third trench forming the floating gate.

[0018] In some embodiments, prior to forming the isolation dielectric layer, the method further includes:

[0019] A silicon dioxide layer is formed on the substrate;

[0020] A first silicon nitride layer is formed on the silicon dioxide layer;

[0021] Remove the first silicon nitride layer in the second region;

[0022] A second silicon nitride layer is formed, wherein the first silicon nitride layer and the second silicon nitride layer in the first region constitute a first etch barrier layer, and the second silicon nitride layer in the second region constitutes a second etch barrier layer.

[0023] The first trench is formed in the first region, and the second trench is formed in the second region.

[0024] The technical solution of this application has at least the following advantages:

[0025] By forming a first etch barrier layer in the first region where a flash memory cell device is formed and a second etch barrier layer in the second region where a logic device is formed during the flash memory manufacturing process, and making the thickness of the first etch barrier layer greater than that of the second etch barrier layer, after the trench etching of the isolation structure in the first and second regions is completed and the isolation dielectric layer is filled, the second etch barrier layer is not exposed when the first etch barrier layer is exposed through a planarization process. Thus, the second etch barrier layer can be shielded and protected without using a photomask to cover the photoresist in the second region, thereby reducing process complexity and manufacturing costs to a certain extent. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figures 1 to 2 This is a schematic diagram of the formation of floating gate trenches in the flash memory manufacturing process provided by related technologies;

[0028] Figure 3 This is a flowchart of a method for forming a floating gate provided in an exemplary embodiment of this application;

[0029] Figures 4 to 14 This is a schematic diagram of the formation process of a floating gate provided in an exemplary embodiment of this application. Detailed Implementation

[0030] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0033] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0034] refer to Figure 3 The diagram illustrates a flowchart of a method for forming a floating gate according to an exemplary embodiment of this application, as shown below. Figure 3 As shown, the method includes:

[0035] Step S1: A substrate is provided, wherein the substrate has a first region and a second region for forming devices. The first region is used to form flash memory cell devices, and the second region is used to form logic devices. A first trench is formed in the first region, and a second trench is formed in the second region. A floating gate dielectric layer and a first etch stop layer are sequentially formed on the substrate in the first region except for the first trench. A gate dielectric layer and a second etch stop layer are sequentially formed on the substrate in the second region except for the second trench. The thickness of the first etch stop layer is greater than the thickness of the second etch stop layer.

[0036] refer to Figure 10 It shows a cross-sectional schematic diagram after etching to form the first and second trenches. For example, as shown... Figure 10 As shown, the regions on substrate 210 used for forming devices include a first region 201 and a second region 202. The first region 201 is used to form flash memory cell devices, and the second region 202 is used to form logic devices. A first trench 511 is formed in the first region 201, and a second trench 512 is formed in the second region 202. A floating gate dielectric layer 223 and a first etch stop layer 221 are sequentially formed on the substrate 210 in the first region 201, excluding the first trench 511. A gate dielectric layer 223 and a second etch stop layer 222 are sequentially formed on the substrate 210 in the second region 202, excluding the second trench 512. The thickness of the first etch stop layer 221 is greater than the thickness of the second etch stop layer 222. The first etch stop layer 221 and the second etch stop layer 222 include silicon nitride (Si3N4) layers, and the depth of the second trench 512 is greater than the depth of the first trench 511.

[0037] Step S2: An isolation dielectric layer is formed, which fills the first trench and the second trench while exposing the first etch barrier layer and covering the second etch barrier layer.

[0038] refer to Figure 11 It shows a schematic cross-sectional view after the formation of the insulating dielectric layer. For example, such as... Figure 11 As shown, step S2 includes, but is not limited to: depositing an isolation dielectric layer 224 to fill the first trench 511 and the second trench 512 using a chemical vapor deposition (CVD) process, and planarizing the isolation dielectric layer 224 using a planarization process (e.g., chemical mechanical polishing (CMP)) until the first etch barrier layer 221 is exposed. Since the thickness of the first etch barrier layer 221 is greater than the thickness of the second etch barrier layer 222, the planarization process can be controlled to expose the first etch barrier layer 221 while simultaneously covering the second etch barrier layer 222 with the isolation dielectric layer 224 (e.g., ...). Figure 11(As shown in the area enclosed by the dashed line). The isolation dielectric layer 224 may include a silicon dioxide (SiO2) layer.

[0039] Step S3: Remove the first etch barrier layer and form a third trench in the area of ​​the first etch barrier layer.

[0040] refer to Figure 12 This illustrates a cross-sectional view after the first etch barrier layer has been removed. For example, as shown... Figure 12 As shown, the first etch barrier layer 221 can be removed by a wet etching process to form the third trench 503. Since the second etch barrier layer 222 is covered by the isolation dielectric layer 224, no additional photomask is required for coating, exposure and development to block the second etch barrier layer 222.

[0041] Step S4: Form a floating gate in the third trench.

[0042] refer to Figure 13 It shows a schematic cross-sectional view after the deposition of the first polycrystalline silicon layer; Reference Figure 14 This illustrates a cross-sectional view of the first polysilicon layer after planarization. For example, as shown... Figure 13 and Figure 14 As shown, step S4 includes, but is not limited to: forming a first polysilicon layer 271; planarizing the first polysilicon layer 271 until the second etch barrier layer 222 is exposed; removing the first polysilicon layer 271 outside the third trench 503; and forming a floating gate from the first polysilicon layer 271 inside the third trench 503. In subsequent processes, an isolation layer (e.g., an oxide-nitride-oxide (ONO) layer) and a control gate (CG) can be formed sequentially, which will not be elaborated here.

[0043] In summary, in this embodiment of the application, by forming a first etch barrier layer in the first region forming the flash memory cell device and a second etch barrier layer in the second region forming the logic device during the flash memory manufacturing process, and making the thickness of the first etch barrier layer greater than that of the second etch barrier layer, after the trench etching of the isolation structure in the first and second regions is completed and the isolation dielectric layer is filled, the second etch barrier layer is not exposed when the first etch barrier layer is exposed through a planarization process. Thus, the second etch barrier layer can be shielded and protected without using a photomask to cover the photoresist in the second region, thereby reducing the process complexity and manufacturing costs to a certain extent.

[0044] For example, before step S1, the method further includes: step S12, forming a silicon dioxide layer on a substrate; forming a first silicon nitride layer on the silicon dioxide layer; removing the first silicon nitride layer in the second region; forming a second silicon nitride layer, wherein the first silicon nitride layer and the second silicon nitride layer in the first region constitute a first etch barrier layer, and the second silicon nitride layer in the second region constitutes a second etch barrier layer; forming a first trench in the first region and forming a second trench in the second region.

[0045] refer to Figure 4 It shows a schematic cross-sectional view of the first silicon nitride layer in the first region after photoresist has been applied; Reference Figure 5 It shows a schematic cross-sectional view after the first silicon nitride layer in the second region has been removed; Reference Figure 6 It shows a schematic cross-sectional view after removing the photoresist from the first region. For example, as shown... Figures 4 to 6 As shown, a silicon dioxide layer 223 can be formed on the substrate 210 by thermal oxidation (the silicon dioxide layer 223 in the first region 201 is used to form the floating gate dielectric layer of the flash memory, and the silicon dioxide layer 223 in the second region 202 is used to form the gate dielectric layer of the logic device). A first silicon nitride layer 220 is deposited on the silicon dioxide layer 223 by CVD process. A photoresist 401 is covered on the first silicon nitride layer 220. The photoresist 401 in the second region 202 is removed by exposure and development in sequence. The first silicon nitride layer 220 in the second region 202 is removed by etching, thereby removing the photoresist 401.

[0046] refer to Figure 7 This shows a schematic cross-sectional view after the formation of the second silicon nitride layer. For example, as shown... Figure 7 As shown, a second silicon nitride layer can be deposited by CVD process. The first silicon nitride layer and the second silicon nitride layer in the first region 201 constitute a first etch barrier layer 221, and the second silicon nitride layer in the second region 202 constitutes a second etch barrier layer 222.

[0047] refer to Figure 8 It shows a schematic cross-sectional view after forming a photoresist mask to etch the first and second trenches; Reference Figure 9 It shows a cross-sectional schematic diagram after the first etching; Reference Figure 10 It shows a cross-sectional schematic diagram after etching to form the first and second trenches. For example, as shown... Figure 8 and Figure 9As shown, an advanced patterning film (APF) layer 230, a dielectric anti-reflective coating (DARC) layer 240, and a bottom anti-reflective coating can be sequentially formed on the first etch barrier layer 221 and the second etch barrier layer 222. After covering the photoresist 402, the coating (BARC) layer 250 is sequentially exposed and developed to remove the photoresist 402 in the target area (the area corresponding to the first trench 511 and the second trench 512). The first etching is performed, with the first region 201 etched to a predetermined depth in the first etch barrier layer 221 in the target area and the second region 202 etched to expose the substrate 210 in the target area. The DARC layer 240, BARC layer 250 and photoresist 402 are removed. The second etching is performed, with the first region 201 etched to a predetermined depth in the substrate 210 in the target area and the second region 202 etched to a predetermined depth in the substrate 210 in the target area. The APF layer 230 is removed, and the first trench 511 is formed in the substrate 210 of the first region 201 and the second trench 512 is formed in the substrate of the second region 202.

[0048] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for forming a floating gate, characterized in that, include: A substrate is provided, wherein the substrate has a first region and a second region for forming devices, the first region is used to form a flash memory cell device, the second region is used to form a logic device, a first trench is formed in the first region, a second trench is formed in the second region, a floating gate dielectric layer and a first etch barrier layer are sequentially formed on the substrate in the first region excluding the first trench, and a gate dielectric layer and a second etch barrier layer are sequentially formed on the substrate in the second region excluding the second trench, wherein the thickness of the first etch barrier layer is greater than the thickness of the second etch barrier layer. The first trench and the second trench are filled by depositing an isolation medium layer using a CVD process; The isolation dielectric layer is planarized using a planarization process until the first etch barrier layer is exposed. The process of planarization is controlled so that the first etch barrier layer is exposed while the second etch barrier layer is covered by the isolation dielectric layer. Remove the first etch barrier layer, form a third trench in the area of ​​the first etch barrier layer, and the second area is covered by the isolation dielectric layer and is not etched; A floating gate is formed in the third trench.

2. The method according to claim 1, characterized in that, The first etch barrier layer and the second etch barrier layer comprise silicon nitride layers.

3. The method according to claim 2, characterized in that, The depth of the second trench is greater than the depth of the first trench.

4. The method according to claim 3, characterized in that, The removal of the first etch barrier layer includes: The first etching barrier layer is removed by a wet etching process.

5. The method according to claim 4, characterized in that, The formation of the floating grid in the third trench includes: Forming the first polycrystalline silicon layer; The first polysilicon layer is planarized until the second etch barrier layer is exposed, and the first polysilicon layer outside the third trench is removed, with the first polysilicon layer inside the third trench forming the floating gate.

6. The method according to any one of claims 2 to 5, characterized in that, Before forming the isolation medium layer, the method further includes: A silicon dioxide layer is formed on the substrate; A first silicon nitride layer is formed on the silicon dioxide layer; Remove the first silicon nitride layer in the second region; A second silicon nitride layer is formed, wherein the first silicon nitride layer and the second silicon nitride layer in the first region constitute a first etch barrier layer, and the second silicon nitride layer in the second region constitutes a second etch barrier layer. The first trench is formed in the first region, and the second trench is formed in the second region.

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