Semiconductor device monitoring process method
By making semiconductor workpieces with air bridges on the substrate of the semiconductor device, and performing metal evaporation and photoresist removal treatments, the problem that the prior art cannot measure the electrical properties of semiconductor devices after Gate is completed, and the electrical performance of semiconductor devices is achieved efficient measurement of properties.
Patent Information
- Application Number
- CN202411534880.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-14
AI Technical Summary
The existing semiconductor monitoring program cannot measure its electrical properties after Gate is completed.
By using silicon wafers and positive photoresist to make the first semiconductor workpiece of metal wiring on the substrate and performing semiconductor manufacturing technology on it, a second semiconductor workpiece with an air bridge in the open pattern area at the top of the gate is obtained, and metal evaporation is followed by metal evaporation. The plating and photoresist removal process enables three control electrodes to be connected to the circuit lead-out device for measurement through an air bridge.
The electrical properties of semiconductor devices can be measured after the Gate is completed, and the problem that the prior art cannot perform electrical properties measurement is solved, and the electrical properties data measurement of each control electrode is realized through the circuit-induced device.
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Figure CN119446949A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of semiconductor processing technology, and in particular, relates to a semiconductor device monitoring process method. Background Art
[0002] In the field of semiconductor technology, a phase change memory PCM area is usually placed in the exposure area shot to monitor the process; for pseudo-morphological high electron mobility transistor pHEMT, a Gate device is usually placed in the layout layer to monitor electrical properties. For example, Fig.13 As shown, the monitoring during the Gate period generally includes F1x75 (1 Gate, length 75um), F2x75, F4x75 and F8x75; F1x75 and F2x75 can use SD (ohmic contact metal) metal wiring, and the electrical properties can be measured after the Gate metal layer is completed. For electrical monitoring of Gates greater than 2, subsequent metal connections are required. Summary of the invention
[0003] An embodiment of the present application provides a semiconductor device monitoring process method to solve the problem that the existing semiconductor monitoring process method cannot measure the electrical properties of the gate after the gate is completed.
[0004] In a first aspect, an embodiment of the present application provides a semiconductor device monitoring process method, comprising the following steps:
[0005] Obtain a substrate, and use a silicon wafer and a positive photoresist to manufacture a first semiconductor workpiece with metal wiring on the substrate;
[0006] The first semiconductor workpiece is manufactured by using semiconductor manufacturing technology to obtain a second semiconductor workpiece having an air bridge in the patterning area at the top of the gate;
[0007] The second semiconductor workpiece is subjected to metal evaporation and photoresist removal treatment to obtain a semiconductor device, wherein three control electrodes of the semiconductor device are connected to a circuit lead-out device for measurement through an air bridge.
[0008] Optionally, obtaining a substrate, and using a silicon wafer and a positive photoresist to manufacture a first semiconductor workpiece with metal wiring on the substrate includes:
[0009] Placing the silicon wafer on the substrate by ion implantation to obtain an active area component;
[0010] Applying the positive photoresist on the active area component and then performing an evaporation process to obtain a metal wiring component; and / or
[0011] The positive photoresist of the metal wiring component is removed to obtain a first semiconductor workpiece of the metal wiring.
[0012] Optionally, the first semiconductor workpiece is manufactured by using semiconductor manufacturing technology to obtain a second semiconductor workpiece having an air bridge in the patterning area at the top of the gate, which includes:
[0013] After coating a first photoresist on the first semiconductor workpiece, alignment, development and baking are performed to obtain a first gate component in the patterning area at the bottom end of the gate;
[0014] After coating a second photoresist on the first gate component, alignment and development are performed to obtain a second gate component in the patterned area at the top of the gate;
[0015] An air bridge is provided on the top of the gate of the second gate component located in the common patterning area of the first photoresist and the second photoresist to obtain a second semiconductor workpiece.
[0016] Optionally, the thickness of the first photoresist is
[0017] Optionally, the thickness of the second photoresist is
[0018] Optionally, performing metal evaporation and photoresist removal on the second semiconductor workpiece to obtain a semiconductor device includes: performing gate metal evaporation on the second semiconductor workpiece and then removing the first photoresist and the second photoresist to obtain a semiconductor device.
[0019] Optionally, the first photoresist is a positive photoresist, and the second photoresist is a negative photoresist.
[0020] Optionally, the semiconductor manufacturing technology includes a Gate process, an l-line process or an E-beam process.
[0021] Optionally, the l-line process is an l-line process with a line width of not less than 0.25um; and / or, the Gate process is a Gate process of 0.15um; and / or, the E-beam process is an E-beam process of 0.1um.
[0022] Optionally, the substrate is made of gallium arsenide material.
[0023] An embodiment of the present application provides a semiconductor device monitoring process method, including obtaining a substrate, using a silicon wafer and a positive photoresist to manufacture on the substrate to obtain a first semiconductor workpiece with metal wiring; using semiconductor manufacturing technology to manufacture the first semiconductor workpiece to obtain a second semiconductor workpiece with an air bridge in the top opening area of the gate; performing metal evaporation and photoresist removal on the second semiconductor workpiece to obtain a semiconductor device, wherein the three control electrodes of the semiconductor device are connected to a circuit lead device for measurement through an air bridge. The semiconductor device monitoring process method can obtain a semiconductor device in which three control electrodes are connected to a circuit lead device for measurement through an air bridge, and the electrical data of each control electrode of the semiconductor device can be measured through the circuit lead device, thereby solving the problem that the existing semiconductor monitoring process method cannot measure its electrical properties after the gate is completed. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solution in an embodiment of the present application, the following briefly introduces the drawings required for use in the description of the embodiment. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can also obtain other drawings based on these drawings without creative work.
[0025] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings. In the following description, the same reference numerals represent the same parts.
[0026] Figure 1 A flowchart of a semiconductor device monitoring process method provided for one embodiment of the present application.
[0027] Figure 2 A top view of a first semiconductor workpiece in a method for monitoring a semiconductor device process provided by one embodiment of the present application.
[0028] Figure 3 A semiconductor device diagram of a semiconductor device monitoring process method provided by one embodiment of the present application.
[0029] Figure 4 A schematic diagram of a source first semiconductor workpiece in a semiconductor device monitoring process method provided by one embodiment of the present application.
[0030] Figure 5 A schematic diagram of a gate first semiconductor workpiece in a semiconductor device monitoring process method provided by one embodiment of the present application.
[0031] Figure 6 A schematic diagram of a source first gate component in a semiconductor device monitoring process method provided by one embodiment of the present application.
[0032] Figure 7 A schematic diagram of a first gate component of a gate in a semiconductor device monitoring process method provided by an embodiment of the present application.
[0033] Figure 8 A schematic diagram of a source second gate component in a semiconductor device monitoring process method provided by one embodiment of the present application.
[0034] Fig. 9 A schematic diagram of a gate and a second gate component in a semiconductor device monitoring process method provided by one embodiment of the present application.
[0035] Fig.10 A schematic diagram of a source second semiconductor workpiece in a semiconductor device monitoring process method provided by one embodiment of the present application.
[0036] Fig.11 A schematic diagram of a source second semiconductor workpiece in a semiconductor device monitoring process method provided by another embodiment of the present application.
[0037] Fig.12 A schematic diagram of a gate second semiconductor workpiece in a semiconductor device monitoring process method provided by one embodiment of the present application.
[0038] Fig.13 It is a schematic diagram of the structure of an existing semiconductor device. DETAILED DESCRIPTION
[0039] The technical scheme in one embodiment of the present application will be clearly and completely described below in conjunction with the drawings in one embodiment of the present application. Obviously, the described embodiment is only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.
[0040] Patent terms:
[0041] GaAs refers to gallium arsenide.
[0042] An embodiment of the present application provides a semiconductor device monitoring process method to solve the problem that the existing semiconductor monitoring process method cannot measure the electrical properties of the gate after the gate is completed.
[0043] Embodiment 1:
[0044] An embodiment of the present application provides a semiconductor device monitoring process method, for example, see Figure 1 , Figure 1 A flowchart of a semiconductor device monitoring process method provided by an embodiment of the present application, Figure 2A top view of a first semiconductor workpiece in a semiconductor device monitoring process method provided by an embodiment of the present application, Figure 3 A semiconductor device diagram of a semiconductor device monitoring process method provided by one embodiment of the present application.
[0045] like Figure 1 As shown, the present invention provides a semiconductor device monitoring process method, comprising the following steps:
[0046] S100. Obtain a substrate, and use a silicon wafer and a positive photoresist to produce a first semiconductor workpiece with metal wiring on the substrate;
[0047] S200. The first semiconductor workpiece is manufactured by using semiconductor manufacturing technology to obtain a second semiconductor workpiece having an air bridge in the top opening area of the gate;
[0048] S300. Perform metal evaporation and photoresist removal processing on the second semiconductor workpiece to obtain a semiconductor device, wherein three control electrodes of the semiconductor device are connected to a circuit lead-out device for measurement through an air bridge.
[0049] It is further explained that the substrate is made of gallium arsenide material. Step S100 is to coat the positive photoresist and silicon wafer on the substrate in sequence to obtain Figure 2 The first semiconductor workpiece with metal wiring structure shown in the figure. Step S200 is to use semiconductor manufacturing technology to process the first semiconductor workpiece to obtain a second semiconductor workpiece with an air bridge. Step S300 is to perform evaporation and photoresist removal on the second semiconductor workpiece in sequence to obtain Figure 3 A semiconductor device of the structure shown. In this embodiment, the circuit lead device can be selected as a pin. The semiconductor device monitoring process method can obtain a semiconductor device in which three control electrodes are connected to the circuit lead device through an air bridge, and the electrical data of each control electrode of the semiconductor device is measured through the circuit lead device.
[0050] In an embodiment of the present invention, the semiconductor manufacturing technology includes a Gate process, an l-line process or an E-beam process, etc.
[0051] It is further explained that the l-line process can be an l-line process with a line width of not less than 0.25um; and / or, the Gate process can be a Gate process with a line width of 0.15um; and / or, the E-beam process can be an E-beam process with a line width of 0.1um. In this embodiment, the semiconductor manufacturing technology is described using the l-line process as an example.
[0052] An embodiment of the present application provides a semiconductor device monitoring process method, including obtaining a substrate, using a silicon wafer and a positive photoresist to manufacture on the substrate to obtain a first semiconductor workpiece with metal wiring; using semiconductor manufacturing technology to manufacture the first semiconductor workpiece to obtain a second semiconductor workpiece with an air bridge in the top opening area of the gate; performing metal evaporation and photoresist removal on the second semiconductor workpiece to obtain a semiconductor device, and the three control electrodes of the semiconductor device are connected to the circuit lead device for measurement through the air bridge. The semiconductor device monitoring process method can obtain a semiconductor device in which three control electrodes are connected to the circuit lead device for measurement through the air bridge, and the electrical data of each control electrode of the semiconductor device can be measured through the circuit lead device, thereby solving the problem that the existing semiconductor monitoring process method cannot measure its electrical properties after the gate is completed.
[0053] Figure 4 A schematic diagram of a source first semiconductor workpiece in a semiconductor device monitoring process method provided by an embodiment of the present application, Figure 5 A schematic diagram of a gate first semiconductor workpiece in a semiconductor device monitoring process method provided by one embodiment of the present application.
[0054] In the invention embodiment of the application, a substrate is obtained, and a first semiconductor workpiece for obtaining metal wiring is prepared on the substrate using a silicon wafer and a positive photoresist, and the first semiconductor workpiece includes:
[0055] Placing a silicon wafer on a substrate by ion implantation to obtain an active area component;
[0056] After coating the active area components with positive photoresist, an evaporation process is performed to obtain metal wiring components;
[0057] The positive photoresist of the metal wiring component is removed to obtain a first semiconductor workpiece of the metal wiring.
[0058] Further explanation is that if the semiconductor device monitoring process method is performed with source electrical properties, a positive photoresist is coated on the active area component, and then aligned, IR inverted, and fully exposed to form a positive trapezoidal morphology, and then evaporated, the following is obtained. Figure 4 In this embodiment, if the semiconductor device monitoring process method is performed with source electrical properties, the positive photoresist of the metal wiring component is removed to obtain the first semiconductor workpiece of the metal wiring.
[0059] In the invention embodiment of the application, a substrate is obtained, and a first semiconductor workpiece for obtaining metal wiring is prepared on the substrate using a silicon wafer and a positive photoresist, and the first semiconductor workpiece includes:
[0060] Placing a silicon wafer on a substrate by ion implantation to obtain an active area component;
[0061] After coating positive photoresist on the active area components, an evaporation process is performed to obtain metal wiring components.
[0062] Further explanation is that if the semiconductor device monitoring process method is performed by gate electrical properties, a positive photoresist is coated on the active area component, and then aligned, IR inverted, and fully exposed to form a positive trapezoidal morphology, and then evaporated, the following is obtained. Figure 5 In this embodiment, if the semiconductor device monitoring process method is performed using gate electrical properties, the metal wiring component is directly used as the first semiconductor workpiece.
[0063] Figure 6 A schematic diagram of a source first gate component in a semiconductor device monitoring process method provided by an embodiment of the present application, Figure 7 A schematic diagram of a first gate component of a gate in a semiconductor device monitoring process method provided by an embodiment of the present application, Figure 8 A schematic diagram of a source and second gate component in a semiconductor device monitoring process method provided by an embodiment of the present application, Fig. 9 A schematic diagram of a gate and a second gate component in a semiconductor device monitoring process method provided by an embodiment of the present application, Fig.10 A schematic diagram of a second semiconductor workpiece at a source in a semiconductor device monitoring process method provided by an embodiment of the present application, Fig.11 A schematic diagram of a second semiconductor workpiece at a source in a semiconductor device monitoring process method provided by another embodiment of the present application, Fig.12 A schematic diagram of a gate second semiconductor workpiece in a semiconductor device monitoring process method provided by one embodiment of the present application.
[0064] If the semiconductor device monitoring process method is performed based on source electrical properties, in the embodiment of the invention applied, the first semiconductor workpiece is manufactured using semiconductor manufacturing technology to obtain a second semiconductor workpiece having an air bridge in the top patterning area of the gate, including:
[0065] After coating a first photoresist on a first semiconductor workpiece, alignment, development and baking are performed to obtain a first gate component in a patterned area at the bottom end of the gate;
[0066] After coating a second photoresist on the first gate component, alignment and development are performed to obtain a second gate component in the patterned area at the top of the gate;
[0067] An air bridge is provided on the top of the gate of the second gate component located in the common patterning area of the first photoresist and the second photoresist to obtain a second semiconductor workpiece.
[0068] It is further explained that the semiconductor device monitoring process method is described by taking the l-line process as an example, and coating a first semiconductor workpiece with a thickness of The first photoresist is then aligned, developed, and baked to obtain Figure 6 The first gate component of the gate bottom opening area of the structure shown in the figure. The top process of the gate process is performed on the first gate component, and a coating thickness of After the second photoresist is applied, alignment and development are performed to obtain the following Figure 8 The second gate component of the gate top patterning area of the structure shown in the figure. On the second gate component, an air bridge is arranged at the gate top of the common patterning area of the first photoresist and the second photoresist, so as to obtain the following Fig.10 and Fig.11 A second semiconductor workpiece of the structure shown in FIG. 1 . In this embodiment, the first photoresist may be a positive photoresist, and the second photoresist may be a negative photoresist.
[0069] If the semiconductor device monitoring process method is performed by gate electrical properties, in the invention embodiment of the application, the first semiconductor workpiece is manufactured by using semiconductor manufacturing technology to obtain a second semiconductor workpiece having an air bridge in the top patterning area of the gate, including:
[0070] After coating a first photoresist on a first semiconductor workpiece, alignment, development and baking are performed to obtain a first gate component in a patterned area at the bottom end of the gate;
[0071] After coating a second photoresist on the first gate component, alignment and development are performed to obtain a second gate component in the patterned area at the top of the gate;
[0072] An air bridge is provided on the top of the gate of the second gate component located in the common patterning area of the first photoresist and the second photoresist to obtain a second semiconductor workpiece.
[0073] It is further explained that the semiconductor device monitoring process method is described by taking the l-line process as an example, and coating a first semiconductor workpiece with a thickness of The first photoresist is then aligned, developed, and baked to obtain Figure 7 The first gate component of the gate bottom opening area of the structure shown in the figure. The top process of the gate process is performed on the first gate component, and a coating thickness of After the second photoresist is applied, alignment and development are performed to obtain the following Fig. 9 The second gate component of the gate top patterning area of the structure shown in the figure. On the second gate component, an air bridge is arranged at the gate top of the common patterning area of the first photoresist and the second photoresist, so as to obtain the following Fig.12 A second semiconductor workpiece of the structure shown in FIG. 1 . In this embodiment, the first photoresist may be a positive photoresist, and the second photoresist may be a negative photoresist.
[0074] In an embodiment of the invention of the application, metal evaporation and photoresist removal are performed on the second semiconductor workpiece to obtain a semiconductor device, including: gate metal evaporation is performed on the second semiconductor workpiece and then the first photoresist and the second photoresist are removed to obtain a semiconductor device.
[0075] It is further explained that after the gate metal is evaporated on the second semiconductor workpiece, the first photoresist and the second photoresist are removed to obtain Figure 3 A semiconductor device having the structure shown.
[0076] In the invention embodiment of the application, if the semiconductor device monitoring process method is performed using source electrical properties, the resulting semiconductor device completes source terminal connection in the form of an air bridge, and the electrical data of all monitored roots can be measured after the gate process of the semiconductor device is completed. This is completed based on the existing gate process of the semiconductor device, without adding new masks and steps, thereby reducing the process production cost.
[0077] In the invention embodiment of the application, if the semiconductor device monitoring process method is performed using gate electrical properties, the resulting semiconductor device uses gate metal to form an air bridge to connect the gate terminal, and the three control electrodes (including gate, source and drain) of the semiconductor device are all connected to the circuit lead-out device for measurement after the gate process is completed, thereby achieving electrical property measurement at the current station.
[0078] It is further explained that compared with the method for monitoring semiconductor devices by source electrical properties, the method for monitoring semiconductor devices by gate electrical properties does not require additional metal as a bridge pier, but uses the existing gate head as a bridge pier; reducing non-baseline graphics helps to reduce the change of photoresist thickness in the gate patterning area and reduce the impact on the gate line width; especially for gates with smaller line widths (0.15um in E-beam process), it is more sensitive to photoresist thickness. In particular, in the process of operating 0.15um (E-beam operation) gate line width, the bottom graphics of the gate are less, and electrical monitoring is achieved in a shorter tape-out time. The method for monitoring semiconductor devices by gate electrical properties uses the gate head area as a bridge pier, the bridge pier is the original baseline graphic, and the short distance between the bridge piers makes the air bridge more stable, thereby making the monitored semiconductor device more stable; it is conducive to the monitored semiconductor device to continue to serve the monitoring purpose in the subsequent operation process.
[0079] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0080] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features.
[0081] The semiconductor device monitoring process method provided by an embodiment of the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A semiconductor device monitoring process method, characterized in that: The following steps are involved: Obtain a substrate, and use a silicon wafer and a positive photoresist to manufacture a first semiconductor workpiece with metal wiring on the substrate; The first semiconductor workpiece is manufactured by using semiconductor manufacturing technology to obtain a second semiconductor workpiece having an air bridge in the patterning area at the top of the gate; The second semiconductor workpiece is subjected to metal evaporation and photoresist removal treatment to obtain a semiconductor device, wherein three control electrodes of the semiconductor device are connected to a circuit lead-out device for measurement through an air bridge.
2. The semiconductor device monitoring process method according to claim 1, characterized in that: A substrate is obtained, and a first semiconductor workpiece with metal wiring is manufactured on the substrate using a silicon wafer and a positive photoresist, comprising: Placing the silicon wafer on the substrate by ion implantation to obtain an active area component; Applying the positive photoresist on the active area component and then performing an evaporation process to obtain a metal wiring component; and / or The positive photoresist of the metal wiring component is removed to obtain a first semiconductor workpiece of the metal wiring.
3. The semiconductor device monitoring process method according to claim 1, characterized in that: The first semiconductor workpiece is manufactured by using semiconductor manufacturing technology to obtain a second semiconductor workpiece having an air bridge in the top opening area of the gate, comprising: After coating a first photoresist on the first semiconductor workpiece, alignment, development and baking are performed to obtain a first gate component in the patterning area at the bottom end of the gate; After coating a second photoresist on the first gate component, alignment and development are performed to obtain a second gate component in the patterned area at the top of the gate; An air bridge is provided on the top of the gate of the second gate component located in the common patterning area of the first photoresist and the second photoresist to obtain a second semiconductor workpiece.
4. The semiconductor device monitoring process method according to claim 3, characterized in that: The thickness of the first photoresist is 5. The semiconductor device monitoring process method according to claim 3, characterized in that: The thickness of the second photoresist is 6. The semiconductor device monitoring process method according to claim 3, characterized in that: Performing metal evaporation and photoresist removal on the second semiconductor workpiece to obtain a semiconductor device includes: performing gate metal evaporation on the second semiconductor workpiece and then removing the first photoresist and the second photoresist to obtain a semiconductor device.
7. The semiconductor device monitoring process method according to claim 3, characterized in that: The first photoresist is a positive photoresist, and the second photoresist is a negative photoresist.
8. The semiconductor device monitoring process method according to any one of claims 1 to 7, characterized in that: The semiconductor manufacturing technology includes Gate process, l-line process or E-beam process.
9. The semiconductor device monitoring process method according to claim 8, characterized in that: The l-line process is an l-line process with a line width of not less than 0.25um; and / or, the Gate process is a Gate process of 0.15um; and / or, the E-beam process is an E-beam process of 0.1um.
10. The semiconductor device monitoring process method according to any one of claims 1 to 7, characterized in that: The substrate is made of gallium arsenide material.