Method for manufacturing semiconductor structure
By forming an active area and a filling groove in the array area of the semiconductor structure, and forming an isolation layer and a support layer on its sidewalls and top surface, the bump defects of the isolation layer are eliminated, the problem of defects in the isolation material on the active area is solved, and the yield and word line quality of the semiconductor structure are improved.
Patent Information
- Application Number
- CN202310976041.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-02
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2043-08-02
AI Technical Summary
In the prior art, during the fabrication of the isolation structure of a semiconductor structure, defects are easily formed in the isolation material on the active region, which affects the quality of the subsequently formed word line structure and results in a low yield of the semiconductor structure.
An active area and a filling groove surrounding the active area are formed in the array area, and an isolation layer and a support layer are formed on the side walls and top surfaces thereof. After removing the isolation layer on the top surface of the active area, the isolation layer on the side walls and bottom walls is retained, and then a flat second isolation layer is formed on the active area and the top surface of the support layer to eliminate the convex point defects.
The quality of word lines is improved, word line interconnections are reduced, the yield of semiconductor structures is improved, and the stability and performance of subsequent processes are ensured.
Smart Images
Figure CN119447021B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art
[0002] With the advancement of semiconductor technology, the variety of semiconductor structures has increased, and their applications are becoming increasingly widespread. A semiconductor structure includes a substrate within which multiple active areas (AAs) are formed, spaced apart from each other. To isolate the AAs, an isolation structure is also provided within the substrate. The isolation material forming the isolation structure fills the gaps between adjacent AAs and covers the top surfaces of the AAs. However, during the fabrication of the isolation structure, the isolation material formed on the AAs is prone to defects, which can affect the quality of subsequently formed structures such as word lines (WLs), resulting in a low yield rate for the semiconductor structure. Summary of the Invention
[0003] In view of the above problems, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure to reduce defects in the film layer on the first active region and improve the yield of the semiconductor structure.
[0004] According to some embodiments, the present disclosure provides a method for fabricating a semiconductor structure, comprising:
[0005] Providing a substrate, the substrate comprising an array region and a peripheral region;
[0006] forming a plurality of first active regions spaced apart from each other in the array region, and a first filling trench surrounding each of the first active regions;
[0007] forming a first isolation layer and a first supporting layer, wherein the first isolation layer covers the sidewalls and bottom wall of the first filling groove and the top surface of the first active area, and the first supporting layer fills the remaining first filling groove;
[0008] removing the first isolation layer on the top surface of the first active region and retaining the first isolation layer on the sidewalls and bottom wall of the first filling trench to expose the top surface of the first active region;
[0009] A second isolation layer is formed, where the second isolation layer covers a top surface of the first active region, a top surface of the remaining first isolation layer, and a top surface of the first supporting layer.
[0010] In some possible embodiments, before removing the first isolation layer located on the first active region, the method further includes:
[0011] forming a third isolation layer, wherein the third isolation layer covers a top surface of the first isolation layer opposite to the array region and a top surface of the first supporting layer;
[0012] Removing the first isolation layer located on the first active region includes:
[0013] The third isolation layer opposite to the array region and the first isolation layer on the first active region are removed by wet cleaning with a hydrofluoric acid solution to expose a top surface of the first active region and a top surface of the first supporting layer.
[0014] In some possible embodiments, forming the second isolation layer includes:
[0015] The second isolation layer is deposited on the first isolation layer and the first support layer opposite to the first active area and the array area, and the thickness of the second isolation layer is greater than or equal to the sum of the thicknesses of the first isolation layer and the third isolation layer.
[0016] In some possible embodiments, forming a plurality of first active regions spaced apart in the array region and a first filling trench surrounding each of the first active regions includes:
[0017] The first active area and the first filling groove are formed in the array area; wherein the extension direction of each first active area is the same, and there is a first gap or a second gap between adjacent first active areas, the size of the first gap in the first direction is smaller than the size of the second gap in the first direction, and the first direction is perpendicular to the extension direction of the first active area.
[0018] In some possible embodiments, forming the first isolation layer and the first supporting layer includes:
[0019] forming a first isolation layer on the sidewalls and bottom wall of the first filling groove and the first active area, wherein the first isolation layer fills the first gap, and the first isolation layer located in the second gap encloses a filling hole;
[0020] depositing an initial first supporting layer, wherein the initial first supporting layer completely fills the filling hole and covers a top surface of the first isolation layer;
[0021] A portion of the initial first supporting layer is removed, and the remaining initial first supporting layer forms the first supporting layer, wherein a top surface of the first supporting layer is aligned with a top surface of the first active region.
[0022] In some possible embodiments, a plurality of first active regions spaced apart from each other are formed in the array region, and a first filling trench surrounding each of the first active regions is formed, further comprising:
[0023] forming a plurality of second active regions spaced apart from each other in the peripheral region, and a second filling trench surrounding each of the second active regions;
[0024] Forming a first isolation layer and a first support layer, comprising:
[0025] forming the first isolation layer on the sidewalls and bottom wall of the first filling trench, the top surface of the first active region, the sidewalls and bottom wall of the second filling trench, and the top surface of the second active region, and the first isolation layer in the second filling trench enclosing a third filling trench;
[0026] Depositing an initial first supporting layer on the first isolation layer, wherein the initial first supporting layer opposite to the array region fills the remaining first filling groove and covers the top surface of the first isolation layer opposite to the array region; and the initial first supporting layer opposite to the peripheral region covers the sidewalls and bottom wall of the third filling groove and the top surface of the first isolation layer opposite to the peripheral region;
[0027] The initial first supporting layer is etched back to remove the initial first supporting layer on the first isolation layer opposite to the array region and the initial first supporting layer in the peripheral region, and the remaining initial first supporting layer forms the first supporting layer.
[0028] In some possible embodiments, before removing the first isolation layer located on the first active region, the method further includes:
[0029] forming a third isolation layer, wherein the third isolation layer covers a top surface of the first isolation layer and a top surface of the first support layer opposite to the array region, and covers the first isolation layer opposite to the peripheral region, and the third isolation layer located in the third filling trench encloses a fourth filling trench;
[0030] A second supporting layer and a filling layer are formed, wherein the second supporting layer covers the sidewalls and the bottom wall of the fourth filling groove, and the filling layer fills the remaining portion of the fourth filling groove.
[0031] In some possible embodiments, forming the second supporting layer and the filling layer includes:
[0032] Depositing the second supporting layer, the second supporting layer covering the top surface of the third isolation layer opposite to the array region and the top surface of the third isolation layer opposite to the peripheral region, and covering the sidewalls and bottom wall of the fourth filling trench, wherein the second supporting layer located in the fourth filling trench encloses a fifth filling trench;
[0033] forming the filling layer, wherein the filling layer covers the top surface of the second supporting layer opposite to the array region and the peripheral region and completely fills the fifth filling groove;
[0034] performing a planarization process on the filling layer, removing the filling layer on the second supporting layer opposite to the array region and the peripheral region, and exposing the second supporting layer;
[0035] The second supporting layer opposite to the array region and the second supporting layer on the third isolation layer opposite to the peripheral region are removed by etching, and the remaining second supporting layer, the filling layer and the third isolation layer are aligned.
[0036] In some possible embodiments, after forming the second supporting layer and the filling layer, the method further includes:
[0037] Each of the first active regions is doped to form a first source region and a first drain region.
[0038] In some possible embodiments, removing the first isolation layer on the first active region includes:
[0039] Using hydrofluoric acid wet cleaning to remove the third isolation layer opposite to the array region, the first isolation layer on the first active region, the third isolation layer opposite to the peripheral region, and the first isolation layer, the second supporting layer, and the filling layer on the second active region;
[0040] Forming the second isolation layer includes:
[0041] The second isolation layer is deposited, and the second isolation layer covers the top surface of the first active area, the top surfaces of the first isolation layer and the first support layer opposite to the array area, the top surface of the second active area, the top surface of the filling layer, and the top surfaces of the first isolation layer, the second support layer and the third isolation layer opposite to the peripheral area.
[0042] The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:
[0043] In the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, a first active area and a first filling groove surrounding each first active area are formed in an array area, and a first isolation layer is formed on the top surface of the first active area, the sidewalls and bottom wall of the first filling groove, and a first support layer is formed in the remaining first filling groove. The first isolation layer on the top surface of the first active area is then removed, and the first isolation layer located on the sidewalls and bottom wall of the first filling groove is retained to eliminate the convex defects of the first isolation layer. After a second isolation layer is formed on the top surface of the first active area, the top surface of the remaining first isolation layer, and the top surface of the first support layer, the top surface of the second isolation layer is relatively flat and has fewer defects, thereby improving the quality of the subsequently formed word lines, reducing word line interconnections, and improving the yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 A schematic diagram of defects in the first isolation layer in the related art;
[0045] Figure 2 Schematic diagram of defects in a mask layer in the related art;
[0046] Figure 3 Schematic diagram of defects in the first active region in the related art;
[0047] Figure 4 is a flow chart of a method for manufacturing a semiconductor structure in one embodiment of the present disclosure;
[0048] Figure 5 Schematic diagram of the structure of a substrate in one embodiment of the present disclosure;
[0049] Figure 6 A diagram of a manufacturing process of a semiconductor structure in one embodiment of the present disclosure;
[0050] Figure 7 is another manufacturing process diagram of a semiconductor structure in one embodiment of the present disclosure;
[0051] Figure 8 is a top view of the first active region in one embodiment of the present disclosure;
[0052] Figure 9 is a schematic diagram of a filling hole in one embodiment of the present disclosure;
[0053] Figure 10 is a schematic diagram of an initial first isolation layer in an embodiment of the present disclosure;
[0054] Figure 11 Schematic diagram of the first isolation layer and the first support layer in one embodiment of the present disclosure
[0055] Figure 12 is a schematic diagram after forming a first active region in one embodiment of the present disclosure;
[0056] Figure 13 is a schematic diagram after forming the second active region in one embodiment of the present disclosure;
[0057] Figure 14 This is a schematic diagram of a first isolation layer formed opposite to the array region in one embodiment of the present disclosure;
[0058] Figure 15 This is a schematic diagram of a first isolation layer formed opposite to the peripheral region in one embodiment of the present disclosure;
[0059] Figure 16 This is a schematic diagram of an embodiment of the present disclosure after forming an initial first supporting layer opposite to the array region;
[0060] Figure 17 A schematic diagram of an embodiment of the present disclosure after forming an initial first supporting layer opposite to the peripheral region;
[0061] Figure 18This is a schematic diagram of a first supporting layer formed opposite to the array region in one embodiment of the present disclosure;
[0062] Figure 19 This is a schematic diagram of an embodiment of the present disclosure after the first supporting layer opposite to the peripheral area is removed;
[0063] Figure 20 This is a schematic diagram of a third isolation layer formed opposite to the array region in one embodiment of the present disclosure;
[0064] Figure 21 This is a schematic diagram of an embodiment of the present disclosure after a third isolation layer is formed opposite to the peripheral region;
[0065] Figure 22 This is a schematic diagram of a second supporting layer formed opposite to the array region in one embodiment of the present disclosure;
[0066] Figure 23 This is a schematic diagram of a second supporting layer formed opposite to the peripheral region in one embodiment of the present disclosure;
[0067] Figure 24 This is a schematic diagram of a filling layer formed opposite to the array region in one embodiment of the present disclosure;
[0068] Figure 25 This is a schematic diagram of a filling layer formed relative to the peripheral area in one embodiment of the present disclosure;
[0069] Figure 26 This is a schematic diagram of an embodiment of the present disclosure after removing the filling layer opposite to the array area;
[0070] Figure 27 This is a schematic diagram of an embodiment of the present disclosure after removing the filling layer corresponding to the peripheral area;
[0071] Figure 28 This is a schematic diagram of an embodiment of the present disclosure after the second supporting layer opposite to the array area is removed;
[0072] Figure 29 This is a schematic diagram of an embodiment of the present disclosure after the second supporting layer opposite to the peripheral area is removed;
[0073] Figure 30 This is a schematic diagram showing the removal of the third isolation layer opposite to the array region in one embodiment of the present disclosure;
[0074] Figure 31 This is a schematic diagram showing the removal of the third isolation layer opposite to the peripheral region in one embodiment of the present disclosure;
[0075] Figure 32 This is a schematic diagram of a second isolation layer formed opposite to the array region in one embodiment of the present disclosure;
[0076] Figure 33FIG. 1 is a schematic diagram of a second isolation layer formed opposite to the peripheral region in one embodiment of the present disclosure.
[0077] Description of reference numerals:
[0078] 10-substrate; 11-first active region;
[0079] 12-first filling groove; 13-second active area;
[0080] 14-second filling slot; 15-third filling slot;
[0081] 16- fourth filling slot; 17- fifth filling slot;
[0082] 18-first gap; 19-second gap;
[0083] 21-first isolation layer; 22-second isolation layer;
[0084] 23-third isolation layer; 24-filling hole;
[0085] 31-initial first supporting layer; 32-first supporting layer;
[0086] 33-second supporting layer; 34-filling layer;
[0087] 40-Mask layer. DETAILED DESCRIPTION
[0088] The related art has the problem of low yield of semiconductor structure. The inventors have found that: Figures 1 to 3 During the semiconductor structure fabrication process, a first isolation layer 21 is first formed on the first active area 11. A mask layer 40 is then formed on the first isolation layer 21 and the first active area 11, and the first isolation layer 21 and the first active area 11 are etched using the mask layer 40 as a mask to form wordline trenches. However, during the processes preceding and following the formation of the first isolation layer 21, the first isolation layer 21 is susceptible to bump defects. The mask layer 40 is prone to breakpoints, which can lead to pits and broken lines when etching the first active area 11. After the wordline trenches are formed, the wordline trenches are easily interconnected, causing wordline interconnections and reducing the yield of the semiconductor structure.
[0089] The disclosed embodiment provides a method for manufacturing a semiconductor structure, wherein a first active area and a first filling groove surrounding each first active area are formed in an array area, and a first isolation layer is formed on the top surface of the first active area, the sidewalls and bottom wall of the first filling groove, and a first support layer is formed in the remaining first filling groove. The first isolation layer on the top surface of the first active area is then removed, and the first isolation layer located on the sidewalls and bottom wall of the first filling groove is retained to eliminate the bump defects of the first isolation layer. A second isolation layer is formed on the top surface of the first active area, the top surface of the remaining first isolation layer, and the top surface of the first support layer. The top surface of the second isolation layer is relatively flat and has fewer defects, thereby improving the quality of the subsequently formed word lines, reducing word line interconnections, and improving the yield of the semiconductor structure.
[0090] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.
[0091] See Figure 4 , an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which includes the following steps:
[0092] Step S100: providing a substrate, the substrate including an array region and a peripheral region.
[0093] See Figure 5 The substrate 10 can be a semiconductor substrate such as a silicon substrate, a germanium substrate, a gallium nitride substrate, or a silicon-on-insulator substrate (SOI). The substrate 10 includes an array region and a peripheral region. The array region is adjacent to the peripheral region. The array region is used to form a memory cell, and the peripheral region is used to form a peripheral circuit. Figure 5 As shown in A, the peripheral area is as follows Figure 5 As shown in B.
[0094] Step S200 : forming a plurality of first active regions spaced apart from each other in the array region, and forming a first filling trench surrounding each of the first active regions.
[0095] See Figure 6 , forming a plurality of first active regions 11 and first filling grooves 12 in the array region. The plurality of first active regions 11 are arranged at intervals, and the plurality of first active regions 11 can be arranged in an array. The first filling grooves 12 surround the first active regions 11 to isolate the first active regions 11. Figure 6 As shown, a plurality of first active regions 11 independent of each other are formed in the first filling trench 12 .
[0096] Step S300 : forming a first isolation layer and a first supporting layer, wherein the first isolation layer covers the sidewalls and bottom wall of the first filling trench and the top surface of the first active area, and the first supporting layer fills the remaining first filling trench.
[0097] Continue reading Figure 6 A first isolation layer 21 is formed on the sidewalls and bottom wall of the first filling trench 12 and the top surface of the first active area 11, and a first supporting layer 32 is formed on the first isolation layer 21. The first isolation layer 21 partially fills the first filling trench 12, and the first supporting layer 32 fills the remaining first filling trench 12. The first isolation layer 21 can be made of an oxide, such as silicon oxide; the first supporting layer 32 can be made of a nitride, such as silicon nitride.
[0098] The first isolation layer 21 and the first supporting layer 32 can both be formed by deposition, and the first isolation layer 21 covers the sidewalls and bottom wall of the first filling trench 12 and the top surface of the first active region 11. The top surface of the first isolation layer 21 can be higher than the top surface of the first supporting layer 32. For example, the top surface of the first supporting layer 32 can be flush with the top surface of the first active region 11.
[0099] Step S400 : removing the first isolation layer on the top surface of the first active region and retaining the first isolation layer on the sidewalls and bottom wall of the first filling trench to expose the top surface of the first active region.
[0100] Continue reading Figure 6 The first isolation layer 21 on the top surface of the first active area 11 is removed to expose the top surface of the first active area 11, for example, by wet cleaning with a hydrofluoric acid (DHF) solution. By removing the first isolation layer 21 on the top surface of the first active area 11, bump defects in the first isolation layer 21 can be eliminated, thereby preventing interconnection problems during the subsequent formation of word lines, especially buried word lines (BWLs).
[0101] like Figure 6 As shown, the first isolation layer 21 located on the sidewalls and bottom wall of the first filling trench 12 is retained, that is, the first isolation layer 21 in contact with the first supporting layer 32 is retained. The top surface of the remaining first isolation layer 21, the top surface of the first active region 11, and the top surface of the first supporting layer 32 are flush, so that the top surfaces of the three form a relatively flat surface.
[0102] Step S500 : forming a second isolation layer, where the second isolation layer covers a top surface of the first active region, a top surface of the remaining first isolation layer, and a top surface of the first supporting layer.
[0103] Continue reading Figure 6A second isolation layer 22 is formed (e.g., deposited) on the top surface of the first active area 11, the top surface of the remaining first isolation layer 21, and the top surface of the first support layer 32. The top surface of the formed second isolation layer 22 is relatively flat and has fewer defects, thereby improving the quality of subsequently formed word lines, reducing word line interconnections, and improving the yield of the semiconductor structure.
[0104] In some examples, the second isolation layer 22 is thicker than the first isolation layer 21 to compensate for the removal of the first isolation layer 21. This arrangement creates a thicker second isolation layer 22 on the first active area 11, preventing wordline switching failures due to hot electron effects. This improves gate control capabilities and ensures the performance of the semiconductor structure. The second isolation layer 22 can be made of the same material as the first isolation layer 21.
[0105] In summary, in the method for manufacturing the semiconductor structure in the embodiment of the present disclosure, a first active area 11 and a first filling groove 12 surrounding each first active area 11 are formed in the array area, and a first isolation layer 21 is formed on the top surface of the first active area 11, the sidewalls and bottom walls of the first filling groove 12, and a first support layer 32 is formed in the remaining first filling groove 12. The first isolation layer 21 on the top surface of the first active area 11 is then removed, and the first isolation layer 21 located on the sidewalls and bottom walls of the first filling groove 12 is retained to eliminate the convex defects of the first isolation layer 21. A second isolation layer 22 is formed on the top surface of the first active area 11, the top surface of the remaining first isolation layer 21, and the top surface of the first support layer 32. The top surface of the second isolation layer 22 is relatively flat and has fewer defects, thereby improving the quality of the subsequently formed word lines, reducing word line interconnections, and improving the yield of the semiconductor structure.
[0106] For some possible examples, see Figure 7 Before removing the first isolation layer 21 located on the first active area 11 (step S400), the method further includes: forming a third isolation layer 23, the third isolation layer 23 covering the top surface of the first isolation layer 21 opposite to the array area and the top surface of the first support layer 32.
[0107] Accordingly, the first isolation layer 21 located on the first active area 11 is removed (step S400), including: using a hydrofluoric acid solution to wet clean and remove the third isolation layer 23 opposite to the array area and the first isolation layer 21 on the first active area 11 to expose the top surface of the first active area 11 and the top surface of the first support layer 32.
[0108] See Figure 7A third isolation layer 23 is formed on the first isolation layer 21 and the first support layer 32 corresponding to the array region. The third isolation layer 23 covers the top surfaces of the first isolation layer 21 and the first support layer 32. The third isolation layer 23 is provided. The first active region 11 has a stacked structure formed by the first isolation layer 21 and the third isolation layer 23. The thickness is relatively large to ensure the performance of the first active region 11 during subsequent manufacturing processes.
[0109] Continue reading Figure 7 , using a hydrofluoric acid solution, the third isolation layer 23 opposite to the array area and the first isolation layer 21 on the first active area 11 are etched away, that is, the first isolation layer 21 and the third isolation layer 23 on the first active area 11 and the third isolation layer 23 on the first supporting layer 32 are wet-etched away to expose the top surface of the first active area 11 and the top surface of the first supporting layer 32.
[0110] Based on the above example, a second isolation layer 22 is formed (step S500), including: depositing a second isolation layer 22 on the first active area 11, the first isolation layer 21 opposite to the array area, and the first support layer 32, wherein the thickness of the second isolation layer 22 is greater than or equal to the sum of the thicknesses of the first isolation layer 21 and the third isolation layer 23.
[0111] like Figure 7 As shown, the second isolation layer 22 covers the top surface of the first active area 11, the top surface of the first isolation layer 21 opposite the array area, and the top surface of the first support layer 32 opposite the array area. The thickness of the second isolation layer 22 is greater than or equal to the sum of the thicknesses of the first isolation layer 21 and the third isolation layer 23 to ensure that the gate control capability of the array area is at least maintained or even improved after the formation of the second isolation layer 22.
[0112] The first, second, and third isolation layers 21, 22, and 23 can be made of the same material, for example, oxide. This facilitates cleaning and removal of the third isolation layer 23 and a portion of the first isolation layer 21. Furthermore, the insulation performance of the second isolation layer 22 is consistent with that of the third and first isolation layers 23, ensuring their insulation effectiveness.
[0113] For some possible examples, see Figure 8 , forming a plurality of spaced-apart first active areas 11 in the array area, and first filling trenches 12 surrounding each first active area 11 (step S200), including: forming the first active areas 11 and the first filling trenches 12 in the array area, wherein the first active areas 11 have the same extension direction, and there is a first gap 18 or a second gap 19 between adjacent first active areas 11, wherein the size of the first gap 18 in the first direction is smaller than the size of the second gap 19 in the first direction, and the first direction is perpendicular to the extension direction of the first active areas 11.
[0114] See Figure 8 , the extension directions of the plurality of first active regions 11 are the same, for example, all along the second direction ( Figure 8 The extension direction of the first active region 11 is consistent with the extension direction of the subsequently formed bit line ( Figure 8 The Y direction shown in FIG2 intersects with the extension direction of the word line formed subsequently ( Figure 8 The plurality of first active areas 11 are arranged in an array, with the column direction being the direction in which the bit lines extend, i.e., a bit line passes through a column of first active areas 11 and the first active areas 11 of two adjacent columns; the row direction is the direction in which the first active areas 11 extend.
[0115] like Figure 8 As shown, there is a first gap 18 or a second gap 19 between adjacent first active regions 11. The first gap 18 is as shown in FIG. Figure 8 The area enclosed by the middle dotted line, the second gap 19 is as follows Figure 8 In the area enclosed by the middle dot, the first gap 18 is connected to the second gap 19. The size of the first gap 18 in the first direction is smaller than the size of the second gap 19 in the first direction, that is, along the first direction, the size of the first gap 18 is smaller than the size of the second gap 19. Figure 8 The N direction shown in FIG. 1 is perpendicular to the extension direction of the first active region 11 .
[0116] It is understood that the first gap 18 is as follows Figure 6 and Figure 7 As shown at K in the middle, the second gap 19 is as shown in FIG. Figure 6 and Figure 7 As shown at L in the middle. Since the size of the first gap 18 along the first direction is smaller than the size of the second gap 19 along the first direction, the exposed area in the second gap 19 is larger, and during the etching process, the depth at the first gap 18 is smaller than the depth at the second gap 19.
[0117] In some possible implementations, forming the first active area 11 and the first filling groove 12 in the array area includes: etching the array area to form a plurality of initial active areas spaced apart, and initial filling grooves isolating the initial active areas; forming a compensation layer conformally covering the sidewalls and bottom walls of the initial filling grooves, and the top surface of the initial active areas, the remaining initial filling grooves forming the first filling grooves 12, and the initial active areas and the compensation layer forming the first active area 11.
[0118] The compensation layer does not completely fill the initial filling groove, and the shape of the formed first filling groove 12 matches the shape of the initial filling groove. The compensation layer can avoid consumption of the initial active area during the subsequent formation of the first isolation layer 21, thereby ensuring the critical dimensions of the first active area 11. The compensation layer is made of the same material as the array area—for example, the array area is made of silicon, while the compensation layer is made of polycrystalline silicon. This ensures that the first active area 11 is a single structure and avoids delamination.
[0119] For some possible examples, see Figures 6 to 10 , forming a first isolation layer 21 and a first support layer 32 (step S300), including:
[0120] Step S301 : forming a first isolation layer 21 on the sidewalls and bottom wall of the first filling trench 12 and the first active area 11 . The first isolation layer 21 fills the first gap 18 , and the first isolation layer 21 in the second gap 19 encloses a filling hole 24 .
[0121] See Figure 9 The first isolation layer 21 covers the sidewalls and bottom wall of the first filling trench 12, as well as the top surface of the first active area 11. The first isolation layer 21 fills the first gap 18 but does not fill the second gap 19. The first isolation layer 21 within the second gap 19 encloses a plurality of filling holes 24. The plurality of filling holes 24 are spaced apart and separated by the first isolation layer 21. The thickness of the first isolation layer 21 is greater than half the dimension of the first gap 18 along the first direction and less than half the dimension of the second gap 19 along the first direction.
[0122] The first isolation layer 21 can be formed by a deposition process, for example, the first isolation layer 21 is formed in sequence by furnace-tube atmospheric pressure chemical vapor deposition (APCVD), inductively coupled plasma chemical vapor deposition (ICPCVD), and furnace-tube atmospheric pressure chemical vapor deposition.
[0123] Step S302 : depositing an initial first supporting layer 31 . The initial first supporting layer 31 completely fills the filling hole 24 and covers the top surface of the first isolation layer 21 .
[0124] See Figure 9 and Figure 10 An initial first supporting layer 31 is deposited in the filling hole 24 and on the top surface of the first isolation layer 21. The initial first supporting layer 31 fills the filling hole 24. The first isolation layer 21 fills the first gap 18. The initial first supporting layer 31 and the first isolation layer 21 fill the second gap 19.
[0125] Step S303 : removing a portion of the initial first supporting layer 31 , and forming the remaining initial first supporting layer 31 into a first supporting layer 32 , wherein the top surface of the first supporting layer 32 is aligned with the top surface of the first active region 11 .
[0126] See Figure 10 and Figure 11The initial first supporting layer 31 within the second gap 19 is retained, and the remaining initial first supporting layer 31 is removed. The remaining initial first supporting layer 31 forms a first supporting layer 32. The top surface of the first supporting layer 32 is aligned with the top surface of the first active area 11 and is lower than the top surface of the first isolation layer 21. The portion between adjacent first active areas 11 forms a stack of the first isolation layer 21, the first supporting layer 32, and the first isolation layer 21, thereby improving the isolation performance between the first active areas 11.
[0127] For some possible examples, see Figure 12 and Figure 13 The process further includes forming a plurality of spaced-apart first active regions 11 in the array region and first filling trenches 12 surrounding each first active region 11 (step S200), and forming a plurality of spaced-apart second active regions 13 in the peripheral region and second filling trenches 14 surrounding each second active region 13. The plurality of first active regions 11, the plurality of second active regions 13, the first filling trenches 12, and the second filling trenches 14 can be formed simultaneously to reduce the number of fabrication steps, for example, by etching the array region and the peripheral region simultaneously.
[0128] Accordingly, see Figures 14 to 19 , forming a first isolation layer 21 and a first support layer 32 (step S300), including:
[0129] Step S301 ′: forming a first isolation layer 21 on the sidewalls and bottom wall of the first filling trench 12 , the top surface of the first active area 11 , the sidewalls and bottom wall of the second filling trench 14 , and the top surface of the second active area 13 . The first isolation layer 21 in the second filling trench 14 encloses a third filling trench 15 .
[0130] See Figure 14 and Figure 15 A first isolation layer 21 is deposited. The first isolation layer 21 covers the sidewalls and bottom wall of the first filling trench 12, the top surface of the first active area 11, the sidewalls and bottom wall of the second filling trench 14, and the top surface of the second active area 13. The first isolation layer 21 does not completely fill the first filling trench 12 or the second filling trench 14. For example, the first isolation layer 21 in the second filling trench 14 encloses a third filling trench 15.
[0131] Step S302': depositing an initial first supporting layer 31 on the first isolation layer 21. The initial first supporting layer 31 opposite the array region fills the remaining first filling grooves 12 and covers the top surface of the first isolation layer 21 opposite the array region; the initial first supporting layer 31 opposite the peripheral region covers the sidewalls and bottom wall of the third filling grooves 15 and the top surface of the first isolation layer 21 opposite the peripheral region.
[0132] See Figure 16 and Figure 17An initial first supporting layer 31 is deposited. The initial first supporting layer 31 covers the top surface of the first isolation layer 21, fills the remaining first filling trench 12, and conformally covers the second filling trench 14. The initial first supporting layer 31 opposite the array region fills the remaining first filling trench 12 and covers the first isolation layer 21 above the first active region 11. The initial first supporting layer 31 opposite the peripheral region covers the sidewalls and bottom wall of the third filling trench 15, as well as the first isolation layer 21 above the second active region 13. The initial first supporting layer 31 opposite the peripheral region does not fill the third filling trench 15.
[0133] Step S303 ′: etching back the initial first supporting layer 31 to remove the initial first supporting layer 31 on the first isolation layer 21 opposite the array region and the initial first supporting layer 31 in the peripheral region. The remaining initial first supporting layer 31 forms the first supporting layer 32 .
[0134] See Figure 18 and Figure 19 The initial first supporting layer 31 is etched back, leaving the initial first supporting layer 31 in the first filling trench 12. The remaining initial first supporting layer 31 opposite the array region and the entire initial first supporting layer 31 opposite the peripheral region are removed. The remaining initial first supporting layer 31 forms the first supporting layer 32.
[0135] In order to ensure the gate control capability of the peripheral region and the performance of the second active region 13, in some examples, refer to Figures 20 to 24 Before removing the first isolation layer 21 located on the first active region 11 (step S400), the method further includes:
[0136] A third isolation layer 23 is formed, and the third isolation layer 23 covers the top surface of the first isolation layer 21 and the top surface of the first supporting layer 32 opposite to the array area, and covers the first isolation layer 21 opposite to the peripheral area. The third isolation layer 23 located in the third filling groove 15 encloses the fourth filling groove 16; a second supporting layer 33 and a filling layer 34 are formed, and the second supporting layer 33 covers the side wall and bottom wall of the fourth filling groove 16, and the filling layer 34 fills the remaining fourth filling groove 16.
[0137] The first isolation layer 21 in the array region includes the first isolation layer 21 above the first active region 11 and the first isolation layer 21 on the sidewalls and bottom wall of the first filling trench 12. The first isolation layer 21 in the peripheral region includes the first isolation layer 21 above the second active region 13 and the first isolation layer 21 on the sidewalls and bottom wall of the second filling trench 14.
[0138] See Figure 20 and Figure 21The third isolation layer 23 does not completely fill the third filling groove 15. The third isolation layer 23 located in the third filling groove 15 encloses the fourth filling groove 16. The provision of the third isolation layer 23 increases the thickness of the film layer above the first active area 11 and the thickness of the film layer above the second active area 13, ensuring that the performance of the first active area 11 and the second active area 13 is maintained during subsequent manufacturing processes, thereby ensuring the gate control capability of the array area and the peripheral area.
[0139] See Figures 21 to 24 A second supporting layer 33 is formed on the sidewalls and bottom walls of the fourth filling groove 16. The second supporting layer 33 conformally covers the sidewalls and bottom walls of the fourth filling groove 16, but does not completely fill the fourth filling groove 16. A filling layer 34 is formed in the remaining fourth filling groove 16. The filling layer 34 completely fills the remaining fourth filling groove 16, that is, the second supporting layer 33 and the filling layer 34 together fill the fourth filling groove 16. The top surface of the second supporting layer 33 and the top surface of the filling layer 34 are flush with the top surface of the third isolation layer 23. The material of the second supporting layer 33 may include nitride, and the material of the filling layer 34 may include spin-on dielectrics (SOD), so as to facilitate filling larger grooves.
[0140] For some possible implementations, see Figures 21 to 29 , forming a second supporting layer 33 and a filling layer 34, including:
[0141] Step a: Deposit a second supporting layer 33. The second supporting layer 33 covers the top surface of the third isolation layer 23 opposite to the array area and the top surface of the third isolation layer 23 opposite to the peripheral area, and covers the side walls and bottom walls of the fourth filling groove 16. The second supporting layer 33 located in the fourth filling groove 16 encloses the fifth filling groove 17.
[0142] See Figure 21 and Figure 23 A second supporting layer 33 is deposited on the third isolation layer 23 opposite the array region and the third isolation layer 23 opposite the peripheral region. The second supporting layer 33 covers the third isolation layer 23 opposite the array region and the third isolation layer 23 opposite the peripheral region, and conformally covers the sidewalls and bottom wall of the fourth filling trench 16. The second supporting layer 33 does not completely fill the fourth filling trench 16. The second supporting layer 33 within the fourth filling trench 16 encloses the fifth filling trench 17. The material of the second supporting layer 33 can be nitride.
[0143] Step b: forming a filling layer 34 , the filling layer 34 covers the top surface of the second supporting layer 33 opposite to the array region and the peripheral region, and completely fills the fifth filling groove.
[0144] See Figure 24 and Figure 25A filling layer 34 is spin-coated on the second supporting layer 33 opposite to the array area and the second supporting layer 33 opposite to the peripheral area. The filling layer 34 covers the second supporting layer 33 opposite to the array area and the second supporting layer 33 opposite to the peripheral area and fills the fifth filling groove 17.
[0145] Step c: performing a planarization process on the filling layer 34 , removing the filling layer 34 on the second supporting layer 33 opposite to the array region and the peripheral region, and exposing the second supporting layer 33 .
[0146] See Figure 26 and Figure 27 Chemical mechanical polishing is then used to partially remove the filling layer 34 until the second supporting layer 33 opposite the array region and the second supporting layer 33 opposite the peripheral region are exposed. Specifically, the second supporting layer 33 opposite the array region is completely removed, while the portion of the second supporting layer 33 opposite the peripheral region located within the fifth filling trench 17 is retained to form an isolation structure for the second active regions 13, ensuring that the second active regions 13 are insulated from each other.
[0147] Step d: etching away the second supporting layer 33 opposite to the array region and the second supporting layer 33 on the third isolation layer 23 opposite to the peripheral region, and aligning the remaining second supporting layer 33, the filling layer 34 and the third isolation layer 23.
[0148] See Figure 28 and Figure 29 The entire second supporting layer 33 opposite the array region is etched away, exposing the third isolation layer 23 opposite the array region. The second supporting layer 33 on the third isolation layer 23 opposite the peripheral region is also etched away, exposing the third isolation layer 23 opposite the peripheral region. The second supporting layer 33 within the fourth filling trench 16 is retained. The remaining second supporting layer 33, filling layer 34, and third isolation layer 23 are aligned to form a relatively flat surface on the peripheral region.
[0149] In some possible examples, after forming the second supporting layer 33 and the filling layer 34, the process further includes doping each first active region 11 to form a first source region and a first drain region. For example, each first active region 11 is doped by a process such as ion implantation to form the first source region and the first drain region. While doping each first active region 11, each second active region 13 may also be doped to form a second source region and a second drain region.
[0150] For some examples, see Figures 28 to 31 , removing the first isolation layer 21 on the first active area 11 (step S400), including: using hydrofluoric acid wet cleaning to remove the third isolation layer 23 opposite to the array area, the first isolation layer 21 on the first active area 11, the third isolation layer 23 opposite to the peripheral area, and the first isolation layer 21, the second supporting layer 33 and the filling layer 34 on the second active area 13.
[0151] Accordingly, see Figure 32 and Figure 33 , forming a second isolation layer 22 (step S500), including: depositing the second isolation layer 22, the second isolation layer 22 covering the top surface of the first active area 11, the top surfaces of the first isolation layer 21 and the first support layer 32 opposite to the array area, the top surface of the second active area 13, the top surface of the filling layer 34, and the top surfaces of the first isolation layer 21, the second support layer 33 and the third isolation layer 23 opposite to the peripheral area.
[0152] The third isolation layer 23 opposite the array region and the third isolation layer 23 opposite the peripheral region are removed by hydrofluoric acid etching. The first isolation layer 21 on the first active region 11 and the second active region 13 is also removed by etching, exposing the top surface of the first active region 11. The first isolation layer 21 and the first support layer 32 between the first active regions 11 remain. The second support layer 33 and the filling layer 34 on the second active regions 13 are also removed by etching, while the second support layer 33 and the filling layer 34 between the second active regions 13 remain.
[0153] A second isolation layer 22 is deposited on the top surface of the first active area 11, the top surfaces of the first isolation layer 21 and the first support layer 32 opposite the array area, the top surface of the second active area 13, the top surface of the filling layer 34, and the top surfaces of the first isolation layer 21, the second support layer 33, and the third isolation layer 23 opposite the peripheral area. The top surface of the formed second isolation layer 22 is higher than the top surface of the first active area 11, the top surfaces of the first isolation layer 21 and the first support layer 32, the top surface of the second active area 13, and the top surface of the filling layer 34. By removing at least the first isolation layer 21 on the first active area 11 and the second active area 13 and re-forming the second isolation layer 22 on the first active area 11 and the second active area 13, convex defects generated in the first isolation layer 21 during the processes of forming the first isolation layer 21, forming the first support layer 32, and removing a portion of the first support layer 32 can be eliminated. That is, when the first isolation layer 21 is removed, the bump defects of the first isolation layer 21 are also removed, and the top surface of the formed second isolation layer 22 is relatively flat, so as to ensure the quality of other structures, especially the continuity of the word line.
[0154] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array region and a peripheral region; forming a plurality of first active regions spaced apart from each other in the array region, and a first filling trench surrounding each of the first active regions; forming a first isolation layer and a first supporting layer, wherein the first isolation layer covers the sidewalls and bottom wall of the first filling groove and the top surface of the first active area, and the first supporting layer fills the remaining first filling groove; removing the first isolation layer on the top surface of the first active region and retaining the first isolation layer on the sidewalls and bottom wall of the first filling trench to expose the top surface of the first active region; A second isolation layer is formed, where the second isolation layer covers a top surface of the first active region, a top surface of the remaining first isolation layer, and a top surface of the first supporting layer.
2. The production method according to claim 1, characterized in that Before removing the first isolation layer located on the first active area, the method further includes: forming a third isolation layer, wherein the third isolation layer covers a top surface of the first isolation layer opposite to the array region and a top surface of the first supporting layer; Removing the first isolation layer located on the first active region includes: The third isolation layer opposite to the array region and the first isolation layer on the first active region are removed by wet cleaning with a hydrofluoric acid solution to expose a top surface of the first active region and a top surface of the first supporting layer.
3. The production method according to claim 2, characterized in that: forming a second isolation layer, comprising: The second isolation layer is deposited on the first isolation layer and the first support layer opposite to the first active area and the array area, and the thickness of the second isolation layer is greater than or equal to the sum of the thicknesses of the first isolation layer and the third isolation layer.
4. The production method according to any one of claims 1 to 3, characterized in that A plurality of first active regions spaced apart from each other are formed in the array region, and a first filling trench surrounding each of the first active regions is formed, comprising: The first active area and the first filling groove are formed in the array area; wherein the extension direction of each first active area is the same, and there is a first gap or a second gap between adjacent first active areas, the size of the first gap in the first direction is smaller than the size of the second gap in the first direction, and the first direction is perpendicular to the extension direction of the first active area.
5. The production method according to claim 4, characterized in that: Forming the first isolation layer and the first support layer includes: forming a first isolation layer on the sidewalls and bottom wall of the first filling groove and the first active area, wherein the first isolation layer fills the first gap, and the first isolation layer located in the second gap encloses a filling hole; depositing an initial first supporting layer, wherein the initial first supporting layer completely fills the filling hole and covers a top surface of the first isolation layer; A portion of the initial first supporting layer is removed, and the remaining initial first supporting layer forms the first supporting layer, wherein a top surface of the first supporting layer is aligned with a top surface of the first active region.
6. The manufacturing method according to claim 1, characterized in that A plurality of first active regions spaced apart from each other are formed in the array region, and a first filling trench surrounding each of the first active regions is formed, further comprising: forming a plurality of second active regions spaced apart from each other in the peripheral region, and a second filling trench surrounding each of the second active regions; Forming a first isolation layer and a first support layer, comprising: forming the first isolation layer on the sidewalls and bottom wall of the first filling trench, the top surface of the first active region, the sidewalls and bottom wall of the second filling trench, and the top surface of the second active region, and the first isolation layer in the second filling trench enclosing a third filling trench; Depositing an initial first supporting layer on the first isolation layer, wherein the initial first supporting layer opposite to the array region fills the remaining first filling groove and covers the top surface of the first isolation layer opposite to the array region; and the initial first supporting layer opposite to the peripheral region covers the sidewalls and bottom wall of the third filling groove and the top surface of the first isolation layer opposite to the peripheral region; The initial first supporting layer is etched back to remove the initial first supporting layer on the first isolation layer opposite to the array region and the initial first supporting layer in the peripheral region, and the remaining initial first supporting layer forms the first supporting layer.
7. The production method according to claim 6, characterized in that: Before removing the first isolation layer located on the first active area, the method further includes: forming a third isolation layer, wherein the third isolation layer covers a top surface of the first isolation layer and a top surface of the first support layer opposite to the array region, and covers the first isolation layer opposite to the peripheral region, and the third isolation layer located in the third filling trench encloses a fourth filling trench; A second supporting layer and a filling layer are formed, wherein the second supporting layer covers the sidewalls and the bottom wall of the fourth filling groove, and the filling layer fills the remaining portion of the fourth filling groove.
8. The production method according to claim 7, characterized in that: Forming a second support layer and a filling layer, including: Depositing the second supporting layer, the second supporting layer covering the top surface of the third isolation layer opposite to the array region and the top surface of the third isolation layer opposite to the peripheral region, and covering the sidewalls and bottom wall of the fourth filling trench, wherein the second supporting layer located in the fourth filling trench encloses a fifth filling trench; forming the filling layer, wherein the filling layer covers the top surface of the second supporting layer opposite to the array region and the peripheral region and completely fills the fifth filling groove; performing a planarization process on the filling layer, removing the filling layer on the second supporting layer opposite to the array region and the peripheral region, and exposing the second supporting layer; The second supporting layer opposite to the array region and the second supporting layer on the third isolation layer opposite to the peripheral region are removed by etching, and the remaining second supporting layer, the filling layer and the third isolation layer are aligned.
9. The production method according to claim 8, characterized in that: After forming the second support layer and the filling layer, the method further includes: Each of the first active regions is doped to form a first source region and a first drain region.
10. The production method according to any one of claims 7 to 9, characterized in that: Removing the first isolation layer on the first active region includes: Using hydrofluoric acid wet cleaning to remove the third isolation layer opposite to the array region, the first isolation layer on the first active region, the third isolation layer opposite to the peripheral region, and the first isolation layer, the second supporting layer, and the filling layer on the second active region; Forming the second isolation layer includes: The second isolation layer is deposited, and the second isolation layer covers the top surface of the first active area, the top surfaces of the first isolation layer and the first support layer opposite to the array area, the top surface of the second active area, the top surface of the filling layer, and the top surfaces of the first isolation layer, the second support layer and the third isolation layer opposite to the peripheral area.
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