A packaging structure and method for a frame - type product

Abstract

The present invention provides a packaging structure and method for a frame-type product. The packaging structure of the frame-type product includes: a lead frame, on which a carrier table and conductive pins are provided; a chip and N resistor components are arranged on the carrier table. The first end of the i-th resistor component is connected to the conductive pin of the lead frame through the i-th bonding wire, and the second end of the i-th resistor component is connected to the i-th power supply pin of the chip through the (N + i)-th bonding wire, where 1 ≤ i ≤ N; the voltage drop corresponding to the i-th power supply line is the i-th target voltage drop, and the i-th power supply line includes the i-th bonding wire, the i-th resistor component, and the (N + i)-th bonding wire. By converting the external power supply through the power supply lines with different target voltage drops, the conversion from a single external power supply to diversified different internal power supplies is realized, and the requirements of multiple power supplies are met without affecting its compatibility.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and more particularly, to a packaging structure and method for frame-like products. Background Art

[0002] Currently, the promotion of chip autonomy and self-control is a requirement of the general environment. There are a large number of self-developed in-situ replacement products. The package size, pin definition, external usage environment, etc. of the replaced products are already fixed. Therefore, there are many restrictions on self-developed chips. For example, for some frame-like single-voltage products, self-developed replacement will encounter the problem that the self-developed chip requires multi-voltage power supply, but the packaged product only has single-voltage power supply.

[0003] How to ensure that under the condition of package compatibility for in-situ replacement, the problem of converting external single voltage into internal multi-voltage power supply has become a difficult problem for those skilled in the art. Summary of the Invention

[0004] The purpose of the present invention is to provide a packaging structure and method for frame-like products to improve the above problems.

[0005] To achieve the above purpose, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides a packaging structure for frame-like products, and the packaging structure for frame-like products includes:

[0007] A lead frame, on which a carrier table and conductive pins are provided;

[0008] A chip and N resistor components are provided on the carrier table. The first end of the i-th resistor component is connected to the conductive pin of the lead frame through the i-th bonding wire, and the second end of the i-th resistor component is connected to the i-th power supply pin of the chip through the (N + i)-th bonding wire, where 1 ≤ i ≤ N;

[0009] The voltage drop corresponding to the i-th power supply line is the i-th target voltage drop, and the i-th power supply line includes the i-th bonding wire, the i-th resistor component, and the (N + i)-th bonding wire.

[0010] By converting the external power supply through power supply lines with different target voltage drops, the conversion from a single external power supply to diverse internal power supplies is realized, and the requirements for multiple power supplies are met without affecting its compatibility.

[0011] Optionally, the resistor component is a chip resistor, and N sets of mounting areas are provided on the carrier table, and each mounting area is insulated and isolated from the carrier table;

[0012] Both ends of the i-th chip resistor are respectively mounted on the first mounting area and the second mounting area in the i-th group of mounting areas;

[0013] The i-th bonding wire is connected to the first mounting area in the i-th group of mounting areas;

[0014] The (N + i)-th bonding wire is connected to the second mounting area in the i-th group of mounting areas.

[0015] Since each mounting area is insulated from the carrier stage, the current flowing into the mounting area will not directly short-circuit from the mounting area to the metal-conductive carrier stage, thus avoiding affecting the voltage conversion.

[0016] In a second aspect, an embodiment of the present invention provides a method for encapsulating a frame-type product, and the method further includes:

[0017] Opening mounting areas, opening N groups of mounting areas on the carrier stage provided on the lead frame, and each mounting area is insulated from the carrier stage;

[0018] Performing resistor mounting, mounting both ends of the i-th chip resistor on the first mounting area and the second mounting area in the i-th group of mounting areas, where 1 ≤ i ≤ N;

[0019] Performing chip mounting, mounting the chip on a predetermined area on the carrier stage;

[0020] Performing gold wire bonding, including: connecting the first mounting area in the i-th group of mounting areas to the conductive pin of the lead frame through the i-th bonding wire, and connecting the second mounting area in the i-th group of mounting areas to the i-th power supply pin of the chip through the (N + i)-th bonding wire;

[0021] The voltage drop corresponding to the i-th power supply line is the i-th target voltage drop, and the i-th power supply line includes the i-th bonding wire, the i-th resistor component, and the (N + i)-th bonding wire.

[0022] Converting the external power supply through power supply lines with different target voltage drops, realizing the conversion from a single external power supply to diversified different internal power supplies, and meeting the requirements of multiple power supplies without affecting its compatibility.

[0023] Optionally, the step of opening the mounting areas includes: etching N groups of target areas pre-planned on the carrier stage to obtain N groups of etched areas; performing plastic encapsulation and curing on the etched areas to form N groups of insulated isolation areas; performing silvering treatment on the wire bonding areas in the insulated isolation areas to obtain N groups of mounting areas.

[0024] Since resistor mounting cannot be achieved in the insulation isolation area, silvering treatment needs to be performed on the wire bonding area in the insulation isolation area. The wire bonding area after silvering treatment is the mounting area. The edge of the wire bonding area is at least separated from the edge of the insulation isolation area by a preset distance, so as to avoid short circuit between the encapsulated area after silvering treatment and the carrier stage.

[0025] Optionally, the etching thickness is half of the thickness of the carrier stage.

[0026] It should be understood that half of the thickness is etched in the target area on the upper surface (the side away from the lead frame) of the carrier stage, and the shape of the lower surface of the carrier stage remains unchanged. After packaging is completed, the lower surface will be completely exposed, without changing the appearance size of the packaging pads, ensuring appearance and welding compatibility.

[0027] Optionally, after the gold wire bonding is completed, the method further includes: integrally encapsulating the lead frame after the gold wire bonding is completed, and the encapsulating material used for the integral encapsulation is the same as the encapsulating material used for encapsulating and curing the etched area.

[0028] The encapsulating material used for the subsequent integral encapsulation is the same as the encapsulating material used for encapsulating and curing the etched area. Since the materials used for encapsulation molding are the same, the delamination problem caused by different CTEs (coefficient of thermal expansion) of the materials is avoided, and the packaging reliability is improved.

[0029] Optionally, before performing the encapsulation operation on the lead frame, the method further includes:

[0030] Performing simulation modeling on the lead frame and the chip to obtain a simulation model;

[0031] Performing simulation iteration according to the simulation model to determine the i-th target path, where the i-th target path is the i-th simulation power supply line between the lead frame and the chip in the simulation model, the voltage drop corresponding to the i-th target path is the i-th target voltage drop, and the i-th target path includes the position information of the i-th group of target areas on the carrier stage.

[0032] Determining the relevant information of each target path through simulation, ensuring that each power supply line completed subsequently can achieve the corresponding voltage drop, and ensuring the accuracy of the voltage conversion result.

[0033] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. Description of the Drawings

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the embodiments. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0035] Figure 1 It is a schematic structural diagram of the lead frame provided by the embodiment of the present invention.

[0036] Figure 2 It is one of the schematic flowcharts of the encapsulation method for frame-like products provided by the embodiment of the present invention.

[0037] Figure 3 It is a schematic diagram of the encapsulation structure of the frame-like product provided by the embodiment of the present invention.

[0038] Figure 4 It is a schematic diagram of the etching result provided by the embodiment of the present invention.

[0039] Figure 5 It is a schematic diagram of the plastic encapsulation curing result provided by the embodiment of the present invention.

[0040] Figure 6 It is a schematic diagram of the silvering result provided by the embodiment of the present invention.

[0041] Figure 7 It is a schematic diagram of the resistor mounting result provided by the embodiment of the present invention.

[0042] Figure 8 It is a schematic diagram of the chip mounting result provided by the embodiment of the present invention.

[0043] Figure 9 It is a schematic diagram of the gold wire bonding result provided by the embodiment of the present invention.

[0044] Figure 10 It is the second schematic flowchart of the encapsulation method for frame-like products provided by the embodiment of the present invention.

[0045] Figure 11 It is the third schematic flowchart of the encapsulation method for frame-like products provided by the embodiment of the present invention.

[0046] Figure 12 It is the fourth schematic flowchart of the encapsulation method for frame-like products provided by the embodiment of the present invention. Detailed implementation manners

[0047] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. The components of the embodiments of the present invention usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0048] Therefore, the detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0049] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive distinction and cannot be understood as indicating or implying relative importance.

[0050] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship in which the inventive product is usually placed during use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0051] In the description of the present invention, it should also be noted that unless otherwise clearly specified and defined, the terms "set", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0052] The following will describe in detail some embodiments of the present invention with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0053] It should be noted that the lead frame is usually made of a layer of copper foil, and the circuit and structure are very simple. It is very difficult to place devices inside by conventional processes. Specifically, please refer to Figure 1 . Figure 1 It is a schematic structural diagram of the lead frame provided by the embodiment of the present invention.

[0054] The periphery of the lead frame is wire bonding pins (also known as wire bonding pins, including but not limited to conductive pins). The lead frame has a small size and there is no position to mount a resistor. Only the middle carrier stage (also known as a heat sink pad, on which the bare chip is also mounted) can be used to mount the resistor. However, the carrier stage is a single piece of metal, and directly mounting the resistor on it will cause a short circuit between the two terminals and the voltage conversion cannot be achieved.

[0055] Therefore, the embodiment of the present invention provides a packaging method for frame products. By using etching and plastic encapsulation curing processes, an insulating isolation area of the carrier stage is realized. After silvering, resistor mounting can be achieved without short circuit, thereby realizing the effect of converting an external single voltage into an internal multi-voltage power supply. Specifically, please refer to Figure 2 and Figure 3 , Figure 2 which is one of the flow schematic diagrams of the packaging method for frame products provided by the embodiment of the present invention, Figure 3 and Figure 3 which is the schematic diagram of the packaging structure of the frame product provided by the embodiment of the present invention. Figure 2 In

[0056] S110, opening a mounting area, opening N groups of mounting areas on the carrier stage provided on the lead frame.

[0057] Each mounting area is insulated from the carrier stage, and the current flowing into this mounting area will not directly short circuit from the mounting area to the metal conductive carrier stage.

[0058] S120, performing resistor mounting, mounting the two ends of the i-th chip resistor on the first mounting area and the second mounting area in the i-th group of mounting areas respectively.

[0059] Where 1≤i≤N, and N is a positive integer greater than or equal to 1. When N = 1, based on the packaging method for frame products provided by the embodiment of the present invention, the obtained packaging structure of the frame product can complete single-phase voltage conversion; when N is greater than 1, based on the packaging method for frame products provided by the embodiment of the present invention, the obtained packaging structure of the frame product can complete the conversion from single-phase voltage to multi-phase voltage.

[0060] S130, performing chip mounting, mounting the chip on the specified area on the carrier stage.

[0061] S150, perform gold wire bonding. Connect the first mounting area in the i-th group of mounting areas to the conductive pin of the lead frame through the i-th bonding wire, and connect the second mounting area in the i-th group of mounting areas to the i-th power supply pin of the chip through the (N + i)-th bonding wire.

[0062] The voltage drop corresponding to the i-th power supply line is the i-th target voltage drop. The i-th power supply line includes the i-th bonding wire, the i-th resistor component, and the (N + i)-th bonding wire. The i-th target voltage drop is the difference between the input voltage of the conductive pin and the standard voltage corresponding to the i-th power supply pin of the chip.

[0063] As Figure 3 shown, the conductive pin of the lead frame corresponds to the external power supply V1. After passing through the first power supply line and the second power supply line, the first power supply pin of the chip corresponds to the internal power supply V2, and the second power supply pin of the chip corresponds to the internal power supply V3. It can realize the conversion from a single external power supply V1 to diversified different internal power supplies V2 and V3.

[0064] Based on the above, regarding the content in S110, the embodiment of the present invention also provides an optional implementation manner. Please refer to the following. S110, the step of opening the mounting area, includes: S111, S112, and S113, specifically as follows.

[0065] S111, perform etching on N groups of target areas pre-planned on the carrier stage to obtain N groups of etched areas.

[0066] Please refer to Figure 4 , Figure 4 which is the schematic diagram of the etching result provided by the embodiment of the present invention.

[0067] In an optional implementation manner, perform semi-etching on N groups of target areas pre-planned on the carrier stage, and the etching thickness is half of the thickness of the carrier stage.

[0068] It should be understood that when etching half of the thickness of the target area on the upper surface (the side away from the lead frame) of the carrier stage, the shape of the lower surface of the carrier stage remains unchanged, and the lower surface will be completely exposed after packaging, without changing the appearance size of the packaging pad, ensuring the compatibility of appearance and welding.

[0069] Of course, the etching thickness can also be one-third or two-thirds of the thickness of the carrier stage.

[0070] S112, perform plastic encapsulation and curing on the etched areas to form N groups of insulating isolation areas.

[0071] Please refer to Figure 5 , Figure 5 which is the schematic diagram of the plastic encapsulation and curing result provided by the embodiment of the present invention.

[0072] The etched area is encapsulated and cured to form an insulating isolation area. In an alternative embodiment, the encapsulation material used for subsequent overall encapsulation is the same as the encapsulation material used for encapsulating and curing the etched area. Since the materials used for encapsulation molding are the same, the delamination problem caused by different material CTEs (coefficient of thermal expansion) is avoided, and the packaging reliability is improved.

[0073] S113, silver-plate the wire bonding area in the insulating isolation area to obtain N sets of mounting areas.

[0074] Please refer to Figure 6 , Figure 6 , which is a schematic diagram of the silver-plating result provided by an embodiment of the present invention.

[0075] It should be noted that since the insulating isolation area cannot achieve resistor mounting, the wire bonding area in the insulating isolation area needs to be silver-plated. The wire bonding area after silver-plating is the mounting area. The edge of the wire bonding area is at least separated from the edge of the insulating isolation area by a preset distance, so as to avoid short-circuiting of the packaged area after silver-plating and the wafer stage.

[0076] After the mounting area is opened, S120 can be executed for resistor mounting. The resistor mounting result is as Figure 7 shown, Figure 7 , which is a schematic diagram of the resistor mounting result provided by an embodiment of the present invention.

[0077] After the resistor mounting is completed, S130 can be executed for chip mounting. The chip mounting result is as Figure 8 shown, Figure 8 , which is a schematic diagram of the chip mounting result provided by an embodiment of the present invention.

[0078] After the chip mounting is completed, S150 can be executed for gold wire bonding. The gold wire bonding result is as Figure 9 shown, Figure 9 , which is a schematic diagram of the gold wire bonding result provided by an embodiment of the present invention.

[0079] On the basis of Figure 2 , an alternative embodiment is further provided in the embodiment of the present invention. Please refer to Figure 10 , Figure 10 , which is the second flowchart of the packaging method for frame-like products provided by an embodiment of the present invention. After the gold wire bonding is completed, the packaging method for frame-like products further includes: S160, which is as follows.

[0080] S160, perform overall encapsulation on the lead frame after the gold wire bonding is completed.

[0081] The encapsulation material used for the overall encapsulation is the same as the encapsulation material used for curing the etched area. Since the materials used for encapsulation molding are the same, the delamination problem caused by different CTEs (Coefficient of Thermal Expansion) of the materials is avoided, and the packaging reliability is improved.

[0082] In an alternative embodiment, after the overall encapsulation is completed, it can be cut to form a single packaged finished product.

[0083] On the basis of Figure 2 the present invention's embodiments also provide an alternative embodiment. Please refer to Figure 11 , Figure 11 which is the third flow chart of the packaging method for the frame-type product provided by the embodiments of the present invention. Before wire bonding, the packaging method for the frame-type product further includes: S140, which is specifically as follows.

[0084] S140, silver-plate the conductive pins of the lead frame.

[0085] Optionally, the lead frame material is copper and cannot be wire-bonded. It is necessary to have silver on the copper. Therefore, the conductive pins of the lead frame are silver-plated, and the silver-plated area obtained can be wire-bonded.

[0086] In the packaging method for the frame-type product provided by the embodiments of the present invention, the carrier stage forms an insulating isolation area through processes such as semi-etching and dispensing curing. After surface silver-plating, device mounting can be realized, and there will be no metal short circuit with the carrier stage. The external power supply V1 is connected to resistors with different resistances through different wire bonds, and then wire-bonded to the power supply pad of the bare die, which can realize converting different voltages V2, V3, etc. to supply power to the bare die inside the package, achieving the purpose of voltage conversion power supply.

[0087] On the basis of the foregoing, regarding the relevant information on how to determine the power supply line, the embodiments of the present invention also provide an alternative embodiment. Please refer to Figure 12 , Figure 12 which is the fourth flow chart of the packaging method for the frame-type product provided by the embodiments of the present invention. Before performing the packaging operation on the lead frame, the packaging method for the frame-type product further includes: S210 and S220, which are specifically described as follows.

[0088] S210, perform simulation modeling on the lead frame and the chip to obtain a simulation model.

[0089] S220, perform simulation iteration according to the simulation model to determine the i-th target path.

[0090] The i-th target path is the i-th simulated power supply line between the lead frame and the chip in the simulation model. The voltage drop corresponding to the i-th target path is the i-th target voltage drop. The i-th target path includes the position information of the i-th group of target areas on the wafer stage.

[0091] Optionally, the i-th target path further includes the bonding wire attribute information of the i-th bonding wire, the bonding wire attribute information of the (N + i)-th bonding wire, and the resistance value information of the i-th chip resistor. The bonding wire attribute information includes wire diameter and wire length. The bonding wire attribute information of the i-th bonding wire, the bonding wire attribute information of the (N + i)-th bonding wire, and the resistance value information of the i-th chip resistor can be used as the execution standard for the subsequent packaging process.

[0092] By simulating to determine the relevant information of each target path, it is ensured that each power supply line completed subsequently can achieve the corresponding voltage drop, thus ensuring the accuracy of the voltage conversion result.

[0093] An embodiment of the present invention further provides a packaging structure for a frame-like product, as Figure 3 shown. The packaging structure for the frame-like product includes:

[0094] A lead frame, on which a wafer stage and conductive pins are provided.

[0095] A chip and N resistor components are arranged on the wafer stage. The first end of the i-th resistor component is connected to the conductive pin of the lead frame through the i-th bonding wire, and the second end of the i-th resistor component is connected to the i-th power supply pin of the chip through the (N + i)-th bonding wire, where 1 ≤ i ≤ N.

[0096] The voltage drop corresponding to the i-th power supply line is the i-th target voltage drop. The i-th power supply line includes the i-th bonding wire, the i-th resistor component, and the (N + i)-th bonding wire.

[0097] Optionally, the resistor component is a chip resistor, and N groups of mounting areas are provided on the wafer stage, and each mounting area is insulated and isolated from the wafer stage.

[0098] Both ends of the i-th chip resistor are respectively mounted on the first mounting area and the second mounting area in the i-th group of mounting areas.

[0099] The i-th bonding wire is connected to the first mounting area in the i-th group of mounting areas; the (N + i)-th bonding wire is connected to the second mounting area in the i-th group of mounting areas.

[0100] Optionally, the mounting area includes: an insulation isolation area formed by etching on the wafer stage and cured by plastic encapsulation; a silver-plated area provided on the upper layer of the insulation isolation area, and the silver-plated area is insulated and isolated from the wafer stage. The silver-plated area is used for resistor mounting and connecting bonding wires.

[0101] In summary, a packaging structure and method for a frame-type product provided by an embodiment of the present invention. The packaging structure of the frame-type product includes: a lead frame, on which a carrier stage and conductive pins are provided; a chip and N resistor components are provided on the carrier stage. The first end of the i-th resistor component is connected to the conductive pin of the lead frame through the i-th bonding wire, and the second end of the i-th resistor component is connected to the i-th power supply pin of the chip through the (N + i)-th bonding wire, where 1 ≤ i ≤ N; the voltage drop corresponding to the i-th power supply line is the i-th target voltage drop. The i-th power supply line includes the i-th bonding wire, the i-th resistor component, and the (N + i)-th bonding wire. By converting the external power supply through power supply lines with different target voltage drops, it is possible to convert from a single external power supply to diverse internal power supplies, meeting the requirements of multiple power supplies without affecting its compatibility.

[0102] The foregoing is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and changes can be made to the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

[0103] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to encompass all changes falling within the meaning and scope of the equivalent elements of the claims in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.

Claims

1. A frame product packaging structure, characterized in that: The frame product packaging structure includes: A lead frame, on which a wafer carrier and conductive pins are arranged; The chip carrier is provided with a chip and N resistor components, the first end of the i-th resistor component is connected to the conductive pin of the lead frame through the i-th bonding wire, and the second end of the i-th resistor component is connected to the i-th power supply pin of the chip through the N+i-th bonding wire, 1≤i≤N, N>1; The voltage drop corresponding to the i-th power supply line is the i-th target voltage drop, and the i-th power supply line includes the i-th bonding wire, the i-th resistor component and the N+i-th bonding wire; The resistor component is a chip resistor, and N groups of mounting areas are provided on the chip carrier, and each mounting area is insulated and isolated from the chip carrier; The two ends of the i-th chip resistor are mounted on the first mounting area and the second mounting area of ​​the i-th group of mounting areas respectively; The i-th bonding wire is connected to the first mounting area in the i-th group of mounting areas; The N+i th bonding wire is connected to the second mounting area in the i th group of mounting areas.

2. The frame product packaging structure according to claim 1, characterized in that: The mounting area includes: An insulating isolation area is provided in the etching area on the wafer stage and formed by plastic sealing and curing; A silvering area is arranged on the upper layer of the insulating isolation area, the silvering area is insulated and isolated from the wafer carrier, and the silvering area is used for resistor mounting and connecting bonding wires.

3. A method for packaging frame products, characterized in that: The method comprises: Opening a mounting area, and opening N groups of mounting areas on a wafer carrier set on a lead frame, each mounting area is insulated and isolated from the wafer carrier; Perform resistor mounting, mounting the two ends of the i-th chip resistor on the first mounting area and the second mounting area of ​​the i-th group of mounting areas, respectively, 1≤i≤N, N>1; Perform chip mounting, mounting the chip on a designated area on the wafer stage; Performing gold wire bonding, including: connecting a first mounting area in the i-th group of mounting areas to a conductive pin of the lead frame through an i-th bonding wire, and connecting a second mounting area in the i-th group of mounting areas to an i-th power supply pin of the chip through an N+i-th bonding wire; The voltage drop corresponding to the ith power supply line is the ith target voltage drop, and the ith power supply line includes the ith bonding wire, the ith resistance component, and the N+ith bonding wire.

4. The frame product packaging method according to claim 3, characterized in that: The step of opening a mounting area includes: Etching N groups of target areas pre-planned on the wafer stage to obtain N groups of etched areas; Plastic-sealing and curing the etched areas to form N groups of insulating isolation areas; Silver treatment is performed on the wire bonding area in the insulating isolation area to obtain N groups of mounting areas.

5. The frame product packaging method according to claim 4, characterized in that: The etching thickness is half of the thickness of the wafer stage.

6. The frame product packaging method according to claim 4, characterized in that: After the gold wire bonding is completed, the method further comprises: The lead frame after gold wire bonding is integrally encapsulated, and the encapsulation material used for the overall encapsulation is the same as the encapsulation material used for encapsulating and curing the etched area.

7. The frame product packaging method according to claim 4, characterized in that: Before performing gold wire bonding, the method further includes: The conductive pins of the lead frame are silvered.

8. The frame product packaging method according to claim 4, characterized in that: Before packaging the lead frame, the method further comprises: Performing simulation modeling on the lead frame and the chip to obtain a simulation model; Simulation iterations are performed according to the simulation model to determine the i-th target path, the i-th target path is the i-th simulated power supply line between the lead frame and the chip in the simulation model, the voltage drop corresponding to the i-th target path is the i-th target voltage drop, and the i-th target path includes position information of the i-th group of target areas on the wafer stage.

9. The frame product packaging method according to claim 8, characterized in that: The i-th target path also includes bonding wire attribute information of the i-th bonding wire, bonding wire attribute information of the N+i-th bonding wire, and resistance value information of the i-th chip resistor, and the bonding wire attribute information includes wire diameter and wire length.

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