Semiconductor packaging structure

Abstract

A semiconductor package structure includes a package substrate and a semiconductor chip. The package substrate includes a core structure, an integrated capacitor structure, and a redistribution layer. The integrated capacitor structure is embedded in the core structure. The redistribution layer is disposed over the integrated capacitive structure. And the semiconductor chip is arranged above the packaging substrate and is electrically connected with the integrated capacitor structure through the rewiring layer.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and in particular to a semiconductor packaging structure including a capacitor. Background Art

[0002] In addition to providing protection for semiconductor chips from environmental pollutants, semiconductor packaging structures can also provide electrical connections between the semiconductor chips packaged therein and a substrate (eg, a printed circuit board (PCB)).

[0003] Although existing semiconductor packaging structures generally meet the requirements, they are not completely satisfactory in all aspects. For example, in order to meet the requirements of high electrical signal performance, more and more metal layers are required in the packaging substrate. However, as the size of the semiconductor packaging structure increases, the warping of the packaging substrate becomes a key issue. Therefore, the semiconductor packaging structure needs to be further improved. Summary of the invention

[0004] The present invention provides a semiconductor packaging structure. An exemplary embodiment of the semiconductor packaging structure includes a packaging substrate and a semiconductor chip. The packaging substrate includes a core structure, an integrated capacitor structure, and a redistribution layer. The integrated capacitor structure is embedded in the core structure. The redistribution layer is arranged above the integrated capacitor structure. The semiconductor chip is arranged above the packaging substrate and is electrically connected to the integrated capacitor structure through the redistribution layer.

[0005] The semiconductor packaging structure of another embodiment includes a packaging substrate. The packaging substrate includes a core structure, a first capacitor, a second capacitor, a first insulating filler, a first redistribution layer, and a second redistribution layer. The first capacitor and the second capacitor are vertically stacked and embedded in the core structure. The first insulating filler is arranged in the core structure and surrounds the first capacitor and the second capacitor. The first redistribution layer is arranged below the core structure. The second redistribution layer is arranged above the core structure and is electrically connected to the first capacitor and the second capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention may be more fully understood by reading the following detailed description and examples and by referring to the accompanying drawings, in which:

[0007] Figures 1A to 1E are cross-sectional views of various stages in the manufacture of an exemplary semiconductor package structure according to some embodiments of the present disclosure;

[0008] FIG. 2A to FIG. 2C are cross-sectional views of various stages in the manufacture of an exemplary semiconductor package structure according to some embodiments of the present disclosure;

[0009] Figure 3is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure;

[0010] Figure 4 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure;

[0011] Figure 5 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure;

[0012] Figure 6 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure;

[0013] Figure 7 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure; and

[0014] Figure 8 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure.

[0015] Description of Figure Numbers

[0016] 100:Semiconductor packaging structure

[0017] 101:Packaging substrate

[0018] 102: Core Structure

[0019] 102a: bottom surface

[0020] 102b: Top surface

[0021] 104: Opening

[0022] 106:Through hole

[0023] 108: Insulation filler

[0024] 110:Metal layer

[0025] 112: Cavity

[0026] 114: Capacitor

[0027] 114b: back surface

[0028] 114f: front surface

[0029] 115: Adhesive layer

[0030] 116:Capacitor

[0031] 116b: back surface

[0032] 116f: front surface

[0033] 118: Integrated capacitor structure

[0034] 120: Insulation filler

[0035] 122: Dielectric layer

[0036] 124: Wiring layer

[0037] 126: Rewiring layer

[0038] 128: Solder mask

[0039] 130: Semiconductor Chip

[0040] 132: Semiconductor Chip

[0041] 134: Solder connector

[0042] 136: Conductive connector

[0043] 138: Conductive terminal

[0044] 202:Dummy chip

[0045] 300:Semiconductor packaging structure

[0046] 302:Through hole

[0047] 400:Semiconductor packaging structure

[0048] 500:Semiconductor packaging structure

[0049] 600:Semiconductor packaging structure

[0050] 700:Semiconductor packaging structure

[0051] 800:Semiconductor packaging structure

[0052] D1: Thickness

[0053] D2: Thickness

[0054] D3: Thickness

[0055] D4: Thickness

[0056] D5: Thickness

[0057] D6: Thickness DETAILED DESCRIPTION

[0058] The following description is made for the purpose of illustrating the general principles of the invention and is not to be construed in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0059] The present disclosure will be described with respect to specific embodiments and with reference to certain drawings, but the present disclosure is not limited thereto and is limited only by the claims. The drawings described are illustrative only and are not restrictive. In the drawings, the size of certain elements may be exaggerated and not drawn to scale for illustrative purposes. Dimensions and relative dimensions do not correspond to actual dimensions in the practice of the present disclosure.

[0060] On the basis of the embodiments described below, additional elements may be added. For example, the description of "a first element on / covering a second element" may include an embodiment in which the first element is in direct contact with the second element, and may also include an embodiment in which an additional element is provided between the first element and the second element, so that the first element and the second element are not in direct contact.

[0061] Furthermore, the description of “a first element passing through a second element” may include embodiments in which the first element is disposed in the second element and extends from one side of the second element to an opposite side of the second element, wherein a surface of the first element may be substantially flush with a surface of the second element, or a surface of the first element may be outside a surface of the second element.

[0062] The spatial relative descriptors of the first element and the second element may change as the structure is operated or used in different directions. In addition, the present disclosure may repeat reference numbers and / or letters in various embodiments. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments discussed.

[0063] In semiconductor packaging, such as notebook central processing unit (CPU) packaging structures, silicon capacitors embedded in the substrate may be used to enhance decoupling performance. However, embedded solutions are limited to thin core structures due to the thickness of silicon capacitors. If the core structure is not thick enough, package substrate warping may occur, and warping may become more severe as the package substrate size increases.

[0064] In view of this, the present disclosure describes a semiconductor package structure including an integrated capacitor structure, which includes stacked capacitors and is embedded in a core structure. Therefore, the thickness of the core structure can be increased to meet the large size requirements of the package substrate.

[0065] Figures 1A to 1E 1 is a cross-sectional view of various stages of manufacturing a semiconductor package structure 100 according to some embodiments of the present disclosure. Additional features may be added to the semiconductor package structure 100. Some of the features described below may be replaced or eliminated for different embodiments. To simplify the diagram, only a portion of the semiconductor package structure 100 is shown.

[0066] like Figure 1AAs shown, a core structure 102 is provided according to some embodiments. The core structure 102 can be formed of an organic material, a glass material, a ceramic material, a semiconductor material, a similar material, or a combination thereof. The organic material can include a glass fiber resin (e.g., FR4), a bismaleimide triazine (BT) resin, a similar material, or a combination thereof. The semiconductor material can include silicon, germanium, or a compound material, including silicon germanium, silicon carbide, gallium arsenide, silicon germanium carbide, a similar material, or a combination thereof.

[0067] Then, according to some embodiments, a plurality of openings 104 and a cavity 112 are formed in the core structure 102. The openings 104 and the cavity 112 may be formed through the core structure 102, such as by laser drilling or any suitable method. According to some embodiments, the openings 104 and the cavity 112 may be formed simultaneously.

[0068] Afterwards, if Figure 1B As shown, according to some embodiments, an integrated capacitor structure 118 is placed in the cavity 112. The integrated capacitor structure 118 can be embedded in the core structure 102. The integrated capacitor structure 118 can include two capacitors 114 and 116, which are stacked vertically. That is, the capacitors 114 and 116 can be stacked in a direction perpendicular to the bottom surface of the core structure 102.

[0069] Capacitors 114 and 116 may include silicon capacitors. The thickness D1 of the core structure 102 may be substantially equal to the thickness D2 of the integrated capacitor structure 118. Since the thickness D2 of the embedded integrated capacitor structure 118 is greater than the thickness of any of the capacitors 114 and 116, the thickness D1 of the core structure 102 may be increased. As a result, the warpage of the package substrate may be reduced. At the same time, the enhancement of the decoupling performance may also be achieved.

[0070] In some embodiments, the thickness D2 of the integrated capacitor structure 118 may be in a range of about 0.8 mm to about 1.4 mm, such as about 1.0 mm. The thickness D1 of the core structure 102 may be in a range of about 0.8 mm to about 1.4 mm, such as about 1.0 mm.

[0071] Capacitors 114 and 116 may be assembled back-to-back. In particular, backside surface 114b of capacitor 114 may face backside surface 116b of capacitor 116. Frontside surface 114f of capacitor 114 may be substantially aligned with bottom surface 102a of core structure 112, and frontside surface 116f of capacitor 116 may be substantially aligned with top surface 102b of core structure 112. This allows subsequent layers (e.g., redistribution layers) to be formed on a flat surface.

[0072] Capacitors 114 and 116 may be bonded using glue layer 115. Glue layer 115 may be a die-cut film or any suitable material. Alternatively, capacitors 114 and 116 may be bonded using fusion bonding, hybrid bonding, or any suitable method. Fusion bonding may include dielectric-to-dielectric bonding and / or conductor-to-conductor bonding. Hybrid bonding may be a combination of dielectric-to-dielectric bonding and conductor-to-conductor bonding, and may be a direct metal-to-metal bonding, such as a direct copper-to-copper bonding. When hybrid bonding or metal-to-metal bonding is used, the heat dissipation efficiency may be further improved compared to dielectric-to-dielectric bonding or die-cut film.

[0073] One or more active and passive devices (not shown) may also be provided in the core structure 102 to meet the structural and functional requirements of the design. For example, the active and passive devices may include transistors, capacitors, resistors, the like, or a combination thereof.

[0074] Then, according to some embodiments, an insulating filler 120 is formed in the cavity 112 to fix the integrated capacitor structure 118. The insulating filler 120 may be formed by filling the space between the cavity 112 and the integrated capacitor structure 118 with an insulating material (eg, resin).

[0075] Due to the characteristics of the insulating filler 120, the thickness D3 of the insulating filler 120 may be equal to or less than 0.6 mm. Therefore, the top surface of the insulating filler 112 may be lower than the top surface 102b of the core structure 102. The thickness D3 of the insulating filler 120 may be less than the thickness D1 of the core structure 102, and may be less than the thickness D2 of the integrated capacitor structure 118. In other words, the insulating filler 120 may surround the bottom of the integrated capacitor structure 118 and may expose the top of the integrated capacitor structure 118.

[0076] Then, if Figure 1C As shown, a plurality of vias 106 are formed on the sidewalls of the opening 104, according to some embodiments. The vias 106 may be formed by plating at least the sidewalls of the opening 104 with a metal, including copper, silver, gold, etc., alloys thereof, or combinations thereof.

[0077] Afterwards, according to some embodiments, an insulating filler 108 is formed in each through hole 106. The insulating filler 108 may be formed by filling an insulating material, such as a resin, in a space surrounded by the through hole 106. Then, grinding may be performed to remove excess insulating material to form a flat surface. The bottom surface of the insulating filler 108 and the bottom surface of the insulating filler 112 may be substantially coplanar with the bottom surface 102a of the core structure 102.

[0078] Afterwards, if Figure 1DAs shown, a plurality of metal layers 110 are formed on the opposite surfaces of the insulating filler 108 and the integrated capacitor structure 118 by electroplating or any suitable method, according to some embodiments. The metal layer 110 can be made of a material similar to that of the via 106, including copper, silver, gold, etc., alloys thereof, or combinations thereof.

[0079] Then, a dielectric layer 122 fills the remaining space in the cavity 112, according to some embodiments. The dielectric layer 122 may surround the top of the integrated capacitor structure 118 and may contact the insulating filler 120. The dielectric layer 122 may be a construction film and may be made of a dielectric material, including Ajinomoto construction film (ABF) or other suitable materials. The dielectric layer 122 may be formed by a lamination process, a coating process or other suitable processes.

[0080] An additional dielectric layer 122 may be formed on the opposite surface of the core structure 102 and may be patterned to form an opening therein (not shown). The opening may be a through hole or a trench. Then, a routing layer 124 is formed in the opening. The routing layer 124 may include horizontal interconnects, such as conductive layers or conductive pads, and vertical interconnects, such as conductive vias. The conductive vias may electrically connect conductive layers and conductive pads at different levels. The routing layer 124 may be formed by electroplating or any suitable method. The routing layer 124 may be made of a material similar to the through hole 106, including copper, silver, gold, etc., alloys thereof, or combinations thereof.

[0081] Routing layer 124 may be electrically connected to via 106 and integrated capacitor structure 118. Dielectric layer 122 and routing layer 124 may be referred to as redistribution layer 126. Redistribution layers 126 on opposite surfaces of core structure 102 may be electrically connected to each other through via 106.

[0082] Then, a solder resist layer 128 is formed on the dielectric layer 122 to protect the redistribution layer from external damage, according to some embodiments. A package substrate 101 is formed.

[0083] Afterwards, if Figure 1E As shown, a plurality of openings may be formed in solder resist 128 by a photolithography process or any suitable method to expose the conductive pads of routing layer 124. Then, a plurality of solder connectors 134 are formed in the openings and may contact the conductive pads of routing layer 124. Solder connectors 134 may include solder balls or other conductive connectors. Solder connectors 134 may be placed in a grid array of rows and columns by a printing process or any suitable method.

[0084] Afterwards, according to some embodiments, semiconductor chips 130 and 132 are placed on the package substrate 101. A plurality of conductive connectors 136 may be formed under the semiconductor chips 130 and 132 to connect the solder connectors 134. The semiconductor chips 130 and 132 may be electrically connected to the routing layer 124 through the solder connectors 134 and the conductive connectors 136.

[0085] The conductive connector 136 may include a micro flip chip, a controlled collapse chip connection (C4) flip chip, a conductive pillar, etc., or a combination thereof. The conductive connector 136 may be made of a metal such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, etc., alloys thereof, or combinations thereof.

[0086] In some embodiments, each of the semiconductor chips 130 and 132 independently includes a system-on-chip (SoC) chip, a logic device, a memory, a radio frequency (RF) device, etc., or a combination thereof. For example, the semiconductor chips 130 and 132 may include a microcontroller unit (MCU) chip, a microprocessor unit (MPU) chip, a power management integrated circuit (PMIC) chip, a radio frequency front end (RFFE) chip, an accelerated processing unit (APU) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input output (IO) chip, a dynamic random access memory (DRAM) controller, a static random access memory (SRAM), a high bandwidth memory (HBM), an application processor (AP) chip, an application specific integrated circuit (ASIC) chip, etc., or a combination thereof.

[0087] The integrated capacitor structure 118 can be electrically connected to the semiconductor chip 130 and / or the semiconductor chip 132 through the routing layer 124 and the through hole 108. The integrated capacitor structure 118 can be placed closer to the semiconductor chip that needs more power to prevent voltage drop, such as the semiconductor chip 132. In other words, the integrated capacitor structure 118 can be placed directly below the semiconductor chip 130 or the semiconductor chip 132. For example, Figure 1E As shown, the semiconductor chip 132 may vertically overlap the integrated capacitor structure 118 .

[0088] It should be noted that the two semiconductor chips 130 and 132 are only for illustration purposes, and more semiconductor chips may be placed on the package substrate 101. In addition, one or more passive components (such as resistors, capacitors, or inductors) may also be placed on the package substrate 101.

[0089] A plurality of conductive terminals 138 are disposed on the surface of the package substrate 101 opposite to the semiconductor chips 130 and 132, and according to some embodiments, a semiconductor package structure 100 is formed. The conductive terminals 138 may include micro flip-chip, controlled collapse chip connection (C4) flip-chip, solder balls, ball grid array (BGA) balls, the like, or a combination thereof. The conductive terminals 138 may be made of metal, such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, alloys thereof, or a combination thereof. The conductive terminals 138 may be electrically connected to the wire layer 124.

[0090] FIG. 2A to FIG. 2C are cross-sectional views of various stages in the manufacture of a semiconductor package structure according to certain embodiments of the present disclosure. Figure 2A exist Figure 1A After the process steps are shown, the same or similar reference numbers are used to describe the same or similar components as the semiconductor package structure 100, so for the sake of simplicity, these components will not be discussed in detail. In the following embodiments, the process order is adjusted.

[0091] like Figure 2A As shown, after the opening 104 and the groove 112 are formed, according to some embodiments, a plurality of through holes 106 are formed on the sidewalls of the opening 104 .

[0092] Then, if Figure 2B As shown, an integrated capacitor structure 118 is disposed in the recess 112 according to some embodiments.

[0093] Afterwards, if Figure 2C As shown, according to some embodiments, an insulating filler 108 is formed in each through hole 106, and an insulating filler 120 is formed in the groove 112. Then, grinding can be performed to remove excess insulating material to form a flat surface. Then, reference Figure 1D and Figure 1E The process described is to continue to manufacture the semiconductor package structure. These process sequences are only examples, and other process sequences are also possible.

[0094] Figure 3 is a cross-sectional view of a semiconductor package structure 300 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 300 may include Figure 1E For simplicity, the components of the semiconductor package structure 100 shown are not discussed in detail. In the following embodiments, an integrated capacitor structure includes a dummy chip.

[0095] like Figure 3As shown, the integrated capacitor structure 118 includes a dummy chip 202 and a vertically stacked capacitor 116, according to some embodiments. The dummy chip 202 and the capacitor 116 can be bonded using a glue layer 115 or by fusion bonding, hybrid bonding, or any suitable method. By including the dummy chip 202, the thickness of the embedded integrated capacitor structure 118 can be increased, thereby increasing the thickness of the core structure 102. Therefore, the warping of the package substrate 101 can be reduced.

[0096] The thickness and width of dummy chip 202 and the thickness and width of capacitor 116 may be substantially the same as shown, or may be different. The thickness of dummy chip 202 may be adjusted according to the desired thickness of core substrate 102 .

[0097] Figure 4 is a cross-sectional view of a semiconductor package structure 400 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 400 may include Figure 1E For simplicity, the components of the semiconductor package structure 100 shown are the same or similar, and these components will not be discussed in detail. In the following embodiments, the thickness of the core structure is greater than the thickness of the integrated capacitor structure.

[0098] like Figure 4 As shown, the thickness D1 of the core structure 102 can be further increased to be greater than the thickness D4 of the integrated capacitor structure 118. Therefore, the warpage of the package substrate 101 can be further reduced. The thicknesses D5 and D6 of the capacitor 114 and the capacitor 116 may be different as shown, or may be substantially the same. The dielectric layer 122 and the wire layer 124 can be formed above the integrated capacitor structure 118 and in the core structure 102.

[0099] The integrated capacitor structure 118 may include a dummy chip, for example, the capacitor 114 or the capacitor 116 may be replaced by a dummy chip, similar to the reference Figure 3 described.

[0100] Figure 5 is a cross-sectional view of a semiconductor package structure 500 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 500 may include Figure 1E For simplicity, the components of the semiconductor package structure 100 are the same or similar, and will not be discussed in detail. In the following embodiments, an integrated capacitor structure includes capacitors with different sizes.

[0101] like Figure 5As shown, integrated capacitor structure 118 includes two vertically stacked capacitors 114 and 116 having different sizes, according to certain embodiments. Capacitors 114 and 116 can be bonded using glue layer 115 or by fusion bonding, hybrid bonding, or any suitable method. For example, the size (e.g., width) of capacitor 114 may be larger than the size (e.g., width) of capacitor 116. Insulating filler 120 may cover the top surface of capacitor 114. The width of glue layer 115 may be substantially equal to the width of capacitor 116 and may be smaller than the width of capacitor 114.

[0102] According to some embodiments, the thickness of capacitors 114 and 116 may also be different, similar to the reference Figure 4 described.

[0103] The integrated capacitor structure 118 may include a dummy chip, for example, the capacitor 114 or the capacitor 116 may be replaced by a dummy chip, similar to the reference Figure 3 described.

[0104] Figure 6 and Figure 7 is a cross-sectional view of semiconductor package structures 600 and 700 according to some embodiments of the present disclosure. It should be noted that each semiconductor package structure 600 and 700 may include Figure 1E For simplicity, the components of the semiconductor package structure 100 are the same or similar, and will not be discussed in detail. In the following embodiments, an integrated capacitor structure includes one or more through holes in a capacitor.

[0105] like Figure 6 As shown, an integrated capacitor structure 118 includes one or more vias 302, according to some embodiments. Vias 302 can be disposed in capacitor 116 and can be electrically connected to capacitor 114. Vias 302 can be made of metal, including tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, alloys thereof, or combinations thereof. Thus, capacitors 114 and 116 can be assembled face-to-face or back-to-back. For example, as Figure 6 As shown, the front side surface 114f of the capacitor 114 can be bonded to the front side surface 116f of the capacitor 116. As another example, Figure 7 As shown, the front side surface 114 f of the capacitor 114 may be bonded to the back side surface 116 b of the capacitor 116 .

[0106] Capacitors 114 and 116 may be bonded using fusion bonding, hybrid bonding, or any suitable method. In some embodiments, capacitors 114 and 116 are assembled face to face and are electrically connected to semiconductor chip 130 and / or semiconductor chip 132 through vias 302 and routing layer 124, such as Figure 6In some other embodiments, capacitors 114 and 116 are assembled face to back, capacitor 114 is electrically connected to semiconductor chip 130 and / or semiconductor chip 132 through via 302 and routing layer 124, and capacitor 116 is electrically connected to semiconductor chip 130 and / or semiconductor chip 132 through routing layer 124, as shown. Figure 7 shown.

[0107] Although as shown, capacitors 114 and 116 are substantially the same size, capacitors 114 and 116 may be different sizes, such as Figure 5 As discussed in .

[0108] Figure 8 is a cross-sectional view of a semiconductor package structure 800 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 800 may include Figure 1E For simplicity, these components will not be discussed in detail. In the following embodiments, an integrated capacitor structure includes a dummy chip disposed above a capacitor.

[0109] like Figure 8 As shown, according to some embodiments, an integrated capacitor structure 118 includes a dummy chip 202 disposed above the capacitor 114. The capacitor 114 and the dummy chip 202 can be bonded using fusion bonding, hybrid bonding, or any suitable method. The integrated capacitor structure 118 may include one or more through-holes 302 disposed in the dummy chip 202 and electrically connected to the capacitor 114. Therefore, the capacitor 114 can be electrically connected to the semiconductor chip 130 and / or the semiconductor chip 132 through the through-holes 302 and the routing layer 124.

[0110] In summary, the semiconductor package structure according to the present disclosure includes an integrated capacitor structure embedded in a core structure of a package substrate. The integrated capacitor structure includes stacked capacitors. Therefore, the thickness of the core structure can be increased, thereby reducing the warping of the package substrate. In addition, the decoupling performance can be improved.

[0111] Although the present invention has been described in an exemplary manner and according to a preferred embodiment, it should be understood that the invention is not limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements (which will be obvious to those skilled in the art). Therefore, the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor packaging structure, comprising: A package substrate includes: A core structure; an integrated capacitor structure embedded in the core structure; and a redistribution layer disposed on the integrated capacitor structure; and A semiconductor chip is disposed on the packaging substrate and electrically connected to the integrated capacitor structure through the redistribution layer. 2 . The semiconductor package structure as claimed in claim 1 , further comprising an insulating filler located in the core structure and surrounding a bottom of the integrated capacitor structure. 3 . The semiconductor package structure as claimed in claim 2 , wherein a thickness of the insulating filler is smaller than a thickness of the core structure.

4. The semiconductor package structure according to claim 1, wherein the package substrate further comprises: A dielectric layer surrounds the redistribution layer and surrounds the top of the integrated capacitor structure. 5 . The semiconductor package structure as claimed in claim 1 , wherein a bottom surface of the integrated capacitor structure is substantially aligned with a bottom surface of the core structure. 6 . The semiconductor package structure of claim 5 , wherein a top surface of the integrated capacitor structure is substantially aligned with a top surface of the core structure. 7 . The semiconductor package structure as claimed in claim 1 , wherein the integrated capacitor structure comprises a plurality of capacitors assembled back to back. 8 . The semiconductor package structure of claim 7 , wherein the plurality of capacitors are bonded using a glue layer, fusion bonding, or hybrid bonding.

9. The semiconductor package structure according to claim 1, wherein the integrated capacitor structure comprises: a first capacitor; as well as A second capacitor is disposed above the first capacitor and includes a through hole penetrating through the first capacitor and electrically connecting the second capacitor to the redistribution layer. 10 . The semiconductor package structure according to claim 9 , wherein the first capacitor and the second capacitor are bonded using fusion bonding or hybrid bonding.

11. The semiconductor package structure as claimed in claim 9, wherein the integrated capacitor structure comprises a dummy chip and vertically stacked capacitors. 12 . The semiconductor package structure as claimed in claim 11 , wherein the dummy chip is disposed above the capacitor and comprises a through hole penetrating through the capacitor and electrically connected to the redistribution layer.

13. A semiconductor packaging structure, comprising: A package substrate includes: A core structure; A first capacitor and a second capacitor are vertically stacked and embedded in the core structure; a first insulating filler disposed in the core structure and surrounding the first capacitor and the second capacitor; a first redistribution layer disposed below the core structure; and A second redistribution layer is disposed above the core structure and electrically connected to the first capacitor and the second capacitor.

14. The semiconductor package structure according to claim 13, further comprising: A through hole passes through the core structure and electrically connects the first redistribution layer and the second redistribution layer.

15. The semiconductor package structure according to claim 14, further comprising: a second insulating filler formed in the through hole, The top surface of the second insulating filler is higher than the top surface of the first insulating filler. 16 . The semiconductor package structure according to claim 13 , wherein the first capacitor is electrically connected to the first redistribution layer. 17 . The semiconductor package structure according to claim 13 , wherein a size of the first capacitor is larger than a size of the second capacitor. 18 . The semiconductor package structure according to claim 17 , wherein the first insulating filler extends to a top surface of the first capacitor. 19 . The semiconductor package structure according to claim 13 , wherein a top surface of the first insulating filler is lower than a top surface of the second capacitor.

20. The semiconductor package structure according to claim 13, wherein the second redistribution layer is partially disposed in the core structure.

Images