Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application relates to a semiconductor structure preparation method and a semiconductor structure, which comprises the following steps: providing an initial plastic sealing structure, the initial plastic sealing structure comprising a first carrier plate, a first bonding layer, a first circuit layer, a first chip and a plastic sealing layer which are stacked in sequence along a first direction; part of first connectors of the first circuit layer are electrically connected with second connectors of the first chip; the first chip comprises the second connectors and a semiconductor layer wrapping the second connectors; part of the plastic sealing layer and part of the semiconductor layer are removed along the first direction until the second connectors are exposed; after forming a second circuit layer on the plastic sealing layer, a second carrier plate is formed on the second circuit layer, the second circuit layer is electrically connected with the second connectors; the first carrier plate and the first bonding layer are removed, the first circuit layer is exposed, and the first circuit layer is used for electrical connection with at least one second chip, so that the bearing pressure of a single circuit is reduced, and the yield of a semiconductor packaging product is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure preparation method and a semiconductor structure. BACKGROUND

[0002] Fan-out packaging technology is a commonly used packaging method in integrated circuit design. By connecting multiple transistors or other electronic components together, a small circuit module is formed and packaged in a package, thereby realizing the integration of functions and greatly reducing the volume of the package.

[0003] However, as the integration of the package increases, the bearing pressure of the single line in the package greatly increases. Therefore, how to reduce the bearing pressure of the single line in the package has become one of the technical problems to be solved. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor structure preparation method and a semiconductor structure to at least improve the yield and reliability of the semiconductor structure in view of the problem of high bearing pressure of the single line in the fan-out packaging integration in the prior art.

[0005] To achieve the above-mentioned purpose, on the one hand, the present application provides a semiconductor structure preparation method, comprising:

[0006] An initial plastic packaging structure is provided, which comprises a first carrier plate, a first bonding layer, a first circuit layer, a first chip and a plastic packaging layer stacked in a first direction; wherein the first direction is perpendicular to the top surface of the first carrier plate; part of the first connecting piece of the first circuit layer is electrically connected with the second connecting piece of the first chip; the first chip comprises the second connecting piece and a semiconductor layer wrapping the second connecting piece;

[0007] Part of the plastic packaging layer and part of the semiconductor layer are removed along the first direction until the second connecting piece is exposed;

[0008] After forming a second circuit layer on the plastic packaging layer, a second carrier plate is formed on the second circuit layer, and the second circuit layer is electrically connected with the second connecting piece;

[0009] The first carrier plate and the first bonding layer are removed to expose the first circuit layer, and the first circuit layer is used for electrical connection with at least one second chip.

[0010] In one of the embodiments, the part of the plastic packaging layer and the part of the semiconductor layer are removed along the first direction until the second connecting piece is exposed, comprising:

[0011] remove the plastic encapsulation layer and the semiconductor layer along the first direction until the second connecting member of the first chip is exposed;

[0012] remove part of the semiconductor layer along the first direction, so that the second connecting member protrudes from the remaining semiconductor layer, to remove the circuit material remaining on the semiconductor layer; wherein the circuit material is the same material as the second connecting member.

[0013] In one embodiment, the preparation method further comprises forming a plurality of metal pillars on the first circuit layer, the metal pillars being connected to the remaining first connecting members of the first circuit layer; and removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction until the second connecting member is exposed, comprising:

[0014] remove part of the plastic encapsulation layer and part of the semiconductor layer along the first direction, so that the remaining plastic encapsulation layer covers the metal pillars when the second connecting member of the first target height is exposed on the remaining semiconductor layer;

[0015] form a dielectric layer on at least the remaining semiconductor layer and the second connecting member of the first target height exposed;

[0016] remove part of the dielectric layer and part of the remaining plastic encapsulation layer along the first direction until the second connecting member and the metal pillars are exposed; the surface of the remaining dielectric layer is flush with the surface of the remaining plastic encapsulation layer.

[0017] In one embodiment, removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction, so that the remaining plastic encapsulation layer covers the metal pillars when the second connecting member of the first target height is exposed on the remaining semiconductor layer, comprises:

[0018] remove part of the plastic encapsulation layer and part of the semiconductor layer along the first direction using a grinding process, so that the remaining semiconductor layer and the remaining plastic encapsulation layer cover the second connecting member and the metal pillars, respectively;

[0019] remove part of the semiconductor layer along the first direction to expose the second connecting member of the first target height.

[0020] In one embodiment, the first target height is 10-15 microns.

[0021] In one embodiment, the method for providing an initial plastic encapsulation structure comprises:

[0022] providing a substrate, the substrate comprising a first carrier plate and the first bonding layer on the first carrier plate;

[0023] A first circuit layer is formed on the first bonding layer; wherein the first circuit layer includes a plurality of the first connectors;

[0024] A first chip is formed on the first circuit layer, and a second connector of the first chip is electrically connected to a portion of the first connector.

[0025] The molding layer is formed on the first circuit layer and the first chip.

[0026] In one embodiment, forming a second circuit layer includes:

[0027] A plurality of third connectors are formed on the molding layer; wherein the third connectors are at least electrically connected to the second connectors;

[0028] A solder pad is formed at the end of the third connector that faces away from the first carrier plate;

[0029] Solder joints are formed on the solder pads; the side of the solder joint facing away from the first carrier plate is used to fix it to the second carrier plate.

[0030] In one embodiment, forming a second carrier plate includes:

[0031] A protective layer is formed on the solder joint;

[0032] The side of the protective layer facing away from the first carrier plate is fixed to the second carrier plate.

[0033] Secondly, this application also provides a semiconductor structure, including: a second substrate, a molding compound, a first chip, a first circuit layer, and a second circuit layer; the molding compound is located on the second substrate, and the molding compound includes at least one first chip; wherein, the first chip includes a second connector and a semiconductor layer encapsulating the second connector; the second connector is electrically connected to the second circuit layer; the first circuit layer is located on the first chip and the molding compound; a portion of the first connector of the first circuit layer is electrically connected to the second connector; the first circuit layer is used for electrical connection with at least one second chip; the second circuit layer is located on the molding compound and is electrically connected to the second connector; the second substrate is located on the second circuit layer.

[0034] In one embodiment, the height by which the second connector protrudes from the semiconductor layer is a first target height; the semiconductor structure further includes:

[0035] A dielectric layer, located between the second substrate and the semiconductor layer, surrounds the second connector at the first target height; the surface of the dielectric layer near the second substrate is flush with the surface of the molding compound near the second substrate.

[0036] The method for manufacturing the semiconductor structure and the semiconductor structure have the following beneficial effects:

[0037] The method for manufacturing the semiconductor structure and the semiconductor structure, comprising: providing an initial plastic sealing structure, the initial plastic sealing structure comprising a first carrier plate, a first bonding layer, a first circuit layer, a first chip and a plastic sealing layer which are stacked in sequence along a first direction; wherein the first direction is a direction perpendicular to a top surface of the first carrier plate; a part of the first connecting members of the first circuit layer is electrically connected with a second connecting member of the first chip; the first chip comprises the second connecting member and a semiconductor layer wrapping the second connecting member; a part of the plastic sealing layer and a part of the semiconductor layer are removed along the first direction until the second connecting member is exposed; wherein the second connecting member protrudes from the remaining semiconductor layer; a second carrier plate is formed on the plastic sealing layer, and the second carrier plate is electrically connected with the second connecting member; the first carrier plate and the first bonding layer are removed to expose the first circuit layer, and the first circuit layer is used to be electrically connected with at least one second chip. By providing the initial plastic sealing structure, the initial plastic sealing structure comprises the first circuit layer and the first chip, and a part of the first connecting members of the first circuit layer is electrically connected with the second connecting member of the first chip, the first circuit layer is electrically connected with at least one second chip, and the second connecting member of the first chip is also electrically connected with the second circuit layer, the first chip is directly connected with the second circuit layer and the second chip respectively, the number of circuits is increased, and the bearing pressure of a single circuit is reduced. In addition, in the embodiment of the present application, after a part of the plastic sealing layer and a part of the semiconductor layer are removed and the second connecting member of the first chip is exposed, the second circuit layer electrically connected with the second connecting member is formed on the plastic sealing layer, the second carrier plate is formed on the second circuit layer, then the first carrier plate and the first bonding layer are removed by debonding to expose the first circuit layer, and then the second chip is formed on the first circuit layer, that is, the second chip is formed after the step of removing the first carrier plate and the first bonding layer by debonding, compared with the step of removing the first carrier plate and the first bonding layer by debonding after the second chip is formed, the embodiment avoids the adverse effects of the debonding process on the second chip, and effectively improves the yield and reliability of the semiconductor structure.

[0038] Further, the second connecting member can be partially protruded from the remaining semiconductor layer to form a groove, and a dielectric layer covering the top surface of the second connecting member is filled in the groove, so that in the process of planarizing the top surface of the dielectric layer, the circuit material is prevented from diffusing into the remaining semiconductor layer, and thus when the second connecting member is electrically connected with the second circuit layer, the devices, circuit materials and the like in the semiconductor layer are not electrically connected, thereby avoiding short circuit. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0040] Figure 1 Flow chart of the method for manufacturing the semiconductor structure provided in an embodiment;

[0041] Figures 2a-2j Cross-sectional schematic view of the semiconductor structure provided in an embodiment;

[0042] Figure 3 Flow chart of step S102 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0043] Figures 4a-4h Cross-sectional schematic view of the structure obtained in step S102 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0044] Figure 5 Flow chart of step S104 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0045] Figures 6a-6e Cross-sectional schematic view of the structure obtained in step S104 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0046] Figure 7 Flow chart of step S106 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0047] Figures 8a-8c Cross-sectional schematic view of the structure obtained in step S106 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0048] Figure 9 Flow chart of step S104 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0049] Figures 10a-10c Cross-sectional schematic view of the structure obtained in step S108 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0050] Reference signs and descriptions:

[0051] 101, first carrier plate; 102, protective layer; 103, second carrier plate; 20, first bonding layer; 40, first chip; 401, adhesive layer; 402, semiconductor layer; 403, internal connection; 404, second connection; 301, first dielectric layer; 302, metal column; 303, first connection; 501, first plastic sealing layer; 502, second plastic sealing layer; 503, plastic sealing layer; 60, first redistribution layer; 601, second dielectric layer; 602, first metal layer; 603, pad; 701, second chip; 702, adhesive layer; 80, second redistribution layer; 801, third dielectric layer; 802, second metal layer; 803, solder point; 804, third connection; 805, fourth dielectric layer; 90, dielectric layer. DETAILED DESCRIPTION

[0052] For the purpose of facilitating an understanding of the present application, a more complete appreciation of the application will be had by reference to the following detailed description and the accompanying drawings. The preferred embodiments of the application are illustrated in the drawings. However, the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0054] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be p-type and a second doped type can be n-type, or the first doped type can be n-type and the second doped type can be p-type.

[0055] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0056] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Also, as used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0057] Embodiments of the application are described herein with reference to the drawings, which show ideal embodiments (and intermediate structures) of the application as schematic cross-sectional views. Variations in the shapes of the regions shown are to be expected as a result, for example, of manufacturing processes and / or tolerances, and are to be considered within the scope of the application. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation can result in some implantation in a region between the buried region and the surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.

[0058] In one embodiment, referring to Figure 1 The application provides a method for manufacturing a semiconductor structure, comprising steps S102-S108.

[0059] Step S102: providing an initial plastic package structure, the initial plastic package structure comprising a first carrier plate, a first bonding layer, a first circuit layer, a first chip and a plastic package layer stacked in sequence along a first direction; wherein the first direction is a direction perpendicular to a top surface of the first carrier plate; a part of first connectors of the first circuit layer are electrically connected with second connectors of the first chip; the first chip comprises the second connectors and a semiconductor layer wrapping the second connectors.

[0060] As an example, the material of the first carrier plate can comprise one of glass, metal, semiconductor, polymer and ceramic; in other embodiments, the application does not limit the material and shape of the first carrier plate, which is used to support the film layers formed subsequently.

[0061] As an example, the material of the first bonding layer can comprise a double-sided adhesive tape or an adhesive layer. The application does not limit the material of the first bonding layer, as long as it can satisfy the requirement of bonding the first carrier plate and the first circuit layer.

[0062] As an example, the first circuit layer can comprise one circuit layer, for example, a stack of one dielectric layer and one metal layer; the first circuit layer can also comprise multiple circuit layers, for example, a stack of multiple dielectric layers and multiple metal layers. In other embodiments, the application does not limit the number of layers of the first circuit layer, which is used to connect the chips or other circuit layers on both sides of the first circuit layer along the first direction.

[0063] As an example, the first chip can include a bridge chip, a system on chip (SOC) high bandwidth memory (HBM), etc. In other embodiments, the present application does not specifically limit the type of the first chip, and the first chip is used to implement a certain function.

[0064] As an example, the material of the plastic package layer can include one or a combination of a polyimide layer (PI), a silica gel layer, and an epoxy resin layer. The present application does not specifically limit the material of the first plastic package layer.

[0065] As an example, the material of the first connecting member and the second connecting member can include one or more of a metal material such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0066] As an example, the material of the semiconductor layer can include one or more of a silicon (Si) material, a silicon germanium (SiGe) material, a silicon germanium carbon (SiGeC) material, a silicon carbide (SiC) material, a gallium arsenide (GaAs) material, an indium arsenide (InAs) material, an indium phosphide (InP) material, or other III / V semiconductor materials or II / VI semiconductor materials. The second connecting member is located in the semiconductor layer, and one end of the second connecting member is exposed outside the semiconductor layer. The surface of the semiconductor layer exposing the one end of the second connecting member is the active surface of the first chip.

[0067] Step S104: removing part of the plastic package layer and part of the semiconductor layer in the first direction until the second connecting member is exposed.

[0068] As an example, one or more of a grinding process, dry etching, and wet etching can be used to remove part of the plastic package layer and part of the semiconductor layer. The one end of the second connecting member protruding from the remaining semiconductor layer away from the first carrier plate.

[0069] Step S106: after forming the second wiring layer on the plastic package layer, forming a second carrier plate on the second wiring layer, and the second wiring layer is electrically connected with the second connecting member.

[0070] As an example, the second carrier plate can be a single-layer structure including a carrier plate, or a multi-layer structure including different film layers.

[0071] Step S108: removing the first carrier plate and the first bonding layer to expose the first wiring layer, and the first wiring layer is used to electrically connect with at least one second chip.

[0072] As an example, the adhesion of the first bonding layer can be reduced by exposure, so that the first carrier plate and the first bonding layer are removed without damaging other film layers. The specific method for removing the first carrier plate and the first bonding layer is not limited in the present application, and can be selected according to the material of the first bonding layer.

[0073] As an example, the second chip can include a bridge chip, a system on chip (SOC) high bandwidth memory (HBM), and the like. In other embodiments, the type of the second chip is not specifically limited in the present application, and the second chip is used to implement a certain function.

[0074] In the above embodiments, the present application provides an initial plastic package structure, which includes a first circuit layer and a first chip, and part of the first connecting members of the first circuit layer are electrically connected with the second connecting members of the first chip. The first circuit layer is electrically connected with at least one second chip, and the second connecting members of the first chip are further electrically connected with a second circuit layer. The first chip is directly connected with the second carrier plate and the second chip, respectively, which increases the number of circuits and reduces the load pressure of a single circuit. Meanwhile, the present application makes the second connecting members protrude from the remaining semiconductor layers, so that the circuit material generated in the process of exposing the second connecting members will not spread into the remaining semiconductor layers. Therefore, when the second connecting members are electrically connected with the second circuit layer, the devices, circuit materials, second connecting members, and the like in the semiconductor layers will not be electrically connected, thereby avoiding the formation of short circuits.

[0075] In addition, in some related technologies, please refer to Figures 2a-2jThe method for manufacturing the semiconductor structure can further include: providing the first carrier substrate 101, forming the first bonding layer 20 on the first carrier substrate 101, bonding the back surface (i.e., the surface opposite to the active surface) of the at least one first chip 40 to the first bonding layer 20 by using the adhesive layer 401, and forming the first dielectric layer 301 and the plurality of metal pillars 302 on the first bonding layer 20, wherein the first chip 40 includes the internal connection 403 and the semiconductor layer 402 wrapping the internal connection, forming the first encapsulation layer 501 on the first bonding layer 20, the first chip 40, and the metal pillars 302, removing part of the first encapsulation layer 501 in a direction perpendicular to the top surface of the first carrier substrate to expose the connection pins of the active surface of the first chip 40 and the metal pillars 302, forming the first redistribution layer 60 on the remaining first encapsulation layer 501, the first redistribution layer 60 including the second dielectric layer 601, the first metal layer 602, and the pads 603; the first redistribution layer 60 is connected to the connection pins of the first chip 40 and the metal pillars 302, forming the at least one second chip 701 on the first redistribution layer 60, the pads 603 of the second chip 701 being connected to the pads 603 of the first redistribution layer 60, wrapping the pads 603 by using the adhesive layer 702, forming the second encapsulation layer 502 on the first redistribution layer 60 and the second chip 701, flipping the semiconductor structure, removing the first bonding layer 20 and the first carrier substrate 101 to expose the back surface of the first chip 40, removing part of the first encapsulation layer 501 and the adhesive layer 401 to expose the metal pillars 302, forming the second redistribution layer 80 and the plurality of solder joints 803 on the remaining first encapsulation layer 501, the second redistribution layer 80 including the third dielectric layer 801 and the second metal layer 802, the second metal layer 802 being connected to the metal pillars 302 and the plurality of solder joints 803, respectively. In the above example, since the performance of the semiconductor device is easily degraded due to high temperature during the process of removing the first bonding layer 20 and forming the solder joints 803, and the production cost of the second chip 701 is relatively high, the process of forming the second chip 701 first and then removing the first bonding layer 20 and forming the solder joints 803 greatly increases the probability of scrapping the second chip 701, resulting in an increase in the manufacturing cost of the semiconductor structure. In the present application, the second chip 701 is connected to the first circuit layer after the first carrier substrate 101 and the first bonding layer 20 are removed, which greatly reduces the probability of scrapping the second chip 701 and saves the production cost.

[0076] Please refer to Figure 3 In one embodiment, the step S102 of providing the initial encapsulation structure includes steps S302-S308.

[0077] The step S302 includes providing a substrate including a first carrier substrate and a first bonding layer on the first carrier substrate.

[0078] As an example, please refer to Figure 4aand Figure 4b The step S302 can further include a step of forming a reflective layer (not shown) on the first bonding layer 20; wherein the material of the reflective layer can include one or more of cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al) and the like. In the above example, by forming the reflective layer on the first bonding layer 20, the reflection can be enhanced when the first bonding layer 20 is removed, thereby improving the efficiency of removing the first bonding layer 20.

[0079] The step S304 includes forming a first circuit layer on the first bonding layer; wherein the first circuit layer includes a plurality of first connecting members.

[0080] As an example, please refer to Figure 4c and Figure 4d The step S304 of forming the first circuit layer on the first bonding layer 20 can include: forming a first dielectric layer 301 on the first bonding layer 20, the first dielectric layer 301 including a plurality of openings exposing the first bonding layer 20; forming a plurality of first connecting members 303 on the first bonding layer 20 and the first dielectric layer 301 exposed by the openings; forming a second dielectric layer 601 on the plurality of first connecting members 303 and the first dielectric layer 301, the second dielectric layer 601 including a plurality of openings exposing the plurality of first connecting members 303; the first dielectric layer 301, the plurality of first connecting members 303 and the second dielectric layer 601 are used to jointly constitute the first circuit layer.

[0081] The step S306 includes forming a first chip on the first circuit layer, the second connecting members of the first chip being electrically connected with the first connecting members.

[0082] As an example, please refer to Figures 4e-4g Before the second connecting members 404 of the first chip 40 are electrically connected with the first connecting members 303, the step of forming a pad 603 on the first connecting members 303 exposed by the part of the openings is further included. By forming the pad 603 on one end of the second connecting members 404 exposed by the active surface of the first chip 40, the pad 603 on the first chip 40 is connected with the pad 603 on the first connecting members 303 by soldering technology such as reflow soldering, so that the second connecting members 404 of the first chip 40 are electrically connected with the first connecting members 303.

[0083] The step S308 includes forming a plastic encapsulation layer on the first circuit layer and the first chip.

[0084] As an example, please refer to Figure 4g and Figure 4hBefore forming the plastic layer 503 on the first circuit layer and the first chip 40, a bottom filling glue process can be used to form a glue layer 702 between the active surface of the first chip 40 and the first circuit layer, and the glue layer 702 wraps the pads 603, the solder joints 605 on the first chip 40 and the pads 603 on the first connecting elements 303, thereby enhancing the stability of the connection between the first chip 40 and the first circuit layer.

[0085] In one embodiment, the preparation method further comprises: forming a plurality of metal columns on the first circuit layer, the metal columns being connected with the remaining first connecting elements of the first circuit layer; and in addition, the plastic layer covers the plurality of metal columns.

[0086] As an example, please continue to refer to Figure 4h The material of the metal column 302 can include one or more of cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al).

[0087] In one embodiment, please refer to Figure 5 In step S304, part of the plastic layer and part of the semiconductor layer are removed along the first direction until the second connecting elements are exposed, comprising steps S502-S506.

[0088] In step S502, part of the plastic layer and part of the semiconductor layer are removed along the first direction, and in the case that the remaining semiconductor layer exposes the second connecting elements of the first target height, the remaining plastic layer covers the metal column.

[0089] In one embodiment, in step S502, part of the plastic layer and part of the semiconductor layer are removed along the first direction, and in the case that the remaining semiconductor layer exposes the second connecting elements of the first target height, the remaining plastic layer covers the metal column, comprising: using a grinding process to remove part of the plastic layer and part of the semiconductor layer along the first direction, so that the remaining semiconductor layer and the remaining plastic layer cover the second connecting elements and the metal column; and using a dry etching process to remove part of the semiconductor layer along the first direction to expose the second connecting elements of the first target height.

[0090] Please refer to Figure 6a and Figure 6bAs an example, the removal thickness of the plastic layer 503 and the semiconductor layer 402 in the first direction is the same at the same time by the grinding process. Part of the plastic layer 503 and part of the semiconductor layer 402 are removed in the first direction by the grinding process, so that the remaining semiconductor layer 402 and the remaining plastic layer 503 cover the second connecting piece 404 and the metal pillar 302. After the grinding process, the surface of the remaining semiconductor layer 402 away from the first carrier plate is higher than the surface of the second connecting piece 404 away from the first carrier plate, and the second target distance B between the surface of the remaining semiconductor layer 402 away from the first carrier plate and the surface of the second connecting piece 404 away from the first carrier plate is 5-15 microns.

[0091] As an example, the second target distance B is 5 microns, 8 microns, 10 microns, 12 microns, 13 microns, 14 microns, 15 microns, etc.

[0092] As an example, the dry etching at least includes any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-density plasma etching (HDP).

[0093] In one embodiment, the first target height A is 10-15 microns.

[0094] As an example, please refer to Figure 6c The first target height A is 10 microns, 11 microns, 12 microns, 13 microns, 14 microns, 15 microns.

[0095] In the above embodiment, by first removing part of the plastic layer 503 and part of the semiconductor layer 402 in the first direction by the grinding process, so that the remaining semiconductor layer 402 and the remaining plastic layer 503 do not expose the second connecting piece 404 and the metal pillar 302, and then removing part of the semiconductor layer 402 in the first direction by the dry etching process, exposing the second connecting piece 404 of the first target height A, on the one hand, compared with the dry etching process, the grinding process is shorter in time, which can improve the removal efficiency of the plastic layer 503 and the semiconductor layer 402, on the other hand, it can avoid the grinding process to produce line material in the process of removing the semiconductor layer 402 and exposing the second connecting piece 404, which causes the line material in the semiconductor layer 402 to diffuse into the remaining semiconductor layer 402, causing the line material in the semiconductor layer 402 and the device and line structure in the semiconductor layer 402 to form a short circuit structure in the process of connecting the second connecting piece 404 and the second line layer.

[0096] Step S504: Forming a dielectric layer on at least the remaining semiconductor layer and the second connecting piece exposed to the first target height.

[0097] As an example, please refer to Figure 6dThe material of the dielectric layer 90 can include, but is not limited to, one or more of a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide (Al2O3), or a silicon oxynitride layer (SiON), etc.

[0098] As an example, the dielectric layer 90 has a thickness in the first direction that is greater than the first target height. In addition, the dielectric layer 90 can also cover the remaining molding layer 503.

[0099] As an example, a spin coating process can be used to form the dielectric layer 90 on the remaining semiconductor layer 402 and the second connecting member 404 exposed at the first target height.

[0100] Step S506: removing part of the dielectric layer and the remaining molding layer in the first direction until the second connecting member and the metal pillar are exposed; the surface of the remaining dielectric layer is flush with the surface of the remaining molding layer.

[0101] As an example, please refer to Figure 6e A grinding process can be used to remove part of the dielectric layer 90 and the remaining molding layer 503 in the first direction until the second connecting member 404 and the metal pillar 302 are exposed.

[0102] In the above embodiment, since the line material generated during the grinding process does not spread to the dielectric layer 90, and the dielectric layer 90 does not have other line structures or components, using the dielectric layer 90 to cover the remaining semiconductor layer 402 can avoid forming a short circuit structure.

[0103] In one embodiment, please refer to Figure 7 Step S106: forming a second line layer on the molding layer, including: steps S702-S708.

[0104] Step S702: forming a plurality of third connecting members on the molding layer; wherein the third connecting member is electrically connected to at least the second connecting member.

[0105] As an example, please refer to Figure 8a and Figure 8b The second line layer includes a third dielectric layer 801, a third connecting member 804, and a fourth dielectric layer 805.

[0106] Step S704: forming a pad on the end of the third connecting member away from the first carrier board.

[0107] As an example, please continue to refer to Figure 8b The pad 603 is electrically connected to the third connecting member 804.

[0108] Step S706: forming a solder joint on the pad, the side of the solder joint away from the first carrier board being used to fix the second carrier board.

[0109] As an example, please continue to refer toFigure 8b The soldering point 803 can be formed on the soldering pad 603 by using a reflow soldering process or a wave soldering process.

[0110] In one embodiment, forming the second carrier board comprises: forming a protective layer on the soldering point, and fixing the protective layer away from one side of the first carrier board to the second carrier board.

[0111] For example, referring to Figure 8c The material of the protective layer 102 can comprise an adhesive layer with adhesion, and the soldering point 803 and the second carrier board 103 are fixed by the adhesive layer.

[0112] In one embodiment, referring to Figure 9 In step S304, part of the plastic encapsulation layer and part of the semiconductor layer are removed along the first direction until the second connecting element is exposed, comprising steps S902-S904.

[0113] In step S902, a grinding process is used to remove the plastic encapsulation layer and the semiconductor layer along the first direction until the second connecting element of the first chip is exposed.

[0114] For example, the preparation method further comprises a step of forming a plurality of metal pillars on the first circuit layer, the metal pillars being connected to the remaining first connecting elements of the first circuit layer; and in step S092, the metal pillars are exposed at the same time as the second connecting element of the first chip is exposed.

[0115] In step S904, a dry etching process is used to remove part of the semiconductor layer along the first direction, so that the second connecting element protrudes from the remaining semiconductor layer, and the circuit material remaining in the semiconductor layer is removed; wherein the circuit material is the same as the material of the second connecting element.

[0116] In the above embodiment, since the grinding residue (i.e. the circuit material) of the second connecting element is generated in the process of exposing the second connecting element of the first chip, the circuit material will diffuse into the remaining semiconductor layer, and in the process of connecting the second connecting element and the second circuit layer, the circuit material in the semiconductor layer and the original components or connecting circuits in the semiconductor layer will be connected together to form a short circuit structure. Therefore, after the second connecting element is exposed, part of the semiconductor layer is removed by using a dry etching process to remove the circuit material remaining in the semiconductor layer, so as to avoid the formation of a short circuit structure, and in the process of forming the second circuit layer on the plastic encapsulation layer, the exposed second connecting element can be wrapped by the material such as the third medium layer in the process, so as to improve the flatness of each film layer.

[0117] In one embodiment, referring to Figures 10a-10cIn step S108, the first carrier plate and the first bonding layer are removed to expose the first circuit layer, and the first circuit layer is used to electrically connect with the at least one second chip. The method further comprises: removing the first bonding layer 20 and the first carrier plate 101 by using an exposure process to form a pad 603 on the exposed first connecting member 303, connecting the pad 603 on the active surface of the second chip 701 with the pad 603 on the first connecting member 303, and wrapping the pad 603 with a glue layer 702 to fix the second chip 701.

[0118] In the foregoing embodiment of the present application, the initial plastic sealing structure is provided, the initial plastic sealing structure comprises the first circuit layer and the first chip, and part of the first connecting member of the first circuit layer is electrically connected with the second connecting member of the first chip. The first circuit layer is electrically connected with the at least one second chip, and the second connecting member of the first chip is further electrically connected with the second circuit layer. The first chip is directly connected with the second circuit layer and the second chip respectively, the number of circuits is increased, and the bearing pressure of a single circuit is reduced. After the part of the plastic sealing layer and the part of the semiconductor layer are removed to expose the second connecting member of the first chip, the second circuit layer electrically connected with the second connecting member is formed on the plastic sealing layer, the second carrier plate is formed on the second circuit layer, and then the first carrier plate and the first bonding layer are removed by debonding to expose the first circuit layer. Then, the second chip is formed on the first circuit layer, that is, the second chip is formed after the step of removing the first carrier plate and the first bonding layer by debonding. Compared with the step of removing the first carrier plate and the first bonding layer by debonding after the second chip is formed, the embodiment avoids the adverse effects of the debonding process on the second chip, and effectively improves the yield and reliability of the semiconductor structure.

[0119] Further, the second connecting member can be partially protruded from the remaining semiconductor layer to form a groove, and a dielectric layer covering the top surface of the second connecting member is filled in the groove. In the process of planarizing the top surface of the dielectric layer, the circuit material is prevented from diffusing into the remaining semiconductor layer, so that the devices, circuit materials, etc. in the semiconductor layer are not electrically connected when the second connecting member is electrically connected with the second circuit layer, thereby avoiding the formation of short circuits.

[0120] It should be understood that, although Figure 1 , Figure 3 , Figure 5 , Figure 7 , Figure 9 the steps in the flowchart of the present application are displayed in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figure 1 , Figure 3 , Figure 5 , Figure 7 , Figure 9At least one of the steps in the above method can comprise a plurality of steps or stages which are not necessarily performed at the same time but can be performed at different times and in which the order of the steps or stages is not necessarily sequential but can be performed in rotation or alternation with other steps or steps or stages of at least one of the other steps.

[0121] Reference is made to Figure 10c In one embodiment, the application further provides a semiconductor structure, comprising: a second carrier board 103, a plastic encapsulation layer 503, a first chip 40, a first circuit layer (not shown) and a second circuit layer (not shown); wherein the plastic encapsulation layer 503 is on the second carrier board 103, and the plastic encapsulation layer 503 comprises at least one first chip 40; wherein the first chip 40 comprises a second connecting member 404 and a semiconductor layer 402 wrapping the second connecting member 404; the first circuit layer is on the first chip 40 and the plastic encapsulation layer 503; part of the first connecting members 303 of the first circuit layer are electrically connected with the second connecting member 404; the first circuit layer is used to electrically connect with at least one second chip 701; the second circuit layer is on the plastic encapsulation layer 503, and the second circuit layer is electrically connected with the second connecting member 404; the second carrier board 103 is on the second circuit layer.

[0122] Reference is made to Figures 6c-6d In one embodiment, the height of the second connecting member 404 protruding from the semiconductor layer 402 is a first target height A; the semiconductor structure further comprises: a dielectric layer 90 between the second carrier board 103 and the semiconductor layer 402, and surrounding the second connecting member 404 of the first target height A; the surface of the dielectric layer 90 close to the second carrier board 103 is flush with the surface of the plastic encapsulation layer 503 close to the second carrier board 103.

[0123] In one embodiment, the first target height A is 10-15 microns.

[0124] As an example, the first target height A is 10 microns, 11 microns, 12 microns, 13 microns, 14 microns or 15 microns.

[0125] The technical features of the above embodiments can be combined in any manner. In order to make the description concise, not all possible combinations of the technical features of the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0126] The above embodiments only express several implementation ways of the present application, and the description is specific and detailed, but it should not be understood as a limitation to the patent scope of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The application relates to a method for manufacturing a semiconductor device, and the method comprises the following steps: providing an initial plastic sealing structure, wherein the initial plastic sealing structure comprises a first carrier plate, a first bonding layer, a first circuit layer, a first chip and a plastic sealing layer which are sequentially formed and stacked along a first direction; the first direction is perpendicular to the top surface of the first carrier plate; part of the first connecting elements of the first circuit layer are electrically connected with second connecting elements of the first chip; the first chip comprises the second connecting elements and a semiconductor layer which wraps the second connecting elements; the first circuit layer comprises a plurality of metal columns which are located at the periphery of the first chip and are connected with the remaining first connecting elements of the first circuit layer; removing part of the plastic sealing layer and part of the semiconductor layer along the first direction until the second connecting elements of a first target height are exposed, and the remaining plastic sealing layer covers the metal columns, thereby forming a dielectric layer which covers the remaining semiconductor layer and the exposed second connecting elements; the first target height is 10-15 microns; simultaneously removing part of the dielectric layer, part of the metal columns and part of the plastic sealing layer along the first direction until the second connecting elements and the metal columns are exposed; the top surface of the remaining dielectric layer is flush with the top surface of the remaining plastic sealing layer; after forming a second circuit layer on the plastic sealing layer, a second carrier plate is formed on the second circuit layer, and the second circuit layer is electrically connected with the second connecting elements; removing the first carrier plate and the first bonding layer to expose the first circuit layer, and the first circuit layer is used for electrical connection with at least one second chip; the method for removing part of the plastic sealing layer and part of the semiconductor layer along the first direction comprises the following steps: the plastic sealing layer and the semiconductor layer are removed along the first direction by using a grinding process until the second connecting elements of the first chip are exposed; part of the semiconductor layer is removed along the first direction by using a dry etching process, the second connecting elements are partially exposed from the remaining semiconductor layer, and circuit materials remaining on the semiconductor layer are removed; the circuit materials are the same as the materials of the second connecting elements, and the dry etching process comprises reactive ion etching or high-concentration plasma etching.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: the method for removing part of the plastic sealing layer and part of the semiconductor layer along the first direction until the second connecting elements are exposed comprises the following steps: the plastic sealing layer and the semiconductor layer are removed along the first direction by using a grinding process until the second connecting elements of the first chip are exposed; part of the semiconductor layer is removed along the first direction, the second connecting elements are partially exposed from the remaining semiconductor layer, and circuit materials remaining on the semiconductor layer are removed; the circuit materials are the same as the materials of the second connecting elements.

3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: the method for removing part of the plastic sealing layer and part of the semiconductor layer along the first direction until the second connecting elements are exposed comprises the following steps: part of the plastic sealing layer and part of the semiconductor layer are removed along the first direction by using a grinding process, the remaining plastic sealing layer covers the metal columns when the second connecting elements of a first target height are exposed from the remaining semiconductor layer. forming a dielectric layer on the remaining semiconductor layer and the second connecting element exposed to the first target height by a spin coating process; removing part of the dielectric layer and the remaining plastic encapsulation layer along the first direction by a dry etching process until the second connecting element and the metal column are exposed; the surface of the remaining dielectric layer is flush with the surface of the remaining plastic encapsulation layer.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: removing part of the plastic encapsulation layer and part of the semiconductor layer along the first direction, in the case that the remaining semiconductor layer exposes the second connecting element to the first target height, the remaining plastic encapsulation layer covers the metal column, comprising: At the same time, the grinding process removes the same thickness of different areas of the plastic encapsulation layer and the semiconductor layer in the first direction.

5. The method of claim 4, wherein the semiconductor structure is prepared by a method comprising: The first circuit layer comprises a plurality of circuit layers.

6. The method of producing a semiconductor structure according to any one of claims 1 to 4, wherein The initial plastic encapsulation structure comprises: providing a substrate, the substrate comprising a first carrier plate and the first bonding layer on the first carrier plate; forming a first circuit layer on the first bonding layer; wherein the first circuit layer comprises a plurality of first connecting elements; forming a first chip on the first circuit layer, the second connecting element of the first chip being electrically connected to part of the first connecting elements; forming the plastic encapsulation layer on the first circuit layer and the first chip.

7. The method of producing a semiconductor structure according to any one of claims 1 to 4, wherein forming the second circuit layer, comprising: forming a plurality of third connecting elements on the plastic encapsulation layer; wherein the third connecting elements are electrically connected to at least the second connecting elements; forming a pad on the end of the third connecting element away from the first carrier plate; forming a soldering point on the pad; the side of the soldering point away from the first carrier plate is used to fix the second carrier plate.

8. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: forming the second carrier plate, comprising: forming a protective layer on the soldering point; fixing the side of the protective layer away from the first carrier plate to the second carrier plate.

9. A semiconductor structure, characterized by The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1-8, comprising: a second carrier plate; a plastic encapsulation layer on the second carrier plate, the plastic encapsulation layer comprising at least one first chip; wherein the first chip comprises a second connecting element and a semiconductor layer wrapping the second connecting element; the second connecting element is electrically connected to the second circuit layer; a first circuit layer on the first chip and the plastic encapsulation layer; part of the first connecting elements of the first circuit layer are electrically connected to the second connecting elements; the first circuit layer is used to electrically connect to at least one second chip; a second circuit layer on the plastic encapsulation layer, the second circuit layer being electrically connected to the second connecting elements; the second carrier plate is on the second circuit layer.

10. The semiconductor structure of claim 9, wherein, The height of the second connecting element protruding from the semiconductor layer is a first target height. The semiconductor structure further comprises: a dielectric layer between the second carrier plate and the semiconductor layer, surrounding the second connecting element to the first target height; the surface of the dielectric layer close to the second carrier plate is flush with the surface of the plastic encapsulation layer close to the second carrier plate.

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