Core resonance suppression in signal integrity optimized packages

Abstract

The invention relates to core resonance suppression in a signal integrity optimization package. An apparatus includes a core including a top surface, a bottom surface, and a first plane coupled to the top surface of the core. The first plane includes a first region defined by a first channel, where the first region includes a conductive material, and where the first channel is configured to electrically isolate the first region.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document and the patent disclosure as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure generally relates to methods, systems, and apparatus for signal integrity optimized semiconductor packaging. Background Art

[0004] Serializer / deserializer (SerDes) ICs continue to support increasing data rates. At the planned 200G (e.g., 224 Gigabits per second (Gbps)) data rate, the Nyquist frequency for such applications is 56 Gigahertz (GHz). Conventional packages with a core thickness of 1440 microns (μm) have known core resonances in the range of approximately 47 to 49 GHz. Therefore, at the expected data rates for 200G SerDes applications, signal integrity performance may be degraded. Similar issues may occur with other combinations of data rate and package thickness, where package resonances may affect the signal integrity performance of the IC.

[0005] Thus, methods, systems, and apparatus are provided for signal integrity optimized semiconductor packaging. Summary of the invention

[0006] In one aspect, the present disclosure relates to an apparatus comprising: a core comprising a top surface, a bottom surface, and a first plane coupled to the top surface of the core, wherein the first plane comprises a first region defined by a first channel, wherein the first region comprises a conductive material, wherein the first channel is configured to electrically isolate the first region.

[0007] On the other hand, the present disclosure relates to a semiconductor package: a core comprising a top surface and a bottom surface, wherein the core is formed of a dielectric material; and one or more first planes coupled to the top surface of the core, wherein each of the one or more first planes comprises a respective first region defined by a respective first channel, wherein each respective first region comprises a conductive material, wherein each respective first channel is configured to electrically isolate the respective first region.

[0008] On the other hand, the present disclosure relates to a substrate comprising: a dielectric core including a top surface and a bottom surface; and a first ground plane coupled to the top surface of the dielectric core, wherein the first ground plane includes a first ground island defined by a first channel, and wherein the first channel is configured to electrically isolate the first ground island from other regions of the first ground plane. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A further understanding of the nature and advantages of particular embodiments can be realized by reference to the remainder of the specification and drawings, in which like reference numerals refer to like components. In some instances, a sub-label is associated with a reference numeral to denote one of a plurality of like components. When reference is made to a reference numeral without specifying an existing sub-label, it is intended to refer to all such plurality of like components.

[0010] Figure 1A is a schematic top view of a top layer of a signal integrity optimized package according to various embodiments.

[0011] Figure 1B is a schematic top view of an internal layer of a signal integrity optimized package according to various embodiments.

[0012] Figure 2A is a schematic cross-sectional view of a top layer of a signal integrity optimized package according to various embodiments;

[0013] Figure 2B is a schematic cross-sectional view of an internal layer of a signal integrity optimized package according to various embodiments; and

[0014] Figure 3 is a schematic perspective view of a signal integrity optimized package according to various embodiments. DETAILED DESCRIPTION

[0015] Various embodiments set forth a signal integrity optimized package.

[0016] In some embodiments, a device for a signal integrity optimized package is provided. The device includes a core having a top surface, a bottom surface, and a first plane coupled to the top surface of the core. The first plane includes a first region defined by a first channel, wherein the first region includes a conductive material, and wherein the first channel is configured to electrically isolate the first region.

[0017] In another embodiment, a semiconductor package optimized for signal integrity and resonance suppression is provided. The semiconductor package includes a core having a top surface and a bottom surface, where the core is formed of a dielectric material, and one or more first planes are coupled to the top surface of the core. Each first plane of the one or more first planes includes a respective first region defined by a respective first channel, where each respective first region includes a conductive material, and where each respective first channel is configured to electrically isolate the respective first region.

[0018] In another embodiment, a signal integrity optimized package substrate is provided. The substrate includes a dielectric core having a top surface and a bottom surface, and a first ground plane coupled to the top surface of the dielectric core. The first ground plane includes a first ground island defined by a first channel, where the first channel is configured to electrically isolate the first ground island from other regions of the first ground plane.

[0019] In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the described embodiments. However, it will be apparent to one of ordinary skill in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although various features are ascribed to different embodiments, it should be understood that features described with respect to one embodiment may also be combined with other embodiments. However, for the same reason, no single or multiple features of any of the described embodiments should be considered necessary for every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0020] When an element is referred to herein as being "connected" or "coupled" to another element, it should be understood that the element can be directly connected to the other element, or there can be intervening elements between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it should be understood that there are no intervening elements in the "direct" connection between the elements. However, the existence of a direct connection does not exclude other connections in which there may be intervening elements.

[0021] When an element is referred to herein as being "disposed" in a certain manner relative to another element (e.g., disposed on it, disposed between it, disposed under it, disposed adjacent to it, or disposed in some other relative manner), it should be understood that the element can be directly disposed relative to the other element (e.g., directly disposed on the other element), or there can be intervening elements between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it should be understood that there are no intervening elements in the "direct" instance. However, the existence of a direct disposition does not exclude other instances in which there may be intervening elements.

[0022] Similarly, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include an intervening element present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which intervening elements may be present.

[0023] In addition, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0024] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context indicates otherwise, intervening processes may occur before and / or after any portion of the described process, and various other procedures may be reordered, added, and / or omitted according to various embodiments.

[0025] Unless otherwise indicated, all numbers used herein to indicate quantities, dimensions, etc. should be understood to be modified by the term "about" in all instances. In this application, unless otherwise specifically indicated, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms "and" and "or" means "and / or". In addition, the use of the terms "including" and "having" and other forms such as "includes", "included", "has", "have" and "had" should be considered non-exclusive. In addition, terms such as "element" or "component" cover elements and components that make up one unit and elements and components that make up more than one unit, unless otherwise specifically stated.

[0026] As used herein, the phrase "at least one of..." preceding a series of items using the terms "and" or "or" to separate any of the items modifies the list as a whole, rather than each member of the list (i.e., each item). The phrase "at least one of..." does not require selection of at least one of each item listed; in contrast, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where the desired selection is "at least one of each of A, B, C," or alternatively "at least one of A, at least one of B, and at least one of C," it is so explicitly described.

[0027] Conventional packages with a core thickness of 1440 μm exhibit core resonances in the 47 to 49 GHz range. Given the Nyquist frequency of 56 GHz, the resonance of the package core can interfere with the operation of 200G SerDes ICs with data rates up to 224 Gbps. The core resonances can be attributed to large ground planes disposed at both sides of the core (e.g., the top of the core and the bottom of the core), forming planar resonances that affect package performance by insertion loss and crosstalk. Therefore, signal integrity optimized packages mitigate core resonances by changing the shape of the analog ground (AGND) plane, and further provide isolation of any planar resonances.

[0028] Figure 1A 1 is a schematic top view of the top layer of a signal integrity optimized package (hereinafter referred to as "package layer 100A") according to various embodiments. Package layer 100A includes ground plane 105, first trench 110a, second trench 110b, first ground island 115a, second ground island 115b, first signal pair 120a, and second signal pair 120b. It should be noted that Figure 1A Various features and components of the encapsulation layer 100A are schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of the encapsulation layer 100A may be possible and according to various embodiments.

[0029] In various embodiments, the packaging layer 100A may include a ground plane 105 in which corresponding trenches 110a, 110b and ground islands 115a, 115b are formed. Therefore, the packaging layer 100A may be a metal layer electrically coupled to a ground, such as an analog ground (e.g., a signal ground for analog signals in a given circuit). In some examples, the packaging layer 100A and in particular the ground plane 105 may be formed of copper (Cu), such as copper foil. As used herein, a ground island may refer to a local ground electrically isolated from a larger ground plane (e.g., ground plane 105) via a trench (e.g., trenches 110a, 110b). A ground island may be, for example, a metal layer connected to an analog ground or other ground, and generally has a smaller footprint than a ground plane. In some examples, a ground island is a region (interchangeably referred to as a "ground island region") formed from a larger ground plane 105 via a channelization process, as described in more detail below.

[0030] In various examples, the grounded islands 115a, 115b may be formed via a channeling process that forms the channels 110a, 110b. Thus, as depicted, the channels 110a, 110b define respective grounded islands 115a, 115b. In some examples, the boundaries of the respective grounded islands 115a, 115b may be defined at least in part by the shape of the respective channels 110a, 110b.

[0031] For the purpose of illustration, the ground islands 115a, 115b are depicted as a pair of elliptical structures. It should be understood that the shape, size and number of the ground islands are not limited in the manner depicted, and in other embodiments, other types of ground island shapes and sizes and other numbers of ground islands may be possible. By forming the ground islands 115a, 115b in the ground plane 105, the large surface area of ​​the ground plane can be destroyed by the trenches 110a, 110b, thus changing any planar resonance formed by the stacked layers of the ground plane. In addition, due to the structure of the islands, any existing planar resonance in the ground plane 105 is isolated from the ground islands 115a, 115b by the trenches 110a, 110b defining the corresponding ground islands 115a, 115b.

[0032] In some examples, the size and / or shape of respective ground islands (e.g., first and second ground islands 115a, 115b) can be determined based at least in part on a planar resonance with at least one other ground plane (e.g., another packaging layer). The planar resonance can be given by the following formula:

[0033]

[0034] where c is the speed of light, ε r is the dielectric constant, μ ris the magnetic permeability, a, b and h are the dimensions of the cavity formed between the two ground planes, and m, n and p correspond to the resonant modes.

[0035] Thus, by forming the ground islands 115a, 115b through channeling, the planar resonance can be altered by changing the size of the cavity formed between any two layers (e.g., between ground islands on separate packaging layers). In some instances, the trench may have a width of 50 μm, which is the distance separating the ground islands 115a, 115b from the rest of the ground plane 105. In some embodiments, trenches, such as the first and second trenches 110a, 110b, may be formed through etching. In other instances, other techniques may be utilized, including, but not limited to, photolithography, grinding, drilling, cutting, or other suitable processes. In some embodiments, the trenches 110a, 110b may be filled with a dielectric material (e.g., a dielectric material deposited into the trenches). In some instances, for example, the trenches 110a, 110b may be filled with a buildup material, such as GL103, GL107, FR-4, or FR-5. In other instances, other materials may be utilized, such as epoxy, resin, or other dielectric materials. In yet other examples, the trench may remain unfilled.

[0036] In various embodiments, packaging layer 100A may be disposed directly above at least one other ground layer (e.g., a packaging layer that includes a ground plane) of a signal integrity optimized package. In some examples, packaging layer 100A is a layer disposed above a package core (e.g., a dielectric core), collectively referred to as an "FC" layer (e.g., FC1, FC2, etc.). In the depicted example, packaging layer 100A may be a ground layer (FC2) disposed above a ground layer (FC1), where FC1 is disposed on the top surface of the package core. In contrast, as described below with respect to Figure 1B Describing in more detail, the packaging layer disposed below the dielectric core may be referred to as a "BC" layer (e.g., BC1, BC2, BC3, BC4, etc.). As used herein, "ground layer" is used to refer to a layer of a package that includes a ground plane such as a separate ground island. However, it should be understood that the ground plane itself may be a layer of the package, and the ground island itself may be a smaller local ground plane.

[0037] In various embodiments, the packaging layer 100A further includes corresponding signal pairs 120a, 120b. The signal pairs 120a, 120b may be signal lines configured to carry the signals of the SerDes IC through the ground layer to a ball grid array (BGA), a through-hole via (e.g., a plated through-hole (PTH) via, a through-silicon via (TSV), etc.), or other interconnect structures. As used herein, an interconnect may refer to a structure for carrying a signal from one circuit (or part of a circuit) to another circuit (or other part of the circuit). Suitable interconnects may include, but are not limited to, conductive traces, microstrips, pads, wiring layers, through-hole vias, BGAs, etc. In various examples, the signal pairs 120a, 120b may pass through the packaging layer 100A through corresponding cutouts in the corresponding ground islands 115a, 115b.

[0038] Figure 1B 1 is a schematic top view of an inner layer 100B of a signal integrity optimized package (hereinafter referred to as “package layer 100B”) according to various embodiments. Package layer 100B includes ground plane 105, first trench 110a, second trench 110b, first ground island 115a, second ground island 115b, first signal pair 120a, second signal pair 120b, first plurality of through-hole vias 125a, and second plurality of through-hole vias 125b. It should be noted that in Figure 1B Various features and components of encapsulation layer 100B are schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of encapsulation layer 100B may be possible and according to various embodiments.

[0039] and Figure 1A Like the packaging layer 100A of FIG. 1 , in various embodiments, the packaging layer 100B may be a ground layer having a ground plane 105 in which corresponding trenches 110a, 110b and ground islands 115a, 115b are formed. Compared to the packaging layer 100A, the packaging layer 100B includes ground islands 115a, 115b in the form of a ring with a hollow / empty center. The ground islands 115a, 115b may be formed via a channeling process that forms the trenches 110a, 110b. In some examples, the boundaries of the corresponding ground islands 115a, 115b may be defined at least in part by the shape of the corresponding trenches 110a, 110b. The centers of the ground islands 115a, 115b may be hollow, and further allow the signal pairs 120a, 120b to pass through the openings in the centers of the ground islands 115a, 115b.

[0040] For purposes of illustration, the ground islands 115a, 115b are depicted as a pair of elliptical rings. It should be understood that the shape, size, and number of ground islands are not limited in the manner depicted, and in other embodiments, other types of ground island shapes and sizes and other numbers of ground islands may be possible. In some embodiments, as previously described, the trenches 110a, 110b may be filled with a dielectric material (e.g., a dielectric material deposited into the trenches), such as epoxy, resin, or other dielectric material. In other examples, the trenches may remain unfilled.

[0041] In various embodiments, the packaging layer 100B may be disposed above and / or below the core of the signal integrity optimized package (as will be described below with respect to FIG. Figure 3 In some embodiments, the encapsulation layer 100B is disposed above the top surface of the core, between the top surface of the core and below the encapsulation layer 100A, and / or below the bottom surface of the core. In some embodiments, the encapsulation layer 100B is disposed below at least one other ground layer of the signal integrity optimized package (e.g., a encapsulation layer including a ground plane, such as the encapsulation layer 100A). In some embodiments, the encapsulation layer 100B is a layer disposed above the encapsulation core (e.g., a dielectric core), collectively referred to as a FC layer (e.g., FC1, FC2, etc.). In the depicted example, the encapsulation layer 100B may be a ground layer (FC1) disposed below the ground layer (FC2), wherein FC1 is disposed on the top surface of the encapsulation core.

[0042] In another embodiment, packaging layer 100B may be a packaging layer disposed below the dielectric core, referred to as a "BC" layer (eg, see Figure 3 : one of BC1, BC2, BC3, BC4). Therefore, in some examples, the packaging layer 100B is a ground layer (e.g., BC2 to BC4) disposed directly below the core and / or below another ground layer directly below the core. For example, in some embodiments, the packaging layer 100B may be a ground layer (e.g., BC1) disposed directly below the core. Subsequent ground layers (e.g., BC2 to BC4) may have similar "ring-shaped" ground islands 115a, 115b. In other examples, subsequent ground layers (e.g., BC2 to BC4) may include ground islands 115a, 115b with rings of different shapes (e.g., having a hollow center, but having "rings" of different shapes). For example, the "ring" may be wider on one side relative to the opposite side, have an irregular profile, etc.

[0043] In various embodiments, the package layer 100B further includes respective signal pairs 120a, 120b. As previously described, the signal pairs 120a, 120b pass through the center of respective ground islands 115a, 115b to a BGA or other interconnect structure.

[0044] In various embodiments, the first and second ground islands 115a, 115b may include a plurality of perforated vias, such as a first plurality of perforated vias 125a and a second plurality of perforated vias 125b, respectively. In some examples, the respective plurality of perforated vias 125a, 125b may be PTH vias. In other examples, the respective ground islands 115a, 115b are not limited to including a plurality of PTH vias, and may instead include one or more perforated vias (e.g., a single perforated via or more than one perforated via, etc.). In various examples, as previously described, the perforated vias 125a, 125b may be coupled to one or more interconnect structures.

[0045] Figure 2A 1 is a schematic diagram of a partial cross section of packaging layers 100A, 200A taken across line 11 according to various embodiments. The cross-sectional view of packaging layer 200A shows the different structures described above, but is blocked in the top view and only shows a portion of the ground plane and a cross section of a single ground island of packaging layer 100A. Specifically, it includes the ground plane 205, trench 210, ground island 215 and signal line 220 of the corresponding signal pair (120a or 120b). It should be noted that in Figure 2A Various features and components of encapsulation layer 200A are schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of encapsulation layer 200A may be possible and according to various embodiments.

[0046] As shown in the cross-sectional view, the trench 210 can be filled with a dielectric material, as described above. In some examples, the area around the signal line 220 (eg, the cutout in the ground island 215, 115a, 115b) can be similarly filled with a dielectric material, or alternatively, remain unfilled.

[0047] Figure 2B is a schematic diagram of a partial cross section of packaging layers 100B, 200B taken across line x-xl according to various embodiments. The cross-sectional view of packaging layer 200B shows the different structures described above, but is blocked in the top view and only shows a portion of the ground plane and a cross section of a single ground island of packaging layer 100B. Thus, packaging layer 200B includes ground plane 205, trench 210, ground island 215, signal line 220 of a corresponding signal pair (120a or 120b), and one or more through-hole vias 225a, 225b. It should be noted that in Figure 2BVarious features and components of encapsulation layer 200B are schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of encapsulation layer 200B may be possible and in accordance with various embodiments.

[0048] Compared to the cross-section of the package layer 200A, the ground island 215 of the package layer 200B includes one or more through-hole vias 225a-225b, and further adopts the outer dimensions of a ring, wherein the ground island 215 area is thinner (e.g., smaller width) than the corresponding area in the package layer 200A. Therefore, the cutout area around the signal line 220 is also wider, corresponding to the hollow center of the ground island 215, while the package layer 200A has a solid center. In another example, as depicted, one or more through-hole vias 225a, 225b can be PTH vias, wherein the vias can be plated with metal (e.g., Cu plated).

[0049] Therefore, in various embodiments, when the packaging layers 100B, 200B are stacked, the ground island 215, the trench 210, the one or more through-vias 225a-225b, and the signal line 220 may be aligned so as to reduce the volume of any resonant cavity formed between the ground layers. Figure 3 Describe the stack-up layers for a signal integrity optimized package.

[0050] Figure 3 300 ) according to various embodiments. Package 300 includes: a first set of ground layers 305, which includes a top FC layer (FC2) 305a and a bottom FC layer (FC1) 305b; a core 340; a second set of ground layers 350, which includes a first BC layer (BC1) 350a, a second BC layer (BC2) 350b, a third BC layer (BC3) 350c, and a fourth BC layer (BC4) 350d; and an interconnect structure 345. It should be noted that in Figure 3 Various features and components of package 300 are schematically illustrated in , and modifications to the various components and other arrangements of package 300 may be possible and in accordance with various embodiments.

[0051] In various embodiments, the top FC layer FC2 305a is previously described with respect to Figure 1A Thus, FC2 305a includes the corresponding first channel 310a, the second channel 310b, the first ground island 315a, the second ground island 315b, and the first signal pair 320a and the second signal pair 320b and the ground plane 330. The bottom FC layer FC1 305b is the same as previously described with respect to FIG. Figure 1B305a. Thus, FC1 305b may include respective first and second channels (not shown) and respective first and second ground islands (not shown). Compared to FC1 305a, the first and second ground islands of FC2 305b may have a ring shape and further include one or more through-hole vias 365a to 365d, as can be seen with respect to ground island 360a of BC1 350a.

[0052] The core 340 may be a dielectric core of the package 300. Thus, the core may include one or more dielectric layers through which one or more through-hole vias 365a to 365d and corresponding signal pairs 320a, 320b pass. In various examples, the core 340 may be a complete dielectric layer, which may be a metal layer compared to the ground layers 305, 350. In some examples, the dielectric material of the core 340 may include, but is not limited to, GL103, GL107, FR-4, FR-5, or other suitable core dielectric materials. The core may include a top surface, a bottom surface, and three or more sidewalls.

[0053] In the depicted example, a first set of ground layers 305 may be disposed on the top surface of core 140 with bottom FC layer FC1 305b disposed just above the top surface of core 340. A second set of ground layers 350 may be disposed below the bottom surface of core 340 with first BC layer BC1 350a disposed just below the bottom surface of core 350.

[0054] In various embodiments, BC1 to BC4 350a to 350d may be ground planes for package 300, as previously described with respect to Figure 1B 305a) and the packaging layer 100B of BC1 350a. Therefore, BC1 305a may include corresponding first and second channels (not shown) and corresponding first and second ground islands (not shown). Compared with FC1 305a, the first and second ground islands of FC2 305b may have the shape of a ring and further include one or more perforated vias 365a to 365d, as can be seen with respect to the first ground island 360a of BC1 350a. For the purpose of visualization and clarity of the accompanying drawings, only a selected number of perforated vias 365a to 365d with respect to the first ground island 360a are shown. It should be understood that the ground island 360a may include more (less) than the depicted number of perforated vias, and their positions may also be variable. In addition, it should be understood that in some embodiments, the second ground island 360b may also include one or more corresponding perforated vias.

[0055] In addition, in various embodiments, subsequent BC layers BC2 to BC4 350b to 350d may include the features described above with respect to BC1 350a, respectively. Thus, in various examples, the first and second channels 355a to 355b shown on BC1 350a are understood to extend through each BC layer 350b to 350d (as shown in dashed lines) through to the interconnect structure 345. Thus, one or more through-hole vias 365a to 365d may pass through the respective ground islands 360a, 360b of each of the second set of ground layers 350 to the interconnect structure 345. Similarly, the respective signal pairs 320a, 320b may pass through the hollow centers of the respective ground islands 360a, 360b of each of the second set of ground layers 350 to the interconnect structure 345.

[0056] Compared to BC1 350a, BC layers BC2 to BC4 350b to 350d may have annular ground islands (e.g., with hollow / empty centers) that are different in shape from the rings of BC1 350a and / or FC2 305b. Similarly, in other examples, the shapes of the ground islands 360a to 360b of BC1 350a may be different from the shapes of the ground islands of FC2 305b. In some examples, the shapes of the corresponding ground islands 360a, 360b may be consistent (within the limits of manufacturing tolerances) throughout BC1 to BC4 350a to 350d. In other examples, at one or more of BC1 to BC4 350a to 350d, the size and shape of the ground islands may be different. In addition, in some embodiments, the first and second ground islands 360a, 360b may also be different in size and shape from each other.

[0057] In various embodiments, package 300 is shown to include two FC layers FC1 305b and FC2 305a in the first set of ground layers 305, and four BC layers BC1 to BC4 350a to 350d in the second set of ground layers 350. However, it should be understood that in other embodiments, the first set of ground layers 305 may include more layers or fewer layers. Similarly, in other embodiments, the second set of ground layers 350 may include more layers or fewer layers. In yet another embodiment, package 300 may include an additional layer disposed above the first set of ground layers 305. For example, package 300 may include an additional layer 335 disposed above FC2 305a. In some examples, additional layer 335 is a ground layer, as described above. In other examples, additional layer 335 may be an active layer (which may include active elements, such as a die, logic or other integrated circuits (ICs)), an interposer, a redistribution layer (RDL) or other types of packaging layers. In yet further examples, as described above, additional layers (not shown) may be further disposed before the second set of ground layers 350 .

[0058] In various examples, the package 300 can further include an interconnect structure 345 disposed below the second set of ground layers 350. As previously described, the interconnect structure 345 can include a BGA, solder balls, pads, or other suitable interconnect structures.

[0059] In experimental data, the signal integrity optimized package 300 exhibits no insertion loss resonance peaking and flattened crosstalk peaking when compared to a conventional ground plane. This is expected because the local ground islands 315a, 315b, 360a, 360b isolate and mitigate core resonances, and further isolate any core resonances from the signal lines. Thus, in one embodiment, the planar resonance is shifted to 35GHz with a -60dB peak, compared to the approximately -20dB peak at 48GHz exhibited in a conventional 1440μm package utilizing a conventional ground plane. Thus, the package 300 set forth above has been experimentally demonstrated to allow existing 1440μm core packages to support 200G SerDes applications.

[0060] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. In addition, although the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may instead be implemented in any suitable hardware configuration. Similarly, although some functionality is attributed to one or more system components, unless the context indicates otherwise, according to several embodiments, this functionality may be distributed throughout various other system components.

[0061] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, various procedures may be reordered, added, and / or omitted according to various embodiments unless the context indicates otherwise. In addition, the procedures described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to one system may be organized into alternative structural architectures and / or incorporated into other described systems. Therefore, although those embodiments are described with or without some features for ease of description and in order to illustrate aspects of various embodiments, various components and / or features described herein with respect to specific embodiments may be replaced, added, and / or subtracted from other described embodiments unless the context indicates otherwise. Therefore, although several embodiments are described above, it will be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A device comprising: a core comprising a top surface, a bottom surface, and A first plane is coupled to the top surface of the core, wherein the first plane includes a first region defined by a first trench, wherein the first region includes a conductive material, wherein the first trench is configured to electrically isolate the first region. The apparatus of claim 1 , wherein the first plane is a ground plane. 3 . The apparatus of claim 1 , wherein the first plane includes a second region defined by a second trench, wherein the second trench is configured to electrically isolate the second region. The apparatus of claim 1 , wherein the first region has an elliptical shape whose boundary is defined by the first channel. The apparatus of claim 1 , wherein the first trench is filled with a dielectric material.

6. The apparatus of claim 1, further comprising: A second plane is coupled to the bottom surface of the core, wherein the second plane includes a second region defined by a second trench, wherein the second region includes a conductive material, wherein the second trench is configured to electrically isolate the second region. The apparatus of claim 6 , wherein the second region is a ground plane.

8. The apparatus of claim 6, further comprising one or more through-vias, wherein the one or more through-vias are configured to couple the second region to the first region.

9. The apparatus of claim 6, further comprising one or more ground planes disposed on the first plane, the one or more ground planes formed of a conductive material, each ground in the one or more ground planes comprising a respective first region defined by the first trench.

10. A semiconductor package: a core comprising a top surface and a bottom surface, wherein the core is formed of a dielectric material; and One or more first planes coupled to the top surface of the core, wherein each of the one or more first planes includes a respective first region defined by a respective first channel, wherein each respective first region includes a conductive material, wherein each respective first channel is configured to electrically isolate the respective first region. The semiconductor package according to claim 10 , wherein the one or more first planes are ground planes, respectively. 12 . The semiconductor package of claim 10 , wherein each respective first region is coupled to an analog ground. 13 . The semiconductor package according to claim 10 , wherein each respective first region has an elliptical shape whose boundary is defined by the respective first trench. The semiconductor package of claim 10 , wherein each respective first trench is filled with a dielectric material.

15. The semiconductor package according to claim 10, further comprising: One or more second planes coupled to the bottom surface of the core, wherein each of the one or more second planes includes a second region defined by a respective second channel, wherein each respective second region includes a conductive material, wherein each respective second channel is configured to electrically isolate the respective second region.

16. A substrate comprising: a dielectric core comprising a top surface and a bottom surface; and A first ground plane is coupled to the top surface of the dielectric core, wherein the first ground plane includes a first ground island defined by a first trench, wherein the first trench is configured to electrically isolate the first ground island from other areas of the first ground plane.

17. The substrate of claim 16, wherein the first ground island is coupled to an analog ground. 18 . The substrate of claim 16 , wherein the first ground island has an elliptical shape whose boundary is defined by the first trench.

19. The substrate of claim 16, further comprising a second ground plane coupled to the bottom surface of the dielectric core, wherein the second ground plane comprises a second ground island defined by a second trench, wherein the second trench is configured to electrically isolate the second ground island from other areas of the second ground plane.

20. The substrate of claim 19, wherein the second ground island is coupled to an analog ground.

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