A packaged chip and a method of manufacturing the same

Abstract

The application provides a packaging chip and a manufacturing method thereof, which comprises a first adapter plate and a second adapter plate which are bonded together, a working chip arranged on a side of the first adapter plate away from the second adapter plate, at least one recess arranged on a surface of the first adapter plate close to the second adapter plate, at least one protrusion arranged on a surface of the second adapter plate close to the first adapter plate, the protrusion and the recess being in position and nested, a first metal layer laid on the surface of the first adapter plate close to the second adapter plate, the first metal layer covering the recess, a second metal layer laid on the surface of the second adapter plate close to the first adapter plate, the second metal layer covering the protrusion, and an insulating layer arranged between the first metal layer and the second metal layer, the first metal layer, the insulating layer and the second metal layer forming a capacitor. The packaging chip and the manufacturing method thereof can solve the problem of the capacity and position requirement of the capacitor for the system on chip.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit manufacturing, and particularly relates to a packaged chip and a manufacturing method thereof. BACKGROUND

[0002] When packaging a chip, the chip of each module is independently packaged, and the packaged chips are tiled on a circuit board to form a system on chip through the circuit board. For a capacitor device with a large structure, it is tiled on the circuit board together with the packaged chip.

[0003] However, with the increase of the integration of the system on chip, two-dimensional packaging cannot meet the volume requirement of the system on chip. In addition, the system on chip with increased integration requires a larger current support, and thus requires a larger capacitor device. With the continuous increase of the voltage switching frequency of the power chip, the capacitor needs to be as close to the power network as possible. The capacitor arranged on the circuit board cannot meet the capacity and position requirements of the system on chip for the capacitor. SUMMARY

[0004] The present application aims to provide a packaged chip and a manufacturing method thereof, which can solve the problem that the capacitor on the circuit board cannot meet the capacity and position requirements of the system on chip for the capacitor.

[0005] To achieve the above-mentioned purpose, the present application provides a packaged chip, which at least comprises:

[0006] A first adapter plate and a second adapter plate, the second adapter plate is bonded to the first adapter plate;

[0007] A working chip is arranged on the side of the first adapter plate away from the second adapter plate;

[0008] At least one recess is arranged on the surface of the first adapter plate close to the second adapter plate;

[0009] At least one recess is arranged on the surface of the second adapter plate close to the first adapter plate, and the convex part is nested with the recess in position;

[0010] A first metal layer is arranged on the surface of the first adapter plate close to the second adapter plate, and the first metal layer covers the recess;

[0011] A second metal layer is arranged on the surface of the second adapter plate close to the first adapter plate, and the second metal layer covers the convex part; and

[0012] An insulating layer is arranged between the first metal layer and the second metal layer, and the first metal layer, the insulating layer and the second metal layer form a capacitor device.

[0013] In an embodiment of the present application, a through silicon via structure is arranged in the first adapter plate and the second adapter plate.

[0014] In an embodiment of the present application, a recess is arranged between two adjacent through silicon via structures on the surface of the first adapter plate close to the second adapter plate; and a protrusion is arranged between two adjacent through silicon via structures on the surface of the second adapter plate close to the first adapter plate.

[0015] In an embodiment of the present application, two or more recesses are arranged between two adjacent through silicon via structures on the surface of the first adapter plate close to the second adapter plate; and two or more protrusions are arranged between two adjacent through silicon via structures on the surface of the second adapter plate close to the first adapter plate.

[0016] In an embodiment of the present application, the recess and the protrusion are arranged in a rectangular shape, a pentagonal shape, a hexagonal shape, or a rectangular shape, a pentagonal shape, or a hexagonal shape with rounded corners.

[0017] In an embodiment of the present application, the first metal layer includes a first capacitor metal layer, the first capacitor metal layer covers the recess; the second metal layer includes a second capacitor metal layer, the second capacitor metal layer covers the protrusion, and the second capacitor metal layer and the first capacitor metal layer are arranged in register.

[0018] In an embodiment of the present application, the first metal layer includes a first contact metal layer, the first contact metal layer is arranged on both sides of the first capacitor metal layer; the second metal layer includes a second contact metal layer, the second contact metal layer is arranged on both sides of the second capacitor metal layer, and the second contact metal layer and the first contact metal layer are arranged in register.

[0019] In an embodiment of the present application, the sum of the thicknesses of the first contact metal layer and the second contact metal layer is equal to the sum of the thicknesses of the first capacitor metal layer, the second capacitor metal layer, and the insulating layer.

[0020] In an embodiment of the present application, the first metal layer includes one first capacitor metal layer and two first contact metal layers, and the second metal layer includes one second capacitor metal layer and two second contact metal layers.

[0021] In an embodiment of the present application, the first metal layer comprises at least two first capacitor metal layers, the at least two first capacitor metal layers are laid on the surface of the first adapter plate, and each of the first capacitor metal layers covers one of the recesses, and adjacent two of the first capacitor metal layers are provided with a spacing; the second metal layer comprises at least two second capacitor metal layers, the at least two second capacitor metal layers are laid on the surface of the second adapter plate, and each of the second capacitor metal layers covers one of the protrusions, and adjacent two of the second capacitor metal layers are provided with a spacing.

[0022] The present application also provides a manufacturing method of a packaged chip, comprising at least the following steps:

[0023] providing a first adapter plate and a second adapter plate;

[0024] etching the surface of the first adapter plate close to the second adapter plate to form at least one recess;

[0025] etching the surface of the second adapter plate close to the first adapter plate to form at least one protrusion, and the protrusion is in registration and nested with the recess;

[0026] laying a first metal layer on the surface of the first adapter plate close to the second adapter plate, and the first metal layer covers the recess;

[0027] laying a second metal layer on the surface of the second adapter plate close to the first adapter plate, and the second metal layer covers the protrusion;

[0028] bonding the second adapter plate and the first adapter plate, and providing an insulating layer between the first metal layer and the second metal layer, and the first metal layer, the insulating layer and the second metal layer form a capacitor device.

[0029] In summary, the present application provides a packaged chip and a manufacturing method thereof, which adopts a system-in-package structure, and multiple functional chips are packaged in one package, so that the system is more integrated and smaller in size. The capacitor device is integrated in three-dimensional direction, so that the package size is smaller, the system is more integrated, and the device performance is more superior. Through the chip bonding between the adapter plates, a large capacitor device is formed, and the entire system has the same size as the chip, and is smaller in size and lower in thickness. Compared with a surface-mounted capacitor, the capacitor structure provided by the present application is closer to the device itself, and the device performance can be better improved. Meanwhile, the electrode sheets of the capacitor device are formed on the bonding surfaces of the two passive silicon-based adapter plates, so that the area of the capacitor device is greatly increased, and the capacitance of the capacitor device is improved. Further, the capacitor is designed as a tooth shape, so that the capacitor area is effectively increased, and the capacitance is further improved, thereby greatly improving the system performance. Furthermore, compared with the SIP package, the package structure is smaller in size, and has a better market prospect. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the following embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0031] Figure 1 is a structural schematic diagram of a first adapter plate in an embodiment of the present application.

[0032] Figure 2 is a structural schematic diagram of a second adapter plate in an embodiment of the present application.

[0033] Figure 3 is a structural schematic diagram of forming a recess on the first adapter plate in an embodiment of the present application.

[0034] Figure 4 is a structural schematic diagram of forming a convex part on the second adapter plate in an embodiment of the present application.

[0035] Figure 5 is a structural schematic diagram of forming a first metal layer on the recess of the first adapter plate in an embodiment of the present application.

[0036] Figure 6 is a structural schematic diagram of forming a second metal layer on the convex part of the second adapter plate in an embodiment of the present application.

[0037] Figure 7 is a structural schematic diagram of bonding the first adapter plate and the second adapter plate in an embodiment of the present application.

[0038] Figure 8 is a structural schematic diagram of disposing a working chip on the first adapter plate in an embodiment of the present application.

[0039] REFERENCE NUMERALS:

[0040] 100, first adapter plate; 101, through-silicon via structure; 102, first pad; 103, recess; 104, first metal layer; 1041, first capacitive metal layer; 1042, first contact metal layer; 105, insulating layer; 106, connecting metal layer; 107, protective layer; 1071, first protective layer; 1072, second protective layer; 200, second adapter plate; 201, second pad; 202, convex part; 203, second metal layer; 2031, second capacitive metal layer; 2032, second contact metal layer; 204, solder ball; 300, first chip; 400, second chip. DETAILED DESCRIPTION

[0041] For the purpose of promoting an understanding of the application, the application will now be described in greater detail with reference to the figures. The preferred embodiments of the application are illustrated in the figures. However, the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0043] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or component referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" are only for the purpose of description and cannot be understood as indicating or implying relative importance.

[0044] In some embodiments, when forming an integrated circuit, the working modules of various functions are independently packaged to form independent working chips, and then the working chips and capacitor devices are tiled on a circuit board, and the working chips and the capacitors are connected to each other through the circuit board to form a two-dimensional system on a chip. With the continuous improvement of the integration of the system on a chip, more and more working chips need to be integrated on the circuit board, and the circuit board cannot meet the line connection between the chips. Therefore, in an embodiment of the present application, a packaging chip is provided, and the working chip is arranged on a conversion board with a through silicon via structure to realize 2.5D packaging of the working chip, so as to ensure that the connection between the packaged working chips is shorter.

[0045] Please refer to Figure 8 As shown in the drawings, in an embodiment of the present application, the packaging chip provided by the present application includes a conversion board, a capacitor device arranged between the conversion boards, and a working chip arranged on the conversion board. The conversion board includes a first conversion board 100 and a second conversion board 200, and the first conversion board 100 and the second conversion board 200 are stacked in the thickness direction, and the capacitor device is integrated between the two conversion boards stacked in the thickness direction.

[0046] It should be noted that, as Figure 8As shown, the distinction between the first adapter plate 100 and the second adapter plate 200 is for integrating capacitor components between the adapter plates. In some embodiments, a single adapter plate may be divided in the thickness direction to form the first adapter plate 100 and the second adapter plate 200.

[0047] Please see Figure 8 As shown, in one embodiment of the present invention, the number of working chips disposed on the first adapter plate 100 is set according to requirements. That is, this application does not limit the specific number of working chips in the packaged chip or the function of the working chips. The function of each working chip can be the same or different, depending on whether it can realize the function of the packaged chip. Similarly, this application does not limit the number of capacitors formed between adjacent adapter plates. One capacitor can be formed between two working chips, or two or more capacitors can be formed between two working chips. It can be determined based on the required capacitance value of the capacitor and the area occupied by the capacitor between two working chips.

[0048] Please see Figure 8 As shown, in one embodiment of the present invention, the capacitor is positioned close to the power network; that is, when a power chip is present on the adapter board, the capacitor is positioned in the adapter board where the power chip is located. In one embodiment, the example of two working chips, a first chip 300 and a second chip 400, on the adapter board is described. The first chip 300 is a memory chip, and the second chip 400 is a power chip; the first chip 300 and the second chip 400 form a complete system. In other embodiments, a third, fourth, or fifth chip may also be positioned on the adapter board. The third, fourth, or fifth chip is positioned side-by-side with the first chip 300 and the second chip 400 on the first adapter board 100, and the third, fourth, or fifth chip can be any type of chip, such as a central processing unit chip, a communication chip, or a sensor.

[0049] For details, please refer to Figure 1 and Figure 2 As shown, in one embodiment of the present invention, a through-silicon via (TSV) structure 101 is provided in the first adapter plate 100 and the second adapter plate 200. The TSV structure 101 extends from the first surface of the first adapter plate 100 and the second adapter plate 200 into the interior of the first adapter plate 100 and the second adapter plate 200. The first surface and the second surface of the first adapter plate 100 and the second adapter plate 200 are two opposing surfaces in the thickness direction. Pads are provided on the first surface of the first adapter plate 100 and the second adapter plate 200, and the pads are connected to the TSV structure 101, serving as external connection points of the first adapter plate 100 and the second adapter plate 200.

[0050] Referring to Figure 1 and Figure 2 In an embodiment of the present application, the through-silicon via structure 101 extends from the first surface of the first and second adapter boards 100, 200 to the interior of the first and second adapter boards 100, 200. In forming the through-silicon via structure 101 in the first and second adapter boards 100, 200, a through-silicon via can be formed in the first and second adapter boards 100, 200 from the first surface of the first and second adapter boards 100, 200 by means of an etching process, and the through-silicon via extends through the first and second adapter boards 100, 200. After the through-silicon via is formed, a conductive material, such as a metal material, e.g., copper, aluminum, gold, or an alloy of two or three of these metal materials, is deposited in the through-silicon via to form the through-silicon via structure 101.

[0051] Referring to Figure 1 and Figure 2 In an embodiment of the present application, after the through-silicon via structure 101 is formed, a conductive metal material, such as a metal material, e.g., copper, aluminum, gold, or an alloy of two or three of these metal materials, is deposited at the location of the through-silicon via structure 101 to form a pad. The pad formed on the first surface of the first adapter board 100 is the first pad 102, and the pad formed on the first surface of the second adapter board 200 is the second pad 201.

[0052] Referring to Figures 1 to 4 In an embodiment of the present application, after the first pad 102 is formed on the first surface of the first adapter board 100 and the second pad 201 is formed on the first surface of the second adapter board 200, the second surface of the first and second adapter boards 100, 200 is thinned until the through-silicon via structure 101 is exposed from the second surface of the first and second adapter boards 100, 200. Specifically, the second surface of the first and second adapter boards 100, 200 can be ground using a chemical mechanical polishing (CMP) method to thin the first and second adapter boards 100, 200.

[0053] Referring to Figures 1 to 4 In an embodiment of the present application, after the second surface of the first and second adapter boards 100, 200 is thinned, the second surface of the first and second adapter boards 100, 200 is etched to form a recess 103 on the second surface of the first adapter board 100 and a protrusion 202 on the second surface of the second adapter board 200, and the recess 103 on the second surface of the first adapter board 100 and the protrusion 202 on the second surface of the second adapter board 200 correspondingly nest.

[0054] Referring to Figures 1 to 4As shown, in an embodiment of the present application, when etching the second surface of the first and second TSVs 100 and 200, the first and second TSVs 100 and 200 can be etched according to the material of the first and second TSVs 100 and 200. In some embodiments, the second surface of the first and second TSVs 100 and 200 is made of silicon, for example, then the first and second TSVs 100 and 200 can be dry etched using hydrogen fluoride (HF). The first and second TSVs 100 and 200 can also be wet etched using a solution of hydrogen fluoride (HF) or nitric acid (HNO3). In other embodiments, the substrate of the first and second TSVs 100 and 200 can also be an organic material substrate, then the corresponding etching material can be selected according to the organic material of the first and second TSVs 100 and 200 for etching.

[0055] Please refer to Figures 3 to 4 As shown, in an embodiment of the present application, the recesses 103 on the second surface of the first TSV 100 are located between adjacent TSV structures 101, and the recesses 103 between the plurality of TSV structures 101 form a tooth-like structure. The protrusions 202 on the second surface of the second TSV 200 are located between adjacent TSV structures 101, and the protrusions 202 between the plurality of TSV structures form a tooth-like structure. The present application does not specifically limit the positions of the recesses 103 on the second surface of the first TSV 100 and the protrusions 202 on the second surface of the second TSV 200, as long as the recesses 103 on the second surface of the first TSV 100 and the protrusions 202 on the second surface of the second TSV 200 are arranged in a nested manner, i.e., when the first TSV 100 and the second TSV 200 are bonded, the protrusions 202 on the second surface of the second TSV 200 are nested in the recesses 103 on the second surface of the first TSV 100.

[0056] It should be noted that, as Figures 3 to 4 As shown, the recesses 103 and the protrusions 202 do not need to be arranged between every two adjacent TSV structures 101. The recesses 103 or the protrusions 202 can be arranged between the TSV structures 101 according to specific requirements, as long as the recesses 103 or the protrusions 202 have a spacing with the TSV structures 101.

[0057] In combination with Figures 5 to 6As shown, in the subsequent processes of the present application, metal layers will be deposited on the recesses 103 on the second surface of the first adapter plate 100 and the protrusions 202 on the second surface of the second adapter plate 200, and then two electrode plates of the capacitor device are formed. Therefore, the surface area of the recesses 103 on the second surface of the first adapter plate 100 and the protrusions 202 on the second surface of the second adapter plate 200 is related to the capacitance value of the capacitor device formed. In order to match the capacitance value of the capacitor device formed, the number of the recesses 103 on the second surface of the first adapter plate 100 and the protrusions 202 on the second surface of the second adapter plate 200 can be adaptively adjusted. In some embodiments, one recess 103 is arranged between two adjacent through silicon via structures 101 on the second surface of the first adapter plate 100, and one protrusion 202 is arranged between two adjacent through silicon via structures 101 on the second surface of the second adapter plate 200. In other embodiments, two, three or more recesses 103 are arranged between two adjacent through silicon via structures 101 on the second surface of the first adapter plate 100, and two, three or more protrusions 202 are arranged between two adjacent through silicon via structures 101 on the second surface of the second adapter plate 200. By increasing the number of recesses 103 and protrusions 202 between two adjacent through silicon via structures 101, the surface area of the second surface of the first adapter plate 100 and the second surface of the second adapter plate 200 can be increased, and then the area of the two electrode plates of the capacitor device can be increased, and the capacitance value of the capacitor device can be changed.

[0058] Please refer to Figures 3 to 4 As shown, the present application also does not limit the shape of the recesses 103 on the second surface of the first adapter plate 100 and the protrusions 202 on the second surface of the second adapter plate 200. In some embodiments, the recesses 103 on the second surface of the first adapter plate 100 and the protrusions 202 on the second surface of the second adapter plate 200 are arranged in a rectangular shape. In other embodiments, the recesses 103 on the second surface of the first adapter plate 100 can be arranged in a pentagonal shape, a hexagonal shape, or a rectangular shape with rounded corners, a pentagonal shape, a hexagonal shape, etc., and the protrusions 202 on the second surface of the second adapter plate 200 are correspondingly arranged in a pentagonal shape, a hexagonal shape, or a rectangular shape with rounded corners, a pentagonal shape, a hexagonal shape, etc. After the metal layer and the insulating layer 105 are deposited on the second surface of the first adapter plate 100 and the second surface of the second adapter plate 200, the second surface of the first adapter plate 100 and the second surface of the second adapter plate 200 can be seamlessly bonded.

[0059] Please refer to Figures 3 to 6As shown, in one embodiment of the present invention, after a recess 103 is formed on the second surface of the first adapter plate 100 and a protrusion 202 is formed on the second surface of the second adapter plate 200, a conductive metal material is deposited on the second surface of the first adapter plate 100 to form a first metal layer 104. A conductive metal material is then deposited on the second surface of the second adapter plate 200 to form a second metal layer 203. The first metal layer 104 covers the recess 103 on the second surface of the first adapter plate 100, and the second metal layer 203 covers the protrusion 202 on the second surface of the second adapter plate 200. The conductive metal material is, for example, copper, aluminum, gold, or an alloy of two or three of these metals.

[0060] Please see Figure 5 and Figure 6 As shown, in one embodiment of the present invention, the first metal layer 104 includes a first capacitor metal layer 1041 and a first contact metal layer 1042. The second metal layer 203 includes a second capacitor metal layer 2031 and a second contact metal layer 2032. The first capacitor metal layer 1041 covers the recess 103 on the second surface of the first adapter plate 100, and the second capacitor metal layer 2031 covers the protrusion 202 on the second surface of the second adapter plate 200. The first contact metal layer 1042 is disposed on both sides of the first capacitor metal layer 1041 and has a distance between it and the first capacitor metal layer 1041. The second contact metal layer 2032 is disposed on both sides of the second capacitor metal layer 2031 and has a distance between it and the second capacitor metal layer 2031. The first contact metal layer 1042 is connected to the through-silicon via (TSV) structure 101 in the first adapter plate 100, and the second contact metal layer 2032 is connected to the TSV structure 101 in the second adapter plate 200. After the first adapter plate 100 and the second adapter plate 200 are bonded, signal transmission is realized.

[0061] Please see Figure 5 and Figure 6As shown in the embodiment of the present application, the first capacitor metal layer 1041 and the second capacitor metal layer 2031 are arranged in register, and the first contact metal layer 1042 and the second contact metal layer 2032 are arranged in register. The thickness of the first contact metal layer 1042 is greater than the thickness of the first capacitor metal layer 1041, and the thickness of the second contact metal layer 2032 is greater than the thickness of the second capacitor metal layer 2031. More specifically, the sum of the thicknesses of the first contact metal layer 1042 and the second contact metal layer 2032 is equal to the sum of the thicknesses of the first capacitor metal layer 1041, the second capacitor metal layer 2031 and the insulating layer 105 filled between the first capacitor metal layer 1041 and the second capacitor metal layer 2031. The thickness of the insulating layer 105 is determined by the capacity of the capacitor to be formed. In the embodiment of the present application, the thickness of the first capacitor metal layer 1041 and the second capacitor metal layer 2031 is, for example, 2-5um, and specifically, for example, 3um, 4um or 5um. The thickness of the first contact metal layer 1042 and the second contact metal layer 2032 is, for example, 8-15um, and specifically, for example, 10um, 11um or 13um.

[0062] Referring to Figure 5 and Figure 6 As shown in the embodiment of the present application, when the first adapter board 100 and the second adapter board 200 are bonded, the first contact metal layer 1042 and the second contact metal layer 2032 are connected, and the first capacitor metal layer 1041 and the second capacitor metal layer 2031 are in register. That is, when the first adapter board 100 and the second adapter board 200 are bonded, in the thickness direction of the first adapter board 100 and the second adapter board 200, the first contact metal layer 1042 and the second contact metal layer 2032 are aligned, and the first capacitor metal layer 1041 and the second capacitor metal layer 2031 are aligned. When the first adapter board 100 and the second adapter board 200 are bonded, the connection of the first contact metal layer 1042 and the second contact metal layer 2032 realizes the bonding and signal transmission between the first adapter board 100 and the second adapter board 200. The first capacitor metal layer 1041 forms one electrode plate of the capacitor, and the second capacitor metal layer 2031 forms another electrode plate of the capacitor.

[0063] Referring to Figure 5 and Figure 6As shown, in an embodiment of the present application, the first metal layer 104 includes a first capacitor metal layer 1041 and two first contact metal layers 1042 arranged on both sides of the first capacitor metal layer 1041. The second metal layer 203 includes a second capacitor metal layer 2031 and two second contact metal layers 2032 arranged on both sides of the second capacitor metal layer 2031. At this time, a capacitor device can be formed in the subsequent process. In other embodiments of the present application, the first metal layer 104 includes at least two first capacitor metal layers 1041 which are laid on the second surface of the first adapter board 100, each of the at least two first capacitor metal layers 1041 covers at least one recess 103, and adjacent two of the at least two first capacitor metal layers 1041 are arranged with a spacing. Correspondingly, the second metal layer 203 includes at least two second capacitor metal layers 2031 which are laid on the second surface of the second adapter board 200, each of the at least two second capacitor metal layers 2031 covers at least one protrusion 202, and adjacent two of the at least two second capacitor metal layers 2031 are arranged with a spacing. In other embodiments of the present application, the first metal layer 104 includes a plurality of first contact metal layers 1042, and the second metal layer 203 includes a plurality of second contact metal layers 2032. The plurality of first contact metal layers 1042 are distributed on the second surface of the first adapter board 100, and the plurality of second metal layers 203 are distributed on the second surface of the second adapter board 200. After the first adapter board 100 and the second adapter board 200 are bonded, each of the first contact metal layers 1042 is connected with one of the second contact metal layers 2032. At this time, the number of capacitor devices formed is equal to the number of capacitor metal layers. Each of the first capacitor metal layer 1041 and the second capacitor metal layer 1042 arranged in pairs and the insulating layer 107 arranged between the first capacitor metal layer 1041 and the second capacitor metal layer 1042 forms a capacitor device.

[0064] Please refer to Figures 5 to 7In an embodiment of the present application, as shown in the figure, the first metal layer 104 is formed on the second surface of the first adapter plate 100, and the second metal layer 203 is formed on the second surface of the second adapter plate 200, and then the first adapter plate 100 and the second adapter plate 200 are bonded. When the first adapter plate 100 and the second adapter plate 200 are bonded, the insulating material is filled between the first metal layer 104 and the second metal layer 203, and between the gaps of the first adapter plate 100 and the second adapter plate 200, to form the insulating layer 105. The material of the insulating layer 105 is a thermoplastic material with high dielectric constant, such as ABF (Ajinomoto Build-up Film) material, chip low filling glue, etc. The insulating layer 105 with high dielectric constant can isolate the two electrode sheets of the capacitor, and then cooperate with the first metal layer 104 and the second metal layer 203 to form the capacitor. When the insulating layer 105 is arranged between the first adapter plate 100 and the second adapter plate 200, the thermoplastic material with high dielectric constant can be heated to have fluidity, and then the thermoplastic material can be filled into the gap between the first adapter plate 100 and the second adapter plate 200. After the gap between the first adapter plate 100 and the second adapter plate 200 is filled, the thermoplastic material is cooled and solidified to form the insulating layer 105.

[0065] Referring to Figure 7 In an embodiment of the present application, as shown in the figure, after the first adapter plate 100 and the second adapter plate 200 are bonded, the tooth-like structure formed by the recessed part 103 on the second surface of the first adapter plate 100 is nested with the tooth-like structure formed by the protruding part 202 on the second surface of the second adapter plate 200. The insulating layer 105 fills the gap between the first capacitor metal layer 1041 and the second capacitor metal layer 2031 to form the capacitor. At the same time, the first contact metal layer 1042 and the second contact metal layer 2032 are connected, and the insulating layer 105 fills the gaps on both sides of the first contact metal layer 1042 and the second contact metal layer 2032, and plays a supporting role between the first adapter plate 100 and the second adapter plate 200.

[0066] Referring to Figures 7 to 8 In an embodiment of the present application, as shown in the figure, after the capacitor is formed, the conductive metal material, such as copper, aluminum, gold, or an alloy of two or three of these metal materials, is deposited on the first surface of the first adapter plate 100 to form the connecting metal layer 106. The connecting metal layer 106 realizes the connection between the working chips.

[0067] Referring to Figures 7 to 8As shown in the embodiment of the present application, after the connection metal layer is formed, the first chip 300 and the second chip 400 are soldered on the connection metal layer 106, and the insulating material is deposited on the first chip 300 and the second chip 400 to form the protective layer 107. The solder balls 204 are formed on the second pads 201 of the first surface of the second adapter plate 200 by reflow soldering. The packaging of the first adapter plate 100, the second adapter plate 200, the first chip 300 and the second chip 400 is completed. In the embodiment, the protective layer 107 includes the first protective layer 1071 and the second protective layer 1072. The first protective layer 1071 is arranged between the first chip 300 and the first adapter plate 100, and between the second chip 400 and the first adapter plate 100, and fills the gap between the first chip 300, the second chip 400 and the first adapter plate 100. The second protective layer 1072 is arranged on the first chip 300 and the second chip 400, and covers the first chip 300 and the second chip 400. In the embodiment, the granularity of the first protective layer 1071 is smaller than the granularity of the second protective layer 1072. The first protective layer 1071 is made of, for example, a resin material with small granularity, and the second protective layer 1072 is made of, for example, an organic plastic packaging material with large granularity.

[0068] In summary, the present application provides a packaged chip and a manufacturing method thereof. The capacitor device is integrated between the first adapter plate and the second adapter plate. The working chip is arranged on the first adapter plate, and at least one recess is formed on the surface of the first adapter plate close to the second adapter plate, and at least one protrusion is formed on the surface of the second adapter plate close to the first adapter plate, and the protrusion is nested in the recess in a position relationship. Then, the first metal layer is laid on the surface of the first adapter plate close to the second adapter plate, and the first metal layer covers the recess, and the second metal layer is laid on the surface of the second adapter plate close to the first adapter plate, and the second metal layer covers the protrusion. Finally, the first adapter plate and the second adapter plate are bonded, and the insulating layer is arranged between the first metal layer and the second metal layer, and the first metal layer, the insulating layer and the second metal layer form the capacitor device. The capacitor device is integrated in the packaged chip, and the capacitor structure is close to the power supply network.

[0069] The embodiments disclosed above are only used to help explain the present application. The embodiments do not describe all the details, and do not limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of the present application. The embodiments are selected and described in detail in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well understand and utilize the present application. The present application is limited by the claims and the entire scope and equivalents thereof.

Claims

1. A packaged chip, comprising: At least comprising: a first adapter plate and a second adapter plate, the second adapter plate is bonded with the first adapter plate; a working chip, disposed on the side of the first adapter plate away from the second adapter plate; at least one recess, disposed on the surface of the first adapter plate close to the second adapter plate; at least one protrusion, disposed on the surface of the second adapter plate close to the first adapter plate, and the protrusion is nested with the recess in alignment; a first metal layer, laid on the surface of the first adapter plate close to the second adapter plate, and the first metal layer covers the recess; a second metal layer, laid on the surface of the second adapter plate close to the first adapter plate, and the second metal layer covers the protrusion; and an insulating layer, disposed between the first metal layer and the second metal layer, the first metal layer, the insulating layer and the second metal layer form a capacitor device; wherein, when the working chip disposed on the adapter plate is a power chip, a capacitor device is disposed in the adapter plate at the position of the power chip; wherein, the first metal layer comprises a first capacitor metal layer, the first capacitor metal layer covers the recess; the second metal layer comprises a second capacitor metal layer, the second capacitor metal layer covers the protrusion, and the second capacitor metal layer and the first capacitor metal layer are disposed in alignment; the first metal layer comprises a first contact metal layer, the first contact metal layer is disposed on both sides of the first capacitor metal layer; the second metal layer comprises a second contact metal layer, the second contact metal layer is disposed on both sides of the second capacitor metal layer, and the second contact metal layer and the first contact metal layer are disposed in alignment. In the first adapter plate and the second adapter plate, a through-silicon via structure is disposed.

2. The chip package of claim 1, wherein On the surface of the first adapter plate close to the second adapter plate, one recess is disposed between two adjacent through-silicon via structures; on the surface of the second adapter plate close to the first adapter plate, one protrusion is disposed between two adjacent through-silicon via structures.

3. The chip package of claim 2, wherein On the surface of the first adapter plate close to the second adapter plate, two or more recesses are disposed between two adjacent through-silicon via structures; on the surface of the second adapter plate close to the first adapter plate, two or more protrusions are disposed between two adjacent through-silicon via structures.

4. The chip package of claim 2, wherein The recess and the protrusion are rectangular, pentagonal, hexagonal, or rectangular, pentagonal, hexagonal with rounded corners.

5. The chip package of claim 1, wherein The sum of the thicknesses of the first contact metal layer and the second contact metal layer is equal to the sum of the thicknesses of the first capacitor metal layer, the second capacitor metal layer and the insulating layer.

6. The chip package of claim 1, wherein The first metal layer comprises one first capacitor metal layer and two first contact metal layers, and the second metal layer comprises one second capacitor metal layer and two second contact metal layers.

7. The chip package of claim 1, wherein ​ 8. The chip package of claim 1, wherein The first metal layer comprises at least two first capacitor metal layers, the at least two first capacitor metal layers are laid on the surface of the first adapter plate, each of the first capacitor metal layers covers one of the recesses, and adjacent two of the first capacitor metal layers are provided with a spacing; the second metal layer comprises at least two second capacitor metal layers, the at least two second capacitor metal layers are laid on the surface of the second adapter plate, each of the second capacitor metal layers covers one of the protrusions, and adjacent two of the second capacitor metal layers are provided with a spacing.

9. A method of manufacturing a packaged chip, characterized by: At least comprising the following steps: providing a first adapter plate and a second adapter plate; etching the surface of the first adapter plate close to the second adapter plate to form at least one recess; etching the surface of the second adapter plate close to the first adapter plate to form at least one protrusion, and the protrusion is in registration and nested with the recess; laying a first metal layer on the surface of the first adapter plate close to the second adapter plate, and the first metal layer covers the recess; laying a second metal layer on the surface of the second adapter plate close to the first adapter plate, and the second metal layer covers the protrusion; bonding the second adapter plate and the first adapter plate, and providing an insulating layer between the first metal layer and the second metal layer, the first metal layer, the insulating layer and the second metal layer form a capacitor device; wherein, when the working chip provided on the adapter plate is a power chip, a capacitor device is provided in the adapter plate at the position of the power chip; wherein, the first metal layer comprises a first capacitor metal layer, the first capacitor metal layer covers the recess; the second metal layer comprises a second capacitor metal layer, the second capacitor metal layer covers the protrusion, and the second capacitor metal layer and the first capacitor metal layer are in registration; the first metal layer comprises a first contact metal layer, the first contact metal layer is provided on both sides of the first capacitor metal layer; the second metal layer comprises a second contact metal layer, the second contact metal layer is provided on both sides of the second capacitor metal layer, and the second contact metal layer and the first contact metal layer are in registration.

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