Three-dimensional chip packaging structure and manufacturing method thereof

Abstract

The invention discloses a three-dimensional chip packaging structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. The packaging structure comprises a first chip and a second chip, the first chip and the second chip are oppositely arranged, and the first chip and the second chip are bonded through a connection bonding pad; the capacitor is arranged between the first chip and the second chip, the capacitor comprises a first polar plate and a second polar plate, the first polar plate is arranged on the first chip, and the second polar plate is arranged on the second chip; and the first insulating layer is filled among the connecting bonding pad, the first polar plate and the second polar plate. According to the three-dimensional chip packaging structure and the manufacturing method thereof provided by the invention, the capacitor can be integrated in a three-dimensional direction, the capacitance area can be greatly increased, the distance from the capacitor to a power supply network is shortened, and the performance of the packaging structure is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a three-dimensional chip packaging structure and a manufacturing method thereof. Background Art

[0002] In the traditional packaging structure, each module is packaged independently and finally connected to each other through a substrate to form a system. It is a two-dimensional system, which leads to a large size of the packaging structure and does not meet the demand for increased integration. In the packaging structure, capacitors are provided for energy storage, filtering, tuning and decoupling. However, in the current packaging structure, the capacitor and the chip are often laid flat on a substrate, and the capacitor is connected to the chip through the substrate. There are problems such as large occupied area, far from the power supply network, and inability to integrate large capacitors, which limits the integration of semiconductor packaging structures. Summary of the invention

[0003] The purpose of the present invention is to provide a three-dimensional chip packaging structure and a manufacturing method thereof. Through the three-dimensional chip packaging structure and a manufacturing method thereof provided by the present invention, chips with multiple functions can be packaged together in one package. The packaging structure is the same size as the chip, and a capacitor structure is innovatively added between the two chip bonding surfaces, which can greatly increase the capacitance area, shorten the distance from the capacitor to the power supply network, and improve the performance of the packaging structure.

[0004] In order to solve the above technical problems, the present invention provides a three-dimensional chip packaging structure, which at least comprises:

[0005] A first chip and a second chip, wherein the first chip and the second chip are arranged opposite to each other and are bonded to each other via a connection pad;

[0006] a capacitor, disposed between the first chip and the second chip, and comprising a first plate and a second plate, wherein the first plate is disposed on the first chip and the second plate is disposed on the second chip; and

[0007] The first insulating layer is filled between the connecting pad, the first electrode plate and the second electrode plate.

[0008] In an embodiment of the present invention, the first chip includes a plurality of first connection structures, and the connection pads on the first chip are connected to the first connection structures at both ends.

[0009] In one embodiment of the present invention, the first electrode plate is located between the connecting pads, and the first electrode plate is connected to a portion of the first connecting structure.

[0010] In an embodiment of the present invention, the second chip includes a plurality of second connection structures, and the connection pads on the second chip are connected to the second connection structures at both ends.

[0011] In one embodiment of the present invention, the second electrode plate is located between the connecting pads, and the second electrode plate is connected to a portion of the second connecting structure.

[0012] In one embodiment of the present invention, the first electrode plate and the second electrode plate have the same thickness and area, and the thickness of the first electrode plate or the second electrode plate is 20% to 50% of the thickness of the connecting pad.

[0013] In an embodiment of the present invention, a first solder ball is disposed on a side of the second chip away from the first chip, a second port and a metal layer are disposed between the first solder ball and the second chip, and the metal layer is disposed on the second port.

[0014] In an embodiment of the present invention, a first port is provided on a side of the first chip away from the second chip, a metal layer is provided on the first port, and a second insulating layer is provided on the metal layer and the first chip.

[0015] In one embodiment of the present invention, a second solder ball is disposed on a side of the first chip away from the second chip, a first port is disposed between the second solder ball and the first chip, and a third chip and a fourth chip are bonded to the second solder ball.

[0016] The present invention also provides a method for manufacturing a three-dimensional chip packaging structure, which at least comprises the following steps:

[0017] providing a first chip and a second chip;

[0018] forming a first electrode plate and a connecting pad on one side of the first chip;

[0019] forming a second electrode plate and a connection pad on opposite sides of the second chip and the first chip;

[0020] The first chip and the second chip are bonded by connecting pads, and the first chip and the second chip are arranged opposite to each other; and

[0021] A first insulating layer is filled between the connection pad, the first electrode plate, and the second electrode plate to form a capacitor between the first chip and the second chip, wherein the capacitor includes the first electrode plate and the second electrode plate.

[0022] In summary, the present invention provides a three-dimensional chip packaging structure and a manufacturing method thereof. By adopting a system-level packaging structure, chips with multiple functions are packaged in one package. The packaging structure is the same size as the chip, with a smaller size, a lower thickness, and a more integrated system. A capacitor structure is innovatively added between the two chip bonding surfaces, and the capacitor is integrated in a three-dimensional direction to ensure that the package size is smaller, the system is more integrated, and the device performance is more superior. The capacitor structure is innovatively added between the two chip bonding surfaces, which can greatly increase the capacitor area and improve the capacity. The capacitor is closer to the chip itself, shortening the distance from the capacitor to the power supply network, and improving the performance of the packaging structure. Through the bonding between the chips, the large capacitor formed is located between the chips, and the entire packaging structure is the same size as the chip, with a smaller size, a lower thickness, and a better market prospect. Without increasing the area of ​​the packaging structure, the function of the packaging structure is increased, the needs of different packaging structures are met, the integration of the packaging structure is improved, and the three-dimensional chip packaging structure is obtained, which can be widely used in various emerging industries such as information, energy, and communications.

[0023] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0025] Figure 1 FIG. 4 is a schematic diagram of a first chip in an embodiment of the present invention.

[0026] Figure 2 FIG. 4 is a schematic diagram of a second chip according to an embodiment of the present invention.

[0027] Figure 3 FIG. 4 is a schematic diagram of a first chip after thinning in one embodiment of the present invention.

[0028] Figure 4 FIG. 4 is a schematic diagram of a second chip after thinning in one embodiment of the present invention.

[0029] Figure 5 It is a schematic diagram of forming a first electrode plate and a connecting pad on a first chip in one embodiment of the present invention.

[0030] Figure 6 It is a schematic diagram of forming a second electrode plate and a connecting pad on a second chip in one embodiment of the present invention.

[0031] Figure 7FIG. 1 is a schematic diagram of forming a capacitor after a first chip and a second chip are bonded together in one embodiment of the present invention.

[0032] Figure 8 FIG. 4 is a schematic diagram of a three-dimensional chip packaging structure according to an embodiment of the present invention.

[0033] Fig. 9 FIG. 4 is a schematic diagram of a three-dimensional chip packaging structure in another embodiment of the present invention.

[0034] Description of labels:

[0035] 100, first chip; 101, first connection structure; 102, first port; 103, first electrode; 104, connecting pad; 111, front side; 112, back side; 200, second chip; 201, second connection structure; 202, second port; 203, first metal layer; 204, second electrode; 211, first surface; 212, second surface; 300, capacitor; 11, first insulating layer; 12, first solder ball; 13, second metal layer; 14, second insulating layer; 15, second solder ball; 16, plastic package substrate; 17, third insulating layer; 21, third chip; 22, fourth chip. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0038] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0039] See also Figures 8 to 9 As shown, the present invention provides a three-dimensional chip packaging structure, which at least includes a first chip 100, a second chip 200 and a capacitor 300. Among them, the first chip 100 and the second chip 200 are arranged relative to each other and connected by a connecting pad 104. The capacitor 300 is arranged between the first chip 100 and the second chip 200, and the first plate 103 of the capacitor 300 is arranged on the first chip 100, and the second plate 204 is arranged on the second chip 200. The two ends of the first plate 103 and the second plate 204 have a preset distance from the connecting pad 104, and the first insulating layer 11 is filled between the first plate 103, the second plate 204 and the connecting pad 104. The present invention adopts a system-level packaging structure, and chips with multiple functions are centrally packaged in one package. The packaging structure is the same size as the chip, with a smaller size, a lower thickness, and a more integrated system. The capacitor structure is innovatively added between the bonding surfaces of the two chips, which can greatly increase the capacitance area and improve the capacitance value. The capacitor is closer to the device itself, which can better improve the performance of the device. Specifically, the specific structure of the three-dimensional chip packaging structure of the present application and the manufacturing method of the three-dimensional chip packaging structure are as follows: Figures 1 to 9 The three-dimensional chip packaging structure and the manufacturing method thereof provided by the present application can improve the performance of the three-dimensional chip packaging structure and the integration of the packaging system. The three-dimensional chip packaging structure can be widely used in various emerging industries such as information, energy, and communications.

[0040] See also Figure 1 As shown, in one embodiment of the present invention, a first chip 100 is provided, and the first chip 100 includes a front side 111 and a back side 112. The front side 111 includes a key part for the first chip 100 to realize its functions, and the back side is a supporting and protecting part of the first chip 100. A plurality of first connection structures 101 are arranged inside the first chip 100, and the first connection structures 101 extend from the front side 111 into the first chip 100, and have a preset distance from the back side. Figure 1 The number and position of the first connection structure 101 in the figure are only taken as examples. The first connection structure 101, for example, includes a conductive material, and the conductive material is, for example, a conductive material or alloy such as copper, aluminum or tungsten. A plurality of first ports 102 are arranged on the front side 111 of the first chip 100, and the first port 102 is, for example, arranged on the first connection structure 101 and connected to the first connection structure 101, wherein the first port 102 is, for example, an input / output port (Input / Output Port, IO), and the first port 102 is, for example, made of a conductive material, and for example, a conductive material or alloy such as copper, aluminum or tungsten. In the present embodiment, the first chip 100 is, for example, a memory chip, etc. In other embodiments, the first chip 100 can be selected according to usage requirements.

[0041] See also Figure 2As shown, in one embodiment of the present invention, the present invention also provides a second chip 200, the second chip 200 includes a first surface 211 and a second surface 212, the first surface 211 includes a key part of the second chip 200 to realize the function, and the second surface 212 is a supporting and protecting part of the second chip 200. Inside the second chip 200, a plurality of second connection structures 201 are arranged, and the second connection structures 201 extend from the first surface 211 into the second chip 200 and have a preset distance from the second surface 212. Figure 2 The number and position of the first connection structure 101 in the figure are only taken as examples. The second connection structure 201, for example, includes a conductive material, and the conductive material is, for example, a conductive material or alloy such as copper, aluminum or tungsten. A plurality of second ports 202 are arranged on the first surface 211 of the second chip 200, and the second ports 202 are, for example, arranged on the second connection structure 201 and connected to the second connection structure 201, wherein the second ports 202 are, for example, input and output ports, and the second ports 202 are, for example, made of a conductive material, and for example, a conductive material or alloy such as copper, aluminum or tungsten. In the present embodiment, the second chip 200 is, for example, a power chip, etc. In other embodiments, the second chip 200 can be selected according to usage requirements.

[0042] See also Figure 2 As shown, in one embodiment of the present invention, a first metal layer 203 is formed on the first surface 211 of the second chip 200, and the first metal layer 203 is, for example, arranged to wrap the second port 202, that is, part of the first metal layer 203 is located on the second port 202, and part of the first metal layer 203 is arranged around the second port 202. The first metal layer 203 is, for example, a conductive material or alloy such as copper, aluminum or silver, and is electrically connected to the second port 202 to connect the signal on the chip, and the center of the first metal layer 203 corresponds to the center of the second port 202. The present application does not limit the method for forming the first metal layer 203, for example, it is obtained by wafer-level manufacturing processes such as exposure, development, and electroplating, which will not be elaborated here.

[0043] See also Figures 1 to 4As shown, in one embodiment of the present invention, the first chip 100 and the second chip 200 are thinned. Specifically, a temporary carrier (not shown in the figure) is bonded to the front side 111 of the first chip 100, and the wafer is thinned from the back side 112 of the first chip 100 until the first connection structure 101 is exposed. A temporary carrier (not shown in the figure) is bonded to the first surface 211 of the second chip 200, and the wafer is thinned from the second surface 212 of the second chip 200 until the second connection structure 201 is exposed. The chip is thinned, for example, by etching, mechanical grinding or chemical mechanical polishing (CMP), etc., to ensure that the first connection structure 101 and the second connection structure 201 are exposed, so as to facilitate subsequent signal connection, and after thinning, the first connection structure 101 or the second connection structure 201 is flush with the structures on both sides thereof, that is, the back side 112 of the first chip 100 is flush, and the second surface 212 of the second chip 200 is flush. A temporary carrier is bonded on the first chip 100 and the second chip 200 to protect the chips during the thinning process and to enhance the mechanical strength of the chips after thinning, thereby facilitating subsequent processes.

[0044] See also Figure 3 and Figure 5As shown, in one embodiment of the present invention, after the first chip 100 is thinned, a first electrode plate 103 and a connecting pad 104 are formed on the back side 112 of the first chip 100, and the first electrode plate 103 and the connecting pad 104 are arranged at intervals. In this embodiment, the first electrode plate 103 is, for example, located between the connecting pads 104, and the materials of the first electrode plate 103 and the connecting pad 104 are, for example, the same, and are, for example, metal materials such as copper, and the thickness of the first electrode plate 103 is less than the thickness of the connecting pad 104, and the thickness of the first electrode plate 103 is, for example, 20% to 50% of the thickness of the connecting pad 104. Specifically, a metal layer (not shown in the figure) is deposited on the back side 112, and a patterned photoresist layer (not shown in the figure) is formed on the metal layer. For example, dry etching is performed and stopped when the back side 112 is reached. The metal layer is segmented, the patterned photoresist layer is removed, and then a new patterned photoresist layer (not shown in the figure) is formed. For example, part of the metal layer is etched by dry etching or other methods and stopped when the back side 112 is reached. The metal layer is segmented, the patterned photoresist layer is removed, and then a new patterned photoresist layer (not shown in the figure) is formed. For example, the metal layer in the middle part is thinned by dry etching, etc., thereby forming the first electrode 103 and the connecting pad 104. In another embodiment of the present invention, for example, after the metal layer is deposited, a photoresist layer is formed on the metal layer, and the thickness of the photoresist layer retained at different positions on the metal layer is different by controlling the exposure amount at different positions, so that part of the metal layer is completely etched, part of the metal layer is partially etched, and part of the metal layer is not etched by etching once, thereby forming the first electrode 103 and the connecting pad 104. In another embodiment of the present invention, if the materials of the first electrode 103 and the connecting pad 104 are different, they can be prepared by depositing the photoresist layer twice. The present application does not limit the specific formation method of the first electrode and the connecting pad, which can be selected according to the manufacturing requirements.

[0045] See also Figure 4 and Figure 6As shown, in one embodiment of the present invention, after the second chip 200 is thinned, a second electrode plate 204 and a connecting pad 104 are formed on the second surface 212 of the second chip 200, and the second electrode plate 204 and the connecting pad 104 are arranged at intervals. In this embodiment, the second electrode plate 204 is, for example, located between the connecting pads 104, and the materials of the second electrode plate 204 and the connecting pad 104 are, for example, the same, and are, for example, metal materials such as copper, and the thickness of the second electrode plate 204 is less than the thickness of the connecting pad 104, and the thickness of the second electrode plate 204 is, for example, 20% to 50% of the thickness of the connecting pad 104. In this embodiment, the thickness of the second electrode plate 204 is, for example, equal to the thickness of the first electrode plate 103, and the area of ​​the second electrode plate 204 and the first electrode plate 103 is equal. The method for forming the second electrode plate 204 and the connecting pad 104 on the second chip 200 is, for example, the same as the method for forming the first electrode plate 103 and the connecting pad 104 on the first chip 100 , and will not be elaborated herein.

[0046] See also Figure 5 and Figure 6 As shown, in one embodiment of the present invention, on the first chip 100, the connection pad 104 is, for example, connected to the first connection structure 101 at both ends of the first chip 100, and the first electrode plate 103 is connected to the first connection structure 101 in the middle. On the second chip 200, the connection pad 104 is, for example, connected to the second connection structure 201 at both ends of the second chip 200, and the second electrode plate 204 is connected to the second connection structure 201 in the middle. After subsequent bonding, the first chip 100 and the second chip 200 can complete signal communication between the chips through the connection pad 104, and part of the connection structure completes the control of the capacitance.

[0047] See also Figures 5 to 7As shown, in one embodiment of the present invention, after forming the electrode plate and the connecting pad, the first chip 100 and the second chip 200 are placed opposite to each other on one side with the connecting pad, that is, the back side 112 and the second surface 212 for bonding. Among them, the connecting pad 104 on the first chip 100 is electrically connected to the connecting pad 104 on the second chip 200 to complete the bonding between the chips. After the bonding is completed, the temporary carrier on the first chip 100 and the second chip 200 is removed. After the first chip 100 and the second chip 200 are bonded, an insulating material with a high dielectric constant is filled between the second chip 200 and the first chip 100 to form a first insulating layer 11, and the opposite surfaces of the first chip 100 and the second chip 200 are completely sealed in the first insulating layer 11. The first insulating layer 11 includes, for example, ABF (Ajinomoto Build-up Film) material, chip low-fill glue and other thermoplastic profiles, which have a certain fluidity after heating. Since the metal layer at the first electrode 103 and the second electrode 204 is relatively thin, it can be ensured that the insulating material can be completely filled between the first chip 100 and the second chip 200, and finally solidified to form the first insulating layer 11. The present invention adopts system-level packaging, which can package chips with multiple functions in one package, making the system more integrated and smaller in size. The two active chips are three-dimensionally docked, and the chips are interconnected to realize the function of the entire system.

[0048] See also Figure 7 As shown, in one embodiment of the present invention, after forming the first insulating layer 11, the first plate 103, the second plate 204 and the first insulating layer 11 between the plates constitute a capacitor 300. Among them, the first plate 103 of the capacitor 300 is arranged on the first chip 100, the second plate 204 is arranged on the second chip 200, the two ends of the first plate 103 and the second plate 204 have a preset distance from the connecting pad 104, and the first plate 103 and the second plate 204 are placed in the area where the power source is concentrated to shorten the distance from the capacitor to the power supply network. In the present invention, the entire capacitor 300 is formed inside the package between the chips, and the capacitor is integrated in a three-dimensional direction to ensure that the package size is smaller, the system is more integrated, and the device performance is more superior. The capacitor structure is innovatively added between the bonding surfaces of the two chips, which can greatly increase the capacitor area and improve the capacity. The capacitor is closer to the chip itself, shortens the distance from the capacitor to the power supply network, and improves the performance of the packaging structure. Through the bonding between the chips, the large capacitor formed is located between the chips, and the entire packaging structure is the same size as the chip, with a smaller size, lower thickness, and better market prospects.

[0049] See also Figures 7 and 8As shown, in one embodiment of the present invention, after forming the first insulating layer 11, a first solder ball 12 is formed on the first metal layer 203 of the second chip 200. The first solder ball 12 is, for example, a tin-silver ball, etc., for connecting the three-dimensional chip packaging structure with the subsequent substrate. The first solder ball 12 is located at the center of the first metal layer 203, and the first solder ball 12 corresponds to the first metal layer 203 one by one, and the first solder ball 12 is electrically connected to the first metal layer 203. On the first chip 100, a second metal layer 13 is formed, and the second metal layer 13 is connected to at least one first port 102 and wraps the first port 102. The second metal layer 13 is, for example, a conductive material or alloy such as copper, aluminum or silver, and is electrically connected to the first port 102 for interconnection of chip signals. The second metal layer 13 is obtained, for example, by wafer-level manufacturing processes such as deposition, exposure, development, and etching, which will not be elaborated here. After forming the second metal layer 13, a second insulating layer 14 is formed on the second metal layer 13 and the first chip 100. The second insulating layer 14 is, for example, an organic plastic material, such as epoxy resin, polyethylene, polypropylene or polyimide, to prevent circuit short circuits, provide mechanical support and prevent the external environment from affecting the three-dimensional chip packaging structure.

[0050] See also Figure 7 and Fig. 9 As shown, in another embodiment of the present invention, after forming the first insulating layer 11, a first solder ball 12 is formed on the first metal layer 203 of the second chip 200. The first solder ball 12 is, for example, a tin-silver ball, etc., for connecting the three-dimensional chip packaging structure with the subsequent substrate. The first solder ball 12 is located at the center of the first metal layer 203, and the first solder ball 12 corresponds to the first metal layer 203 one by one, and the first solder ball 12 is adapted to be electrically connected to the first metal layer 203. On the first chip 100, a second solder ball 15 is formed on the first port 102, wherein the second solder ball 15 is, for example, a tin-silver ball, etc., for connecting the three-dimensional chip packaging structure with other chips. The second solder ball 15 is located at the center of the first port 102, and the second solder ball 15 corresponds to the first port 102 one by one, and the second solder ball 15 is adapted to be electrically connected to the first port 102.

[0051] See also Figure 7 and Fig. 9As shown, in another embodiment of the present invention, after forming the second solder ball 15, a plurality of chips such as the third chip 21 and the fourth chip 22 are bonded to the first chip 100, and the third chip 21 and the fourth chip 22 are bonded to the first chip 100, for example, by a wafer-to-wafer or chip-to-wafer bonding method, and for example, the first chip 100 and the third chip 21 and the fourth chip 22 are connected by the second solder ball 15. The present invention does not limit the specific types of the third chip 21 and the fourth chip 22, which can be selected according to needs or uses. After the third chip 21 and the first chip 100, and the fourth chip 22 and the first chip 100 are bonded, a plastic sealant is filled between the first chip 100, the third chip 21 and the fourth chip 22 and cured to form a plastic sealant matrix 16, and the plastic sealant matrix 16 includes, for example, epoxy resin, silicone sealant or polyurethane sealant. After the plastic sealant matrix 16 is formed, a third insulating layer 17 is formed on the third chip 21, the fourth chip 22 and the first chip 100. The third insulating layer 17 is, for example, an organic plastic material, such as epoxy resin, polyethylene, polypropylene or polyimide, to prevent short circuits, provide mechanical support and prevent the external environment from affecting the three-dimensional chip packaging structure. That is, after the first chip 100 and the second chip 200 are bonded, other chips can be bonded on the first chip 100, and the function of the packaging structure can be increased without increasing the area of ​​the packaging structure, so as to meet the needs of different packaging structures and improve the integration of the packaging structure.

[0052] In summary, the present invention provides a three-dimensional chip packaging structure and a manufacturing method thereof. By adopting a system-level packaging structure, chips with multiple functions are packaged in one package. The packaging structure is the same size as the chip, with a smaller size, a lower thickness, and a more integrated system. A capacitor structure is innovatively added between the two chip bonding surfaces, and the capacitor is integrated in a three-dimensional direction to ensure that the package size is smaller, the system is more integrated, and the device performance is more superior. The capacitor structure is innovatively added between the two chip bonding surfaces, which can greatly increase the capacitor area and improve the capacity. The capacitor is closer to the chip itself, shortening the distance from the capacitor to the power supply network, and improving the performance of the packaging structure. Through the bonding between the chips, the large capacitor formed is located between the chips, and the entire packaging structure is the same size as the chip, with a smaller size, a lower thickness, and a better market prospect. Without increasing the area of ​​the packaging structure, the function of the packaging structure is increased, the needs of different packaging structures are met, the integration of the packaging structure is improved, and the three-dimensional chip packaging structure is obtained, which can be widely used in various emerging industries such as information, energy, and communications.

[0053] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the inventive concept, such as a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

[0054] Except for the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be described here in detail.

Claims

1. A three-dimensional chip packaging structure, characterized in that: At least: A first chip and a second chip, wherein the first chip and the second chip are arranged opposite to each other and are bonded to each other via a connection pad; A capacitor is arranged between the first chip and the second chip, and the capacitor includes a first plate and a second plate, the first plate is arranged on the first chip, and the second plate is arranged on the second chip; as well as The first insulating layer is filled between the connecting pad, the first electrode plate and the second electrode plate.

2. The three-dimensional chip packaging structure according to claim 1, characterized in that: The first chip includes a plurality of first connection structures, and the connection pads on the first chip are connected to the first connection structures at both ends.

3. The three-dimensional chip packaging structure according to claim 2, characterized in that: The first electrode plate is located between the connecting pads, and the first electrode plate is connected to a portion of the first connecting structure.

4. The three-dimensional chip packaging structure according to claim 1, characterized in that: The second chip includes a plurality of second connection structures, and the connection pads on the second chip are connected to the second connection structures at both ends.

5. The three-dimensional chip packaging structure according to claim 4, characterized in that: The second electrode plate is located between the connecting pads, and the second electrode plate is connected to a portion of the second connecting structure.

6. The three-dimensional chip packaging structure according to claim 1, characterized in that: The first electrode plate and the second electrode plate have the same thickness and area, and the thickness of the first electrode plate or the second electrode plate is 20% to 50% of the thickness of the connecting pad.

7. The three-dimensional chip packaging structure according to claim 1, characterized in that: A first solder ball is arranged on a side of the second chip away from the first chip, a second port and a metal layer are arranged between the first solder ball and the second chip, and the metal layer is arranged on the second port.

8. The three-dimensional chip packaging structure according to claim 1, characterized in that: A first port is arranged on a side of the first chip away from the second chip, a metal layer is arranged on the first port, and a second insulating layer is arranged on the metal layer and the first chip.

9. The three-dimensional chip packaging structure according to claim 1, characterized in that: A second solder ball is disposed on a side of the first chip away from the second chip, a first port is disposed between the second solder ball and the first chip, and a third chip and a fourth chip are bonded to the second solder ball.

10. A method for manufacturing a three-dimensional chip packaging structure, characterized in that: At least the following steps are included: providing a first chip and a second chip; forming a first electrode plate and a connecting pad on one side of the first chip; forming a second electrode plate and a connection pad on opposite sides of the second chip and the first chip; The first chip and the second chip are bonded by connecting pads, and the first chip and the second chip are arranged opposite to each other; as well as A first insulating layer is filled between the connection pad, the first electrode plate, and the second electrode plate to form a capacitor between the first chip and the second chip, wherein the capacitor includes the first electrode plate and the second electrode plate.

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