Fnirs host interconnection device and method, host and interconnection components thereof, host computer and imaging system

Abstract

The present application provides an interconnection device and method of an FNIRS host, a host and its interconnection components, a host computer and an imaging system. The interconnection device includes: a first interconnection interface and at least one second interconnection interface, the two interfaces have different explicit physical properties, the FNIRS host plugged into the first interconnection interface is used as a master device, and the FNIRS host plugged into the second interconnection interface is used as a slave device; a main processor is configured to sample the received marking trigger signal based on a second sampling rate greater than the first sampling rate of the FNIRS host, and send out the marking timing data obtained after sampling; a processing circuit is configured to receive the acquisition synchronization timing signal sent by the master device through the first interconnection interface, and send the acquisition synchronization timing signal to each slave device through the second interconnection interface. This solution can conveniently realize the interconnection of multiple low-channel FNIRS hosts, and construct a near-infrared device joint use solution with a compact structure, simple connection and adaptability to various modal collaborative joint use scenarios.

Description

Technical Field

[0001] The present application relates to the field of near-infrared spectroscopy technology, and in particular to an interconnection device and method of an FNIRS host, a host and interconnection components thereof, a host computer and an imaging system. Background Art

[0002] Functional near-infrared spectroscopy (FNIRS) uses the good scattering property of the main components of blood to near-infrared light of 600-900nm. After the near-infrared detection data is collected by the equipment, the changes of oxyhemoglobin and deoxyhemoglobin (blood oxygen data) can be obtained by analyzing the near-infrared detection data.

[0003] This technology has begun to be used in the study of advanced cognition, developmental psychology, abnormal psychology and other fields in natural situations. As fNIRS equipment is more widely used in brain research, the number of brain locations and sites of interest in complex application scenarios has gradually increased. Therefore, the demand for the use of fNIRS systems with high SD channels has also increased. At present, many users already have several low-channel fNIRS systems with low SD channels, such as Figure 1 As shown in the figure, a set of fNIRS system includes a head cap, SD probe and cable, fNIRS host also called acquisition machine, and a host computer for receiving acquisition data and presenting the acquisition and analysis software interface. Due to the high purchase cost of high SD channel number, users often expect to be able to perform simple operations on several existing low-channel fNIRS systems with low SD channel number, and to minimize the cost of updating and modifying the existing low-channel fNIRS systems to achieve the acquisition of brain near-infrared detection data with high SD channel number.

[0004] In the related art, multiple fNIRS systems can be interconnected in a daisy-chain manner using interconnection devices to measure larger brain areas of interest, achieve higher density configurations, and achieve superscanning fNIRS measurements. The dorsal side of the fNIRS host has cascade ports (expanded ports A and B) such as Figure 2 As shown, one is connected to the upstream fnirs host and the other is connected to the downstream fnirs host to expand the number of SD detectors and channels. Currently, the interconnection devices used to interconnect multiple fnirs hosts have the following defects.

[0005] The interconnection method of multiple low-channel FNIRS hosts to obtain a high-channel FNIRS imaging system through a daisy chain is complex and has many lines; in addition, the interconnection device has two connectors and wires that look the same, that is, the two connectors connected to the interconnection device look the same. Users cannot determine which FNIRS host is the main device, nor can they determine which FNIRS host corresponding host computer to go to to view the signal acquisition and analysis results. In addition, when a large number of FNIRS hosts are connected in series in daisy chain mode, the time delay between FNIRS hosts that are far away will be significantly increased. Summary of the invention

[0006] The present application aims to provide an interconnection device and method for an fNIRS host, a host and its interconnection components, a host computer and an imaging system. The interconnection device is compatible with the marking-related functions required in the collaborative data acquisition process of fNIRS and other modalities, so as to conveniently and compactly realize the star-shaped interconnection of multiple low-channel fNIRS hosts, thereby realizing high-channel data acquisition of the subject.

[0007] According to the first aspect of the present application, an interconnection device for an FNIRS host is provided. The interconnection device is box-shaped and realizes star-shaped interconnection of several FNIRS hosts via several strip-shaped interconnection devices. The interconnection device includes: a first interconnection interface and at least one second interconnection interface, a main processor and a processing circuit. Among them,

[0008] A first interconnection interface and at least one second interconnection interface, wherein the second interconnection interface has different explicit physical properties from the first interconnection interface, the first interconnection interface is configured to be removably connected to a single strip interconnection device, so that the FNIRS host plugged on the opposite side of the strip interconnection device is used as a master device in the interconnection, and each second interconnection interface is configured to be removably connected to each strip interconnection device, so that the FNIRS host plugged on the opposite side of each strip interconnection device is used as a slave device in the interconnection. The main processor is configured to sample the received marking trigger signal based on a second sampling rate greater than the first sampling rate of the FNIRS host, and send out the marking timing data obtained after sampling. The processing circuit is configured to receive the acquisition synchronization timing signal sent by the master device through the first interconnection interface, and send the acquisition synchronization timing signal to each of the slave devices through the second interconnection interface. The acquisition synchronization timing signal is used by the master device and each slave device in combination with the local acquisition timing configuration information to synchronously collect near-infrared detection data.

[0009] According to a second aspect of the present application, a FNIRS host for interconnecting with other FNIRS hosts to form a higher number of detection channels is provided. The FNIRS host includes: at least one interface, a processing circuit unit separated from a main processor, and a main processor. The at least one interface is configured to be connected to a first interconnection interface or a second interconnection interface of an interconnection device of the FNIRS host; wherein, via connection with the first interconnection interface, the FNIRS host is used as a master device among multiple interconnected FNIRS hosts, and via connection with the second interconnection interface, the FNIRS host is used as a slave device among multiple interconnected FNIRS hosts. The processing circuit unit separated from the main processor is configured to identify the interface type of the interconnection device interface connected to the at least one interface; when the at least one interface is connected to the first interconnection interface, an acquisition synchronization timing signal is sent to the interconnection device via the at least one interface and the first interconnection interface, and when the at least one interface is connected to the second interconnection interface, an acquisition synchronization timing signal from the second interconnection interface of the interconnection device is received via the at least one interface. The main processor is configured to use the received acquisition synchronization timing signal to control the synchronous acquisition of near-infrared detection data when the processing circuit unit receives the acquisition synchronization timing signal, otherwise use the externally transmitted acquisition synchronization timing signal to control the synchronous acquisition of near-infrared detection data, and the acquisition synchronization timing signal at least indicates the start time of a series of acquisition cycles of synchronous acquisition.

[0010] According to a third aspect of the present application, a host computer for interconnecting FNIRS hosts is provided. Multiple FNIRS hosts are connected to each other through a first interconnection interface or a second interconnection interface of an interconnection device to achieve interconnection. The first interconnection interface is used to connect to a master device in an interconnected host, and the first interconnection interface is used to connect to a slave device in an interconnected host, and the first interconnection interface and the second interconnection interface have different explicit physical properties. The host computer performs the following steps through a processor.

[0011] In response to meeting the sending condition of the acquisition timing configuration information, the acquisition timing configuration information is sent to the master device and the slave device in the multiple interconnected fnirs hosts, so that the master device and the slave device respectively store the acquisition timing configuration information locally in each device.

[0012] In response to satisfying the data acquisition conditions, an acquisition instruction is sent to the master device, so that the master device sends an acquisition synchronization timing signal to the slave device through the interconnection device, and the acquisition synchronization timing signal is used to realize the master device and the slave device to perform synchronous acquisition of near-infrared detection data according to the local acquisition timing configuration information of each device.

[0013] According to a fourth aspect of the present application, a method for interconnecting an FNIRS host is provided, comprising the following steps.

[0014] Among multiple FNIRS hosts, one FNIRS host is determined as a master device and the other FNIRS hosts are slave devices by distinguishing the interface connection mode between the FNIRS host and the interconnection device. The interconnection device is configured as a first interconnection interface and a second interconnection interface with different explicit physical properties, so as to distinguish the master device from the slave device through the first interconnection interface and the second interconnection interface.

[0015] In response to an instruction to receive the timing configuration information for collecting near-infrared detection data, the timing configuration information for collecting is received by the master device and the slave device, and the timing configuration information for collecting is stored locally in each device.

[0016] In response to the synchronous acquisition start instruction sent by the host computer, the master device sends the acquisition synchronization timing signal to each of the slave devices through the interconnection device, so that the master device and the slave device synchronously acquire near-infrared detection data according to the local acquisition timing configuration information of each device.

[0017] According to a fifth aspect of the present application, a FNIRS host interconnection component is provided. The interconnection component comprises: at least two FNIRS hosts of any one of the embodiments of the present application; and an interconnection device of any one of the FNIRS hosts of the embodiments of the present application, wherein the at least two FNIRS hosts are connected to the interconnection device to realize the interconnection of the FNIRS hosts.

[0018] According to the sixth aspect of the present application, a fnirs imaging system is provided. The fnirs imaging system includes any one of the fnirs host interconnection components in the various embodiments of the present application, and a probe group connected to and used in conjunction with each fnirs host, wherein the probe group includes a transmitting probe and a receiving probe. Each probe group matched with each fnirs host has a first number of channels. Among them, each fnirs host is configured to control the corresponding probe group to synchronously collect near-infrared detection data of a second number of channels based on the acquisition synchronization timing signal of the first fnirs host connected to the first interconnection interface, and the second number of channels is greater than the first number of channels.

[0019] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of the present application are as follows. Through multiple interconnection interfaces of a box-shaped interconnection device, multiple low-channel fnirs hosts are connected via several strip-shaped interconnection devices to realize star-shaped interconnection of several low-channel fnirs hosts, thereby combining multiple low-channel fnirs host devices, and in the process of realizing interconnection, the existing interfaces of low-channel fnirs devices are fully utilized, reducing the cost of updating and modifying the existing low-channel fnirs system, and realizing the collection of brain near-infrared detection data with a high SD channel number. On the other hand, the main processor in the interconnection device is configured to sample the received marking trigger signal based on a second sampling rate greater than the first sampling rate of the fnirs host, and send out the marking timing data obtained after sampling. The interconnection device performs refined high-frequency sampling of the marking trigger signal at a higher second sampling rate, so that the time information of each event of interest occurring in the process of collecting the subject's physiological signals can be obtained, and the marking timing data can be generated. Since the sampling rate of the interconnected device is high and the sampling interval is short, the time information of the event of interest can be recorded more completely, reducing the omissions caused by the low first sampling rate of the fnirs host. The embodiment of the present application not only realizes the same-modal combination of multiple low-channel devices to form a high-channel device, but also realizes the cross-modal combination with the high sampling rate device through the box-shaped interconnected device, that is, it realizes the interconnection of different types of combined devices with near-infrared devices, such as combining near-infrared devices with electroencephalogram devices. The embodiment of the present application solves the problems of the same-modal combination scenario and the cross-modal combination scenario of near-infrared devices through an interconnected device, and constructs a near-infrared device combination solution with a compact structure, simple connection lines, and adaptability to various modal collaborative combination scenarios.

[0020] In the embodiment of the present application, the user can distinguish which interface is the first interconnection interface and which interface is the second interconnection interface through the different explicit physical properties of the second interconnection interface and the first interconnection interface is configured to be removably connected to a single strip interconnection device so that the fnirs host plugged on the opposite side of the strip interconnection device is used as the master device in the interconnection, and each second interconnection interface is configured to be removably connected to each strip interconnection device so that the fnirs host plugged on the opposite side of each strip interconnection device is used as the slave device in the interconnection. That is, the user can clearly know which interconnection device corresponds to the interconnected fnirs host as the host of the interconnection, and which interconnection device corresponds to the interconnected fnirs host as the slave device of the interconnection, so as to flexibly specify or clarify the fnirs host that needs to be the master device by plugging a single strip interconnection device, which is conducive to clarifying the master device, and then to clarifying which host computer connected to which fnirs host to view the signal acquisition and analysis results. Through the hardware transmission between the first interconnection interface and the processing circuit part of the master device, and the hardware transmission between the second interconnection interface and the processing circuit part of the slave device, the transmitted acquisition timing signal may at least only include the start time of a series of acquisition cycles of synchronous acquisition (the start time of the first acquisition cycle), or may include the start time of each acquisition cycle. The amount of transmitted data is very small and it is hardware transmission, which can significantly reduce the delay between the interconnected fnirs hosts (for example, controlling the delay to less than 10 microseconds). BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 is a schematic diagram of an existing fNIRS system provided in an embodiment of the present application;

[0023] Figure 2 It is a schematic diagram of the back side of an existing fNIRS host provided by an embodiment of the present application;

[0024] FIG3 (a) is a structural block diagram of two fnirs hosts provided in an embodiment of the present application that form a star-shaped interconnection through an interconnection device;

[0025] FIG3 (b) is a schematic diagram of a plurality of fnirs hosts provided in an embodiment of the present application forming a star-shaped interconnection through an interconnection device;

[0026] Figure 4It is a timing diagram of a synchronous acquisition timing signal between interconnected FNIRS hosts provided in an embodiment of the present application;

[0027] Figure 5 It is a flow chart of a method for interconnecting fnirs hosts provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0029] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0030] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said" and "the" used in the various embodiments of the present application are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in the various embodiments of the present application refers to and includes any or all possible combinations of one or more associated listed items. In the description of the various steps of the method in the various embodiments of the present application, the arrows in the accompanying drawings are not intended to limit the sequence of the various steps, and the order of the sentences and paragraphs of the various steps in the description is not intended to limit the sequence, unless explicitly defined, otherwise the various steps can be performed in any order as long as they meet the logical relationship with each other.

[0031] It should be understood that although the terms first, second, third, etc. may be used to describe various information in various embodiments of the present application, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "under the circumstances of..." or "when..." or "determined in response to...".

[0032] Furthermore, the drawings are schematic illustrations only and are not necessarily drawn to scale. The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities unless the context makes physical independence clear. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0033] In an embodiment of the present application, an interconnection device 100 for an FNIRS host is provided. Referring to FIG. 3 (a) and FIG. 3 (b), the interconnection device 100 is box-shaped, and realizes a star-type interconnection of several FNIRS hosts via several strip-shaped interconnection devices 200. Please note that the "star-type interconnection" in the text is intended to indicate that the interconnection device 100 serves as a collection core and a common relay station for each FNIRS host, and each FNIRS host is connected to the interconnection device 100 through an independent strip-shaped interconnection device 200, thereby forming a star topology. For example, FIG. 3 (a) shows a star-type interconnection formed by connecting two FNIRS hosts, one master device and one slave device, to the interconnection device 100 via interconnection lines. For another example, FIG. 3 (b) shows a star-type interconnection formed by connecting four FNIRS hosts, one master device and three slave devices, to the interconnection device 100 via interconnection lines. Under the star-type interconnection, any FNIRS slave device can communicate with the FNIRS master device via the interconnection device 100, thereby avoiding the delay superposition under the series interconnection.

[0034] 3( a ), the interconnection device 100 specifically includes a first interconnection interface 101 , at least one second interconnection interface 102 , a main processor 103 and a corresponding processing circuit 104 .

[0035] The second interconnection interface 102 has different explicit physical properties from the first interconnection interface 101, for example, see FIG3 (b). The first interconnection interface 101 is configured to be removably plugged into a single strip interconnection device 200, see FIG3 (a) and FIG3 (b), so that the fnirs host plugged into the opposite side of the strip interconnection device 200, that is, the first fnirs host 300a, is used as the master device in the interconnection. Each second interconnection interface 102 is configured to be removably plugged into each strip interconnection device 200, so that the fnirs host plugged into the opposite side of each strip interconnection device 200, that is, the second fnirs host 300b, is used as a slave device in the interconnection. The user can independently select which host to use as the master device in the interconnection, and plug the opposite side of the strip interconnection device 200 plugged into the host into the first interconnection interface 101. Likewise, the user can also independently select which host to use as the slave device in the interconnection, and plug the opposite side of the strip interconnection device 200 plugged into the host into the second interconnection interface 102 .

[0036] It should be noted that the first interconnection interface 101 and the second interconnection interface 102 in FIG. 3 (a) are located on both sides of the interconnection device 100. In actual use, the first interconnection interface 101 and the second interface 102 can also be arranged on the same side of the interconnection device as shown in FIG. 3 (b) to facilitate users to plug in the strip-shaped interconnection device 200.

[0037] The main processor 103 is configured to sample the received marking trigger signal based on a second sampling rate greater than the first sampling rate of the fnirs host, and send out the marking timing data obtained after sampling. The marking timing data at least indicates the time information of the event of interest that occurs during the process of collecting the physiological signal of the subject. The main processor 103 samples the received marking trigger signal at a second sampling rate greater than the first sampling rate of the fnirs host, so that the sampling period is less than the time interval between two adjacent marking trigger operations performed by the subject, so that more events of interest can be identified and the marking timing data containing the time information of more events of interest can be obtained.

[0038] The processing circuit 104 is configured to receive the acquisition synchronization timing signal sent by the master device through the first interconnection interface 101, and send the acquisition synchronization timing signal to each slave device through the second interconnection interface 102. The acquisition synchronization timing signal is used by the master device and each slave device in combination with the local acquisition timing configuration information to synchronously acquire near-infrared detection data. Through the interconnection device 100, the cross-modal connection of the FNIRS host and a device with a higher sampling rate, and the same-modal connection of multiple low-channel FNIRS host devices to form a high-channel device are simultaneously realized.

[0039] In some embodiments, as shown in FIG3(b), a master device (the rightmost FNIRS host in the first row of FIG3(b) is the master device) forms a "star interconnection" with three slave devices through an interconnection device 100 for the FNIRS host. The first interconnection interface 101 of the interconnection device 100 connected to the master device in FIG3(b) is significantly different from the second interconnection interface 102 of the interconnection device connected to the slave device, which facilitates the user to distinguish / adjust the master and slave devices during use.

[0040] It should be noted that the first interconnection interface 101 and the second interconnection interface 102 may have the same appearance as shown in FIG3 (a), that is, the types of interconnection interfaces may not be distinguished by the appearance of the interface, but by other means, such as marking each interface on the surface of the interconnection device. In addition, the interconnection interface may also have different appearances as shown in FIG3 (b), so that the user can directly distinguish the interface type of the interconnection interface by appearance, and it is convenient for the user to distinguish / adjust the master and slave devices.

[0041] In some embodiments, after multiple fnirs hosts are interconnected through the strip interconnection device 200 and the box-shaped interconnection device 100, the host computer interacts with each interconnected fnirs host so that each fnirs host knows its own acquisition timing configuration information (i.e., which transmitting probe of all interconnected SD channels the light source of each fnirs host is connected to, the timing of lighting each light source, the lighting duration of each light source, etc.).

[0042] like Figure 4 As shown, Figure 4 The timing information of the thin lines is the acquisition timing configuration information of each fnirs host, and it is known that the synchronous acquisition should be run according to this interconnection mode, that is, the acquisition synchronization timing signal transmitted by the master device in the interconnection is used as the synchronous acquisition instruction to start the respective synchronous acquisition mode. Therefore, after each slave device knows its own acquisition timing configuration information, as long as it knows the synchronous acquisition start instruction (such as the "acquisition synchronization timing signal" mentioned above), it can autonomously start to execute the lighting / detection of its own S / D probe. When the host computer sends the acquisition synchronization timing signal of the synchronous acquisition to the master device, the processing circuit of the master device transmits the acquisition synchronization timing signal ( Figure 4 The dotted line in the figure is an acquisition synchronization timing signal in the form of a rising edge, the timing signal in the bold line is a periodic acquisition synchronization timing signal including a rising edge, and the moment shown by the dotted line is also the moment when the master device sends the acquisition timing signal) which is transmitted to the processing circuit of each slave device, so that each slave device can start acquisition according to its own acquisition timing configuration information based on the acquisition synchronization timing signal, so as to start acquisition at the same time as the master device, so as to realize the synchronous acquisition of near-infrared detection data.

[0043] like Figure 4 As shown, a near infrared detection data collection process includes multiple collection cycles T, and a collection cycle T may include a first sub-cycle t1 and a second sub-cycle t2. The fnirs host can perform synchronous collection of near infrared detection data in the first sub-cycle t1, and can accept and process other instructions in the second sub-cycle t2, or wait for the start of the next collection cycle T.

[0044] In some embodiments, the processing circuit 104 may be a hardware circuit capable of realizing information recognition and data transmission, so as to recognize whether the first interconnection interface 101 or the second interconnection interface 102 is inserted, and realize transmission and acquisition of synchronous timing signals.

[0045] In some embodiments, in order to facilitate the distinction between the first interconnection interface 101 and the second interconnection interface 102, and then determine which FNIRS host is the master device and which FNIRS host is the slave device, it is not necessary to specify or determine which FNIRS host is the master device or the slave device in advance on the FNIRS host or the host computer. By setting the first interconnection interface 101 and the second interconnection interface 102 to have different explicit physical properties, the first interconnection interface 101 and the second interconnection interface 102 can be distinguished based on the explicit physical properties. The explicit physical property can be a visual feature, the first interconnection interface 101 has a first visual feature, and the second interconnection interface 102 has a second visual feature.

[0046] For example, the explicit physical attributes may include physical attributes on the appearance (e.g., different appearance shapes, different marks on the appearance, different colors, etc.), so that the user can distinguish the first interconnection interface 101 from the second interconnection interface 102 by observing the difference in appearance. The explicit physical attributes also allow the processing circuit in the FNIRS host to distinguish whether the first interconnection interface 101 or the second interconnection interface 102 is inserted, so that the FNIRS host can autonomously identify whether it is a master device or a slave device by identifying whether the first interconnection interface 101 or the second interconnection interface 102 is inserted. In addition, through the hardware transmission between the processing circuit 104 of the interconnection device 100 and the processing circuit of the master device, the hardware transmission between the processing circuit 104 of the interconnection device 100 and the processing circuit of the slave device, and the transmitted acquisition timing signal can at least only include the start time of a series of acquisition cycles of synchronous acquisition (the start time of the first acquisition cycle), or can include the start time of each acquisition cycle, the amount of transmitted data is very small and it is hardware transmission, which can significantly reduce the delay between the interconnected FNIRS hosts (for example, the delay is controlled to be less than 10 microseconds).

[0047] In some embodiments, the interconnection device 100 further includes at least one marking input interface 105; the marking input interface 105 is configured to be detachably plugged into a marking signal transmission line to receive a marking trigger signal sent by the marking input device through the marking signal transmission line.

[0048] As shown in FIG3 (b), in order to enable the interconnected device 100 to receive marking trigger signals sent by different types of marking input devices, a marking input interface 105 of various interface types can be set on the input end side of the interconnected device 100 to adapt to marking input devices using various types of interfaces. Since the near-infrared device itself has a low sampling rate, when a near-infrared device with a low sampling rate (e.g., 11 Hz) is used in conjunction with other devices with a higher sampling rate (e.g., an EEG device, 10 kHz), it is easy to cause the problem of missing or missing labels due to the low sampling rate of the device. Therefore, in order to solve the problem of being unable to fully receive the mark due to the low sampling rate of the near-infrared device itself, the main processor 103 in the interconnected device 100 is configured to sample the received marking trigger signal based on a second sampling rate greater than the first sampling rate of the fnirs host, and send the marking timing data obtained after sampling to the outside. The interconnection device 100 receives the marking trigger signal through the marking input interface 105, and performs refined high-frequency sampling of the marking trigger signal at a higher second sampling rate, so as to obtain the time information of each event of interest that occurs in the process of collecting the subject's physiological signals, and generate marking time series data. Since the sampling rate of the interconnection device 100 is high and the sampling interval is short, the time information of the event of interest can be collected more completely, and each time position can be marked, thereby reducing the loss of the label due to the low sampling rate of the near-infrared device itself.

[0049] In some embodiments, the interconnection device 100 further includes at least one marking output interface 106; the marking output interface 106 is configured to be detachably plugged into a marking timing data transmission line to send marking timing data outwardly through the marking timing data transmission line.

[0050] As shown in FIG. 3( b ), a plurality of marking output interfaces 106 may be provided on the output end side of the interconnection device 100 to adapt to marking output devices using various types of interfaces, so that the interconnection device 100 can transmit marking timing data externally through interconnection devices of different interface types.

[0051] In some embodiments, the interconnected device 100 outputs the marking timing data to an external processing device through the marking output interface 106, so that the processing device can refer to and compare the positions of each mark provided in the marking timing data from the interconnected device to process the marked physiological timing data. For example, when the marked physiological timing data does not contain the time information of each event of interest, the position of each mark is determined in the time domain of the marked physiological timing data. Or, when the marked physiological timing data contains the time information of the event of interest, the time information of the event of interest that is missing in the marked physiological timing data can be determined by comparing it with the marking timing data for analysis or display by the processing device.

[0052] In some embodiments, the above-mentioned marking input device can be a marking device for generating a marking trigger signal, a high sampling rate detection device (such as an electroencephalogram device), etc., and the marking output device can be a low sampling rate detection device such as a near-infrared device, or a data processing and display terminal, etc.

[0053] In some embodiments, the acquisition synchronization timing signal may include the identification of each acquisition cycle of synchronous acquisition, so that the master device and the slave device can identify each acquisition cycle based on the identification. After the collected near-infrared detection data is transmitted to the host computer, the host computer can summarize the near-infrared detection data collected by multiple groups of channels with the same acquisition cycle identification based on the identification, and can also determine which acquisition cycle has a poor acquisition condition of the slave device based on the identification. If there is a slave device with a poor acquisition condition in a certain acquisition cycle, the host computer can discard the near-infrared detection data of other slave devices with good acquisition conditions in this acquisition cycle together, and no longer summarize and use them, so that the near-infrared detection data retained in each acquisition cycle are of good quality.

[0054] In some embodiments, the acquisition synchronization timing signal includes identifiers of each acquisition cycle of synchronous acquisition, so that the master device and the slave device can identify each acquisition cycle based on the identifier. For example, the master device can send only the cycle identifier of the first acquisition cycle to the slave device, and then each device starts counting and adds a cycle identifier to each cycle of the device.

[0055] In some other embodiments, the master device may also send a cycle identifier to the slave device in each acquisition cycle, so that the slave device knows which acquisition cycle is currently in progress, and compares and verifies the cycle identifier learned from the master device with its own cycle identifier to determine whether there is a mismatch in the acquisition timing, etc.

[0056] In some embodiments, the identifiers of each acquisition cycle of the synchronous acquisition included in the acquisition synchronization timing signal may be any identifier that can distinguish the order or the existence of a difference, for example, an identifier in the form of numbers, letters, strings, etc.

[0057] As shown in FIG. 3 (a) and FIG. 3 (b), in some embodiments of the present application, there is also provided an FNIRS host for interconnecting with other FNIRS hosts to form a higher number of detection channels. The FNIRS host can be used as a master device (i.e., a first FNIRS host 300a) or as a slave device (i.e., a second FNIRS host 300b). The FNIRS host includes a main processor, at least one interface, and a processing circuit unit separate from the main processor.

[0058] The at least one interface is configured to be connected to a first interconnection interface 101 or a second interconnection interface 102 of an interconnection device 100 of the fnirs host; wherein, via connection with the first interconnection interface 101, the fnirs host is used as a master device among multiple interconnected fnirs hosts, and via connection with the second interconnection interface 102, the fnirs host is used as a slave device among multiple interconnected fnirs hosts.

[0059] The processing circuit part is separated from the main processor and configured to identify the interface type of the interconnection device 100 interface connected to the at least one interface. The first FNIRS host 300a used as the master device includes a first main processor 301a, a first processing circuit 303a and at least one first interface 302a, and the second FNIRS host 300b used as the slave device includes a second main processor 301b, a second processing circuit 303b and at least one second interface 302b. When the at least one first interface 302a is connected to the first interconnection interface 101, the acquisition synchronization timing signal is sent to the interconnection device 100 via the at least one first interface 302a and the first interconnection interface 101, and when the at least one second interface 302b is connected to the second interconnection interface 102, the acquisition synchronization timing signal of the second interconnection interface 102 of the interconnection device 100 is received via the at least one second interface 302b.

[0060] The main processor is configured to use the received acquisition synchronization timing signal to control the synchronous acquisition of near-infrared detection data when the processing circuit unit receives the acquisition synchronization timing signal (at this time, it acts as a slave device), and to use the externally transmitted acquisition synchronization timing signal to control the synchronous acquisition of near-infrared detection data when the processing circuit unit transmits the acquisition synchronization timing signal of synchronous acquisition externally (at this time, it acts as a master device), wherein the acquisition synchronization timing signal at least indicates the start time of a series of acquisition cycles of synchronous acquisition. Wherein, when the second main processor 301b in the second FNIRS host 300b receives the acquisition synchronization timing signal, the received acquisition synchronization timing signal is used to control the synchronous acquisition of near-infrared detection data; when the first processing circuit 303a transmits the acquisition synchronization timing signal of synchronous acquisition externally, the first main processor 301a in the first FNIRS host 300a uses the externally transmitted acquisition synchronization timing signal to control the synchronous acquisition of near-infrared detection data.

[0061] In some embodiments, the main processor may be any processor chip such as a CPU, an MPU, a GPU, or a SOC. The processing circuit unit may be a hardware circuit capable of realizing information recognition and data transmission, for example, an ASIC circuit or an FPGA circuit.

[0062] In some embodiments, in order to achieve lower cost and more flexibility in modifying the FNIRS host, preferably, the processing circuit part can be an FPGA circuit. If the existing FNIRS host is to be modified, the built-in FPGA circuit of the chassis is opened, and the FPGA is programmed to perform the tasks of access identification of the interface and mutual transmission of the acquisition timing signal, and then interconnected with the main processor, and the application program of the main processor is updated.

[0063] In some embodiments, the processing circuit unit is further configured to: when the main processor of the interconnected slave device is occupied, the acquisition synchronization timing signal of synchronous acquisition is not transmitted externally via the at least one interface. That is, among the multiple interconnected FNIRS hosts, if the main processor of an individual slave device is occupied, the master device temporarily does not transmit the acquisition timing signal of synchronous acquisition externally to each slave device via the at least one interface, that is, temporarily does not send the acquisition synchronization timing signal of synchronous acquisition to each slave device, and when the main processor of each slave device is not occupied, the acquisition synchronization timing signal of synchronous acquisition is transmitted externally to each slave device via the at least one interface to ensure that each slave device can perform synchronous acquisition with the master device based on the acquisition synchronization timing signal.

[0064] In some embodiments, the fnirs host further includes a memory, and the memory is configured to store the acquisition timing configuration information after the fnirs host receives the acquisition timing configuration information sent by the host computer. After receiving the acquisition timing configuration information sent by the host computer, the fnirs host first stores the acquisition timing configuration information locally, and as long as the synchronous acquisition start instruction is obtained, the synchronous acquisition of near-infrared detection data can be started according to the locally stored acquisition timing configuration information.

[0065] In some embodiments, the acquisition timing configuration information stored in any fnirs host includes the lighting moment and lighting time of each transmitting probe of the fnirs host within a collection cycle, as well as the collection moment and collection time of each receiving probe. The acquisition timing configuration information stored in any fnirs host includes the acquisition timing configuration information of the S / D probes connected to each other (i.e., the moment when each S probe of each fnirs host starts to light up, the duration of each S probe lighting up, the moment when each D probe starts to collect and the duration of collection, the order of each other and the simultaneous lighting / detection relationship, etc.). Once the configuration information is known, as long as the synchronous collection start instruction (such as the "acquisition timing signal" mentioned above) is known, the lighting / detection of the S / D probe itself can be started autonomously, thereby realizing the synchronous collection of high-channel near-infrared detection data.

[0066] In some embodiments, the main processor is further configured to send the master-slave mark of the current device to the upper computer according to the interface type of the interconnection device interface connected to the at least one interface. When the at least one interface of the fnirs host is connected to the interconnection interface of the interconnection device for the fnirs host through the interconnection device, the processing circuit part of the fnirs host can identify whether the current fnirs host is used as a master device or a slave device. Specifically, it can be formed by forming a processing circuit with different circuit parameters between the at least one interface and the first interconnection interface and the second interconnection interface, thereby identifying whether the current fnirs host is a master device or a slave device. For example, different circuit parameters can be different starting voltages, etc. The main processor obtains the starting voltage of the processing circuit part, and matches the starting voltage values ​​corresponding to the master device and the slave device respectively preset in the main processor, thereby determining the type of the currently connected interconnection interface, and forming the master-slave mark of the current fnirs host and sending it to the upper computer.

[0067] In some embodiments, in order to reduce the computing cost and data transmission volume, the master and slave marks of the fnirs host can be "0" and "1" respectively, the master device can be marked as "0", and the slave device can be marked as "1". After the main processor of the fnirs host sends the master and slave marks to the host computer, the host computer can determine whether the current fnirs host is a master device or a slave device only by whether the acquired master and slave marks are "0", thereby sending the allocated acquisition timing configuration information to the device and determining whether to send the synchronous acquisition start instruction (such as the "acquisition timing signal" mentioned above) to the fnirs host.

[0068] In some embodiments of the present application, a host computer for interconnecting FNIRS hosts is also provided. Multiple FNIRS hosts are connected to the first interconnection interface or the second interconnection interface of the interconnection device to achieve interconnection. The first interconnection interface is used to connect to the master device in the interconnected host, and the first interconnection interface is used to connect to the slave device in the interconnected host. The first interconnection interface and the second interconnection interface have different explicit physical properties. The host computer performs the following steps through a processor.

[0069] Step 1: In response to meeting the sending condition of the acquisition timing configuration information, the acquisition timing configuration information is sent to the master device and the slave device in the multiple interconnected fnirs hosts, so that the master device and the slave device respectively store the acquisition timing configuration information locally in each device.

[0070] Step 2: In response to satisfying the data acquisition conditions, a collection instruction is sent to the master device, so that the master device sends a collection synchronization timing signal to the slave device through the interconnection device, and the collection synchronization timing signal is used to realize the master device and the slave device to synchronously collect near-infrared detection data according to the local collection timing configuration information of each device.

[0071] In some embodiments, the host computer performs at least one of the following operations through a processor: stop acquisition operation, near infrared detection data receiving operation, near infrared detection data display operation, blood oxygen acquisition parameter adjustment operation. When several fnirs hosts and interconnection devices are connected in a star-shaped manner through several strip-shaped interconnection devices, the host computer is connected to the main device in the fnirs host or to other display / control devices in a wired or wireless manner to send a control instruction to the main device or other display / control device, and the control instruction may include a synchronous acquisition start instruction, a stop acquisition instruction, a near infrared detection data receiving instruction, a near infrared detection data display instruction, a blood oxygen acquisition parameter adjustment instruction, etc.

[0072] In some embodiments, each interconnected fnirs host can be connected to a host computer respectively, but whichever fnirs host is used as the main device, the host computer connected to which fnirs host will be used to uniformly display and analyze the near-infrared detection data synchronously collected by all interconnected fnirs hosts. All interconnected fnirs hosts can also be connected to one host computer, and the one host computer will be used to uniformly display and analyze the near-infrared detection data synchronously collected by all interconnected fnirs hosts.

[0073] In some embodiments, the host computer is connected to the master device and the slave device respectively through one or more wireless transmitters.

[0074] In some embodiments of the present application, a method for interconnecting a fnirs host is also provided, such as Figure 5 As shown, the following steps are included.

[0075] 501. Among multiple FNIRS hosts, one FNIRS host is determined as a master device and the other FNIRS hosts are slave devices by distinguishing the interface connection mode between the FNIRS host and the interconnection device; wherein the interconnection device is configured as a first interconnection interface and a second interconnection interface with different explicit physical properties, so as to distinguish the master device and the slave device through the first interconnection interface and the second interconnection interface.

[0076] 502. In response to an instruction to receive the timing configuration information for collecting near-infrared detection data, the timing configuration information for collecting is received by the master device and the slave device, and the timing configuration information for collecting is stored locally in each device.

[0077] 503. In response to the synchronous acquisition start instruction sent by the host computer, the master device sends the acquisition synchronization timing signal to each of the slave devices through the interconnection device, so that the master device and the slave device synchronously collect near-infrared detection data according to the local acquisition timing configuration information of each device.

[0078] In some embodiments, the interconnection method further includes: after the master device and the slave device are determined, the master device and the slave device respectively send the master-slave mark of the device to the host computer; the host computer sends the allocated acquisition timing configuration information to each device according to the master-slave mark. After several FNIRS hosts are connected to the interconnection device respectively, the main processor of the FNIRS host determines whether the device is a slave device or a master device, and then sends the master-slave mark of the device to the host computer by wired or wireless means, and the host computer sends the allocated acquisition timing configuration information to each device according to the master-slave mark. After each device receives the acquisition timing configuration information, it stores the acquisition timing configuration information locally in each device, and after the master device receives the synchronous acquisition start instruction sent by the host computer, and sends the acquisition synchronization timing signal to each of the slave devices through the interconnection device, the master device and the slave device perform synchronous acquisition according to the locally stored acquisition timing configuration information.

[0079] In some embodiments of the present application, a fnirs host interconnection component is also provided, including: at least two fnirs hosts of any one of the embodiments of the present application; and any one of the interconnection devices for fnirs hosts of the embodiments of the present application, wherein the at least two fnirs hosts are connected to the interconnection device to realize fnirs host interconnection. The interconnection device connects an fnirs host as a master device through the first interconnection interface, and connects at least one fnirs host as a slave device through at least one second interconnection interface, so as to realize star-shaped parallel interconnection between a master device and multiple slave devices, thereby avoiding the superposition of delays of the interconnected fnirs hosts and avoiding delay accumulation.

[0080] After the interconnected FNIRS hosts in the FNIRS host interconnection component are interconnected through the interconnection device for interconnection, the host computer interacts with the interconnected FNIRS hosts so that each FNIRS host knows the acquisition timing configuration information of its respective connection (i.e., which transmitting probe of all SD channels of the interconnection is connected to the light source of each FNIRS host, the timing of lighting each light source, the lighting duration of each light source, etc.), and knows to run the synchronous acquisition according to this interconnection mode, that is, to start the respective synchronous acquisition modes with the acquisition synchronization timing signal transmitted by the master device in the interconnection as the synchronous acquisition start instruction, and the host computer sends the acquisition synchronization timing signal of the synchronous acquisition to the master device, and then the processing circuit part of the master device transmits the acquisition synchronization timing signal to the processing circuit part of each slave device through the interconnection device, so that each slave device can start the acquisition at the same time as the master device based on the acquisition synchronization timing signal to realize synchronous acquisition.

[0081] In some embodiments of the present application, an fnirs imaging system is also provided, which includes any one of the fnirs host interconnection components in the various embodiments of the present application, and a probe group including a transmitting probe (i.e., S) and a receiving probe (i.e., D) connected to and used in conjunction with each fnirs host. Each of the probe groups has a first number of channels. Wherein, each fnirs host is configured to control the corresponding probe group to synchronously collect near-infrared detection data of a second number of channels based on the acquisition synchronization timing signal of the first fnirs host connected to the first interconnection interface, and the second number of channels is greater than the first number of channels.

[0082] In some embodiments, the first channel number is the channel number of each interconnected fnirs host to realize near-infrared detection data collection, and the second channel number is the channel number of near-infrared detection data collection realized by all interconnected interconnected devices through synchronous collection.

[0083] The embodiment of the present application achieves the following technical effects: multiple low-channel FNIRS hosts are connected through the interconnection interface of the interconnection device, so that multiple low-channel FNIRS host devices are used together, and the same-modal connection of multiple low-channel devices to form a high-channel device is realized, and the cross-modal connection with the high sampling rate device is realized through the box-shaped interconnection device, that is, the interconnection of different types of connection devices with near-infrared devices is realized, such as the connection of near-infrared devices and electroencephalogram devices. The embodiment of the present application solves the problems of the same-modal connection scenario and the cross-modal connection scenario of near-infrared devices through an interconnection device, and constructs a near-infrared device connection solution with a compact structure, simple connection lines, and adaptability to various modal collaborative connection scenarios. Through the different explicit physical properties of the first interconnection interface and the second interconnection interface, it is possible to distinguish which interface is the first interconnection interface and which interface is the second interconnection interface, and the first interconnection interface is configured to be plugged in a single strip interconnection device in a detachable manner, so that the fnirs host plugged in the opposite side of the strip interconnection device is used as the main device in the interconnection, that is, which fnirs host is plugged into the first interconnection interface is the main device, and the second interconnection interface is configured to be plugged in each strip interconnection device in a detachable manner, so that the fnirs hosts plugged in the opposite side of each strip interconnection device are all used as interconnection The slave device in the system, that is, which fnirs host is plugged into the second interconnection interface, which fnirs host is the slave device. In this case, the user can arbitrarily and autonomously plug the fnirs host as the master device into the first interconnection interface according to the distinguished first interconnection interface and the second interconnection interface according to different interconnection requirements, so as to realize that the fnirs host that needs to be the master device can be flexibly and arbitrarily specified or clarified by plugging the first interconnection interface, which is conducive to knowing and clarifying the master device, and then to clarify which fnirs host is connected to the host computer to view the signal acquisition and analysis results. The interconnection link is formed by the star topology structure, which avoids the delay superposition of the interconnected fnirs hosts, avoids the delay accumulation, and realizes high-channel data acquisition.

[0084] Obviously, those skilled in the art should understand that the modules or steps of the above-mentioned embodiments of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0085] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the embodiments of the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An interconnection device for a fnirs host, characterized in that: The interconnection device is box-shaped and realizes the star-shaped interconnection of several fnirs hosts via several strip-shaped interconnection devices. The interconnection device specifically includes: A first interconnection interface and at least one second interconnection interface, wherein the second interconnection interface has different explicit physical properties from the first interconnection interface, the first interconnection interface is configured to be detachably plugged into a single strip-shaped interconnection device, so that the fnirs host plugged into the opposite side of the strip-shaped interconnection device is used as a master device in the interconnection, and each second interconnection interface is configured to be detachably plugged into each strip-shaped interconnection device, so that the fnirs host plugged into the opposite side of each strip-shaped interconnection device is used as a slave device in the interconnection; The main processor is configured to sample the received marking trigger signal based on a second sampling rate greater than the first sampling rate of the fnirs host, and send out the marking timing data obtained after the sampling; and The processing circuit is configured to receive the acquisition synchronization timing signal sent by the master device through the first interconnection interface, and send the acquisition synchronization timing signal to each of the slave devices through the second interconnection interface. The acquisition synchronization timing signal is used by the master device and each slave device in combination with local acquisition timing configuration information to synchronously acquire near-infrared detection data.

2. The interconnection device of the fnirs host according to claim 1, characterized in that: The explicit physical attributes include visual characteristics.

3. The interconnection device of the fnirs host according to claim 1, characterized in that: The interconnection device also includes at least one marking input interface; The marking input interface is configured to be plugged into the marking signal transmission line in a detachable manner to receive the marking trigger signal sent by the marking input device through the marking signal transmission line.

4. The interconnection device of the fnirs host according to claim 1 or 3, characterized in that: The interconnection device also includes at least one marking output interface; The marking output interface is configured to be plugged into the marking timing data transmission line in a detachable manner so as to send the marking timing data outward through the marking timing data transmission line.

5. The interconnection device of the fnirs host according to claim 1 or 3, characterized in that: The acquisition synchronization timing signal includes identifiers of each acquisition cycle of synchronous acquisition.

6. A fnirs host for interconnecting with other fnirs hosts to form a higher number of detection channels, characterized in that: include: At least one interface is configured to be connected to a first interconnection interface or a second interconnection interface of an interconnection device of an FNIRS host; wherein, via connection with the first interconnection interface, the FNIRS host is used as a master device among a plurality of interconnected FNIRS hosts, and via connection with the second interconnection interface, the FNIRS host is used as a slave device among a plurality of interconnected FNIRS hosts; A processing circuit unit separate from the main processor is configured to identify the interface type of the interconnection device interface connected to the at least one interface; when the at least one interface is connected to the first interconnection interface, send an acquisition synchronization timing signal to the interconnection device via the at least one interface and the first interconnection interface; when the at least one interface is connected to the second interconnection interface, receive an acquisition synchronization timing signal from the second interconnection interface of the interconnection device via the at least one interface; The main processor is configured to use the received acquisition synchronization timing signal to control the synchronous acquisition of near-infrared detection data when the processing circuit unit receives the acquisition synchronization timing signal, otherwise use the externally transmitted acquisition synchronization timing signal to control the synchronous acquisition of near-infrared detection data, and the acquisition synchronization timing signal at least indicates the start time of a series of acquisition cycles of synchronous acquisition.

7. The fnirs host according to claim 6, characterized in that The processing circuit unit is further configured to temporarily not transmit the acquisition synchronization timing signal to the outside via the at least one interface when the main processor of the interconnected slave device is occupied.

8. The fnirs host according to claim 6 or 7, characterized in that: The fnirs host also includes a memory, and the memory is configured as: After the fnirs host receives the acquisition timing configuration information sent by the host computer, the acquisition timing configuration information is stored.

9. The fnirs host according to claim 6 or 7, characterized in that: Any FNIRS host stores the acquisition timing configuration information, including: The fnirs host records the lighting moment and lighting time of each transmitting probe in a collection cycle, as well as the collection moment and collection time of each receiving probe.

10. The fnirs host according to claim 6 or 7, characterized in that: The main processor is further configured as: According to the identified interface type of the interconnection device interface connected to the at least one interface, the master-slave mark of the current device is sent to the host computer.

11. A host computer for fnirs host interconnection, characterized in that, A plurality of fnirs hosts are connected to the first interconnection interface or the second interconnection interface of the interconnection device to realize interconnection, wherein the first interconnection interface is used to connect to the master device in the interconnection host, and the first interconnection interface is used to connect to the slave device in the interconnection host, and the first interconnection interface and the second interconnection interface have different explicit physical properties, and the host computer performs the following steps through a processor: In response to satisfying the sending condition of the acquisition timing configuration information, the acquisition timing configuration information is sent to the master device and the slave device in the multiple interconnected fnirs hosts, so that the master device and the slave device respectively store the acquisition timing configuration information locally in each device; In response to satisfying the data acquisition conditions, an acquisition instruction is sent to the master device, so that the master device sends an acquisition synchronization timing signal to the slave device through the interconnection device, and the acquisition synchronization timing signal is used to realize the master device and the slave device to perform synchronous acquisition of near-infrared detection data according to the local acquisition timing configuration information of each device.

12. The host computer according to claim 11, characterized in that: The host computer performs at least one of the following operations through the processor: Stop collection operation, receive near-infrared detection data, display near-infrared detection data, and adjust blood oxygen collection parameters.

13. The host computer according to claim 11, characterized in that: The host computer is connected to the master device and the slave device respectively through a wireless transmitter.

14. A method for interconnecting a fnirs host, characterized in that: include: Among multiple FNIRS hosts, one FNIRS host is determined as a master device by distinguishing the interface connection mode between the FNIRS host and an interconnection device, and the other FNIRS hosts are slave devices; wherein the interconnection device is configured as a first interconnection interface and a second interconnection interface having different explicit physical properties, so as to distinguish the master device and the slave device through the first interconnection interface and the second interconnection interface; In response to a near-infrared detection data acquisition timing configuration information receiving instruction, the acquisition timing configuration information is received through the master device and the slave device, and the acquisition timing configuration information is stored locally in each device; In response to the synchronous acquisition start instruction sent by the host computer, the master device sends the acquisition synchronization timing signal to each of the slave devices through the interconnection device, so that the master device and the slave device synchronously acquire near-infrared detection data according to the local acquisition timing configuration information of each device.

15. The interconnection method for fnirs hosts according to claim 14, characterized in that: The method further comprises: After the master device and the slave device are determined, the master device and the slave device respectively send the master and slave marks of the devices to the host computer; The host computer sends the allocated acquisition timing configuration information to each device according to the master-slave mark.

16. A fnirs host interconnection component, characterized in that include: At least two fnirs hosts as claimed in any one of claims 6 to 10; as well as The interconnection device of the fnirs host according to any one of claims 1 to 5, wherein the at least two fnirs hosts are connected to the interconnection device to achieve fnirs host interconnection.

17. An fNIRS imaging system, characterized in that: include: The fnirs host interconnect component of claim 16; and A probe group including a transmitting probe and a receiving probe connected to and used in conjunction with each fnirs host, each of the probe groups having a first number of channels, wherein each fnirs host is configured to control the corresponding probe group to synchronously acquire near-infrared detection data of a second number of channels based on an acquisition synchronization timing signal of a first fnirs host connected to the first interconnection interface, wherein the second number of channels is greater than the first number of channels.

Images