A modulator for a multi-level wireless charging system and method of application

Abstract

This invention proposes a modulator and application method for a multi-level wireless charging system, belonging to the field of wireless power transfer technology. It solves the problems of large output ripple and the need for additional circuitry to maintain flying capacitor balance in current methods. The modulator includes: a finite state machine, a proportional element, an integrator, a multiplier, a delay element, and a microcontroller; the microcontroller provides external signals sign and k. The initial inverter voltage δ... FC‑SDM The input multilevel soft-switching modulator, combined with the external signal sign, obtains signal i. A finite state machine is used to quantize the input signal i. The integrator integrates the input δ with the finite state machine feedback signal y to obtain the output e. The output e of the multiplier is multiplied with the signal sign to obtain the input i of the state machine. The delay element is used to control the signal triggering time.

Description

Technical Field

[0001] This invention relates to a modulator and application method for a multilevel wireless charging system, belonging to the field of wireless power transmission technology. Background Technology

[0002] The main problem with wireless power transfer compared to wired charging is its lower power output. One solution is to replace the traditional full-bridge inverter with a multilevel inverter, enabling it to withstand higher DC voltages. To reduce losses in multilevel power electronic converters, research is needed on soft-switching modulation methods for multilevel wireless power transfer systems. Soft-switching technology can improve equipment efficiency and enable higher frequency power conversion components. Current methods suffer from problems such as large output ripple and the need for additional circuitry to maintain flying capacitor balance. Therefore, developing a new multilevel inverter modulation method that achieves soft-switching operation and flying capacitor voltage self-balancing across the entire range is crucial for enhancing the application value of wireless power transfer technology. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention proposes a modulator and its application method for a multi-level wireless charging system.

[0004] The technical solution adopted by the present invention to solve the above problems is as follows: The present invention proposes a modulator for a multi-level wireless charging system, comprising:

[0005] Proportional circuits, integrators, multipliers, finite state machines, delay circuits, and microcontrollers;

[0006] The microcontroller is used to provide external signals sign and k.

[0007] The initial voltage δ of the inverter FC-SDM The input multilevel soft-switching modulator, proportional circuit, and integrator will input δ FC-SDM The output e is obtained by integrating the finite state machine feedback signal y.

[0008] The multiplier multiplies the signal e with the signal sign to obtain the input i of the state machine;

[0009] Finite state machines are used to quantize input signal i in conjunction with an external signal k;

[0010] The delay element is used to control the signal triggering time.

[0011] Optionally, the modulator is compensated by the applied wireless charging system into a string-compensated network topology, including: primary coil L1, secondary coil L2, primary compensation capacitor C1, secondary compensation capacitor C2, and flying capacitor C. FC Filter capacitor C dc, Load element Load, resistor R1, resistor R2, switch S1, switch S2, switch S3 and switch S4;

[0012] The primary coil L1, resistor R1, and primary compensation capacitor C1 are connected in series, and the flying capacitor C... FC It is connected in parallel with switches S2 and S3, and in series with switches S1 and S4;

[0013] The secondary-side compensation capacitor C2 and resistor R2 are connected in series.

[0014] Filter capacitor C dc It is connected in parallel with the load element.

[0015] A method for applying a modulator to a multilevel wireless charging system includes:

[0016] Step 1: Set the initial output voltage δ FC-SDM The input multilevel modulator and the state machine feedback signal y are subtracted and then passed through a proportional circuit.

[0017] Step 2: Based on the integrator, the output signal of the proportional circuit is shaped and filtered to convert it into signal e;

[0018] Step 3: The microcontroller provides external signals sign and k. The multiplier multiplies the external signals sign and k to obtain signal i.

[0019] Step 4: Based on a finite state machine and combined with an external signal k, quantize signal i to obtain digital outputs S1, S2, and y. Use signal y as a feedback quantity and the next input δ. FC-SDM Combine;

[0020] Step 5: Use the output signals S1 and S2 of the finite state machine as the switching drive signals of the inverter to obtain three output types: full step signal, half step signal and hold signal, so as to realize the soft switching operation of the transmitter inverter.

[0021] Optionally, the initial output voltage δ in step one FC-SDM The calculation formula is:

[0022]

[0023] In formula (1), N 1S N is the number of half-cycles of a full step jump. 0.5S N represents the number of half-cycles of a half-step jump. 0S The number of half-cycles during which the level is maintained.

[0024] Optionally, in step three, the external signal sign is the direction signal of the inverter output current. sign is the two values ​​1 and -1 corresponding to the direction of the inverter output current, and is inverted every half resonance cycle.

[0025] The external signal k is the voltage balance signal of the flying capacitor.

[0026] Optionally, the value of the digital output y in step four is one of 1, 0.5, and 0, where 1, 0.5, and 0 correspond to the three output types of full step signal, half step signal, and hold signal, respectively.

[0027] Optionally, step five may involve obtaining three output types: full step signal, half step signal, and hold signal.

[0028] If the finite state machine is in the "00" state (both switches S1 and S2 are open), and the input signal i < 0.25, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal 0.25 ≤ i ≤ 0.75 and k > 0, the finite state machine changes from the "00" state (both switches S1 and S2 are open) to the "01" state (switching S1 is open and switching S2 is closed), and the output type is a half-step signal. During the path transition, when the signal 0.25 ≤ i ≤ 0.75 and k < 0, the finite state machine changes from the "00" state (both switches S1 and S2 are open) to the "10" state (switching S1 is closed and switching S2 is open), and the output type is a half-step signal. During the path transition, when the signal i > 0.75, the finite state machine changes from the "00" state (both switches S1 and S2 are open) to the "11" state (both switches S1 and S2 are closed), and the output type is a full-step signal.

[0029] If the finite state machine is in the "01" state (switches S1 open, S2 closed), and the input signal |i|≤0.25 and k>0, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal i<-0.25, the finite state machine changes from the "01" state (switches S1 open, S2 closed) to the "00" state (switches S1 and S2 both open), and the output type is a half-step signal. During the path transition, when the signal i>0.25, the finite state machine changes from the "01" state (switches S1 open, S2 closed) to the "11" state (switches S1 and S2 both closed), and the output type is a half-step signal. During the path transition, when the signal |i|≤0.25 and k<0, the finite state machine changes from the "01" state (switches S1 open, S2 closed) to the "10" state (switches S1 closed, S2 open), and the output type is a hold signal.

[0030] If the finite state machine is in state "11" with both switches S1 and S2 closed, and the input signal i > -0.25, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal -0.75 ≤ i ≤ -0.25 and k > 0, the finite state machine transitions from state "11" with both switches S1 and S2 closed to state "01" with switch S1 open and switch S2 closed, and the output type is a half-step signal. During the path transition, when the signal -0.75 ≤ i ≤ -0.25 and k < 0, the finite state machine transitions from state "11" with both switches S1 and S2 closed to state "10" with switch S1 closed and switch S2 open, and the output type is a half-step signal. During the path transition, when the signal i < -0.75, the finite state machine transitions from state "11" with both switches S1 and S2 closed to state "00" with both switches S1 and S2 open, and the output type is a full-step signal.

[0031] If the finite state machine is in state "10" (switches S1 closed, S2 open), and the input signal |i|≤0.25 and k<0, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal i>0.25, the finite state machine changes from state "10" (switches S1 closed, S2 open) to state "11" (switches S1 and S2 both closed), and the output type is a half-step signal. During the path transition, when the signal i<-0.25, the finite state machine changes from state "10" (switches S1 closed, S2 open) to state "00" (switches S1 and S2 both open), and the output type is a half-step signal. During the path transition, when the signal |i|≤0.25 and k>0, the finite state machine changes from state "10" (switches S1 closed, S2 open) to state "01" (switches S1 open, S2 closed), and the signal type is a hold signal.

[0032] Optionally, during the signal step process, the step direction of the signal is consistent with the current transformation direction.

[0033] Optionally, the calculation steps for the external signal k include:

[0034] Step 3.1: Determine whether the states of switches S1 and S2 in the finite state machine are the same. If they are, then k = 1; otherwise, proceed to step 3.2.

[0035] Step 3.2: Determine whether switch S1 is closed. If it is closed, calculate the value of Q according to Q = Q - sign. If Q = 0, determine whether r is greater than 0.5. If it is greater, k = 1. If it is less than, k = -1. If Q ≠ 0, give the value of k according to the sign at the current time.

[0036] Step 3.3: If switch S1 is in the open state, calculate the value of Q according to Q = Q + sign. If Q = 0, determine whether r is greater than 0.5. If it is greater, then k = 1. If it is less than, then k = -1. If Q ≠ 0, then give the value of k according to the sign at the current moment. Wherein, Q is the balance flag bit, the initial value is 0, the value of Q is the difference between the number of charging cycles and the number of discharging cycles, and r is a random number uniformly distributed in the range of 0 to 1.

[0037] The beneficial effects of this invention are:

[0038] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: the present invention realizes full-range zero voltage switching (ZVS) operation, the multi-level inverter output voltage and current ripple is small, and it can automatically achieve the voltage balance of the flying capacitor without any auxiliary circuits. Furthermore, by optimizing the charging and discharging sequence of the flying capacitor, the voltage fluctuation of the flying capacitor is reduced. Attached Figure Description

[0039] Figure 1 This invention provides a schematic diagram of the structure of a modulator for a multilevel wireless charging system.

[0040] Figure 2 A schematic diagram of a wireless charging system for a half-bridge three-level flying capacitor inverter with series compensation provided by the present invention.

[0041] Figure 3 A schematic diagram of the effective working state of the half-bridge three-level flying capacitor inverter provided by the present invention;

[0042] Figure 3 In the diagram, (a) is a schematic diagram of the half-bridge three-level flying capacitor inverter in the "11" working mode, (b) is a schematic diagram of the half-bridge three-level flying capacitor inverter in the "01" working mode, (c) is a schematic diagram of the half-bridge three-level flying capacitor inverter in the "00" working mode, and (d) is a schematic diagram of the half-bridge three-level flying capacitor inverter in the "10" working mode.

[0043] Figure 4 The input δ provided for this invention FCSDM =0.6 and δ FCSDM A schematic diagram showing the changes in inverter output voltage and current when ω = 0.4;

[0044] Figure 4 In the diagram, (a) represents the input δ. FCSDM A schematic diagram showing the changes in inverter output voltage and current when δ = 0.6, where (b) represents δ. FCSDM A schematic diagram showing the changes in inverter output voltage and current when ω = 0.4;

[0045] Figure 5 This invention provides a schematic diagram of the state path transitions of a finite state machine.

[0046] Figure 6 A flowchart illustrating the calculation of the external signal k provided by this invention;

[0047] Figure 7 The given input δ provided by the present invention FCSDM A schematic diagram of the simulation results when = 0.7. Detailed Implementation

[0048] Specific implementation method one: Combining Figure 1 and Figure 2 This implementation method is described as follows: Figure 1 As shown, the structure of a modulator for a multi-level wireless charging system according to this embodiment includes:

[0049] Proportional circuits, integrators, multipliers, finite state machines, delay circuits, and microcontrollers;

[0050] The microcontroller is used to provide external signals sign and k.

[0051] The initial voltage δ of the inverter FC-SDM The input multilevel soft-switching modulator, proportional circuit, and integrator will input δ FC-SDM The output e is obtained by integrating the finite state machine feedback signal y.

[0052] The multiplier multiplies the signal e with the signal sign to obtain the input i of the state machine;

[0053] Finite state machines are used to quantize input signal i in conjunction with an external signal k;

[0054] The delay element is used to control the signal triggering time.

[0055] like Figure 2 As shown, the modulator is compensated by the applied wireless charging system into a string-to-string compensation network topology, including:

[0056] Primary coil L1, secondary coil L2, primary compensation capacitor C1, secondary compensation capacitor C2, flying capacitor C FC Filter capacitor C dc , Load element Load, resistor R1, resistor R2, switch S1, switch S2, switch S3 and switch S4;

[0057] The primary coil L1, resistor R1, and primary compensation capacitor C1 are connected in series, and the flying capacitor C... FC It is connected in parallel with switches S2 and S3, and in series with switches S1 and S4;

[0058] The secondary-side compensation capacitor C2 and resistor R2 are connected in series.

[0059] Filter capacitor C dc It is connected in parallel with the load element.

[0060] Specific Implementation Method Two: Combining Figure 3-6 This embodiment will now be described, and the steps of an application method for a modulator in a multi-level wireless charging system according to this embodiment include:

[0061] S1: Set the initial output voltage δ FC-SDM The input multilevel modulator is subtracted from the state machine feedback signal y, and then passed through a proportional circuit.

[0062] like Figure 4 As shown, Figure 4 It is the input δ FC-SDM =0.6 and δ FC-SDM The inverter output voltage and current are as follows when the current is 0.4. The inverter output voltage can be expressed as:

[0063]

[0064] In formula (1), N 1S N is the number of half-cycles of a full step jump. 0.5S N represents the number of half-cycles of a half-step jump. 0S The number of half-cycles during which the level is maintained.

[0065] S2: Based on the integrator, the output signal of the proportional circuit is shaped and filtered to convert it into signal e;

[0066] S3: The microcontroller provides external signals sign and k, and uses the multiplier to multiply the external signals sign and k to obtain signal i;

[0067] Both sign and k are external signals generated by the microcontroller. Sign is the direction signal of the inverter output current, with two values, 1 and -1. It is inverted every half resonance cycle to satisfy the constraints of the FC-SDM modulation method. k is the flying capacitor voltage balance signal.

[0068] S4: Based on the finite state machine and combined with the external signal k, the signal i is quantized to obtain digital outputs S1, S2, and y. The signal y is used as a feedback quantity and the next input δ. FC-SDM Combine;

[0069] like Figure 3 As shown, the four effective operating modes of the flying capacitor inverter can be represented by the states of S1 and S2, where "1" represents that either S1 or S2 switch is closed and the complementary switch is open, and "0" represents the opposite. Figure 3As shown, there are a total of 4 states. In order to improve the power factor, FC-SDM modulation needs to follow a constraint: the step direction of the step signal must be consistent with the current transformation direction.

[0070] The value of the digital output y is one of 1, 0.5 and 0, where 1, 0.5 and 0 correspond to the three output types of full step signal, half step signal and hold signal, respectively.

[0071] S5: Use the output signals S1 and S2 of the finite state machine as the switching drive signals of the inverter to obtain three output types: full step signal, half step signal and hold signal, so as to realize the soft switching operation of the transmitter inverter.

[0072] like Figure 5 As shown, if the finite state machine is in the "00" state where both switches S1 and S2 are open, and the input signal i < 0.25, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal 0.25 ≤ i ≤ 0.75 and k > 0, the finite state machine changes from the "00" state where both switches S1 and S2 are open to the "01" state where switch S1 is open and switch S2 is closed, and the output type is a half-step signal. During the path transition, when the signal 0.25 ≤ i ≤ 0.75 and k < 0, the finite state machine changes from the "00" state where both switches S1 and S2 are open to the "10" state where switch S1 is closed and switch S2 is open, and the output type is a half-step signal. During the path transition, when the signal i > 0.75, the finite state machine changes from the "00" state where both switches S1 and S2 are open to the "11" state where both switches S1 and S2 are closed, and the output type is a full-step signal.

[0073] If the finite state machine is in the "01" state (switches S1 open, S2 closed), and the input signal |i|≤0.25 and k>0, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal i<-0.25, the finite state machine changes from the "01" state (switches S1 open, S2 closed) to the "00" state (switches S1 and S2 both open), and the output type is a half-step signal. During the path transition, when the signal i>0.25, the finite state machine changes from the "01" state (switches S1 open, S2 closed) to the "11" state (switches S1 and S2 both closed), and the output type is a half-step signal. During the path transition, when the signal |i|≤0.25 and k<0, the finite state machine changes from the "01" state (switches S1 open, S2 closed) to the "10" state (switches S1 closed, S2 open), and the output type is a hold signal.

[0074] If the finite state machine is in state "11" with both switches S1 and S2 closed, and the input signal i > -0.25, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal -0.75 ≤ i ≤ -0.25 and k > 0, the finite state machine transitions from state "11" with both switches S1 and S2 closed to state "01" with switch S1 open and switch S2 closed, and the output type is a half-step signal. During the path transition, when the signal -0.75 ≤ i ≤ -0.25 and k < 0, the finite state machine transitions from state "11" with both switches S1 and S2 closed to state "10" with switch S1 closed and switch S2 open, and the output type is a half-step signal. During the path transition, when the signal i < -0.75, the finite state machine transitions from state "11" with both switches S1 and S2 closed to state "00" with both switches S1 and S2 open, and the output type is a full-step signal.

[0075] If the finite state machine is in state "10" (switches S1 closed, S2 open), and the input signal |i|≤0.25 and k<0, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal i>0.25, the finite state machine changes from state "10" (switches S1 closed, S2 open) to state "11" (switches S1 and S2 both closed), and the output type is a half-step signal. During the path transition, when the signal i<-0.25, the finite state machine changes from state "10" (switches S1 closed, S2 open) to state "00" (switches S1 and S2 both open), and the output type is a half-step signal. During the path transition, when the signal |i|≤0.25 and k>0, the finite state machine changes from state "10" (switches S1 closed, S2 open) to state "01" (switches S1 open, S2 closed), and the signal type is a hold signal.

[0076] The voltage balance condition for a half-bridge three-level flying capacitor inverter is:

[0077]

[0078] This invention achieves full-range zero-voltage switching (ZVS) operation, with low output voltage and current ripple of the multilevel inverter, and can automatically balance the voltage of the flying capacitor without the need for any auxiliary circuits. Furthermore, it reduces voltage fluctuations of the flying capacitor by optimizing the charging and discharging sequence of the flying capacitor.

[0079] This implementation proposes using a random number method to achieve self-balancing of the flying capacitor. Specifically, the method involves making the "01" and "10" states appear randomly with equal probability, which can effectively control the voltage of the flying capacitor to stabilize at U. dc / 2, however, completely random selection of redundant paths may lead to multiple consecutive charging or discharging cycles, causing significant fluctuations in the flying capacitor voltage. To address this issue, this implementation proposes a method for generating a balancing signal k. The sign of k directly determines the selection of the finite state machine's state transition path, as shown below:

[0080] S501: Determine whether the states of switches S1 and S2 in the finite state machine are the same. If they are, then k = 1; otherwise, proceed to S502.

[0081] S502: Determine whether switch S1 is closed. If it is closed, calculate the value of Q according to Q = Q - sign. If Q = 0, determine whether r is greater than 0.5. If it is greater, k = 1. If it is less than, k = -1. If Q ≠ 0, give the value of k according to the sign at the current time.

[0082] S503: If switch S1 is in the open state, calculate the value of Q according to Q = Q + sign. If Q = 0, determine whether r is greater than 0.5. If it is greater, then k = 1. If it is less than, then k = -1. If Q ≠ 0, then give the value of k according to the sign at the current moment. Wherein, Q is the balance flag bit, the initial value is 0, the value of Q is the difference between the number of charging cycles and the number of discharging cycles, and r is a random number uniformly distributed in the range of 0 to 1.

[0083] Example

[0084] Combination Figure 7 To illustrate this embodiment, and to verify the effectiveness of the trans-capacitor voltage self-balancing capability of the modulator for a multi-level wireless charging system described in this invention, the following simulation experiment was designed in this embodiment:

[0085] This embodiment builds a wireless charging system in simulation software to verify the effectiveness of the proposed flying capacitor multilevel soft-switching modulation method. The mutual inductance value M is set to 60.64μH, the load resistance to 40Ω, the bus voltage to 200V, and the initial voltage of the flying capacitor to 0V. Figure 7 It shows the given input δ FCSDM Simulation results at a value of 0.7 include the balancing signal k, switches S1 and S2, inverter output voltage u and current i, and flying capacitor voltage u. c It can be seen that the output voltage has 4 full steps and 6 half steps within one cycle. The output calculated by the formula is 0.7, which is consistent with the theory. The current fluctuation is small and the flying capacitor voltage is stable at around 100V, indicating that the balancing method of the flying capacitor self-balancing soft-switching modulator designed in this invention is effective.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method for applying a modulator to a multi-level wireless charging system, characterized in that, The modulator used in the method for applying the modulator for the multilevel wireless charging system includes: Proportional circuits, integrators, multipliers, finite state machines, delay circuits, and microcontrollers; The microcontroller is used to provide external signals sign and k; Inverter initial voltage δ The FC-SDM input multilevel soft-switching modulator uses a proportional circuit and an integrator to input... δ The output e is obtained by integrating the FC-SDM with the finite state machine feedback signal y. The multiplier multiplies the signal e with the signal sign to obtain the input i of the state machine; Finite state machines are used to quantize input signal i in conjunction with an external signal k; The delay element is used to control the signal triggering time; The modulator is compensated by the applied wireless charging system into a string-compensated network topology, including: primary coil L 1. Secondary coil L 2. Primary-side compensation capacitor C 1. Secondary-side compensation capacitor C 2. Flying capacitor C FC Filter capacitor C dc Load element, resistor R 1. Resistance R 2. Switches S1, S2, S3, and S4; The primary coil L 1. Resistance R 1 and primary-side compensation capacitor C 1. Series connection, the flying capacitor C FC It is connected in parallel with switches S2 and S3, and in series with switches S1 and S4; The secondary compensation capacitor C 2 and resistor R2 are connected in series; Filter capacitor C dc Connected in parallel with the load element; The steps of the method for applying a modulator in a multi-level wireless charging system include: Step 1: Initial output voltage δ FC-SDM The input multilevel modulator is subtracted from the state machine feedback signal y, and then passed through a proportional circuit. Initial output voltage in step one δ The calculation formula for FC-SDM is: （1）； In formula (1), N 1S The number of half-cycles for a full step jump. N 0.5S This represents the number of half-cycles of a half-step jump. N 0S The number of half-cycles in which the level is maintained; Step 2: Based on the integrator, the output signal of the proportional circuit is shaped and filtered to convert it into signal e; Step 3: The microcontroller provides external signals sign and k, and the multiplier multiplies the external signals sign and k to obtain signal i; In step three, the external signal sign is the direction signal of the inverter output current. sign has two values, 1 and -1, corresponding to the direction of the inverter output current, and is inverted every half resonance cycle. The external signal k is the voltage balance signal of the flying capacitor; Step 4: Based on the finite state machine and the external signal k, quantize signal i to obtain digital outputs S1, S2, and y. Use signal y as a feedback quantity for the next input. δ FC-SDM Combine; In step four, the value of the digital output y is one of 1, 0.5, and 0, where 1, 0.5, and 0 correspond to the three output types of full step signal, half step signal, and hold signal, respectively. Step 5: Use the output signals S1 and S2 of the finite state machine as the switching drive signals of the inverter to obtain three output types: full step signal, half step signal and hold signal, so as to realize the soft switching operation of the transmitter inverter.

2. The application method of a modulator for a multi-level wireless charging system according to claim 1, characterized in that, Step five involves obtaining three output types: full step signal, half step signal, and hold signal. Specifically, these include: If the finite state machine is in the "00" state (both switches S1 and S2 are open), and the input signal i < 0.25, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal 0.25 ≤ i ≤ 0.75 and k > 0, the finite state machine transitions from the "00" state (both switches S1 and S2 are open) to the "01" state (switching S1 is open and switching S2 is closed), and the output type is a half-step signal. During the path transition, when the signal 0.25 ≤ i ≤ 0.75 and k < 0, the finite state machine transitions from the "00" state (both switches S1 and S2 are open) to the "10" state (switching S1 is closed and switching S2 is open), and the output type is a half-step signal. During the path transition, when the signal i > 0.75, the finite state machine transitions from the "00" state (both switches S1 and S2 are open) to the "11" state (both switches S1 and S2 are closed), and the output type is a full-step signal. If the finite state machine is in a "01" state where switch S1 is open and switch S2 is closed, the input signal... When i ≤ -0.25 and k > 0, the state remains unchanged, and the output type is a hold signal. During the path transition, when i < -0.25, the finite state machine is opened by switch S1, and the "01" state with switch S2 closed is transformed into the "00" state with both switches S1 and S2 open, and the output type is a half-step signal. During the path transition, when i > 0.25, the finite state machine is opened by switch S1, and the "01" state with switch S2 closed is transformed into the "11" state with both switches S1 and S2 closed, and the output type is a half-step signal. During the path transition, when i > 0.25, the finite state machine is opened by switch S1, and the "01" state with switch S2 closed is transformed into the "11" state with both switches S1 and S2 closed, and the output type is a half-step signal. When k ≤ 0.25 and k < 0, the finite state machine is converted from the "01" state where switch S1 is open and switch S2 is closed to the "10" state where switch S1 is closed and switch S2 is open, and the output type is a hold signal; If the finite state machine is in state "11" with both switches S1 and S2 closed, and the input signal i > -0.25, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal -0.75 ≤ i ≤ -0.25 and k > 0, the finite state machine transitions from state "11" with both switches S1 and S2 closed to state "01" with switch S1 open and switch S2 closed, and the output type is a half-step signal. During the path transition, when the signal -0.75 ≤ i ≤ -0.25 and k < 0, the finite state machine transitions from state "11" with both switches S1 and S2 closed to state "10" with switch S1 closed and switch S2 open, and the output type is a half-step signal. During the path transition, when the signal i < -0.75, the finite state machine transitions from state "11" with both switches S1 and S2 closed to state "00" with both switches S1 and S2 open, and the output type is a full-step signal. If the finite state machine is in state "10" (switching S1 closed and switching S2 open), the input signal... When i ≤ 0.25 and k < 0, the state remains unchanged, and the output type is a hold signal. During the path transition, when i > 0.25, the finite state machine transitions from a "10" state (switching from switch S1 closed to switch S2 open) to a "11" state (switching from both switches S1 and S2 closed), and the output type is a half-step signal. During the path transition, when i < -0.25, the finite state machine transitions from a "10" state (switching from switch S1 closed to switch S2 open) to a "00" state (switching from both switches S1 and S2 open), and the output type is a half-step signal. During the path transition, when i < -0.25, the finite state machine transitions from a "10" state (switching from switch S1 closed to switch S2 open) to a "00" state (switching from both switches S1 and S2 open), and the output type is a half-step signal. When k ≤ 0.25 and k > 0, the finite state machine is transformed from the "10" state (switching from switch S1 closed to switch S2 open) to the "01" state (switching from switch S1 open to switch S2 closed), with the signal type being a hold signal.

3. The application method of a modulator for a multi-level wireless charging system according to claim 2, characterized in that, During a signal step, the step direction of the signal is consistent with the direction of the current transformation.

4. The application method of a modulator for a multi-level wireless charging system according to claim 1, characterized in that, The steps for calculating the external signal k include: Step 3.1: Determine whether the states of switches S1 and S2 in the finite state machine are the same. If they are, then k=1; otherwise, proceed to step 3.

2. Step 3.2: Determine whether switch S1 is closed. If it is closed, calculate the value of Q according to Q=Q-sign. If Q=0, determine whether r is greater than 0.

5. If it is greater, k=1. If it is less than, k=-1. If Q≠0, give the value of k according to the sign at the current time. Step 3.3: If switch S1 is in the open state, then according to... Calculate the Q value. If Q=0, then determine whether r is greater than 0.

5. If it is greater, then k=1. If it is less than, then k=-1. If Q≠0, then give the k value according to the sign at the current time. Here, Q is the balance flag bit, with an initial value of 0. The Q value is the difference between the number of charging cycles and the number of discharging cycles, and r is a random number uniformly distributed in the range of 0 to 1.

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