Digital controller

Abstract

A digital controller for a switching converter configured to receive an input voltage at an input voltage node and to generate an output voltage at an output voltage node, the switching converter comprising one or more power switches and an energy storage element, the digital controller includes a pulse width modulation control circuit configured to receive an output voltage and generate a PWM control signal to control a switching operation of the one or more power switches, the switching circuit is configured to couple the pulse width modulation control circuit to an input voltage node during a first phase and to couple the pulse width modulation control circuit to a supply voltage node during a second phase, the supply voltage node being at a supply voltage.

Description

[0001] The present disclosure relates to a digital controller. In particular, the present disclosure relates to a digital controller for a switching converter.

[0002] background

[0003] 1(a) is a schematic diagram of a digital buck converter 100 having analog-to-digital converters (ADCs) 102, 104, 106 and a controller 108. Buck converter 100 includes switches 110, 112, an inductor 114, and a capacitor 116. During operation, the switching converter receives an input voltage VIN and generates an output voltage VOUT.

[0004] When the power stage and passive components (inductor 114 and capacitor 116) remain the same as for the analog buck converter, ADC 102 converts the output voltage VOUT into a digital value. Optionally, the inductor current IL of inductor 114 and the input voltage VIN can also be converted from analog to digital according to a digital control method.

[0005] We distinguish:

[0006] The switching frequency (FSW) of the buck converter 100, for example 2 MHz. FSW is equal to 1 / TSW, where TSW is the switching period of the buck converter 100. FSW is the frequency of the power stage.

[0007] The processing frequency (FS) of the digital controller 108 , for example, about 100 MHz. FS is equal to 1 / TS, where TS is the processing period of the controller 108 . Optionally, FS may also be the sampling frequency of the ADC 102 .

[0008] Depending on conditions associated with the load, the controller 108 may operate in different modes. A load is a component that consumes electrical power, such as the power provided by the buck converter 100 when the buck converter 100 is coupled to the load. The load may draw a load current from the buck converter 100, where "high load" refers to a higher load current than drawn during "low load" or "light load".

[0009] The digital controller provides pulse width modulation (PWM) control at high loads and pulse frequency modulation (PFM) control at light loads.

[0010] At high loads the digital loop operates in PWM to meet the following requirements:

[0011] When compared with PFM, VOUT requires higher accuracy and low ripple.

[0012] PWM provides a constant frequency.

[0013] Transient load response: PWM can react faster than PFM.

[0014] At light loads, the digital buck converter 100 operates in PFM with less stringent requirements. However, the controller 108 needs to consume less power.

[0015] FIG1( b) is a schematic diagram of a digital buck converter 100 and a controller 108 for providing PWM and PFM control. Buck converter 100 includes a switch circuit 109. Controller 108 includes a PWM control circuit 118 and a PFM control circuit 120. The operation of the circuit components is synchronized using a clock signal FS. The system includes a finite state machine (FSM) 121 that manages the control of the system and a decoupling capacitor 123. FSM 121 is always on. PWM control circuit 118 and PFM control circuit 120 receive a supply voltage VDIG from a low dropout regulator (LDO) 121, which supplies power to the corresponding control subcircuit.

[0016] The PWM control circuit 118 includes an ADC 122, a DIGLOOP circuit 124, and a DIGPWM circuit 126. The PWM control circuit 118 is used for high-performance PWM control and is disabled under light loads.

[0017] The PFM control circuit 120 includes an analog comparator 128 and a DIGPFM circuit 130. The analog comparator 128 detects the output voltage VOUT level during the PFM mode of operation, and the DIGPFM circuit 130 controls the switching operation of the buck converter 100 to "top up" the output voltage VOUT when the output voltage VOUT drops. Note that the DIGPFM circuit 130 can use the clock signal FS, another slower clock, or even no clock at all, thereby reducing its power consumption.

[0018] The PWM control circuit 118 increases power consumption and reduces efficiency. For example, if the load current IOUT is in the range of 100uA to 1mA, when the clock signal FS switches, the typical consumption of the PWM control circuit is 10mA for a total of 100,000 transistor gates. Therefore, the controller 108 consumes 100 times more power than the load on the output voltage VOUT.

[0019] Overview

[0020] It is desirable to reduce the power consumption and improve the efficiency of a controller for a switching converter using a pulse width modulation control scheme.

[0021] According to a first aspect of the present disclosure, a digital controller for a switching converter is provided, the switching converter being configured to receive an input voltage at an input voltage node and to generate an output voltage at an output voltage node, the switching converter comprising one or more power switches and an energy storage element, the digital controller comprising a pulse width modulation control circuit and a switching circuit, the pulse width modulation control circuit being configured to receive the output voltage and to generate a PWM control signal to control the switching operation of the one or more power switches, the switching circuit being configured to couple the pulse width modulation control circuit to the input voltage node during a first stage, and to couple the pulse width modulation control circuit to a power supply voltage node during a second stage, the power supply voltage node being at a power supply voltage.

[0022] Optionally, the switching converter is a buck converter, a boost converter or a buck-boost converter.

[0023] Optionally, the energy storage element is an inductor.

[0024] Optionally, the one or more power switches include a first power switch and a second power switch.

[0025] Optionally, the pulse width modulation control circuit includes an analog-to-digital converter coupled to the output voltage node and configured to digitize the output voltage to provide a digital representation of the output voltage.

[0026] Optionally, the pulse width modulation control circuit comprises a digital loop circuit.

[0027] Optionally, the pulse width modulation control circuit includes a digital PWM circuit.

[0028] Optionally, the first stage precedes the second stage.

[0029] Optionally, the first phase is a charging phase and the second phase is a holding phase.

[0030] Optionally, during the first phase, the supply voltage node is decoupled from the pulse width modulation control circuit, and during the second phase, the input voltage node is decoupled from the pulse width modulation control circuit.

[0031] Optionally, the switching circuit comprises one or more first stage switches for coupling the pulse width modulation control circuit to the input voltage node during the first stage and one or more second stage switches for coupling the pulse width modulation control circuit to the supply voltage node during the second stage.

[0032] Optionally, the first stage precedes the second stage.

[0033] Optionally, the first phase is a charging phase and the second phase is a holding phase.

[0034] Optionally, during the first phase, one or more second phase switches are opened to decouple the supply voltage node from the pulse width modulation control circuit, and during the second phase, one or more first phase switches are opened to decouple the input voltage node from the pulse width modulation control circuit.

[0035] Optionally, the pulse width modulation control circuit includes an analog-to-digital converter coupled to the output voltage node and configured to digitize the output voltage to provide a digital representation of the output voltage, the one or more first stage switches include a first switch for coupling the analog-to-digital converter to the input voltage node during the first stage, and the one or more second stage switches include a second switch for coupling the analog-to-digital converter to the supply voltage node during the second stage.

[0036] Optionally, the pulse width modulation control circuit includes a digital loop circuit, one or more first stage switches include a third switch for coupling the digital loop circuit to an input voltage node during the first stage, and one or more second stage switches include a fourth switch for coupling the digital loop circuit to a supply voltage node during the second stage.

[0037] Optionally, the pulse width modulation control circuit includes a digital PWM circuit, one or more first stage switches include a fifth switch for coupling the digital PWM circuit to an input voltage node during the first stage, and one or more second stage switches include a sixth switch for coupling the digital PWM circuit to a power supply voltage node during the second stage.

[0038] Optionally, the digital controller includes: a circuit component; one or more first-stage switches including a first switch including a first transistor for coupling the circuit component to an input voltage node during the first stage, and one or more second-stage switches including a second switch including a second transistor for coupling the circuit component to a power supply voltage node during the second stage; a third transistor including a gate coupled to the gate of the first transistor; a fourth transistor coupled in series with the third transistor; a comparator including a first comparator input terminal coupled to the first transistor and the second transistor, a second comparator input terminal coupled to the power supply voltage node, and a comparator output terminal for outputting a charging signal; an OR gate including a first OR gate input terminal coupled to a turn-off signal, a second OR gate input terminal coupled to the comparator output terminal for receiving the charging signal, and an OR gate output terminal coupled to the gate of the second transistor; and an AND gate including a first AND gate input terminal coupled to the comparator output terminal for receiving the charging signal, a second AND gate input terminal coupled to the turn-on signal, and an AND gate output terminal coupled to the gate of the fourth transistor.

[0039] Optionally, the circuit component is one of: an analog-to-digital converter coupled to the output voltage node and configured to digitize the output voltage to provide a digital representation of the output voltage, a digital loop circuit, and a digital PWM circuit.

[0040] Optionally, the pulse width modulation control circuit is configured to control switching operation of the one or more switches during the first operating mode.

[0041] Optionally, the digital controller comprises additional control circuitry configured to control switching operation of the one or more switches during the second operating mode.

[0042] Optionally, the additional control circuit comprises a pulse frequency modulation control circuit.

[0043] Optionally, the first operation mode is a high load operation mode, and the second operation mode is a low load operation mode.

[0044] Optionally, the digital controller comprises a voltage regulator or a power rail for providing a supply voltage at the supply voltage node.

[0045] Optionally, the voltage regulator comprises a low dropout regulator or a buck converter.

[0046] Optionally, the voltage regulator comprises a low dropout voltage regulator configured to receive an input voltage and provide a supply voltage at a supply voltage node.

[0047] According to a second aspect of the present disclosure, a method for controlling a switching converter is provided, the switching converter being configured to receive an input voltage at an input voltage node and to generate an output voltage at an output voltage node, the switching converter comprising one or more power switches and an energy storage element, the method comprising receiving the output voltage at a pulse width modulation control circuit, generating a PWM control signal using the pulse width modulation control circuit to control the switching operation of the one or more power switches, coupling the pulse width modulation control circuit to the input voltage node during a first phase, and coupling the pulse width modulation control circuit to a power supply voltage node during a second phase, the power supply voltage node being at a power supply voltage.

[0048] It is to be understood that the method of the second aspect may include the features set out in the first aspect, and may be combined with other features as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0051] FIG. 1( a ) is a schematic diagram of a digital buck converter, and FIG. 1( b ) is a schematic diagram of the digital buck converter of FIG. 1( a ) and a controller for providing PWM and PFM control;

[0052] Figure 2 is a schematic diagram of the system of FIG. 1( b ), the system being configured to use a known power gating method;

[0053] Figure 3 is a schematic diagram of a digital controller for a switching converter according to a first embodiment of the present disclosure;

[0054] FIG. 4( a ) is a schematic diagram of a digital controller according to a second embodiment of the present disclosure, and FIG. 4( b ) is a schematic diagram of a specific embodiment of a switching circuit of the digital controller of FIG. 4( a ) according to a third embodiment of the present disclosure;

[0055] FIG. 5( a ) is a schematic diagram of a digital controller and a switching converter according to a fourth embodiment of the present disclosure, and FIG. 5( b ) is a schematic diagram of a digital controller and a switching converter according to a fifth embodiment of the present disclosure;

[0056] FIG6( a ) is a schematic diagram of a portion of a digital controller as may be implemented in one of the specific embodiments of the digital controller, and FIG6( b ) is a graph showing example waveforms over time for a practical implementation of the digital controller of FIG6( a );

[0057] FIG. 7( a ) is a schematic diagram of a digital controller according to a sixth embodiment of the present disclosure, and FIG. 7( b ) is a graph showing simulation results of the system shown in FIG. 7( a ); and

[0058] Figure 8 is a schematic diagram of a specific embodiment of a PWM control circuit.

[0059] Detailed Description

[0060] It is desirable to reduce the power consumption of modules DIGLOOP 124 and DIGPWM 126. ADC 122 can be switched off when not in use so that its power consumption is reduced to zero.

[0061] A straightforward approach is to gate the clock signal FS, where the total supply current IDD budget can be as follows:

[0062] piece IDD (when FS is not switched) ACOMP 10μA DIGLOOP+DIGPWM 20μA DIGPFM+FSM 5μA

[0063] The remaining 20 μA consumption of DIGLOOP+DIGPWM is due to digital leakage (also called subthreshold current).

[0064] If the load current IOUT is 100μA (i.e., when the output voltage VOUT = 1V, the output power POUT = 100μW), the input power PIN we get is finally:

[0065] PIN=VIN×(Total_IDD+(IOUT×VOUT) / VIN) (1)

[0066] Where Total_IDD is the total supply current IDD, and the other symbols have the meanings as described above.

[0067] PIN=3.6V×(35μA+(100μA×1V) / 3.6V)=226μW (2)

[0068] The POUT / PIN efficiency is 44%, and this 20μA leakage results in a loss of 72μW. Without this leakage, the efficiency would be 66%.

[0069] Figure 2 1( b ) is a schematic diagram of the system of FIG. 1( b ) configured to use a known power gating method. The controller 108 further includes switches 200 , 202 , 204 .

[0070] The PWM control circuit 118 can be disconnected from VDIG so that leakage is suppressed. A daisy chain of switches 200, 202, 204 is created to create a power gated power supply VDIG1, ​​VDIG2, VDIG3 to control the inrush current occurring from VDIG. VDIG1, ​​VDIG2, VDIG3 represent voltage rails.

[0071] However, applying this approach in the context of a buck converter 100 results in the following disadvantages:

[0072] Daisy chain wake-up (powering up VDIG1, ​​VDIG2, VDIG3) is typically 100ns: it cannot be used for a buck converter 100 which needs to wake up its PWM control circuit 118 within 20ns in case of a sudden load transient on the output voltage VOUT.

[0073] Due to the daisy chain 200, 202, 204, there is residual kick-back on VDIG.

[0074] If the buck converter is instantiated in a power management integrated circuit (PMIC) having a plurality of buck converters 100

[0075] The device 100 can further slow down the wake-up of the power supply voltage VDIG.

[0076] Attention must be paid to the top-level unit PMIC layout: metal traces serving VDIG1, ​​VDIG2, and VDIG3

[0077] The metal tracks must be oversized to support the large inrush currents required to charge these nodes compared to their normal consumption. For example: if the total equivalent capacitance on VDIG1 is 100pF (due to all digital gates) and a wake-up time of 20ns is preferred at 1V supply, then the inrush current is: I_Surge = 100pF ×

[0078] (1V / 20ns) = 5mA, while the normal consumption of the block might be, for example, 2.5mA: just to be able to

[0079] To charge within 20ns, the power connection to VDIG1 must be twice as large.

[0080] Figure 3 is a schematic diagram of a digital controller 300 for a switching converter 302 according to a first embodiment of the present disclosure. The switching converter 302 receives an input voltage VIN at an input voltage node NVIN and generates an output voltage VOUT at an output voltage node NOUT. The switching converter 302 includes one or more power switches 304 and an energy storage element 306.

[0081] The switching converter 302 may be, for example, a buck converter, a boost converter, or a buck-boost converter. The energy storage element 306 may be an inductor. The switching converter 302 may include a first power switch and a second power switch (as in the case of the buck converter of FIG. 1( a )).

[0082] The digital controller 300 also includes a pulse width modulation (PWM) control circuit 310, which is configured to receive the output voltage VOUT and generate a PWM control signal 312 for controlling the switching operation of the power switch 304. It is to be understood that for the purpose of illustration, a single power switch is shown. According to the understanding of the skilled person, a specific embodiment may include one or more power switches.

[0083] The PWM control circuit 310 may include a gate driver such that a PWM control signal 312 in a high state is used to enable a high-side switch and a PWM control signal 312 in a low state is used to enable a low-side switch.

[0084] The PWM control signal 312 may be generated as follows: The digitized output voltage is compared to a reference voltage (a target or "desired" voltage setting: a synthetic or configurable output voltage setting), and based on the result, a PWM signal 312 is generated and used to control switches to be turned on or off in order to regulate VOUT to the desired value.

[0085] The digital controller 300 also includes a switching circuit 314. During operation, the switching circuit 314 couples the PWM control circuit 310 to the input voltage node NVIN during a first phase of operation. During operation, the switching circuit 314 couples the PWM control circuit 310 to the supply voltage node Nsupply during a second phase of operation. The supply voltage node is at a supply voltage VDIG.

[0086] In certain embodiments, the digital controller 300 may include a low dropout regulator LDO 308 configured to receive an input voltage VIN and provide a supply voltage VDIG at a supply voltage node Nsupply.

[0087] The following description and embodiments will include LDO 308 for providing the supply voltage VDIG. It is to be understood that other embodiments may use alternative methods and / or components to provide the supply voltage VDIG. For example, the supply voltage VDIG may be provided by a different type of regulator (e.g., a buck converter); or it may be provided by a power rail.

[0088] Therefore, during the first phase, the power of the PWM control circuit 310 is provided by the input voltage VIN; and during the second phase, the power of the PWM control circuit 310 is provided by the power supply voltage VDIG.

[0089] The first phase may precede the second phase. For example, when the digital controller 300 initially activates the PWM control mode, the first phase may be a startup phase. When a certain condition is reached, when the PWM control circuit 310 is powered using the power supply VDIG, the digital controller 300 may then switch to a second phase associated with normal operation during the PWM control mode. The first phase may be a charging phase, and the second phase may be a holding phase.

[0090] During the first phase, the supply voltage node Nsupply may be decoupled from the PWM control circuit 310. During the second phase, the input voltage node NVIN may be decoupled from the PWM control circuit 310.

[0091] The switching circuit 314 may include one or more first-stage switches, wherein the one or more first-stage switches include a first switch 316 for coupling the PWM control circuit 310 to the input voltage node NVIN during the first stage, and the switching circuit 314 may include one or more second-stage switches, wherein the one or more second-stage switches include a second switch 318 for coupling the PWM control circuit 310 to the power supply voltage node Nsupply during the second stage.

[0092] During the first phase, the second switch 318 may be turned off, so that the supply voltage node Nsupply is decoupled from the PWM control circuit 310. During the second phase, the first switch 316 may be turned off, so that the input voltage node NVIN is decoupled from the PWM control circuit 310.

[0093] By having a first stage in which power is provided at the input voltage VIN rather than the supply voltage VDIG, the inrush current occurs from the input voltage VIN supply (typically 3.6V), which can support the kickback effect and thus can withstand a much larger voltage drop (e.g., from a 3.6V to a 1.0V rail). This therefore suppresses the current drawn by the supply voltage VDIG and resolves the issue with the reference Figure 2 The disadvantages associated with the controller 108 described in .

[0094] FIG4( a ) is a schematic diagram of a digital controller 400 according to a second embodiment of the present disclosure. The digital controller 400 is a specific implementation of the digital controller 300 .

[0095] In the present embodiment, the PWM control circuit 310 includes an analog-to-digital converter (ADC) 402 coupled to the output voltage node NOUT and configured to digitize the output voltage VOUT.

[0096] The PWM control circuit 310 may further include a digital loop circuit 404 .

[0097] The PWM control circuit 310 may further include a digital PWM circuit 406 .

[0098] FIG. 4( b ) is a schematic diagram of a specific embodiment of the digital controller 400 of FIG. 4( a ) regarding the switch circuit 314 according to the third embodiment of the present disclosure.

[0099] The first stage switches include a first switch 316 , a third switch 408 , and a fifth switch 410 for respectively coupling the ADC 402 , the digital loop circuit 404 , and the digital PWM circuit 406 to the input voltage node NVIN during the first stage.

[0100] The second phase switches include the second switch 318, the fourth switch 412, and the sixth switch 414 for respectively coupling the ADC 402, the digital loop circuit 404, and the digital PWM circuit 406 to the supply voltage node Nsupply during the second phase.

[0101] 5( a ) is a schematic diagram of a digital controller 500 and a switching converter 302 according to a fourth embodiment of the present disclosure. According to the understanding of a skilled person, the digital controller 500 may include any features described with respect to other embodiments herein.

[0102] In this embodiment, the PWM control circuit 310 is configured to control the switching operation of the one or more power switches 304 during the first operating mode. For example, the first operating mode may be used when there is a "high load" demand where the load current exceeds a threshold.

[0103] The digital controller 500 may include additional circuitry 502 configured to control switching operation of one or more power switches 304 during the second operating mode. For example, the second operating mode may be used when there is a "light load" requirement where the load current is below a threshold. The additional circuitry may, for example, include a PFM control circuit.

[0104] FIG5( b) is a schematic diagram of a digital controller 504 and a switching converter according to a fifth embodiment of the present disclosure. Figure 2 The systems described in share features.

[0105] Embodiments of the digital controller described herein provide the following advantages:

[0106] It suppresses the rebound / recoil on VDIG due to excessive surge (e.g. Figure 2 What happens in the system?

[0107] It allows for a much shorter power-up time, typically 20ns instead of 100ns, making the entire system compatible with the buck PFM-to-PWM transition time.

[0108] It offloads the top-level routing, which limits it back to normal supply current IDD consumption and does not have to deal with surges.

[0109] FIG. 6( a ) is a schematic diagram of a portion of a digital controller 600 , which, as will be appreciated by a skilled artisan, may be implemented in a specific embodiment of one of the digital controllers described herein.

[0110] This embodiment shows an example of how switches 316, 318 can be operated based on the operating phase during the PWM operating mode. Although switches 316, 318 are shown for powering ADC 402, it is to be understood that the system of FIG. 6(a) can be alternatively or additionally applied to control the supply of power to digital loop circuit 404 and / or digital PWM circuit 406, according to the understanding of the skilled person.

[0111] The switches 316, 318 each include a transistor. The digital controller 600 includes a transistor 602 having a gate coupled to the gate of the transistor 316. The digital controller 600 also includes a transistor 604 coupled in series with the transistor 602.

[0112] Digital controller 600 also includes a comparator 606 having a first input coupled to transistors 316, 318 and a second input coupled to supply voltage node Nsupply. During operation, comparator 606 outputs a charging signal (labeled "CHARGE").

[0113] The digital controller 600 further includes an OR gate 608 including a first input terminal for receiving the shutdown signal and a second input terminal for receiving the charge signal. The OR gate 608 has an output terminal coupled to the gate of the transistor 318.

[0114] The digital controller 600 further includes an AND gate 610 having a first input terminal for receiving the charging signal and a second input terminal for receiving the conduction signal. An output terminal of the AND gate 610 is coupled to the gate of the transistor 604.

[0115] The digital controller 600 further includes a resistor 611 and a capacitor 613 .

[0116] FIG6( b) is a graph showing example waveforms over time for an actual implementation of the digital controller 600 of FIG6( a), showing: a trace 612 of the turn-on signal; a trace 614 of the AND gate output signal; a trace 615 of the charge signal; and a trace 617 of the voltage on the voltage rail VDIG1 provided to the ADC 402 during operation.

[0117] As previously described, three instances of portions of the digital controller 600 can be used to control the power supply to each of the ADC 402, the digital loop circuit 404, and the digital PWM circuit 406, with a single instance being used for each of the three components. Such an embodiment would enable all rails VDIG1, ​​VDIG2, VIDG3 to be "wake-up" at the same time.

[0118] Each rail VDIG1 , VDIG2 , VDIG3 is charged individually through its associated switch ( 316 , 408 , 410 ) and provides a large surge current directly from the input voltage VIN, leaving the supply voltage VDIG unloaded.

[0119] Once these rails VDIG1, ​​VDIG2, VDIG3 reach a voltage close to VDIG, switches 316, 408, 410 may be turned off and switches 318, 412, 414 may be turned on to connect each of VDIG1, ​​VDIG2, and VDIG3 to VDIG. Normal operation is then resumed.

[0120] The lines connecting switches 316, 408, 410 to VDIG1, ​​VDIG2, VDIG3 respectively are the only lines that must support the surge current, while switches 318, 412, 414 may be lower voltage switches sized only for current in normal operation.

[0121] 6( b ), before time t1, VDIG1 is disconnected from the power supply and the on signal is equal to zero. Transistor 604 is in an off state and therefore does not allow current to flow, which deactivates the current mirror formed by transistor 316 and transistor 602. In addition, the off signal is equal to 1, so that transistor 602 is turned off. VDIG1 is in a high impedance state and can be selectively pulled down. In this case, VDIG1 becomes less than VDIG, in which case the charge signal is equal to 1.

[0122] It is to be understood that comparator 606 may be a static comparator such that it consumes current only when switching and no current otherwise.

[0123] When FSM 121 sets the on signal to 1 and the off signal to zero at time t1, the output of AND gate 610 becomes 1 and turns on the high voltage current mirror formed by transistor 316 and transistor 602. The mirror will charge VDIG1 from the input voltage VIN.

[0124] In a specific example, the FSM 121 requires information when to enable the buck converter. This can be indicated, for example, from a central point in the system or an external host. The FSM 121 itself will follow a predefined (or configurable) transition sequence for startup and shutdown.

[0125] In summary: FSM 121 monitors the load and switches to PWM for high loads (on asserts and off de-asserts) and to PFM for low loads (on de-asserts and off asserts).

[0126] When VDIG1 exceeds VDIG, comparator 606 sets the charge signal to zero at time t2. This resets the output of AND gate 610 to zero and stops the high voltage current mirror from charging VDIG1, ​​which turns on transistor 318 to connect and hold VDIG1 to the supply voltage VDIG.

[0127] In summary, rail VDIG1 now has two switches for power gating:

[0128] Switch 316 (charging switch): It has a high voltage characteristic for charging VDIG1 from VIN

[0129] • Switch 318 (hold switch): It is a low voltage switch that holds VDIG1 to VDIG.

[0130] FIG. 7( a ) is a schematic diagram of a digital controller 700 according to a sixth embodiment of the present disclosure.

[0131] This embodiment shows a possible implementation with a common-gate amplifier. This embodiment does not use a current mirror, so the charging current is limited by the top resistor and the current can vary with the voltage vdd.

[0132] FIG. 7( b ) is a graph showing simulation results of the system shown in FIG. 7( a ) and using parameters suitable for actual implementation.

[0133] Trace 702 is a turn-on signal; trace 704 shows a start in progress signal; trace 706 shows a first start completion signal; trace 708 shows a second start completion signal; trace 710 shows VDIG (as shown in FIG. 5( b)); and trace 712 shows VDIG1 (as shown in FIG. 5( b)). It should be noted that *_n indicates that the traces startInProgress_n and startFinished_n are "inverted" relative to the behavior implied by the name (these signals are actually active low).

[0134] Figure 83 is a schematic diagram of a specific embodiment of the PWM control circuit 310. According to the understanding of a skilled person, one or more features of the PWM control circuit 310 may be implemented in an embodiment of the present disclosure.

[0135] Figure 8 The operation of the circuit is as follows:

[0136] The output voltage VOUT is digitized by the ADC 402 to provide a digitized output voltage signal DOUT.

[0137] The digitized output voltage signal DOUT is compared with a digital reference voltage DREF corresponding to a target voltage of the output voltage VOUT. The two digital DOUT and DREF can be, for example, 8-bit buses, where

[0138] The digital code [0; 255] corresponds to the analog range [0.50V; 1.50V].

[0139] The digital error voltage signal DVERR is equal to DREF-DOUT, which is provided to the digital loop control proportional-integral-derivative (PID) circuit 800 to convert the digitized error voltage DVERR into a digital target current DITARGET, which is a digital value that is a target setting for the analog inductor current IL. Therefore, if the output voltage VOUT decreases, the digitized output voltage signal DOUT decreases, the digital error voltage signal DVERR increases, and the digital target current DITARGET increases: the digital control PID 800 requests a larger inductor current IL to restore the output voltage VOUT.

[0140] The digital target current DITARGET may be encoded on more bits, such as 16 bits, and the following signal.

[0141] The inductor target current DITARGET enters the (digital current generating circuit 802; PIDI circuit 804;

[0142] The PWM circuit 806 and the power stage 100 form an “inner loop”. The inner loop adjusts the duty cycle MAG / DEMAG so that the analog inductor current IL matches its digital counterpart inductor current target DITARGET on average.

[0143] The digital current generation circuit 802 may be the ADC 104 as shown in FIG. 1( a ), or may be a “synthesizer” so that it can digitally reproduce the inductor current IL behavior based on the input voltage VIN, the output voltage VOUT, the duty cycle, and possibly other parameters.

[0144] The inner loop operates as follows: If the digital target current DITARGET is higher than the digital inductor current DIL, the digital current error DIERR increases. The digital current error DIERR passes through an integrator (PID 804) to generate a filtered and amplified version, the filtered digital current error DIERRF, which is added and enters the digital duty cycle converter (PWM circuit 806) to increase the duty cycle. This results in an increase in the inductor current IL.

[0145] The digital loop circuit 404 also includes addition / subtraction circuits 808 , 810 , and the digital PWM circuit 406 includes logic and gate driver circuits 812 .

[0146] Once the inner loop settles to steady state, the average digital target current is equal to the average digital inductor current, which can be expressed as follows:

[0147] <ditarget> ＝ <dil>(3)

[0148] Variables enclosed in "<>" are used to represent the mean value of the variable. For example, <x>Represents the mean value of variable x.

[0149] In summary, embodiments of the present disclosure use power gating introduced in a time-critical control loop of a DC-DC converter to enable the use of lower power / lower latency / higher leakage voltage techniques. This is ideal because of the time-critical nature of the VOUT regulation of the control loop, and the intensive processing and calculations must be completed within two clock cycles (i.e., 40ns for a 50MHz clock) to achieve the required timing. In addition, embodiments of the present disclosure can use dual-switch charge / hold power gating to accommodate the needs of a buck converter (leakage and 20ns transition time) and the needs of a PMIC top-level unit (routing and kickback / surge on VDIG).

[0150] When compared to known systems, embodiments of the present disclosure can reduce power consumption and improve efficiency of a controller of a switching converter using a pulse width modulation control scheme. In addition, embodiments of the present disclosure can meet power-up timing standards that known systems do not meet.

[0151] Various improvements and modifications may be made to the above without departing from the scope of the present disclosure.< / x> < / dil> < / ditarget>

Claims

1. A digital controller for a switching converter, the switching converter being configured to receive an input voltage at an input voltage node and to generate an output voltage at an output voltage node, the switching converter comprising one or more power switches and an energy storage element, the digital controller comprising: a pulse width modulation control circuit configured to receive the output voltage and generate a PWM control signal to control a switching operation of the one or more power switches; and A switch circuit, wherein the switch circuit is configured to: i) coupling the pulse width modulation control circuit to the input voltage node during a first phase; as well as ii) coupling the pulse width modulation control circuit to a supply voltage node during a second phase, the supply voltage node being at a supply voltage.

2. The digital controller according to claim 1, wherein: The switching converter is a buck converter, a boost converter or a buck-boost converter.

3. The digital controller according to claim 1, wherein: The energy storage element is an inductor.

4. The digital controller according to claim 1, wherein: The pulse width modulation control circuit includes an analog-to-digital converter coupled to the output voltage node, and the analog-to-digital converter is configured to digitize the output voltage to provide a digital representation of the output voltage.

5. The digital controller according to claim 4, wherein: The pulse width modulation control circuit includes a digital loop circuit.

6. The digital controller according to claim 5, wherein: The pulse width modulation control circuit includes a digital PWM circuit.

7. The digital controller according to claim 1, wherein: The pulse width modulation control circuit is configured to control switching operation of the one or more switches during a first operating mode.

8. The digital controller of claim 7, comprising additional control circuitry configured to control switching operation of the one or more switches during the second operating mode.

9. The digital controller according to claim 8, wherein: The additional control circuit includes a pulse frequency modulation control circuit.

10. A digital controller according to any preceding claim, wherein: The switching circuit includes one or more first stage switches for coupling the pulse width modulation control circuit to the input voltage node during the first stage and one or more second stage switches for coupling the pulse width modulation control circuit to the supply voltage node during the second stage.

11. The digital controller according to claim 10, wherein: During the first phase, the one or more second phase switches are opened so that the supply voltage node is decoupled from the pulse width modulation control circuit, and during the second phase, the one or more first phase switches are opened so that the input voltage node is decoupled from the pulse width modulation control circuit.

12. A method of controlling a switching converter, the switching converter being configured to receive an input voltage at an input voltage node and generate an output voltage at an output voltage node, the switching converter comprising one or more power switches and an energy storage element, the method comprising: receiving the output voltage at a pulse width modulation control circuit; generating a PWM control signal using the pulse width modulation control circuit to control the switching operation of the one or more power switches; coupling the pulse width modulation control circuit to the input voltage node during a first phase; and The pulse width modulation control circuit is coupled to a supply voltage node during a second phase, the supply voltage node being at a supply voltage.

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