AC-DC power switch circuit and chip

Abstract

The invention discloses an AC-DC (alternating current-direct current) power switch circuit and a chip, which are applied to an SSR (simple sequence repeat) topology circuit and are used for realizing that the maximum load current and the maximum power in a BCM (body control module) mode do not change along with input voltage, and the AC-DC power switch circuit comprises a timing difference compensation circuit (101) which is used for compensating the maximum load current and the maximum power in each switching period, when the conduction time of the primary side of the AC-DC power supply switching circuit is less than a first duration, after the secondary side of the AC-DC power supply switching circuit finishes discharging, waiting for a second duration and then generating a trigger opening signal (select) for triggering the next switching period to be opened; the first duration is the switch-on duration of a switch tube of the primary side in a single period when the SSR topology circuit works in a BCM mode at the maximum load under the valley voltage of the minimum input voltage of the SSR topology circuit, and the second duration is the difference value between the first duration and the last switch-on duration. The high-voltage and low-voltage maximum working frequencies are the same, and the maximum load currents are the same.

Description

Technical Field

[0001] The present invention relates to the field of converting AC voltage into DC voltage, and in particular to an AC-DC power switch circuit and a chip. Background Art

[0002] refer to Figure 1 , is a traditional SSR topology AC-DC circuit block diagram, the dotted box represents the AC-DC chip. When the chip works in CCM mode, the maximum input power can be achieved without changing with the input voltage Vin, but the requirements for the secondary synchronous rectification chip are higher and the cost is more expensive. Specifically, the information of the output Vo is fed back to the chip com pin through the sampling resistors R1 and R2, TL431 and the optocoupler. The chip adjusts the operating frequency and the inductor current IL according to the voltage of the com pin to achieve constant output voltage. When the maximum load is applied, the com pin voltage reaches the maximum value, the chip's operating frequency is constant, and the maximum value of IL Ipeak is constant. When working in CCM mode, the chip's operating frequency is determined by the operating frequency of the oscillator osc. When the output of osc becomes high, the switch tube M1 is turned on. When the sampling voltage vcs representing the inductor current (i.e., the voltage drop on Rcs) reaches the com pin voltage Vcom, the switch tube is turned off; until the next osc high level comes, the next cycle is started. This switching mode does not detect whether the inductor current drops to zero after the switch tube is turned off, so it will work in CCM mode. Figure 2 This is the working waveform in CCM. The maximum working frequency F set inside the chip is 65KHz, the maximum value of IL Ipeak is 0.9A, the inductance value L is 1mH, the turns ratio is n=Np / Ns=11, and Ipeak, L and turns ratio n can be adjusted externally according to the application scheme. When the input voltage is 264Vac, the maximum voltage is 373V, the output voltage Vo is 12V, the diode conduction voltage VD1 is 0.7V, and when working at the maximum load, Ipeak=0.9A. According to the volt-second balance formula:

[0003] V on t on =V off t off ;

[0004]

[0005]

[0006] T onp is the primary conduction time, T ons is the secondary discharge time, I peak0 is the current value before IL is turned on;

[0007] When Ipeak0=0, T onpand T ons Maximum, get T ons =6.44uS, T onp =2.412uS;

[0008]

[0009] So when Vac is high, it works in DCM mode, and the maximum power is:

[0010]

[0011] The conversion efficiency is η=85%, and the maximum load current Iocp is:

[0012]

[0013] When Vin is 90V, it works at maximum load and the valley voltage is 80Vdc. At this time, we have:

[0014]

[0015]

[0016] When Ipeak0=0, T ons and T onp Maximum, get T ons =6.44uS, T onp =11.25uS, at this time T ons +T onp =17.69uS>15.38uS, which does not conform to the volt-second balance formula, and it works in CCM mode at this time.

[0017] According to the volt-second balance, we can get Ipeak0 = 0.117A. At this time, the maximum input power is:

[0018]

[0019] The conversion efficiency is η=85%, and the maximum load current Iocp is:

[0020]

[0021] It can be seen that the chip working in CCM can achieve the same maximum load current when the input voltage is high voltage Vac and low voltage Vac.

[0022] When the chip is designed to work in BCM mode, the waveform of the maximum load working in BCM mode is as follows Figure 3When the maximum load is working in BCM, IS is the secondary inductor current. Each time the secondary current IS is detected to be reduced to 0, the switch tube is turned on until the vcs representing the inductor current reaches Vcom, the switch tube is turned off, and the secondary side starts to discharge until the current IS drops to 0 and the next cycle starts. Its working cycle is:

[0023]

[0024]

[0025] T=T onp +T ons ;

[0026] It can be seen that when the output is fixed, T ons Fixed, T onp Inversely proportional to the input voltage. When the input voltage is 264Vac, T = 2.412 + 6.44 = 8.852uS; when the input voltage is 90Vac, the valley voltage is 80Vdc, T = 12.5 + 6.44 = 18.94uS. According to the input power formula, the maximum power at high voltage is:

[0027]

[0028] The conversion efficiency is η=85%, and the maximum load current Iocp is:

[0029]

[0030] The maximum power at low voltage is:

[0031]

[0032] The conversion efficiency is η=85%, and the maximum load current Iocp is:

[0033]

[0034] It can be seen from the formula that due to the different working cycles T when high and low voltage inputs occur, the maximum input power and maximum load current differ greatly, which does not meet the application requirements. Summary of the invention

[0035] The technical problem to be solved by the present invention is to provide an AC-DC power switch circuit and a chip in view of the above-mentioned defects of the prior art.

[0036] The technical solution adopted by the present invention to solve its technical problem is:

[0037] On the one hand, an AC-DC power switch circuit is constructed and applied to an SSR topology circuit to achieve that the maximum load current and the maximum power do not change with the input voltage in the BCM mode. The AC-DC power switch circuit includes:

[0038] A timing compensation circuit, used for generating a trigger start signal for triggering the start of the next switching cycle after the secondary side of the AC-DC power switch circuit completes discharge and waits for a second time period in each switching cycle when the primary side conduction time of the AC-DC power switch circuit is less than a first time period;

[0039] Among them, the first time length is the switch-on time length of the primary side switch tube in a single cycle when the SSR topology circuit operates in BCM mode at the maximum load at the valley voltage of the minimum input voltage, and the second time length is the difference between the first time length and the most recent switch-on time length.

[0040] Furthermore, in the AC-DC power switch circuit of the present invention, the timing compensation circuit includes:

[0041] A charging circuit, used for charging by using a current source controlled by a sampled voltage of an output circuit of the SSR topology circuit, and stopping charging during a secondary side discharge process;

[0042] A comparison circuit, connected to the charging circuit, configured to output a timing signal when the charging voltage of the charging circuit reaches a reference voltage;

[0043] The trigger start signal generating circuit is connected to the comparison circuit and is used for outputting the trigger start signal when receiving the timing signal and the discharge signal representing the secondary side discharge.

[0044] Further, in the AC-DC power switch circuit of the present invention, the charging circuit includes a current source controlled by a sampling voltage of the output circuit of the SSR topology circuit, a charging switch tube, a capacitor, and a charging reset tube, the comparison circuit includes a first comparator and a first inverter, and the trigger start signal generating circuit includes a first latch;

[0045] The current source, the charging switch tube, and the capacitor are connected in series to form a charging path, the charging reset tube and the capacitor are connected in parallel to form a discharging path, the opening of the charging switch tube is controlled by the discharge signal, the opening of the charging reset tube is controlled by the start-up reset signal, the start-up reset signal is a short-time pulse signal generated synchronously when the switch tube is turned on, the negative input end of the first comparator is connected to the positive electrode of the capacitor, the positive input end of the first comparator receives the reference voltage, the output end of the first comparator is connected to an input end of the first latch via the first inverter, the other input end of the first latch receives the discharge signal, and the output end of the first latch outputs the trigger start signal.

[0046] Furthermore, in the AC-DC power switch circuit of the present invention, the trigger start signal is directly used as a cycle start signal for starting the next switching cycle, or is triggered together with the valley detection signal to generate the cycle start signal.

[0047] Furthermore, in the AC-DC power switch circuit of the present invention, the AC-DC power switch circuit further includes:

[0048] The primary side inductor current valley detection circuit is used to generate a valley detection signal for triggering the next switching cycle when the sampling voltage of the secondary side reaches the set valley voltage;

[0049] The start signal generating circuit is connected to the timing compensation circuit and the primary inductor current valley detection circuit respectively, and is used to generate a cycle start signal for starting the next switching cycle when both the trigger start signal and the valley detection signal appear.

[0050] Further, in the AC-DC power switch circuit of the present invention, the primary inductor current valley detection circuit includes a second comparator, and the start-up signal generating circuit includes a NAND gate and a second inverter;

[0051] The negative input terminal of the second comparator receives the sampling voltage of the secondary side, the positive input terminal of the second comparator receives the valley voltage, the output terminal of the second comparator is connected to one input terminal of the NAND gate, the other input terminal of the NAND gate receives the trigger start signal, the output terminal of the NAND gate is connected to the input terminal of the second inverter, and the second inverter outputs the period start signal.

[0052] Furthermore, in the AC-DC power switch circuit of the present invention, the AC-DC power switch circuit further includes:

[0053] An on pulse generating circuit, used for receiving the periodic on signal, and generating a narrow pulse signal synchronized with the periodic on signal based on the periodic on signal;

[0054] A switch closing control circuit, used for outputting a period closing signal when the sampled voltage at the primary side is equal to the sampled voltage of the output circuit of the SSR topology circuit;

[0055] The switch control logic circuit is connected to the open pulse generating circuit, the switch closing control circuit and the switch tube respectively, and is used to generate a switch signal to the switch tube. Each time a narrow pulse signal is received, the switch signal turns on the switch tube once to enter a switching cycle. Each time a cycle closing signal is received, the switch signal turns off the switch tube once to end the current switching cycle.

[0056] Furthermore, in the AC-DC power switch circuit described in the present invention, the start pulse generating circuit includes a delay device, a third inverter, and an AND gate, the input end of the delay device and one input end of the AND gate respectively receive the periodic start signal, the output end of the delay device is connected to the other input end of the AND gate via the third inverter, and the output end of the AND gate outputs the narrow pulse signal.

[0057] Further, in the AC-DC power switch circuit of the present invention, the switch closing control circuit includes a third comparator, the negative input terminal of the third comparator receives the sampled voltage of the output circuit of the SSR topology circuit, the positive input terminal of the third comparator receives the sampled voltage of the primary side, and the output terminal of the third comparator outputs the period closing signal;

[0058] The switch control logic circuit includes a second latch and a buffer. Two input ends of the second latch receive the cycle closing signal and the narrow pulse signal respectively. The output end of the second latch outputs the switch signal via the buffer.

[0059] In a second aspect, an AC-DC power switch chip is constructed, which integrates the AC-DC power switch circuit as described above.

[0060] The AC-DC power switch circuit and chip of the present invention have the following beneficial effects: considering that the switch conduction time of the primary switch tube in a single cycle is the longest when the maximum load works in the BCM mode under the valley voltage of the minimum input voltage, the present invention defines this time duration as a first time duration. In each switching cycle, when the primary side conduction time of the AC-DC power switch circuit is less than the first time duration, after the secondary side of the AC-DC power switch circuit completes discharge and waits for the second time duration, a trigger start signal for triggering the next switching cycle to start is generated. The second time duration is the difference between the first time duration and the most recent switch conduction time duration. In this way, it can be ensured that each working cycle is consistent, the maximum operating frequency of the high and low voltages is the same, and the maximum load current is the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without creative work:

[0062] Figure 1 This is the traditional SSR topology AC-DC circuit block diagram;

[0063] Figure 2 This is a schematic diagram of the SSR topology working waveform in CCM mode;

[0064] Figure 3 This is a schematic diagram of the SSR topology working waveform in BCM mode;

[0065] Figure 4 It is the SSR topology working waveform in the BCM mode of the present invention;

[0066] Figure 5 is a schematic diagram of an AC-DC power switch circuit integrated into a chip according to an embodiment of the present invention;

[0067] Figure 6 is a schematic structural diagram of an AC-DC power supply switch circuit according to an embodiment of the present invention;

[0068] Figure 7 This is the schematic diagram of the reset signal tonp_leb;

[0069] Figure 8 This is the schematic diagram of the generation of the discharge signal tons;

[0070] Fig. 9 This is a working waveform diagram of an embodiment of the present invention when the input voltage is 80vdc and the operation is in the BCM mode;

[0071] Fig.10 This is a working waveform diagram of an embodiment of the present invention when the input voltage is greater than 80vdc and the operating mode is BCM. DETAILED DESCRIPTION

[0072] In view of the problem that the maximum input power and the maximum load current are greatly different due to the different working cycles when the high and low voltage inputs are in the prior art, the present invention proposes an AC-DC power switch circuit and chip. The main idea is: according to the formula Among them, F = 1 / T, Ipeak is fixed, L is fixed, as long as the operating frequency F is consistent, the maximum input power of high and low voltage can be guaranteed to be consistent. Because it works in BCM mode, the low voltage operating frequency F is much smaller than the high voltage operating frequency F, and the minimum operating frequency occurs at the valley voltage of the minimum input voltage. For example, if the minimum input voltage is 90Vac, the valley is 80Vdc, so as long as the high voltage operating frequency is designed to be consistent with the frequency of 80vdc, the high voltage works in DCM mode at this time, and the conduction time tonp_80vdc at 80Vdc is designed to be a fixed value, such as Figure 4 As shown, the on-time tonp_vin of each working cycle is compared with tonp_80vdc to make a difference. After the secondary side completes the discharge, it waits for the time tonp_80vdc-tonp_vin to start the next cycle. In this way, it can be ensured that each working cycle is consistent, the maximum operating frequency of the high and low voltages is the same, and the maximum load current is the same.

[0073] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Typical embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, rather than limitations on the technical solutions of the present application. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0074] refer to Figure 5 The AC-DC power switch circuit of the present invention can be integrated into a chip. The AC-DC power switch chip is used in an SSR topology circuit. The input voltage of the SSR topology circuit is Vin, and the output voltage is Vo. The chip includes com, demag, CS, Drain, and VCC pins. The voltage of the com pin is the sampled voltage Vcom of the output circuit of the SSR topology circuit; the voltage of the demag pin is the sampled voltage Vdemag of the secondary side sampled by the voltage divider circuit at both ends of the auxiliary winding; the voltage of the CS pin is the sampled voltage Vcs of the primary side sampled by the sampling resistor Rcs; the Drain pin is connected to the primary winding. These pins of the chip and the peripheral circuits connected thereto are the same as those in the prior art, so they will not be described in detail here. The purpose of the present invention is to achieve that the maximum load current and maximum power in the BCM mode do not change with the input voltage, such as Figure 6 As shown, the AC-DC power switch circuit of the present invention includes a timing compensation circuit 101, a primary inductor current valley detection circuit 102, an open signal generating circuit 103, an open pulse generating circuit 104, a switch closing control circuit 105, and a switch control logic circuit 106.

[0075] Among them, the timing compensation circuit 101 is used to generate a trigger start signal select for triggering the next switching cycle to start after the secondary side of the AC-DC power switch circuit completes discharge and waits for a second time in each switching cycle when the primary side conduction time of the AC-DC power switch circuit is less than a first time.

[0076] The first duration is the switch-on duration of the primary switch tube in a single cycle when the maximum load works in the BCM mode at the valley voltage of the minimum input voltage of the SSR topology circuit. For example, assuming that the minimum input voltage is 90Vac, the valley is 80Vdc, so the on time tonp_80vdc at 80Vdc is the first duration. The second duration is the difference between the first duration and the most recent switch-on duration.

[0077] Specifically, the timing compensation circuit 101 includes a charging circuit 1011, a comparison circuit 1012, and a trigger start signal generating circuit 1013. The charging circuit 1011 is used to charge using a current source Icom controlled by a sampling voltage Vcom, and stops charging during the secondary discharge process; the comparison circuit 1012 is connected to the charging circuit 1011, and is used to output a timing signal counter_b when the charging voltage vcap0 of the charging circuit 1011 reaches a reference voltage vref2; the trigger start signal generating circuit 1013 is connected to the comparison circuit 1012 and the discharge signal circuit, and is used to output the trigger start signal select when receiving the timing signal counter_b and the discharge signal tons output by the discharge signal circuit.

[0078] More specifically, the charging circuit 1011 includes a current source Icom controlled by a sampling voltage Vcom, a charging switch tube pm0, a capacitor C0, and a charging reset tube nm0, the comparison circuit 1012 includes a first comparator comp1 and a first inverter, and the trigger start signal generating circuit 1013 includes a first latch. The current source Icom, the charging switch tube pm0, and the capacitor C0 are connected in series to form a charging path, the charging reset tube nm0 and the capacitor C0 are connected in parallel to form a discharging path, the opening of the charging switch tube pm0 is controlled by the discharge signal tons, the opening of the charging reset tube nm0 is controlled by the opening reset signal tonp_leb, the negative input terminal of the first comparator comp1 is connected to the positive electrode of the capacitor C0, the positive input terminal of the first comparator comp1 receives the reference voltage vref2, the output terminal of the first comparator comp1 is connected to one input terminal of the first latch via the first inverter, the other input terminal of the first latch receives the discharge signal tons, and the output terminal of the first latch outputs the trigger start signal select.

[0079] The on-reset signal tonp_leb is a short-time pulse signal generated synchronously when the switch tube is turned on. The specific generation principle is: Figure 7 , the switch signal tonp passes through an inverter to generate a signal tonp_b, the current source Ibias1 is used to charge the capacitor C1, the switch nm1 is connected in parallel with C1, the control end of the switch nm1 is controlled by the signal tonp_b, the negative input end of the comparator comp3 is connected to the voltage vcap1 of the positive electrode of C1, the positive input end of the comparator comp3 is connected to the reference voltage Vref6, the output end of the comparator comp3 and the signal tonp are respectively input to the two input pins of the NAND gate, and the output end of the NAND gate outputs the signal tonp_leb after passing through the inverter.

[0080] It should be noted that the chip originally has a discharge signal circuit inside, which can generate a discharge signal tons according to the switch signal tonp and the voltage of the demag pin to indicate whether the secondary side has been discharged. Figure 8 As shown, the generation process of the signal tons is: the current source Ibias2 is used to charge the capacitor C2, nm2 is connected in parallel with C2, the control end of the switch nm2 is controlled by the signal tonp, the positive input end of the comparator comp6 is connected to the positive electrode of the capacitor C2, the negative input end of the comparator comp3 is connected to the reference voltage Vref5, the output end of the comparator comp6 and the signal tonp are respectively connected to the two input ends of the latch, the output end of the latch is connected to one input end of the AND gate via an inverter, the other input end of the AND gate is connected to the signal tonp_b, and the output end of the AND gate outputs the signal tons_leb, the signal valley (reference Figure 6 ) is inverted by the inverter and input to the two input ends of the NOR gate together with the signal tonp. The output end of the NOR gate and the signal tons_leb are respectively input to the two input ends of the latch. The output end of the latch outputs the signal tons via the inverter.

[0081] nm0 is an NMOS tube, pm0 is a PMOS tube, and Icom controlled by nm0, pm0, C0, and Vcom and comparator comp1 together are equivalent to a timing circuit counter. Icom is proportional to the Vcom voltage, and the counter time increases as the Vcom voltage decreases. The purpose of turning on the reset signal tonp_leb is to quickly discharge the capacitor C0 when the switch tube is turned on, reset C0, and ensure that the capacitor C0 is charged from 0 charge every time.

[0082] Theoretically, the trigger start signal select can be directly used as the cycle start signal gate_on for starting the next switching cycle. In this embodiment, the trigger start signal select is used together with the valley detection signal valley of the primary inductor current valley detection circuit 102 to be given to the primary inductor current valley detection circuit 102, thereby triggering the generation of the cycle start signal gate_on. Specifically, the primary inductor current valley detection circuit 102 is used to generate the valley detection signal valley for triggering the next switching cycle when the secondary sampling voltage Vdemag reaches the set valley voltage Vref3, and the valley voltage Vref3 is set according to experience. The start signal generating circuit 103 is connected to the timing compensation circuit 101 and the primary inductor current valley detection circuit 102 respectively, and is used to generate the cycle start signal gate_on for starting the next switching cycle when the trigger start signal select and the valley detection signal valley both appear. Because the valleys of the primary and secondary windings are synchronized, the comparator comp2 detects the valley signal through the demag pin, so that the switch tube can be turned on when the Drain end is at the valley, reducing the switch tube loss and improving efficiency.

[0083] More specifically, the primary inductor current valley detection circuit 102 includes a second comparator comp2, and the start signal generating circuit 103 includes a NAND gate and a second inverter. The negative input terminal of the second comparator comp2 receives the secondary sampling voltage Vdemag, the positive input terminal of the second comparator comp2 receives the valley voltage Vref3, the output terminal of the second comparator comp2 is connected to one input terminal of the NAND gate, the other input terminal of the NAND gate receives the trigger start signal select, the output terminal of the NAND gate is connected to the input terminal of the second inverter, and the second inverter outputs the period start signal gate_on.

[0084] Only when gate_on is at a high level can the next cycle be started. In this embodiment, after the cycle start signal gate_on is generated, the start pulse generating circuit 104 receives the cycle start signal gate_on, and generates a narrow pulse signal synchronized with the cycle start signal gate_on based on the cycle start signal gate_on. On the other hand, the switch closing control circuit 105 outputs a cycle closing signal gate_off when the sampling voltage Vcs of the primary side is equal to the sampling voltage Vcom, and the switch control logic circuit 106 is connected to the start pulse generating circuit 104, the switch closing control circuit 105, and the switch tube, respectively. The switch control logic circuit 106 is used to generate a switch signal tonp to the switch tube. When each narrow pulse signal is received, the switch signal tonp turns on the switch tube once to enter a switch cycle, and when each cycle closing signal gate_off is received, the switch signal tonp turns off the switch tube once to end the current switch cycle.

[0085] More specifically, the on pulse generating circuit 104 includes a delayer, a third inverter, and an AND gate. In this embodiment, the delayer specifically has a delay of 200ns. The input end of the delayer and one input end of the AND gate receive the period on signal gate_on respectively. The output end of the delayer is connected to the other input end of the AND gate via the third inverter, and the output end of the AND gate outputs the narrow pulse signal. The switch closing control circuit 105 includes a third comparator comp4, the negative input end of the third comparator comp4 receives the sampling voltage Vcom, the positive input end of the third comparator comp4 receives the primary sampling voltage Vcs, and the output end of the third comparator comp4 outputs the period off signal gate_off; the switch control logic circuit 106 includes a second latch and a buffer, the two input ends of the second latch receive the period off signal gate_off and the narrow pulse signal respectively, and the output end of the second latch outputs the switch signal tonp via the buffer.

[0086] Combination Figure 5-6 , the working principle of this embodiment is:

[0087] At the beginning of a switching cycle, the reset signal tonp_leb is turned on to quickly reduce vcap0 to 0. When working at maximum load, Vcom is the highest and Icom is the largest. The time for vcap0 to continue to rise from 0 to vref2 is recorded as tcounter. This value is designed to be equal to the on-time Tonp when working in BCM at maximum load at 80Vdc.

[0088] When Vin is equal to 80vdc, the conduction time is equal to tcounter. When Vdemag is detected to be less than vref3, the valley signal is high, gate_on becomes high, and the next cycle is started. At this time, it works in BCM mode. Its working waveform is as follows Fig. 9 When the input voltage is 80vdc, Tonp = tcounter, so the switching period at this time is T 80vdc =t counter +T ons .

[0089] When Vin is greater than 80vdc, the conduction time is less than tcounter, and M0 conducts t 1 time, the secondary side starts to discharge after the conduction is completed. At this time, the voltage vcap1 stops charging after the switch tube M0 is turned on. When the secondary side discharge is completed, vcap1 continues to charge for a period of time t2 until counter becomes low level. When Vdemag is less than vref3, the valley signal is high level, gate_on becomes high, and the next cycle is started. At this time, it works in DCM mode. Its working waveform is as follows Fig.10 As shown. At this time, the working cycle is T vin =t 1 +T ons +t 2 , since the voltage vcap1 on C0 remains unchanged in the Tons stage until Tons becomes low and continues to charge, Icom and vref2 remain unchanged until the counter signal becomes low, so t 1 +t 2 =t counter , so the switching period at this time is T vin =t 1 +t ons +t 2 =t counter +t ons =T 80vdc , consistent with the 80vdc duty cycle. According to the formula T is equal, so the maximum input power is equal, and the maximum load current Iocp is also the same. It can be seen that the circuit structure of this embodiment is simple and easy to implement. Of course, it can be understood that when the load current is reduced, Vcom decreases, the on-time decreases, Icom decreases, and tcounter increases, all of which work in DCM mode.

[0090] In summary, the AC-DC power switch circuit and chip of the present invention have the following beneficial effects: considering that the switch on time of the primary switch tube in a single cycle is the longest when the maximum load works in the BCM mode under the valley voltage of the minimum input voltage, the present invention defines this time as the first time. In each switching cycle, when the primary side conduction time of the AC-DC power switch circuit is less than the first time, after the secondary side of the AC-DC power switch circuit completes the discharge and waits for the second time, a trigger start signal for triggering the next switching cycle to start is generated. The second time is the difference between the first time and the most recent switch on time. In this way, it can be ensured that each working cycle is consistent, the high and low voltage maximum operating frequencies are the same, and the maximum load currents are the same.

[0091] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0092] Terms including ordinal numbers such as "first" and "second" used in this specification may be used to describe various components, but these components are not limited by these terms. The purpose of using these terms is only to distinguish one component from other components. For example, without departing from the scope of the present invention, the first component may be named as the second component, and similarly, the second component may also be named as the first component.

[0093] The words "equal", "same", "simultaneous" or other similar terms are not limited to absolute equality or sameness in mathematical terms. When implementing the rights described in this patent, they can be close in the engineering sense or within an acceptable error range. The "connected" or "connected" mentioned above not only includes directly connecting two entities, but also indirectly connecting through other entities with beneficial improvement effects.

[0094] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. An AC-DC power switch circuit, applied to an SSR topology circuit, for realizing that the maximum load current and the maximum power in the BCM mode do not change with the input voltage, characterized in that: The AC-DC power switch circuit comprises: A timing compensation circuit (101) is used for, in each switching cycle, when the primary side conduction time of the AC-DC power switch circuit is less than a first time length, generating a trigger start signal (select) for triggering the start of the next switching cycle after the secondary side of the AC-DC power switch circuit completes discharge and waits for a second time length; Among them, the first time length is the switch-on time length of the primary side switch tube in a single cycle when the SSR topology circuit operates in BCM mode at the maximum load at the valley voltage of the minimum input voltage, and the second time length is the difference between the first time length and the most recent switch-on time length.

2. The AC-DC power switch circuit according to claim 1, characterized in that: The timing compensation circuit (101) comprises: A charging circuit (1011) is used for charging using a current source (Icom) controlled by a sampling voltage (Vcom) of an output circuit of the SSR topology circuit, and stopping charging during a secondary side discharge process; A comparison circuit (1012), connected to the charging circuit (1011), configured to output a timing signal (counter_b) when a charging voltage (vcap0) of the charging circuit (1011) reaches a reference voltage (vref2); The trigger start signal generating circuit (1013) is connected to the comparison circuit (1012) and is used to output the trigger start signal (select) when receiving the timing signal (counter_b) and the discharge signal (tons) representing the secondary discharge.

3. The AC-DC power switch circuit according to claim 2, characterized in that: The charging circuit (1011) comprises a current source (Icom) controlled by a sampling voltage (Vcom) of an output circuit of the SSR topology circuit, a charging switch tube (pm0), a capacitor (C0), and a charging reset tube (nm0); the comparison circuit (1012) comprises a first comparator (comp1) and a first inverter; and the trigger start signal generating circuit (1013) comprises a first latch; The current source (Icom), the charging switch tube (pm0), and the capacitor (C0) are connected in series to form a charging path, the charging reset tube (nm0) and the capacitor (C0) are connected in parallel to form a discharging path, the opening of the charging switch tube (pm0) is controlled by the discharge signal (tons), the opening of the charging reset tube (nm0) is controlled by the start reset signal (tonp_leb), the start reset signal (tonp_leb) is a short-time pulse signal generated synchronously when the switch tube is turned on, the negative input end of the first comparator (comp1) is connected to the positive electrode of the capacitor (C0), the positive input end of the first comparator (comp1) receives the reference voltage (vref2), the output end of the first comparator (comp1) is connected to one input end of the first latch via the first inverter, the other input end of the first latch receives the discharge signal (tons), and the output end of the first latch outputs the trigger start signal (select).

4. The AC-DC power switch circuit according to claim 1, characterized in that: The trigger start signal (select) is directly used as a cycle start signal (gate_on) for starting the next switching cycle, or is triggered together with a valley detection signal (valley) to generate the cycle start signal (gate_on).

5. The AC-DC power switch circuit according to claim 4, characterized in that: The AC-DC power switch circuit further includes: A primary side inductor current valley detection circuit (102), used for generating a valley detection signal (valley) for triggering the next switching cycle when the secondary side sampling voltage (Vdemag) reaches a set valley voltage (Vref3); The start signal generating circuit (103) is connected to the timing compensation circuit (101) and the primary inductor current valley detection circuit (102) respectively, and is used to generate a cycle start signal (gate_on) for starting the next switching cycle when both the trigger start signal (select) and the valley detection signal (valley) appear.

6. The AC-DC power switch circuit according to claim 5, characterized in that: The primary inductor current valley value detection circuit (102) comprises a second comparator (comp2), and the start-up signal generation circuit (103) comprises a NAND gate and a second inverter; The negative input terminal of the second comparator (comp2) receives the sampling voltage (Vdemag) of the secondary side, the positive input terminal of the second comparator (comp2) receives the valley voltage (Vref3), the output terminal of the second comparator (comp2) is connected to one input terminal of the NAND gate, the other input terminal of the NAND gate receives the trigger start signal (select), the output terminal of the NAND gate is connected to the input terminal of the second inverter, and the second inverter outputs the period start signal (gate_on).

7. The AC-DC power switch circuit according to claim 2, characterized in that: The AC-DC power switch circuit further includes: An on pulse generating circuit (104), configured to receive the periodic on signal (gate_on), and generate a narrow pulse signal synchronized with the periodic on signal (gate_on); A switch closing control circuit (105) is used to output a period closing signal (gate_off) when the sampling voltage (Vcs) of the primary side is equal to the sampling voltage (Vcom) of the output circuit of the SSR topology circuit; The switch control logic circuit (106) is connected to the on pulse generating circuit (104), the switch off control circuit (105), and the switch tube, respectively, and is used to generate a switch signal (tonp) for the switch tube, wherein the switch signal (tonp) turns on the switch tube once to enter a switch cycle each time the narrow pulse signal is received, and the switch signal (tonp) turns off the switch tube once to end the current switch cycle each time the cycle off signal (gate_off) is received.

8. The AC-DC power switch circuit according to claim 7, characterized in that: The on-pulse generating circuit (104) comprises a delay device, a third inverter, and an AND gate, wherein an input end of the delay device and an input end of the AND gate respectively receive the periodic on-signal (gate_on), an output end of the delay device is connected to another input end of the AND gate via the third inverter, and an output end of the AND gate outputs the narrow pulse signal.

9. The AC-DC power switch circuit according to claim 7, characterized in that: The switch closing control circuit (105) comprises a third comparator (comp4), a negative input terminal of the third comparator (comp4) receives a sampled voltage (Vcom) of the output circuit of the SSR topology circuit, a positive input terminal of the third comparator (comp4) receives a sampled voltage (Vcs) of the primary side, and an output terminal of the third comparator (comp4) outputs the period closing signal (gate_off); The switch control logic circuit (106) comprises a second latch and a buffer, wherein two input ends of the second latch receive the period off signal (gate_off) and the narrow pulse signal respectively, and the output end of the second latch outputs the switch signal (tonp) via the buffer.

10. An AC-DC power switch chip, characterized in that: An AC-DC power switch circuit as described in any one of claims 1 to 9 is integrated inside.

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