Digital pre-distortion circuit and method for reducing clipping noise in digital pre-distortion circuit

Abstract

The invention provides a digital pre-distortion circuit and a method for reducing amplitude limiting noise in the digital pre-distortion circuit. The digital pre-distortion circuit comprises a pre-distorter, amplitude limiting logic, an error extraction circuit, a filter and a compensation circuit. The predistorter performs predistortion operation according to an input signal to generate an initial predistortion signal, and the amplitude limiting logic limits the amplitude of the initial predistortion signal to generate an amplitude-limited predistortion signal. In addition, an error extraction circuit calculates a difference between the initial predistortion signal and the clipping predistortion signal to generate a clipping error signal, and the filter filters the clipping error signal to generate a filtered error signal, wherein the compensation circuit compensates the amplitude limiting predistortion signal according to the filtered error signal so as to generate an output signal.

Description

Technical Field

[0001] The present invention relates to digital predistortion, and in particular to a digital predistortion circuit and a method for reducing limiting noise in the digital predistortion circuit. Background Art

[0002] Today's wireless transmission devices typically have RF power amplifiers, and the RF power amplifiers are used to amplify the transmission signal in order to offset the energy loss during the transmission process. However, the RF power amplifier is a nonlinear component. Especially when the transmission signal has a high peak-to-average power ratio, the transmission signal will produce severe in-band signal distortion after being processed by the RF power amplifier, thereby reducing the signal quality. At the same time, it will also cause out-of-band energy leakage and interfere with adjacent channels.

[0003] In order to avoid the above problems, the wireless transmission device can perform digital pre-distortion (DPD) processing on the transmission signal before sending it to the power amplifier. However, when the digital pre-distortion processing is performed on a signal with a large amplitude, it will cause the generation of additional noise. When the additional noise is modulated into a radio frequency signal through direct up-conversion, it will form an interference signal outside the frequency band, thereby affecting the transmission of adjacent channels.

[0004] Therefore, a novel method and related architecture are needed to solve the problems of the related art without side effects or with less side effects. Summary of the invention

[0005] The object of the present invention is to provide a digital predistortion circuit and a method for reducing limiting noise in the digital predistortion circuit, so as to reduce the interference of an anti-intermodulation distortion signal in a signal output by a wireless transmission device on an adjacent channel.

[0006] At least one embodiment of the present invention provides a digital predistortion circuit, which includes a predistorter, a limiting logic, an error extraction circuit, a filter, and a compensation circuit, wherein the limiting logic is coupled to the predistorter, the error extraction circuit is coupled to the predistorter and the limiting logic, the filter is coupled to the error extraction circuit, and the compensation circuit is coupled to the limiting logic and the filter. Specifically, the predistorter can perform a predistortion operation according to an input signal to generate an initial predistortion signal, and the limiting logic can limit at least a portion of the amplitude of the initial predistortion signal that exceeds a predetermined range to an upper limit or a lower limit of the predetermined range to generate a limited predistortion signal. In addition, the error extraction circuit can calculate the difference between the initial predistortion signal and the limited predistortion signal to generate a limited error signal, and the filter can filter the limited error signal to generate a filtered error signal, wherein the compensation circuit can compensate the limited predistortion signal according to the filtered error signal to generate an output signal.

[0007] At least one embodiment of the present invention provides a method for reducing clipping noise in a digital predistortion circuit. The method includes: using a predistorter of the digital predistortion circuit to perform a predistortion operation according to an input signal to generate an initial predistortion signal; using a clipping logic of the digital predistortion circuit to adjust the amplitude of the initial predistortion signal beyond the upper or lower bound of at least a portion of a predetermined range to generate a clipping predistortion signal; using an error extraction circuit of the digital predistortion circuit to calculate the difference between the initial predistortion signal and the clipping predistortion signal to generate a clipping error signal; using a filter of the digital predistortion circuit to filter the clipping error signal to generate a filtered error signal; and using a compensation circuit of the digital predistortion circuit to compensate the clipping predistortion signal according to the filtered error signal to generate an output signal.

[0008] The digital predistortion circuit and method provided by the embodiments of the present invention can transmit the noise generated by signal limiting to the filter for processing, so as to extract the components of a specific frequency band, and then fill the filtered result back into the limiting predistortion signal. Although the noise within the signal frequency band cannot be completely eliminated from the final output signal, the noise outside the frequency band can be effectively reduced, thereby avoiding the interference of the anti-intermodulation distortion signal on the adjacent channels. In addition, the embodiments of the present invention will not significantly increase the additional cost. Therefore, the present invention can solve the problems of the related art without side effects or with less side effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a wireless communication device according to an embodiment of the present invention.

[0010] Figure 2is a schematic diagram of a digital pre-distortion circuit according to an embodiment of the present invention.

[0011] Figure 3 According to an embodiment of the present invention Figure 2 Schematic diagram of the spectrum of some signals in the digital pre-distortion circuit shown.

[0012] Figure 4 According to an embodiment of the present invention Figure 2 Schematic diagram of the initial predistortion signal in the digital predistortion circuit shown.

[0013] Figure 5 According to an embodiment of the present invention Figure 2 Schematic diagram of the limiting predistortion signal in the digital predistortion circuit shown.

[0014] Figure 6 According to an embodiment of the present invention Figure 2 Schematic diagram of the limiting error signal in the digital pre-distortion circuit shown.

[0015] Figure 7 According to an embodiment of the present invention Figure 2 Schematic diagram of the spectrum of the limiting error signal in the digital pre-distortion circuit shown.

[0016] Figure 8 According to an embodiment of the present invention Figure 2 Schematic diagram of the filtered error signal in the digital pre-distortion circuit shown.

[0017] Fig. 9 According to an embodiment of the present invention Figure 2 Schematic diagram of the spectrum of the error signal after filtering in the digital pre-distortion circuit shown.

[0018] Fig.10 It is a schematic diagram of a working process of a method for reducing limiting noise in a digital pre-distortion circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] Figure 1 FIG. 1 is a schematic diagram of a wireless communication device 10 (eg, a Wi-Fi system) according to an embodiment of the present invention. Figure 1 As shown, the wireless communication device 10 may include a digital signal processing (DSP) circuit 50, digital to analog converters 51 and 54 (in Figure 1 denoted as "D / A" for simplicity), low pass filters 52 and 55 (in Figure 1The wireless communication device 10 includes a digital signal processing circuit 50, which includes a digital signal processing circuit 50 and a digital signal processing circuit 51. The digital signal processing circuit 50 includes a digital signal processing circuit 51 and a digital signal processing circuit 52. The digital signal processing circuit 51 includes a digital signal processing circuit 52 and a digital signal processing circuit 53. Figure 1 The digital signal processing circuit 50 outputs a digital baseband / intermediate frequency signal, which is then converted from digital to analog by digital-to-analog converters 51 and 54 to generate analog baseband / intermediate frequency signals. Finally, the analog baseband / intermediate frequency signals on the respective channels are converted from digital to analog by digital-to-analog converters 51 and 54 to generate analog baseband / intermediate frequency signals. Finally, the analog baseband / intermediate frequency signals on the respective channels are converted from digital to analog by upconverters 53 and 56 according to the local oscillator signals output by the local oscillator 57 to generate analog RF signals.

[0020] In order to offset the nonlinear distortion generated by the RF power amplifier 59, the digital signal processing circuit 50 may have a related digital predistortion processing operation, wherein the digital predistortion processing may be implemented according to the inverse function of the RF power amplifier 59, for example, the digital input signal is predistorted based on the inverse function corresponding to the nonlinear behavior of the RF power amplifier 59, so that the operation of the digital predistortion processing and the nonlinear distortion of the RF power amplifier 59 offset each other, thereby obtaining an output signal with good linearity. However, the digital predistortion signal generated by the predistortion processing has a limited range of values ​​that can be represented (for example, when the digital predistortion signal is implemented with an 8-bit digital code, the digital predistortion signal can represent a range of values ​​of 00000000 to 11111111). When the amplitude of the digital input signal is too large and the digital predistortion signal generated by the inverse function operation has a peak value that exceeds the representable value range (for example, lower than 00000000 or greater than 11111111), the digital predistortion signal will be hard clipped, for example, the portion that exceeds the value range is clipped to its maximum representable value such as 11111111 or the minimum representable value such as 00000000, thereby generating clipping noise. Spectral analysis is performed on the result of the hard clipping, and the digital predistortion signal after clipping will have odd-order harmonics such as third-order harmonics, fifth-order harmonics, and seventh-order harmonics. If the I / Q channel signals with these odd harmonics are modulated into RF signals through direct up-conversion without any other processing, counter intermodulation (CIM) distortion signals such as third-order CIM (CIM3) and fifth-order CIM (CIM5) will appear. In particular, when using Orthogonal Frequency Division Multiple Access (OFDMA) technology, the channels can be grouped into multiple sub-channels such as data units (RU). Since any data unit only occupies a part of the bandwidth, the above-mentioned counter intermodulation distortion signals are more likely to appear out of band and interfere with adjacent channels.

[0021] In this embodiment, the wireless communication device 10 may further include a digital pre-distortion circuit 100, wherein the digital pre-distortion circuit 100 may be disposed in the digital signal processing circuit 50, but the present invention is not limited thereto. In particular, the digital pre-distortion circuit 100 may provide a corresponding inverse function for digital pre-distortion processing based on the estimation result of the nonlinear distortion of the RF power amplifier 59, and may further provide a corresponding mechanism to eliminate or reduce the influence of the above-mentioned limiting noise.

[0022] Figure 2 is a schematic diagram of a digital predistortion circuit 100 according to an embodiment of the present invention. Figure 2 As shown, the digital predistortion circuit 100 may include a signal scaling circuit 110, a predistorter such as a digital predistorter 120, a limiting logic 130, an error extraction circuit 140, a filter such as a high pass filter 150 (in Figure 2 The digital predistorter 120 is coupled to the signal scaling circuit 110, the limiting logic 130 is coupled to the digital predistorter 120, the error extraction circuit 140 is coupled to the digital predistorter 120 and the limiting logic 130, the high pass filter 150 is coupled to the error extraction circuit 140, and the compensation circuit 160 is coupled to the limiting logic 130 and the high pass filter 150.

[0023] In the present embodiment, the digital predistorter 120 may perform a predistortion operation based on the input signal D0 to generate an initial predistortion signal D2, wherein the predistortion operation is performed based on an estimation result pwsf of the nonlinear distortion of the RF power amplifier 59. For example, the signal scaling circuit 110 may reduce the amplitude of the input signal D0 based on the scaling ratio GS to generate the scaled signal D1. The digital predistorter 120 may perform the predistortion operation on the scaled signal D1 to generate the initial predistortion signal D2. In some embodiments, the signal scaling circuit 110 may be omitted, for example, the digital predistorter 120 may perform the predistortion operation on the input signal D0 to generate the initial predistortion signal D2 without reducing the amplitude of the input signal D0, but the present invention is not limited thereto.

[0024] In this embodiment, the clipping logic 130 may clip at least a portion of the amplitude of the initial predistortion signal D2 that exceeds a predetermined range to an upper limit or a lower limit of the predetermined range to generate a clipping predistortion signal D3. In addition, the error extraction circuit 140 may calculate the difference between the initial predistortion signal D2 and the clipping predistortion signal D3 to generate a clipping error signal D4, wherein the clipping error signal D4 may be regarded as an example of the clipping noise mentioned above. The high-pass filter 150 may filter the clipping error signal D4 (e.g., high-pass filtering) to generate a filtered error signal D5, wherein the filtered error signal D5 may be regarded as a component of a specific frequency band (e.g., an out-of-band component such as a high-frequency component) in the clipping noise generated by the operation of the clipping logic 130. The compensation circuit 160 may compensate the clipping predistortion signal D3 according to the filtered error signal D5 to generate an output signal D6, wherein the out-of-band clipping noise in the output signal D6 may be effectively eliminated or reduced.

[0025] In this embodiment, the initial predistortion signal D2 may be an initial digital predistortion signal, and the upper limit or the lower limit of the predetermined range is determined according to the maximum digital value (e.g., all bits of the initial digital predistortion signal are 1) or the minimum digital value (e.g., all bits of the initial digital predistortion signal are 0) of the initial digital predistortion signal. In addition, the error extraction circuit 140 may be a subtractor to subtract the limited predistortion signal D3 from the initial predistortion signal D2 to generate the limited error signal D4, and the compensation circuit 160 may be an adder to add the filtered error signal D5 to the limited predistortion signal D3 to generate the output signal D6. In some embodiments, the error extraction circuit 140 may generate the limited error signal D4 by subtracting the initial predistortion signal D2 from the limited predistortion signal D3, and the compensation circuit 160 may be implemented by replacing the subtractor to generate the output signal D6 by subtracting the filtered error signal D5 from the limited predistortion signal D3, but the present invention is not limited thereto. As long as the out-of-band components of the clipping noise in the clipping predistortion signal D3 are eliminated or reduced when generating the output signal D6, the implementation of the operational details of the error extraction circuit (such as the subtractor 140) and the compensation circuit (such as the adder 160) may be varied.

[0026] Figure 3 According to an embodiment of the present invention Figure 2 FIG. 1 is a schematic diagram of the spectrum of some signals in the digital predistortion circuit 100, such as the initial predistortion signal D2, the limited predistortion signal D3, and the output signal D6. Figure 3 As shown, since the initial predistortion signal D2 has not been limited, there is no limiting noise in it. After being processed by the limiting logic 130, limiting noise can be observed outside the frequency band (for example, the frequency band of 50MHz to 150MHz) of the limited predistortion signal D3. Through the limiting noise reduction mechanism of the present invention, the output signal D6 can eliminate the limiting noise outside the frequency band under ideal conditions, so that the signal quality outside the frequency band is consistent with the initial predistortion signal D2 that has not been limited. However, in practice, the output signal D6 may still have a signal amplitude that exceeds the range at certain time points, so the limiting noise outside the frequency band cannot be perfectly eliminated. However, according to Figure 3 The results shown show that compared with directly outputting the limited pre-distortion signal D3 , the clipping noise of the output signal D6 can be greatly reduced.

[0027] Figure 4 According to an embodiment of the present invention Figure 2Schematic diagram of the initial predistortion signal D2 in the digital predistortion circuit 100 shown in FIG. 1 , wherein the amplitudes “1” and “−1” may represent the maximum representable value and the minimum representable value of the digital signal output by the limit logic 130. Therefore, the limit logic 130 may limit the signal samples greater than “1” in the initial predistortion signal D2 to “1”, and limit the signal samples less than “−1” in the initial predistortion signal D2 to “−1”, so as to generate a limited predistortion signal D3, as shown in FIG. Figure 5 As shown. Figure 4 In the embodiment, the sample index is (3×10 5 ), it can be observed that the initial predistortion signal D2 has signal samples beyond the above range, so Figure 6 The sample index is (3×10 5 ) can be observed near the error extraction circuit, such as a non-zero signal sample of the limiting error signal D4 output by the subtractor 140.

[0028] Figure 7 According to an embodiment of the present invention Figure 2 FIG. 1 is a schematic diagram of a frequency spectrum of a clipping error signal D4 in the digital pre-distortion circuit 100 , wherein the frequency spectrum of the clipping error signal D4 can be regarded as an example of a frequency spectrum of clipping noise generated by the clipping logic 130 . Figure 8 According to an embodiment of the present invention Figure 2 FIG. 1 is a schematic diagram of a filtered error signal D5 in the digital predistortion circuit 100 shown in FIG. Fig. 9 According to an embodiment of the present invention Figure 2 FIG. 1 is a schematic diagram of the spectrum of the filtered error signal D5 in the digital predistortion circuit 100. Figure 8 As shown, after being processed by the high-pass filter 150, the components in a specific frequency band in the error signal D5 after filtering are suppressed or reduced, so compared with Figure 6 The amplitude of the error signal D5 after filtering is reduced. Figure 7 The spectrum of the limiting error signal D4 is shown as Fig. 9 The in-band components (i.e., in-band limiting noise) in the spectrum of the filtered error signal D5 are eliminated or reduced, while the out-of-band components (i.e., out-of-band limiting noise) in the spectrum of the filtered error signal D5 are retained to offset or reduce the out-of-band limiting noise in the limiting predistortion signal D3.

[0029] Fig.10 According to an embodiment of the present invention, a method for implementing a digital predistortion circuit (eg Figure 2 FIG. 1 is a schematic diagram of the working process of the method for reducing limiting noise in the digital predistortion circuit 100 shown in FIG. 1 . It should be noted that Fig.10The embodiments shown are for illustrative purposes only and are not intended to limit the present invention. For example, one or more steps may be Fig.10 The steps may be added, deleted, or modified from the workflow shown. In addition, the steps do not necessarily need to be followed exactly to achieve the same result. Fig.10 Execute in the order shown.

[0030] In step S110 , the digital predistortion circuit may utilize the predistorter therein to perform a predistortion operation according to the input signal to generate an initial predistortion signal.

[0031] In step S120, the digital predistortion circuit may use the limiting logic therein to limit at least a portion of the amplitude of the initial predistortion signal that exceeds a predetermined range to an upper limit or a lower limit of the predetermined range, so as to generate a limited predistortion signal.

[0032] In step S130 , the digital pre-distortion circuit may utilize an error extraction circuit therein to calculate a difference between the initial pre-distortion signal and the limited pre-distortion signal to generate a limiting error signal.

[0033] In step S140 , the digital pre-distortion circuit may filter the clipping error signal using a filter therein to generate a filtered error signal.

[0034] In step S150 , the digital pre-distortion circuit may utilize the internal compensation circuit to compensate the limited pre-distortion signal according to the filtered error signal to generate an output signal.

[0035] It should be noted that the higher the scaling ratio GS of the signal scaling circuit 110, the smaller the amplitude of the scaled signal D1 transmitted to the digital predistorter 120 is reduced. In some embodiments, the limited predistortion signal D3 output by the limiting logic 130 can be used as the output signal of the digital predistortion circuit 100 and transmitted to the digital-to-analog converter 51 or 54 for subsequent processing, wherein the signal scaling circuit 110 needs to increase the scaling ratio GS to ensure that the amplitude of the signal received and output by the digital predistorter 120 is small enough to avoid excessive limiting noise generated by the operation of the limiting logic 130, thereby solving the above-mentioned inter-channel interference caused by the limiting noise. However, if the scaling ratio GS of the signal scaling circuit 110 is increased (i.e., the amplitude of the signal received and output by the digital predistorter 120 is reduced), the gain of the back-end RF power amplifier 59 needs to be increased, which will greatly increase the complexity and cost of implementing the RF power amplifier 59. Compared to directly outputting the limited predistortion signal D3, the output signal D6 generated by the error extraction circuit 140, the high-pass filter 150 and the compensation circuit 160 of the present invention can have lower out-of-band limiting noise. Therefore, if the output signal D6 is transmitted to the digital-to-analog converter 51 or 54 for subsequent processing, the scaling ratio GS of the signal scaling circuit 110 can be reduced (that is, the amplitude of the signal received and output by the digital predistorter 120 can be increased), and the complexity and cost of implementing the RF power amplifier 59 can be effectively reduced.

[0036] In some embodiments, the clipping predistortion signal D3 output by the clipping logic 130 may be sent to a low-pass filter to eliminate or reduce out-of-band clipping noise therein, and the output of the low-pass filter is sent to the digital-to-analog converter 51 or 54 for subsequent processing. Compared to the low-pass filter, which needs to process a signal with a full dynamic range (signal amplitude varies between "1" and "-1", such as Figure 5 The high-pass filter 150 of the present invention processes the difference between the initial predistortion signal D2 and the limited predistortion signal D3, such as the limited error signal D4. Due to the signal dynamic range of the limited error signal D4 (the signal amplitude varies between "0.5" and "-0.5", such as Figure 6 The signal dynamic range of the limited predistortion signal D3 is smaller than that of the limited predistortion signal D3, so the complexity and cost of implementing the high-pass filter 150 can be smaller than that of the above-mentioned low-pass filter.

[0037] In summary, the digital pre-distortion circuit provided by the embodiment of the present invention can effectively eliminate or reduce the out-of-band limiting noise by utilizing the error extraction, filtering and compensation operations therein, thereby avoiding interference with the signals of adjacent channels. In addition, the embodiment of the present invention will not significantly increase the additional cost. Therefore, the present invention can solve the problems of the related art without side effects or with less side effects. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention should be within the scope of the present invention.

[0038]

Explanation of symbols

[0039] 10: Wireless communication device

[0040] 50: Digital signal processing circuit

[0041] 51,54: Digital to Analog Converter

[0042] 52,55: Low pass filter

[0043] 53,56: Upconverter

[0044] 57: Local Oscillator

[0045] 58: Signal Synthesizer

[0046] 59: RF Power Amplifier

[0047] 60: Antenna

[0048] 100: Digital Pre-Distortion Circuit

[0049] 110: Signal scaling circuit

[0050] 120: Digital Predistorter

[0051] 130: Limiting Logic

[0052] 140: Error extraction circuit

[0053] 150: High pass filter

[0054] 160: Compensation circuit

[0055] D0: Input signal

[0056] D1: scaled signal

[0057] D2: Initial predistortion signal

[0058] D3: Limiting predistortion signal

[0059] D4: Limiting error signal

[0060] D5: Error signal after filtering

[0061] D6: Output signal

[0062] GS: Scale ratio

[0063] pwsf: estimation results

[0064] S110~S150: Steps

Claims

1. A digital predistortion circuit, comprising: A predistorter, used for performing a predistortion operation according to an input signal to generate an initial predistortion signal; A limiting logic, coupled to the predistorter, for limiting at least a portion of the amplitude of the initial predistortion signal that exceeds a predetermined range to an upper limit or a lower limit of the predetermined range to generate a limited predistortion signal; an error extraction circuit, coupled to the predistorter and the clipping logic, for calculating a difference between the initial predistortion signal and the clipped predistortion signal to generate a clipping error signal; a filter, coupled to the error extraction circuit, for filtering the amplitude-limited error signal to generate a filtered error signal; as well as The compensation circuit is coupled to the amplitude limiting logic and the filter, and is used for compensating the amplitude limiting predistortion signal according to the filtered error signal to generate an output signal. 2 . The digital predistortion circuit as claimed in claim 1 , wherein the filter is a high-pass filter for performing high-pass filtering on the clipped error signal to generate the filtered error signal. 3 . The digital predistortion circuit of claim 1 , wherein the initial predistortion signal is an initial digital predistortion signal, and the upper limit or the lower limit of the predetermined range is determined according to a maximum digital value or a minimum digital value of the initial digital predistortion signal.

4. The digital predistortion circuit according to claim 1, further comprising: A signal scaling circuit, coupled to the predistorter, for reducing the amplitude of the input signal to generate a scaled signal; The predistorter is used to perform the predistortion operation on the scaled signal to generate the initial predistortion signal.

5. The digital predistortion circuit of claim 1 , wherein the error extraction circuit is a subtractor to subtract the limited predistortion signal from the initial predistortion signal to generate the limited error signal, and the compensation circuit is an adder to add the filtered error signal to the limited predistortion signal to generate the output signal.

6. A method for reducing clipping noise in a digital predistortion circuit, comprising: Utilizing the predistorter of the digital predistortion circuit to perform predistortion operation according to the input signal to generate an initial predistortion signal; Using the limiting logic of the digital predistortion circuit to limit at least a portion of the amplitude of the initial predistortion signal that exceeds a predetermined range to an upper limit or a lower limit of the predetermined range, so as to generate a limited predistortion signal; Utilizing the error extraction circuit of the digital predistortion circuit to calculate the difference between the initial predistortion signal and the limited predistortion signal to generate a limited error signal; Filtering the amplitude limiting error signal using a filter of the digital predistortion circuit to generate a filtered error signal; as well as The compensation circuit of the digital predistortion circuit is used to compensate the amplitude limiting predistortion signal according to the filtered error signal to generate an output signal.

7. The method of claim 6, wherein filtering the clipping error signal using the filter of the digital predistortion circuit to generate the filtered error signal comprises: The amplitude-limited error signal is high-pass filtered using a high-pass filter to generate the filtered error signal. 8 . The method of claim 6 , wherein the initial predistortion signal is an initial digital predistortion signal, and the upper limit or the lower limit of the predetermined range is determined according to a maximum digital value or a minimum digital value of the initial digital predistortion signal.

9. The method of claim 6, further comprising: Using the signal scaling circuit of the digital predistortion circuit to reduce the amplitude of the input signal to generate a scaled signal; The predistorter of the digital predistortion circuit performs the predistortion operation according to the input signal to generate the initial predistortion signal, comprising: The digital predistortion circuit is used to perform the predistortion operation on the scaled signal to generate the initial predistortion signal.

10. The method of claim 6, wherein calculating the difference between the initial predistortion signal and the limited predistortion signal using the error extraction circuit of the digital predistortion circuit to generate the limited error signal comprises: subtracting the limited predistortion signal from the initial predistortion signal using a subtractor to generate the limited error signal, and The method of using the compensation circuit of the digital predistortion circuit to compensate the limited predistortion signal according to the filtered error signal to generate the output signal includes: The limited predistortion signal is added to the filtered error signal by an adder to generate the output signal.

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