Circuit and communication system

Abstract

The invention provides a circuit capable of realizing stable operation and a communication system. A circuit, which is an AC-coupled circuit, includes: a receiving circuit having a first input terminal to which a first signal transmitted via a first capacitive element is input, and a second input terminal to which a second signal transmitted via a second capacitive element is input, the second signal having a potential that changes complementarily with respect to the first signal, a first logic signal corresponding to the potential of the first signal and a second logic signal corresponding to the potential of the second signal are output; and a signal supply circuit that supplies, to the first input terminal, a first assurance signal having a potential corresponding to the value of the first logic signal as a signal for assuring the potential of the first signal, and supplies, to the second input terminal, a second assurance signal having a potential that changes complementarily with the first assurance signal as a signal for assuring the potential of the second signal.

Description

Technical Field

[0001] The present disclosure relates to a circuit and a communication system. Background Art

[0002] Patent document 1 discloses a receiving circuit that receives data using a balanced signal, that is, a differential signal, transmitted by an alternating current (AC) coupling method (see Patent document 1). Figure 4 ).

[0003] [Prior art literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Publication No. 2001-503182 Summary of the invention

[0006] [Problems to be solved by the invention]

[0007] Here, in the AC coupling method, a capacitor element that removes DC signals is configured in the transmission path. Therefore, while the data input to the receiving circuit continues to change, the capacitor element is repeatedly charged and discharged, and the potential of the two signals included in the differential signal that change complementarily to each other changes to the H level or L level. Therefore, the receiving circuit can operate normally according to the differential signal.

[0008] However, if the input data does not change within a certain period of time, the energy stored in the capacitor element continues to discharge, so that the potentials of the two signals can become the same level. Therefore, the receiving circuit cannot detect the potential of the differential signal and may malfunction. As such, in the prior art, there is room for improvement in achieving stable operation of the receiving circuit.

[0009] The present disclosure is based on the above-described circumstances, and an object of the present disclosure is to provide a circuit that can achieve stable operation.

[0010] [Technical means to solve the problem]

[0011] In order to solve the above-mentioned problem, the circuit disclosed in the present invention is an AC coupling circuit, comprising: a receiving circuit, having a first input terminal for inputting a first signal transmitted via a first capacitor element, and a second input terminal for inputting a second signal transmitted via a second capacitor element and having a potential that changes complementarily with respect to the first signal, and outputting a first logic signal corresponding to the potential of the first signal and a second logic signal corresponding to the potential of the second signal; and a signal supply circuit, which supplies a first guarantee signal having a potential corresponding to the value of the first logic signal to the first input terminal as a signal for guaranteeing the potential of the first signal, and supplies a second guarantee signal having a potential that changes complementarily with respect to the first guarantee signal to the second input terminal as a signal for guaranteeing the potential of the second signal.

[0012] A semiconductor device disclosed herein includes the receiving circuit.

[0013] The communication system disclosed herein includes: a first semiconductor device having a transmitting circuit for transmitting a first signal and a second signal; and a second semiconductor device having the circuit, wherein the first signal is supplied to the receiving circuit via the first capacitor element, and the second signal is supplied to the circuit via the second capacitor element.

[0014] [Effects of the Invention]

[0015] According to the present disclosure, it is possible to provide a receiving circuit capable of achieving stable operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a diagram showing the structure of a display device according to an embodiment of the present disclosure.

[0017] Figure 2 It is a diagram showing the structure of a communication system according to an embodiment of the present disclosure.

[0018] Figure 3 It is a diagram showing the configuration of a circuit according to an embodiment of the present disclosure.

[0019] Figure 4 It is a diagram for explaining the operation of the circuit.

[0020] Figure 5 This is a timing diagram for explaining the operation of the circuit.

[0021] Figure 6 This is a timing diagram for explaining the operation of the circuit.

[0022] Figure 7 It is a diagram showing a communication system of a comparative example.

[0023] Figure 8 It is a timing chart for explaining the operation of the circuit of the comparative example.

[0024] [Explanation of Symbols]

[0025] 1: First capacitor element

[0026] 2: Second capacitor element

[0027] 3: Transmission path

[0028] 4: Differential signal

[0029] 10: Display Panel

[0030] 11: Timing controller

[0031] 12: Signal output circuit

[0032] 12A: Signal output circuit

[0033] 13: Gate Driver

[0034] 41: First Signal

[0035] 42: Second signal

[0036] 51: First logic signal

[0037] 52: Second logic signal

[0038] 61: First Guarantee Signal

[0039] 62: Second guarantee signal

[0040] 100: Display device

[0041] 111: Transmitting circuit

[0042] 121: Receiving circuit

[0043] 121a: First differential amplifier circuit

[0044] 121b: Second differential amplifier circuit

[0045] 122: Signal supply circuit

[0046] 122a: Voltage divider circuit

[0047] 122b1: First switch

[0048] 122b2: Second switch

[0049] 122b3: Third switch

[0050] 122b4: Fourth switch

[0051] 200: Communication Systems

[0052] 200A: Communication Systems DETAILED DESCRIPTION

[0053] Hereinafter, the embodiments will be described based on the drawings. In addition, the same or similar symbols are attached to the same functions or structures, and the description thereof will be omitted as appropriate.

[0054] [Implementation Method]

[0055] (Display device)

[0056] Figure 1 1 is a diagram showing a structure of a display device according to an embodiment of the present disclosure. The display device 100 can be interpreted as a vehicle display device mounted on a car or the like. The display device 100 includes a display panel 10, a timing controller 11, a driver integrated circuit (IC) 12, and a gate driver 13.

[0057] The display panel 10 may be interpreted as an image display device such as a liquid crystal display panel, an organic electroluminescence (EL) panel, etc. The timing controller 11 may control the display timing of the image in the display panel 10 by controlling a plurality of driver ICs 12A and a gate driver 13. The timing controller 11 may generate a clock signal and supply it to the driver IC 12A. The timing controller 11 may supply a scanning control signal synchronized with the image data to the gate driver 13.

[0058] The driver IC 12A can be interpreted as a semiconductor device including a receiving circuit described later. The driver IC 12A controls the lighting state of a plurality of light emitting elements provided in the display panel 10 .

[0059] The gate driver 13 may generate a gate signal based on a signal supplied from the timing controller 11 and supply it to the display panel 10 .

[0060] The timing controller 11 and the driver IC 12A may constitute a communication system 200. The communication system 200 may be interpreted as a system using mini-Low Voltage Differential Signaling (mini-LVDS). Mini-LVDS may be interpreted as an interface specification for connecting a liquid crystal controller and a liquid crystal driver.

[0061] Next, refer to Figure 2 The configuration of the communication system 200 will be described. Figure 2 2 is a diagram showing a configuration of a communication system according to an embodiment of the present disclosure. The communication system 200 includes a timing controller 11 and a signal output circuit 12. The timing controller 11 and the signal output circuit 12 are connected to each other via a transmission path 3 so as to be communicable.

[0062] The timing controller 11 includes a transmission circuit 111. The transmission circuit 111 can be interpreted as a circuit for transmitting data using a differential signal 4. The differential signal 4 includes two signals that change complementarily to each other. Specifically, the differential signal 4 includes a first signal 41 transmitted via a first capacitor element 1 configured on a transmission path 3, and a second signal 42 transmitted via a second capacitor element 2 configured on the transmission path 3. The second signal 42 can be interpreted as a signal whose potential changes complementarily with respect to the first signal 41.

[0063] The signal output circuit 12 includes a receiving circuit 121 and a signal supply circuit 122 .

[0064] The receiving circuit 121 can be interpreted as an AC-coupled data receiving circuit that supplies a differential signal 4 transmitted via a capacitor element. The AC-coupled method can be interpreted as a method of removing the DC component of the input signal and transmitting only the AC component to the receiving circuit 121. The receiving circuit 121 has a first input terminal IN1 to which a first signal 41 is input, and a second input terminal IN2 to which a second signal 42 is input.

[0065] The receiving circuit 121 outputs a first logic signal 51 corresponding to the potential of the first signal 41 and a second logic signal 52 corresponding to the potential of the second signal 42. Specifically, the first signal 41 and the second signal 42 can be amplified to output the first logic signal 51 and the second logic signal 52 having a voltage level greater than that of the first signal 41 and the second signal 42.

[0066] The first logic signal 51 is sent to the Figure 1 The display panel 10 is shown, and is input to the first input terminal S1 of the signal supply circuit 122.

[0067] The second logic signal 52 is sent to the Figure 1 The display panel 10 is shown, and is input to the second input terminal S2 of the signal supply circuit 122.

[0068] The signal supply circuit 122 can be interpreted as a circuit for ensuring the potential of the first signal 41 and the potential of the second signal 42. The signal supply circuit 122 includes a first input terminal S1 for inputting the first logic signal 51, a second input terminal S2 for inputting the second logic signal 52, a first output terminal Q1 for outputting the first guarantee signal, and a second output terminal Q2 for outputting the second guarantee signal.

[0069] The signal supply circuit 122 may supply a first guarantee signal having a potential corresponding to the value of the first logic signal 51 to the first input terminal IN1 of the receiving circuit 121 via the first output terminal Q1 as a signal for guaranteeing the potential of the first signal 41. In addition, the signal supply circuit 122 may supply a second guarantee signal having a potential that changes complementarily with respect to the first guarantee signal to the second input terminal IN2 of the receiving circuit 121 via the second output terminal Q2 as a signal for guaranteeing the potential of the second signal 42.

[0070] Next, refer to Figure 3 The specific structure of the signal output circuit 12 will be described. Figure 3 It is a diagram showing the configuration of a circuit according to an embodiment of the present disclosure.

[0071] like Figure 3 As shown, the receiving circuit 121 includes a first differential amplifier circuit 121a and a second differential amplifier circuit 121b.

[0072] The first differential amplifier circuit 121a receives a first signal 41 through a first input terminal IN1 and receives a second signal 42 through a second input terminal IN2. The output of the first differential amplifier circuit 121a is input to the second differential amplifier circuit 121b. The second differential amplifier circuit 121b amplifies the input signal and outputs it as a first logic signal 51 and a second logic signal 52.

[0073] The signal supply circuit 122 supplies a second guarantee signal 62 of a second potential VL lower than the first potential VH to the second input terminal IN2 of the receiving circuit 121, while supplying a first guarantee signal 61 of a first potential VH to the first input terminal IN1 of the receiving circuit 121. The signal supply circuit 122 supplies a second guarantee signal 62 of a first potential VH to the second input terminal IN2 of the receiving circuit 121, while supplying a first guarantee signal 61 of a second potential VL to the first input terminal IN1 of the receiving circuit 121. The first potential VH and the second potential VL can be interpreted as reference voltages that suppress current supply capability.

[0074] Specifically, the signal supply circuit 122 includes a voltage dividing circuit 122a and a plurality of switches, including a first switch 122b1, a second switch 122b2, a third switch 122b3, and a fourth switch 122b4.

[0075] The voltage divider circuit 122a can be interpreted as a circuit that generates a first potential VH or a second potential VL by dividing a voltage applied to a resistor disposed between two power supplies (VDD, VSS). By using the voltage divider circuit 122a, the first potential VH or the second potential VL can be generated with a simple structure using a power supply common to the two power supplies (VDD, VSS) supplied to the receiving circuit 121.

[0076] In addition, the signal supply circuit 122 may include a power supply that outputs the first potential VH or the second potential VL instead of the voltage divider circuit 122a including resistors.

[0077] When the value of the first logic signal 51 is a specific potential, the first switch 122b1 is turned on, thereby supplying the first guaranteed signal 61 of the first potential VH to the first input terminal IN1. Specifically, when the value of the first logic signal 51 applied to the first input terminal S1 is H level, the first switch 122b1 is turned on, thereby supplying the first guaranteed signal 61 of the first potential VH to the first input terminal IN1 of the receiving circuit 121 via the first output terminal Q1.

[0078] When the value of the first logic signal 51 applied to the first input terminal S1 is at an L level, the first switch 122b1 is turned off, thereby stopping the output of the first guarantee signal 61 of the first potential VH.

[0079] When the value of the second logic signal 52 is a specific potential, the second switch 122b2 is turned on, thereby supplying the second guarantee signal 62 of the first potential VH to the second input terminal IN2. Specifically, when the value of the second logic signal 52 applied to the second input terminal S2 is H level, the second switch 122b2 is turned on, thereby supplying the second guarantee signal 62 of the first potential VH to the second input terminal IN2 of the receiving circuit 121 via the second output terminal Q2.

[0080] When the value of the second logic signal 52 applied to the second input terminal S2 is at an L level, the second switch 122b2 is turned off, thereby stopping the output of the second assurance signal 62 of the first potential VH.

[0081] When the value of the second logic signal 52 is a specific potential, the third switch 122b3 is turned on, thereby supplying the first guaranteed signal 61 of the second potential VL to the first input terminal IN1. Specifically, when the value of the second logic signal 52 applied to the second input terminal S2 is H level, the third switch 122b3 is turned on, thereby supplying the first guaranteed signal 61 of the second potential VL to the first input terminal IN1 of the receiving circuit 121 via the first output terminal Q1.

[0082] When the value of the second logic signal 52 applied to the second input terminal S2 is at an L level, the third switch 122b3 is turned off, thereby stopping the output of the second assurance signal 62 of the second potential VL.

[0083] When the value of the first logic signal 51 is a specific potential, the fourth switch 122b4 is turned on, thereby supplying the second guarantee signal 62 of the second potential VL to the second input terminal IN2. Specifically, when the value of the first logic signal 51 applied to the first input terminal S1 is an H level, the fourth switch 122b4 is turned on, thereby supplying the second guarantee signal 62 of the second potential VL to the second input terminal IN2 of the receiving circuit 121 via the second output terminal Q2.

[0084] When the value of the first logic signal 51 applied to the first input terminal S1 is at an L level, the fourth switch 122b4 is turned off, thereby stopping the output of the second assurance signal 62 of the second potential VL.

[0085] (Circuit Operation)

[0086] Next, refer to Figure 4 , Figure 5 and Figure 6 The operation of the signal output circuit 12 will be described. Figure 4 It is a diagram for explaining the operation of the circuit.

[0087] Figure 4 The state "1" shown indicates the following state.

[0088] (1) The value of the first logic signal 51 applied to the first input terminal S1 is H level.

[0089] (2) The value of the second logic signal 52 applied to the second input terminal S2 is L level.

[0090] (3) The first switch 122b1 is in the on state.

[0091] (4) The second switch 122b2 is in the off state.

[0092] (5) The third switch 122b3 is in the off state.

[0093] (6) The fourth switch 122b4 is in the on state.

[0094] (7) The potential applied to the first output terminal Q1 is the first potential VH.

[0095] (8) The potential applied to the second output terminal Q2 is the second potential VL.

[0096] Figure 4 The state "2" shown indicates the following state.

[0097] (1) The value of the first logic signal 51 applied to the first input terminal S1 is L level.

[0098] (2) The value of the second logic signal 52 applied to the second input terminal S2 is H level.

[0099] (3) The first switch 122b1 is in the off state.

[0100] (4) The second switch 122b2 is in the on state.

[0101] (5) The third switch 122b3 is in the on state.

[0102] (6) The fourth switch 122b4 is in the off state.

[0103] (7) The potential applied to the first output terminal Q1 is the second potential VL.

[0104] (8) The potential applied to the second output terminal Q2 is the first potential VH.

[0105] Figure 5 and Figure 6 This is a timing diagram used to explain the operation of the circuit. Figure 5 , the first logic signal 51, the second logic signal 52, and the like are shown in FIG. 1 when the data input to the receiving circuit 121, that is, the output data of the transmitting circuit 111, continuously changes. Figure 6 2 shows a first logic signal 51, a second logic signal 52, etc. when the output data does not change within a certain period of time.

[0106] The first signal 41 input to the first input terminal IN1 has the same phase as the first logic signal 51 output from the first output terminal OUT1. The second signal 42 input to the second input terminal IN2 has the same phase as the second logic signal 52 output from the second output terminal OUT2. The first signal 41 and the second signal 42 have opposite phases.

[0107] exist Figure 5 and Figure 6 , the following signals are shown in order from the top.

[0108] (1) The voltage levels of the first signal 41 and the second signal 42 which are data output from the transmission circuit 111 .

[0109] (2) The voltage levels of the first signal 41 and the second signal 42 which are data input to the receiving circuit 121 .

[0110] (3) The data output from the first output terminal OUT1, that is, the voltage level of the first logic signal 51.

[0111] (4) The data output from the second output terminal OUT2, that is, the voltage level of the second logic signal 52.

[0112] (5) The state of the first switch 122b1.

[0113] (6) The state of the second switch 122b2.

[0114] (7) The state of the third switch 122b3.

[0115] (8) The state of the fourth switch 122b4.

[0116] (9) Voltage level of the first output terminal Q1.

[0117] (10) The voltage level of the second output terminal Q2.

[0118] (11) Figure 4 The number corresponding to the "status" shown.

[0119] (When output data changes continuously)

[0120] like Figure 5 As shown, when the first signal 41 is at an H level and the second signal 42 is at an L level during the time from time t1 to time t2, the first logic signal 51 is at an H level, the second logic signal 52 is at an L level, the first switch 122b1 is turned on, and the second switch 122b2 is turned off. In addition, the third switch 122b3 is turned off, and the fourth switch 122b4 is turned on. As a result, the first potential VH from the voltage divider circuit 122a is input to the first input terminal IN1 via the first output terminal Q1. In addition, the second potential VL from the voltage divider circuit 122a is input to the second input terminal IN2 via the second output terminal Q2.

[0121] When the first signal 41 is at an L level and the second signal 42 is at an H level during the period from time t2 to time t3, the first logic signal 51 is at an L level and the second logic signal 52 is at an H level, the first switch 122b1 is turned off and the second switch 122b2 is turned on. In addition, the third switch 122b3 is turned on and the fourth switch 122b4 is turned off. Thus, the second potential VL from the voltage divider circuit 122a is input to the first input terminal IN1 via the first output terminal Q1. In addition, the first potential VH from the voltage divider circuit 122a is input to the second input terminal IN2 via the second output terminal Q2.

[0122] When the first signal 41 changes to the H level and the second signal 42 changes to the L level at time t3, during the time from time t3 to time t4, as in the time from time t1 to time t2, the first potential VH is input to the first input terminal IN1 and the second potential VL is input to the second input terminal IN2.

[0123] (Output data does not change within a certain period of time)

[0124] exist Figure 6 In the time from time t2 to time t3, the output data does not change within a certain period of time. Even in the case where the output data does not change, when the first signal 41 is at an L level and the second signal 42 is at an H level at time t2, the first logic signal 51 is at an L level and the second logic signal 52 is at an H level. As a result, the first switch 122b1 is turned off and the second switch 122b2 is turned on. In addition, the third switch 122b3 is turned on and the fourth switch 122b4 is turned off.

[0125] Therefore, the second potential VL is input to the first input terminal IN1 via the first output terminal Q1. In addition, the first potential VH is input to the second input terminal IN2 via the second output terminal Q2. Then, these first potential VH and second potential VL are continuously output until time t3. Specifically, the potential of the first signal 41 transmitted via the first capacitor 1 and the potential of the second signal 42 transmitted via the second capacitor 2 are guaranteed until time t3. More specifically, even in a situation where the potential of the first signal 41 and the second signal 42 input to the receiving circuit 121 can be reduced by adding the first potential VH or the second potential VL to these signals, the potential of the first signal 41 and the second signal 42 input to the receiving circuit 121 can be guaranteed.

[0126] (Comparative Example)

[0127] Figure 7 is a diagram showing a communication system of a comparative example. Figure 2 The differences of the communication system 200 shown are: Figure 7 The communication system 200A shown includes a signal output circuit 12B instead of the signal output circuit 12. The signal output circuit 12B does not include Figure 2 The signal supply circuit 122 shown in the figure only includes the receiving circuit 121.

[0128] Figure 8 is a timing chart for explaining the operation of the circuit of the comparative example. Figure 8 , the following signals are shown in order from the top.

[0129] (1) The voltage levels of the first signal 41 and the second signal 42 which are data output from the transmission circuit 111 .

[0130] (2) The voltage levels of the first signal 41 and the second signal 42 which are data input to the receiving circuit 121 .

[0131] (3) The data output from the first output terminal OUT1, that is, the voltage level of the first logic signal 51.

[0132] (4) The data output from the second output terminal OUT2, that is, the voltage level of the second logic signal 52.

[0133] As described above, in the AC coupling method, a capacitor is arranged in the transmission path for the purpose of removing a DC signal, and therefore, the capacitor is repeatedly charged and discharged during a period in which data input to the receiving circuit 121 continues to change. In this case, the potentials of the two signals included in the differential signal 4, that is, the first signal 41 and the second signal 42, which change complementarily to each other, change to an H level or an L level within a certain period of time. Therefore, the receiving circuit 121 can operate normally according to the differential signal 4.

[0134] On the other hand, when the data does not change within a certain period of time, the energy stored in the capacitor element continues to be discharged, thereby Figure 8 During the time from time t2a to time t3, the potentials of the first signal 41 and the second signal 42 decrease and may become the same level. That is, the first signal 41 and the second signal 42 may become attached to each other. As a result, the potentials of the first logic signal 51 and the second logic signal 52 of the receiving circuit 121 also decrease, and the output of the receiving circuit 121 becomes unstable.

[0135] (Function, Effect)

[0136] like Figure 3 As shown, the signal output circuit 12 of the embodiment of the present disclosure includes a signal supply circuit 122, which supplies a first guarantee signal 61 with a potential corresponding to the value of the first logic signal 51 to the first input terminal IN1 as a signal to ensure the potential of the first signal 41, and supplies a second guarantee signal 62 with a potential that changes complementarily with respect to the first guarantee signal 61 to the second input terminal IN2 as a signal to ensure the potential of the second signal 42.

[0137] With the above configuration, even when the potentials of the first signal 41 and the second signal 42 may drop because the data from the transmission circuit 111 does not change for a certain period of time, the potentials of the first signal 41 and the second signal 42 can be guaranteed by the guarantee signal from the signal supply circuit 122. Therefore, the potentials of the first logic signal 51 and the second logic signal 52 of the receiving circuit 121 are guaranteed, so that even when no data is transmitted between the transmission circuit 111 and the receiving circuit 121 for a certain period of time in the AC coupling method, accurate data transmission can be achieved.

[0138] In addition, when LVDS is applied to the communication system 200 of the present disclosure, high-speed serial transmission can be achieved by ensuring the potential of the first logic signal 51 and the second logic signal 52. By achieving high-speed serial transmission, the number of wirings between the transmission circuit 111 and the reception circuit 121 can be reduced, and the manufacturing cost of the substrate accompanying the wiring can be reduced. Since LVDS is a differential current mode interface, it has high resistance to external noise and can also reduce crosstalk noise.

[0139] In addition, regarding the above description, the following supplementary notes are further disclosed.

[0140] (Note 1)

[0141] A circuit, which is an AC coupling circuit, includes: a receiving circuit, having a first input terminal for inputting a first signal transmitted via a first capacitor element, and a second input terminal for inputting a second signal transmitted via a second capacitor element and whose potential changes complementarily with respect to the first signal, and outputting a first logic signal corresponding to the potential of the first signal and a second logic signal corresponding to the potential of the second signal; and a signal supply circuit, which supplies a first guarantee signal with a potential corresponding to the value of the first logic signal to the first input terminal as a signal for guaranteeing the potential of the first signal, and supplies a second guarantee signal with a potential changes complementarily with respect to the first guarantee signal to the second input terminal as a signal for guaranteeing the potential of the second signal.

[0142] (Note 2)

[0143] According to the circuit described in Note 1, the signal supply circuit supplies the second guarantee signal of a second potential lower than the first potential to the second input terminal when the first guarantee signal of the first potential is supplied to the first input terminal, and supplies the second guarantee signal of the first potential to the second input terminal when the first guarantee signal of the second potential is supplied to the first input terminal.

[0144] (Note 3)

[0145] The circuit according to Supplementary Note 1 or 2, wherein the signal supply circuit includes a voltage dividing circuit that generates the first potential or the second potential by dividing a voltage applied to a resistor arranged between two power supplies.

[0146] (Note 4)

[0147] A circuit according to any one of Notes 1 to 3, wherein the signal supply circuit includes: a first switch, which becomes conductive when the value of the first logic signal is a specific potential, thereby supplying the first guarantee signal of the first potential to the first input terminal; a second switch, which becomes conductive when the value of the second logic signal is a specific potential, thereby supplying the second guarantee signal of the first potential to the second input terminal; a third switch, which becomes conductive when the value of the second logic signal is a specific potential, thereby supplying the first guarantee signal of the second potential to the first input terminal; and a fourth switch, which becomes conductive when the value of the first logic signal is a specific potential, thereby supplying the second guarantee signal of the second potential to the second input terminal.

[0148] (Note 5)

[0149] A semiconductor device comprising the circuit according to any one of Supplementary Notes 1 to 4.

[0150] (Note 6)

[0151] A communication system comprises: a first semiconductor device having a transmitting circuit for transmitting the first signal and the second signal according to any one of Notes 1 to 5; and a second semiconductor device having a circuit according to any one of Notes 1 to 5, wherein the first signal is supplied to the receiving circuit via the first capacitor element, and the second signal is supplied to the receiving circuit via the second capacitor element.

Claims

1. A circuit, which is an AC coupling circuit, comprising: a receiving circuit having a first input terminal inputting a first signal transmitted via a first capacitor element, and a second input terminal inputting a second signal transmitted via a second capacitor element and having a potential complementary to the first signal, and outputting a first logic signal corresponding to the potential of the first signal and a second logic signal corresponding to the potential of the second signal; as well as A signal supply circuit supplies a first guarantee signal having a potential corresponding to the value of the first logic signal to the first input terminal as a signal for guaranteeing the potential of the first signal, and supplies a second guarantee signal having a potential that changes complementarily with respect to the first guarantee signal to the second input terminal as a signal for guaranteeing the potential of the second signal.

2. The circuit according to claim 1, wherein the signal supply circuit supplies the second guarantee signal of a second potential lower than the first potential to the second input terminal when the first guarantee signal of a first potential is supplied to the first input terminal, When the first guarantee signal of the second potential is supplied to the first input terminal, the second guarantee signal of the first potential is supplied to the second input terminal. 3 . The circuit according to claim 2 , wherein the signal supply circuit includes a voltage dividing circuit that generates the first potential or the second potential by dividing a voltage applied to a resistor disposed between two power supplies.

4. The circuit according to claim 3, wherein The signal supply circuit comprises: a first switch that is turned on when the value of the first logic signal is a specific potential, thereby supplying the first guarantee signal of the first potential to the first input terminal; a second switch that is turned on when the value of the second logic signal is a specific potential, thereby supplying the second guarantee signal of the first potential to the second input terminal; a third switch that is turned on when the value of the second logic signal is a specific potential, thereby supplying the first guarantee signal of the second potential to the first input terminal; as well as The fourth switch is turned on when the value of the first logic signal is a specific potential, thereby supplying the second assurance signal of the second potential to the second input terminal. 5 . The circuit according to claim 1 , wherein the receiving circuit comprises a differential amplifier circuit, and the differential amplifier circuit receives the first signal and the second signal.

6. A communication system comprising: A first semiconductor device having a transmission circuit for transmitting a first signal and a second signal; as well as The second semiconductor device has a circuit, The circuit comprises: a receiving circuit having a first input terminal inputting a first signal transmitted via a first capacitor element, and a second input terminal inputting a second signal transmitted via a second capacitor element and having a potential complementary to the first signal, and outputting a first logic signal corresponding to the potential of the first signal and a second logic signal corresponding to the potential of the second signal; as well as a signal supply circuit that supplies a first guarantee signal having a potential corresponding to the value of the first logic signal to the first input terminal as a signal for guaranteeing the potential of the first signal, and supplies a second guarantee signal having a potential that changes complementarily with respect to the first guarantee signal to the second input terminal as a signal for guaranteeing the potential of the second signal, The first signal is supplied to the circuit via the first capacitive element, and the second signal is supplied to the circuit via the second capacitive element.

7. The communication system according to claim 6, wherein the signal supply circuit supplies the second guarantee signal of a second potential lower than the first potential to the second input terminal when the first guarantee signal of a first potential is supplied to the first input terminal, When the first guarantee signal of the second potential is supplied to the first input terminal, the second guarantee signal of the first potential is supplied to the second input terminal.

8. The communication system according to claim 7, wherein the signal supply circuit includes a voltage dividing circuit that generates the first potential or the second potential by dividing a voltage applied to a resistor disposed between two power supplies.

9. The communication system according to claim 8, wherein The signal supply circuit comprises: a first switch that is turned on when the value of the first logic signal is a specific potential, thereby supplying the first guarantee signal of the first potential to the first input terminal; a second switch that is turned on when the value of the second logic signal is a specific potential, thereby supplying the second guarantee signal of the first potential to the second input terminal; a third switch that is turned on when the value of the second logic signal is a specific potential, thereby supplying the first guarantee signal of the second potential to the first input terminal; as well as The fourth switch is turned on when the value of the first logic signal is a specific potential, thereby supplying the second assurance signal of the second potential to the second input terminal. 10 . The communication system according to claim 6 , wherein the receiving circuit comprises a differential amplifier circuit, and the differential amplifier circuit receives the first signal and the second signal.

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