B code timing method, system and medium based on sequence sampling

Abstract

The present invention discloses a B code timing method, system and medium based on sequence sampling, which includes high and low level counting, duty cycle calculation and outputting corresponding code elements according to the corresponding logical relationship between duty cycle and code elements; storing the identified code elements in a buffer area, setting the current code element pointer to indicate the storage position of the current code element; setting a synchronization record pointer and a synchronization flag, when two consecutive "P" codes appear, the synchronization record pointer indicates the storage position of the second "P" code, and when two consecutive "P" codes appear, the synchronization flag is set to 1; when the synchronization flag is set to 1 and the number of code elements between the current code element pointer and the synchronization record pointer exceeds 60, the code element data on the corresponding storage position segment behind the synchronization record pointer is read to obtain the information of seconds, minutes, hours, days and years respectively. The present invention realizes the synchronization analysis of B code information based on the sampling sequence only by relying on the algorithm, which greatly improves the time accuracy and synchronization degree of synchronization.

Description

Technical Field

[0001] The invention belongs to the technical field of electrical communications, and in particular relates to a B-code timing method, system and medium based on sequence sampling. Background Art

[0002] With the development of science and technology and automation technology, the time synchronization network, as an important infrastructure, has played an important role in the fields of telecommunications, electricity, and national defense. At the same time, the requirements for the time accuracy and synchronization of timing are becoming increasingly higher.

[0003] Patent CN115333714A in the prior art discloses an IRIG-B code-based electric power timing system and timing method, which includes an MCU module, a CPLD module, a clock module and a GPS / BD signal receiving module. The analysis of the B code requires the cooperation of the clock module, which has certain hardware requirements; in addition, there is a certain accuracy error in the recognition of code elements, which cannot meet the usage scenarios with extremely high accuracy requirements.

[0004] Therefore, it is necessary to provide a new B code timing method and control method based on sequence sampling to solve the above technical problems. Summary of the invention

[0005] One of the main purposes of the present invention is to provide a B-code timing method based on sequence sampling, which improves the time accuracy and synchronization of timing, reduces the hardware configuration cost, and improves applicability.

[0006] The present invention achieves the above-mentioned object through the following technical scheme: A B code timing method based on sequence sampling, which comprises the following steps:

[0007] S1. Identification of basic code elements:

[0008] S11, high level count: when the current sampling value is high level and the previous sampling value is low level, the high level count value starts counting, and at the same time, an edge mark is set as a rising edge mark;

[0009] S12, low level counting: when the current sampling value is at a low level and the previous sampling value is at a high level, the low level count value starts counting, and at the same time, the edge flag is set to a falling edge flag; and the low level count stops when the next rising edge appears;

[0010] S13, Duty cycle calculation: Define the duty cycle calculation formula as follows: ;

[0011] Among them, Hlevel_coun is the high level count value, and Llevel_coun is the low level count value;

[0012] S14, outputting corresponding code elements according to the duty cycle: pre-configuring the corresponding logical relationship between the duty cycle and the code element, and outputting the corresponding code element according to the duty cycle calculation result in step S13;

[0013] S2, storing the code element identified and outputted in step S1: the code element identified in step S1 enters the buffer Code_Buf, sets a current code element pointer code_pc to indicate the storage position of the current code element, and moves one storage position backward every time a code element is calculated and enters the buffer; sets a synchronization record pointer sync_pc to indicate the storage position of the second "P" code when two consecutive "P" codes appear; sets a synchronization flag sync_flag, which is set to 1 when two consecutive "P" codes appear in the code element, and is initially set to 0;

[0014] S3. Analyze the code elements stored in step S2: When two consecutive "P" codes appear in the buffer Code_Buf, and the number of code elements between the current code element pointer code_pc and the synchronization record pointer sync_pc exceeds 60, read the code element data on the corresponding storage position segment after the synchronization record pointer sync_pc to obtain the seconds, minutes, hours, days, and years information respectively.

[0015] Furthermore, the corresponding logical relationship between the duty cycle and the code element is: if the duty cycle is in the range of 10~30%, it is judged as a "0" code element; if the duty cycle is in the range of 40~60%, it is judged as a "1" code element; if the duty cycle is in the range of 70~90%, it is judged as a "P" code element; otherwise, it is judged as "Null".

[0016] Furthermore, in the step S1, several parameters and status flags are set, including an edge flag edge_flag, a current sampling level cur_sample, a previous sampling level prv_sample, and a millisecond count value MilliSecond; wherein the value of the edge flag edge_flag includes a high level flag Sam_Edge_Hleve, a low level flag Sam_Edge_Lleve, and an invalid flag Sam_Edge_Null, which is initially set to 0.

[0017] Furthermore, the execution logic of the code element identification and storage in step S1 and step S2 specifically includes the following contents:

[0018] S1001, sampling identification logic starts;

[0019] S1002, obtaining the last sampling level prv_sample and the current sampling level cur_sample;

[0020] S1003, determine whether the edge flag edge_flag is an invalid flag Sam_Edge_Null, if so, execute steps S1004 to S1005, if not, execute steps S1006 to S1009;

[0021] S1004, determine whether the current sampling level cur_sample is a high level, and whether the last sampling level prv_sample is a low level, if yes, execute the next step, if no, end the logic;

[0022] S1005, the edge flag edge_flag is set to the high level flag Sam_Edge_Hlevel, and at the same time, the high level count value Hlevel_count is set to 1, and the low level count value Llevel_count is set to 0, and then the logic ends;

[0023] S1006, determine whether the synchronization flag sync_flag is equal to 1, if so, the millisecond count value MilliSecond starts counting from 0, and then executes the next step, if not, directly executes the next step;

[0024] S1007, determine whether the edge flag edge_flag is a high level flag Sam_Edge_Hleve, if so, execute steps S1008~S1009, if not, execute steps S1010~S1009;

[0025] S1008, determining whether the current sampling level cur_sample is a high level, if so, the high level count value Hlevel_count starts counting, and then the next step is executed, if not, the next step is directly executed;

[0026] S1009, judging whether the current sampling level cur_sample is a low level, and whether the last sampling level prv_sample is a high level, if yes, the edge flag edge_flag is set to the low level flag Sam_Edge_Lleve, and the low level count value Llevel_count is set to 1, and then the logic ends; if no, the logic ends directly;

[0027] S1010, determine whether the edge flag edge_flag is a low level flag Sam_Edge_Lleve, if so, execute the next step, if not, end the logic;

[0028] S1011, determine whether the current sampling level cur_sample is a low level, if so, the low level count value Llevel_count starts counting, and then executes the next step, if not, directly executes the next step;

[0029] S1012, determine whether the current sampling level cur_sample is a high level, and whether the last sampling level prv_sample is a low level, if yes, execute the next step, if no, end the logic;

[0030] S1013, calculating the duty cycle Duty;

[0031] S1014, according to the duty cycle calculation result, according to the duty cycle and the logic relationship between the code element output, the corresponding code element is output as "0" code element, "1" code element, "P" code element or other "Null";

[0032] S1015, determine whether the code element is other "Null", if so, set code err to 1, and then execute the next step, if not, directly execute the next step;

[0033] S1016, the code element outputted in step S1014 is stored in the code element buffer Code_Buf, and at the same time, the current code element pointer code_pc moves backward by one position to point to the current code element storage position;

[0034] S1017, determine whether the synchronization flag sync_flag is equal to 1, if so, the logic ends; if not, execute the next step;

[0035] S1018, determine whether the current code element and the previous code element are both "P" code elements, if so, execute the next step, if not, the logic ends;

[0036] S1019, the synchronization flag sync_flag is set to 1, the millisecond count value MilliSecond is set to 0, the synchronization record pointer sync_pc = the current code element pointer code_pc, and the logic ends.

[0037] Furthermore, the execution logic of parsing the code element in step S3 specifically includes the following contents:

[0038] S2001, B code time calculation logic starts;

[0039] S2002, determine whether the synchronization flag sync_flag is equal to 1, and whether code err is equal to 0, if so, execute the next step, if not, the logic ends;

[0040] S2003, determine whether the number of code elements stored between the current code element pointer code_pc and the synchronization record pointer sync_pc exceeds 60, if so, execute the next step, if not, the logic ends;

[0041] S2004, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, read the codeword data in the following 8 storage units, and calculate the seconds;

[0042] S2005, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 10th to 18th storage units, and calculating the score;

[0043] S2006, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 20th to 28th storage units, and calculating the time;

[0044] S2007, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 30th to 38th and 40th to 42nd storage units, and calculating the day;

[0045] S2008, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 50th to 58th storage units, and calculating the year;

[0046] S2009, the synchronization flag sync_flag is set to 0, and the logic ends.

[0047] Another object of the present invention is to provide a B code timing system based on sequence sampling, comprising a core processing unit and an RS422 module electrically connected to the core processing unit, the RS422 module electrically connected to a satellite time synchronization signal device to receive a B code signal, and the core processing unit identifies, stores, and synchronously parses the B code signal according to the B code timing method as described above, and then sends it to an external device.

[0048] Furthermore, the core processing unit has SPI data communication and serial data UART communication interfaces for data communication with the external device.

[0049] Furthermore, the core processing unit includes:

[0050] A code element recognition module is used to realize the recognition of basic code elements;

[0051] A codeword storage module, storing the codewords identified and output by the codeword identification module;

[0052] A codeword parsing module is used to parse the codewords in the codeword storage module.

[0053] Another object of the present invention is to provide a computer-readable storage medium, wherein the computer can read a computer program stored on the storage medium, and the computer program is executed by a core processing unit to implement the B-code timing method based on sequence sampling as described above.

[0054] Compared with the prior art, the B code timing method, system and medium based on sequence sampling of the present invention have the following beneficial effects: sequence sampling is performed on the B code, and based on the sampling sequence pulse signal, the rising edge and the falling edge are judged to control the high level counting starting point and the low level counting ending point, thereby ensuring that the pulse signal corresponding to the high level counting and the low level counting must be performed within the same code element, and the pulse signal can cover the code element to the greatest extent, thereby greatly improving the accuracy of code element extraction; in addition, the duty cycle is calculated by using the ratio of the high level to the total number of high and low levels, and the code element is identified by using the logical relationship range segment where the duty cycle is located, thereby improving the fault tolerance of the system calculation, and further improving the accuracy of the code element extraction. And reversely improves the accuracy of code element recognition; by setting the synchronization flag, the B code information is parsed only when the synchronization flag is equal to 1, and when two "P" codes appear consecutively, the second "P" code element is the "on time" reference point, thus ensuring the synchronization and accuracy of the B code information parsing; when the number of code elements between the current code element pointer and the synchronization record pointer exceeds 60, the B code information parsing can be started, and the B code synchronization can be performed, thereby improving the parsing efficiency; this method uses the core processing unit as a separate timing parsing unit, reduces the operating pressure of other intelligent devices, and realizes the need for other intelligent devices to directly read high-precision time without clock synchronization and data analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic diagram of the system framework principle structure of an embodiment of the present invention;

[0056] Figure 2 Schematic diagram of basic code elements in an embodiment of the present invention;

[0057] Figure 3 Schematic diagram of the structure of the B code pulse sequence in an embodiment of the present invention;

[0058] Figure 4 A schematic diagram of a method flow chart of an embodiment of the present invention;

[0059] Figure 5 A schematic diagram of a method flow chart of basic symbol recognition in an embodiment of the present invention;

[0060] Figure 6 Schematic diagram of the structure of the rising edge and the falling edge in the embodiment of the present invention;

[0061] Figure 7 A schematic diagram of duty cycle calculation when "0" symbol is identified in an embodiment of the present invention;

[0062] Figure 8 Another schematic diagram of duty cycle calculation when "0" symbol is identified in an embodiment of the present invention;

[0063] Fig. 9 A schematic diagram of the structure of code element storage in an embodiment of the present invention;

[0064] Fig.10 Schematic diagram of the logic flow of code element sampling, identification and storage in an embodiment of the present invention;

[0065] Fig.11 Schematic diagram of the logic flow of code element analysis in an embodiment of the present invention. DETAILED DESCRIPTION

[0066] Embodiment 1:

[0067] Please refer to Figure 1 This embodiment is a B-code timing system based on sequence sampling, which includes a core processing unit and an RS422 module electrically connected to the core processing unit, the RS422 module electrically connected to a satellite time synchronization signal device, and the core processing unit electrically connected to an external device.

[0068] The satellite time synchronization signal device is the signal source of the B code timing system of this embodiment and is also the starting point of the entire system signal. After obtaining multiple satellite times for synchronization, it continuously sends out B code format timing signals to the outside; this signal contains accurate year, month, day, hour, minute, and second time information, providing an accurate time reference source for the time synchronization and analysis of this system.

[0069] The RS422 module adopts a differential signal transmission method (through the A and B pins) to receive the B code signal sent by the satellite time synchronization signal device. After level conversion by the RS422 module, it becomes a level VB signal acceptable to the core processing unit. The ADC of the core processing unit converts the access VB signal and performs digital quantization processing.

[0070] The main function of the core processing unit is to sample, analyze and synchronize the B code to parse out the accurate time information. The core processing unit has SPI data communication and serial data UART communication interfaces, and is responsible for accurate time data communication with the external device. The external device can obtain the current accurate time through the SPI or UART communication interface; the signal Status is the time synchronization output signal of the core processing unit, and only when the core processing unit has obtained accurate clock synchronization, it outputs a high level; otherwise, it outputs a low level.

[0071] The core processing unit includes a code element recognition module, a code element storage module and a code element parsing module. The code element recognition module is mainly used to realize the recognition of basic code elements; the code element storage module is mainly used to store the code elements recognized and output by the code element recognition module; the code element parsing module is mainly used to parse the code elements in the code element storage module.

[0072] The B code signal is a time code with one frame per second. Its basic code elements are "0" code element, "1" code element and "P" code element. Each code element takes 10ms. One frame of code contains 100 code elements. Code elements "0" and "1" correspond to pulse widths of 2ms and 5ms. "P" code element is a position code element, and its corresponding pulse width is 8ms. The schematic diagram of the basic code elements of B code information is as follows: Figure 2 shown.

[0073] The pulse sequence structure diagram of the B code signal with one frame per second is as follows Figure 3 As shown in the figure, two consecutive "P" code elements represent the beginning of a whole second, and the pulse leading edge of the second "P" code element is the "punctual" reference point, which is defined as "Pr". There is a position code element for every 10 code elements, and there are 10 in total, defined as P1, P2, ..., P9, P0. The timing sequence of the B code time format is seconds-minutes-hours-days, and the information bits occupied are 7 bits for seconds, 7 bits for minutes, 6 bits for hours, and 10 bits for days, and its position is between P0 and P5. If the code elements are numbered starting from "Pr", they are defined as code elements 0, 1, 2, ..., 99, respectively. Then the "second" information is located at code elements 1, 2, 3, 4, 6, 7, 8, the "minute" information is located at code elements 10, 11, 12, 13, 15, 16, 17, the "hour" information is located at code elements 20, 21, 22, 23, 25, 26, 27, and the "day" information is located at code elements 30, 31, 32, 33, 35, 36, 37, 38, 40, 41. Code elements 5, 14, and 24 are index marks with a width of 2ms. Days, hours, minutes, and seconds are all represented by BCD codes, with the low digit in front and the high digit in the back; the ones digit is in front and the tens digit is in the back. There is an index mark code element with a pulse width of 2ms between the ones and tens digits. The control code element is located between P5 and P8. The SBS time code starts from the P8 code element. It is a time coding method that directly uses a binary second signal to represent a day. It has a total of 17 binary signals and is repeated every day.

[0074] Please refer to Figure 4 , Figure 5 This embodiment also provides a B code timing method based on sequence sampling, which includes:

[0075] S1. Identification of basic code elements. Identify a complete code element and output whether the code element is a "0" code element, a "1" code element, a "P" code element or others, including:

[0076] S11, high level count: When the current sampling value is high level and the previous sampling value is low level, the high level count value starts counting. At the same time, an edge flag is set as a rising edge flag, such as Figure 6 As shown;

[0077] S12, low level count: when the current sampling value is low level and the previous sampling value is high level, the low level count value starts counting, and at the same time, the edge flag is set to the falling edge flag; and the low level count is stopped when the next rising edge appears, such as Figure 6 As shown;

[0078] In this embodiment, the condition for starting counting at a low level not only satisfies the falling edge, but also satisfies that counting has started at a high level. This is consistent with the pulse signal characteristics of the "0" code element, the "1" code element and the "P" code element. The starting segment of the pulse signal of these basic code elements is a high level, and then enters a low level. The high level and the low level together form a complete basic code element. Therefore, the high level is counted first, and then the low level can be counted, to ensure that the high level and low level corresponding to the count are in the same complete basic code element pulse signal segment, thereby ensuring the accuracy of code element recognition.

[0079] S13, Duty cycle calculation: Define the duty cycle calculation formula as follows: ;

[0080] Among them, Hlevel_coun is the high level count value, and Llevel_coun is the low level count value.

[0081] S14, output corresponding code element according to duty cycle: pre-configure the corresponding logical relationship between duty cycle and code element, as shown in Table 1, if the duty cycle is in the range of 10-30%, it is determined as a "0" code element; if the duty cycle is in the range of 40-60%, it is determined as a "1" code element; if the duty cycle is in the range of 70-90%, it is determined as a "P" code element; otherwise, it is determined as "Null". According to the duty cycle calculation result in step S13, the corresponding code element is output.

[0082] Table 1 Logical relationship between code element and duty cycle

[0083]

[0084] In the recognition of basic code elements, when counting high and low levels, high level counting starts only when a rising edge appears, and low level counting starts only when a falling edge appears and the high level has completed counting. When counting low levels, counting stops immediately after the next rising edge appears, ensuring that the pulse signals corresponding to the high level count and the low level count must be performed in the same code element, and the pulse signal can cover the code element to the greatest extent, greatly improving the accuracy of code element extraction. In addition, using the duty cycle range to identify code elements improves the fault tolerance of system calculations, thereby improving the accuracy of code element recognition in reverse.

[0085] Please refer to Figure 7 , Figure 8 For example, when the pulse signal corresponding to the "0" code element is used for code element recognition, there may be a time interval error between the high-level signal for starting counting and the code element start realization, and since the high-level counting starts only when the previous level signal is low and the current level signal is high, the effective sampling points (the "effective sampling points" are sampling points participating in the high-level counting or low-level counting) in the pulse signal segment corresponding to the "0" code element may be different. If sampling is performed at a sampling rate of 1.2 times / ms, no matter how the above time interval errors are distributed, there will be 11 effective sampling points. Among these 11 effective sampling points, the number of high levels that appear within the pulse width of 2ms corresponding to the "0" code element may be 2 or 3, and the corresponding low-level counts are 9 and 8, and the calculated duty cycle is 2 / 11=18.18% or 3 / 11=27.27%. In this embodiment, the duty cycle corresponding to the "0" code element is expanded to 10~30%, which covers the calculation results caused by any of the above time interval errors, ensuring the effective and accurate recognition of the "0" code element.

[0086] In step S1, several parameters and status flags are set, including edge flag edge_flag, current sampling level cur_sample, last sampling level prv_sample and millisecond count value MilliSecond. The value range of edge flag edge_flag is shown in Table 2, and it is initially set to 0. The millisecond count value MilliSecond is used to provide millisecond accurate time. Since the second "P" code of the two "P" codes of the B code produces an accurate second change, the millisecond is 0 at this time. When the device reads the synchronization time, it needs to obtain the year, month, day, hour, minute, and second at this moment, including millisecond information.

[0087] Table 2 Edge flag value range

[0088]

[0089] S2. Store the code element identified and outputted in step S1. Fig. 9 The code element identified in step S1 enters the buffer Code_Buf, sets a current code element pointer code_pc to indicate the storage position of the current code element, and moves one storage position backward each time a code element is calculated and enters the buffer; sets a synchronization record pointer sync_pc to indicate the storage position of the second "P" code when two "P" codes appear consecutively; sets a synchronization flag sync_flag to be set to 1 when two "P" codes appear consecutively in the code element, and is initially set to 0. The buffer Code_Buf is used to store code element data with a capacity of more than 100.

[0090] S3, parsing the code elements stored in step S2. When two consecutive "P" codes appear in the buffer area Code_Buf, and the number of code elements between the current code element pointer code_pc and the synchronization record pointer sync_pc exceeds 60, the code elements on the corresponding storage position segment after reading the synchronization record pointer sync_pc are respectively obtained to obtain the second, minute, hour, day, and year information.

[0091] By setting the synchronization flag sync_flag, the B code information is parsed only when the synchronization flag sync_flag is equal to 1, and when two "P" codes appear consecutively, the second "P" code element is the "on-time" reference point, thereby ensuring the synchronization and accuracy of the B code information parsing; when the number of code elements between the current code element pointer code_pc and the synchronization record pointer sync_pc exceeds 60, the B code information parsing can be started, and the B code synchronization can be performed, thereby improving the parsing efficiency.

[0092] Please refer to Fig.10 In this embodiment, the execution logic of code element recognition and storage in step S1 and step S2 specifically includes the following contents:

[0093] S1001, sampling identification logic starts;

[0094] S1002, obtaining the last sampling level prv_sample and the current sampling level cur_sample;

[0095] S1003, determine whether the edge flag edge_flag is an invalid flag Sam_Edge_Null, if so, execute steps S1004 to S1005, if not, execute steps S1006 to S1009;

[0096] S1004, determine whether the current sampling level cur_sample is a high level, and whether the last sampling level prv_sample is a low level, if yes, execute the next step, if no, end the logic;

[0097] S1005, the edge flag edge_flag is set to the high level flag Sam_Edge_Hlevel, and at the same time, the high level count value Hlevel_count is set to 1, and the low level count value Llevel_count is set to 0, and then the logic ends;

[0098] S1006, determine whether the synchronization flag sync_flag is equal to 1, if so, the millisecond count value MilliSecond starts counting from 0, and then executes the next step, if not, directly executes the next step;

[0099] S1007, determine whether the edge flag edge_flag is a high level flag Sam_Edge_Hleve, if so, execute steps S1008~S1009, if not, execute steps S1010~S1009;

[0100] S1008, determining whether the current sampling level cur_sample is a high level, if so, the high level count value Hlevel_count starts counting from 1, and then the next step is executed, if not, the next step is directly executed;

[0101] S1009, judging whether the current sampling level cur_sample is a low level, and whether the last sampling level prv_sample is a high level, if yes, the edge flag edge_flag is set to the low level flag Sam_Edge_Lleve, and the low level count value Llevel_count is set to 1, and then the logic ends; if no, the logic ends directly;

[0102] S1010, determine whether the edge flag edge_flag is a low level flag Sam_Edge_Lleve, if so, execute the next step, if not, end the logic;

[0103] S1011, determine whether the current sampling level cur_sample is a low level, if so, the low level count value Llevel_count starts counting from 1, and then executes the next step, if not, directly executes the next step;

[0104] S1012, judging whether the current sampling level cur_sample is a high level and whether the last sampling level prv_sample is a low level, if yes, executing the next step, at this time, it means that a basic symbol sequence has been collected and symbol recognition can be started; if no, ending the logic;

[0105] S1013, calculating the duty cycle Duty;

[0106] S1014, according to the duty cycle calculation result, according to the duty cycle and the logic relationship between the code element output, the corresponding code element is output as "0" code element, "1" code element, "P" code element or other "Null";

[0107] S1015, determine whether the code element is other "Null", if so, set the error flag code err to 1, and then execute the next step, if not, directly execute the next step;

[0108] S1016, the code element outputted in step S1014 is stored in the code element buffer Code_Buf, and at the same time, the current code element pointer code_pc moves backward by one position to point to the current code element storage position;

[0109] S1017, determine whether the synchronization flag sync_flag is equal to 1, if so, the logic ends; if not, execute the next step;

[0110] S1018, determine whether the current code element and the previous code element are both "P" code elements, if so, execute the next step, if not, the logic ends;

[0111] S1019, the synchronization flag sync_flag is set to 1, the millisecond count value MilliSecond is set to 0, and the synchronization record pointer sync_pc records the position of the second "P" code element of two consecutive "P" code elements in the buffer, and the logic ends.

[0112] Please refer to Fig.11 The execution logic of step S3 for parsing the code element specifically includes the following contents:

[0113] S2001, B code time calculation logic starts;

[0114] S2002, determine whether the synchronization flag sync_flag is equal to 1, and whether code err is equal to 0, if so, execute the next step, if not, the logic ends;

[0115] S2003, determine whether the number of code elements stored between the current code element pointer code_pc and the synchronization record pointer sync_pc exceeds 60, if so, execute the next step, if not, the logic ends; the synchronization record pointer sync_pc records the buffer position of the two "P" codes in the buffer, and code_pc is the current latest code element position. The number between the two exceeds 60, indicating that the year position has been sampled and calculated since the two "P" codes, and time synchronization calculation can be performed;

[0116] S2004, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, read the codeword data in the following 8 storage units, and calculate the seconds;

[0117] S2005, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 10th to 18th storage units, and calculating the score;

[0118] S2006, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 20th to 28th storage units, and calculating the time;

[0119] S2007, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 30th to 38th and 40th to 42nd storage units, and calculating the day;

[0120] S2008, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 50th to 58th storage units, and calculating the year;

[0121] S2009, the synchronization flag sync_flag is set to 0, and the logic ends.

[0122] This embodiment also provides a computer-readable storage medium, and the computer can read a computer program stored on the storage medium. The computer program is executed by the core processing unit to implement the above-mentioned B code timing method based on sequence sampling.

[0123] For those skilled in the art, several modifications and improvements can be made without departing from the inventive concept of the present invention, all of which fall within the protection scope of the present invention.

Claims

1. A B-code timing method based on sequence sampling, characterized in that: It includes the following steps: S1. Identification of basic code elements: S11, high level count: when the current sampling value is high level and the previous sampling value is low level, the high level count value starts counting, and at the same time, an edge mark is set as a rising edge mark; S12, low level counting: when the current sampling value is at a low level and the previous sampling value is at a high level, the low level count value starts counting, and at the same time, the edge flag is set to a falling edge flag; and the low level count stops when the next rising edge appears; S13, Duty cycle calculation: Define the duty cycle calculation formula as follows: ； Among them, Hlevel_coun is the high level count value, and Llevel_coun is the low level count value; S14, outputting corresponding code elements according to the duty cycle: pre-configuring the corresponding logical relationship between the duty cycle and the code element, and outputting the corresponding code element according to the duty cycle calculation result in step S13; S2, storing the code element identified and outputted by step S1: the code element identified by step S1 enters the buffer area Code_Buf, sets a current code element pointer code_pc to indicate the storage position of the current code element, and moves one storage position backward every time a code element is calculated and enters the buffer area; sets a synchronization record pointer sync_pc to indicate the storage position of the second "P" code when two consecutive "P" codes appear; sets a synchronization flag sync_flag, which is set to 1 when two consecutive "P" codes appear in the code element, and is initially set to 0; S3. Analyze the code elements stored in step S2: When two consecutive "P" codes appear in the buffer Code_Buf, and the number of code elements between the current code element pointer code_pc and the synchronization record pointer sync_pc exceeds 60, read the code element data on the storage position segment corresponding to the synchronization record pointer sync_pc to obtain the second, minute, hour, day and year information respectively.

2. The B-code timing method based on sequence sampling as claimed in claim 1, characterized in that: The logical relationship between the duty cycle and the code element is: if the duty cycle is within the range of 10-30%, it is determined to be a "0" code element; If the duty cycle is in the range of 40-60%, it is determined as a "1" code element; If the duty cycle is in the range of 70~90%, it is judged as a "P" code element; otherwise, it is judged as "Null".

3. The B-code timing method based on sequence sampling as claimed in claim 1, characterized in that: In the step S1, several parameters and status flags are set, including an edge flag edge_flag, a current sampling level cur_sample, a previous sampling level prv_sample and a millisecond count value MilliSecond; wherein the value of the edge flag edge_flag includes a high level flag Sam_Edge_Hlevel, a low level flag Sam_Edge_Llevel and an invalid flag Sam_Edge_Null, which is initially set to 0.

4. The B-code timing method based on sequence sampling as claimed in claim 1, characterized in that: The execution logic of the code element identification and storage in step S1 and step S2 specifically includes the following contents: S1001, sampling identification logic starts; S1002, obtaining the last sampling level prv_sample and the current sampling level cur_sample; S1003, determine whether the edge flag edge_flag is an invalid flag Sam_Edge_Null, if so, execute steps S1004 to S1005, if not, execute steps S1006 to S1009; S1004, determine whether the current sampling level cur_sample is a high level, and whether the last sampling level prv_sample is a low level, if yes, execute the next step, if no, end the logic; S1005, the edge flag edge_flag is set to the high level flag Sam_Edge_Hlevel, and at the same time, the high level count value Hlevel_count is set to 1, and the low level count value Llevel_count is set to 0, and then the logic ends; S1006, determine whether the synchronization flag sync_flag is equal to 1, if so, the millisecond count value MilliSecond starts counting from 0, and then executes the next step, if not, directly executes the next step; S1007, determine whether the edge flag edge_flag is a high level flag Sam_Edge_Hleve, if so, execute steps S1008~S1009, if not, execute steps S1010~S1009; S1008, judging whether the current sampling level cur_sample is a high level, if so, the high level count value Hlevel_count starts counting, and then the next step is executed, if not, the next step is directly executed; S1009, judging whether the current sampling level cur_sample is a low level, and whether the last sampling level prv_sample is a high level, if yes, the edge flag edge_flag is set to the low level flag Sam_Edge_Lleve, and the low level count value Llevel_count is set to 1, and then the logic ends; if no, the logic ends directly; S1010, determine whether the edge flag edge_flag is a low level flag Sam_Edge_Lleve, if so, execute the next step, if not, end the logic; S1011, determine whether the current sampling level cur_sample is a low level, if so, the low level count value Llevel_count starts counting, and then executes the next step, if not, directly executes the next step; S1012, determine whether the current sampling level cur_sample is a high level, and whether the last sampling level prv_sample is a low level, if yes, execute the next step, if no, end the logic; S1013, calculating the duty cycle Duty; S1014, according to the duty cycle calculation result, according to the duty cycle and the logic relationship between the code element output, the corresponding code element is output as "0" code element, "1" code element, "P" code element or other "Null"; S1015, determine whether the code element is other "Null", if so, set code err to 1, and then execute the next step, if not, directly execute the next step; S1016, the code element outputted in step S1014 is stored in the code element buffer Code_Buf, and at the same time, the current code element pointer code_pc moves backward by one position to point to the current code element storage position; S1017, determine whether the synchronization flag sync_flag is equal to 1, if so, the logic ends; if not, execute the next step; S1018, determine whether the current code element and the previous code element are both "P" code elements, if so, execute the next step, if not, the logic ends; S1019, the synchronization flag sync_flag is set to 1, the millisecond count value MilliSecond is set to 0, the synchronization record pointer sync_pc = the current code element pointer code_pc, and the logic ends.

5. The B-code timing method based on sequence sampling as claimed in claim 1, characterized in that: The execution logic of parsing the code element in step S3 specifically includes the following contents: S2001, B code time calculation logic starts; S2002, determine whether the synchronization flag sync_flag is equal to 1, and whether code err is equal to 0, if so, execute the next step, if not, the logic ends; S2003, determine whether the number of code elements stored between the current code element pointer code_pc and the synchronization record pointer sync_pc exceeds 60, if so, execute the next step, if not, the logic ends; S2004, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, read the codeword data in the following 8 storage units, and calculate the seconds; S2005, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 10th to 18th storage units, and calculating the score; S2006, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 20th to 28th storage units, and calculating the time; S2007, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 30th to 38th and 40th to 42nd storage units, and calculating the day; S2008, starting from the storage unit after the synchronization record pointer sync_pc in the codeword buffer Code_Buf, reading the codeword data in the 50th to 58th storage units, and calculating the year; S2009, the synchronization flag sync_flag is set to 0, and the logic ends.

6. A B-code timing system based on sequence sampling, characterized in that: It includes a core processing unit and an RS422 module electrically connected to the core processing unit, the RS422 module electrically connected to a satellite time synchronization signal device to receive a B code signal, and the core processing unit identifies, stores, and synchronously analyzes the B code signal according to the B code timing method as described in claim 1 and then sends it to an external device.

7. The B-code timing system based on sequence sampling as claimed in claim 6, characterized in that: The core processing unit has SPI data communication and serial data UART communication interfaces for data communication with the external device.

8. The B-code timing system based on sequence sampling as claimed in claim 6, characterized in that: The core processing unit comprises: A code element recognition module is used to realize the recognition of basic code elements; A codeword storage module, storing the codewords identified and output by the codeword identification module; A codeword parsing module is used to parse the codewords in the codeword storage module.

9. A computer-readable storage medium, characterized in that: The computer program stored on the computer-readable storage medium is executed by the core processing unit to implement the B-code timing method based on sequence sampling as claimed in claim 1.

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