A high bandwidth utilization transmission method and system for video transmission interface

Abstract

The present invention discloses a high bandwidth utilization transmission method and system for a video transmission interface. The method comprises caching the extracted valid data into a transmission buffer memory before transmission, generating a transmission buffer memory ready signal, taking the number of valid pixels in a row as the total data volume of a row, monitoring the data volume read in the buffer memory during data reading, and generating a start signal and an end signal of a row according to the data volume read, caching the valid video data obtained by decapsulation into a receiving buffer memory after receiving the data, generating a receiving buffer memory ready signal when the data volume threshold is cached, and then calculating the pixel clock frequency according to the received video parameter information, and then restoring and generating standard video data according to the video parameter information, the pixel clock frequency and the valid video data. The present invention realizes the utilization of idle bandwidth, thereby improving the bandwidth utilization.

Description

Technical Field

[0001] The present invention relates to the technical field of video transmission, and in particular to a high bandwidth utilization transmission method and system for a video transmission interface. Background Art

[0002] Video data is generally transmitted through video interfaces such as HDMI (High Definition Multimedia Interface) or MIPI (Mobile Industry Processor Interface). These video interfaces have their own corresponding interface protocol standards, and different versions of the protocol standards will specify the maximum interface cable transmission rate. Therefore, each interface protocol standard has a maximum transmission rate.

[0003] The interface transmission generally uses the general video signal interface, including Pixel_clk (pixel clock), Vsync (field synchronization), Hsync (line synchronization), DataEnable (data valid), and Data (video data).

[0004] Calculation of bandwidth required for video transmission: (unit: MBps) Bandwidth = Pixel_Freq * bpp / 8bit.

[0005] Pixel_Freq (pixel frequency), bpp (bits per pixel), for example, in the CTA standard, vic95, 3840x2160@30hz, F_pixel_clk is 297Mhz. If it is transmitted according to RGB 8bit, 297x24 / 8=891MBps is required.

[0006] The horizontal parameters in video timing are Hsync (line synchronization), Hfront (line synchronization front edge), Hback (line synchronization back edge), Htotal (total number of pixels in a line), Hblank (blanking pixels in a line), and Vactive (effective pixels in a line). Among them, Hblank = Hsync + Hfront + Hback; Htotal = Hblank + Hactive. Htotal represents the total number of pixels in a line, including effective pixels (Hactive) and blanking pixels (Hblank). Effective pixels are the pixels that actually make up the image, while blanking pixels are used to provide synchronization and buffer time during horizontal scanning.

[0007] During the video interface transmission process, the ratio of the time taken to send effective pixel data in the total time of one line on the high-speed line is consistent with the ratio of Hactive to Htotal in the input video timing. Therefore, the bandwidth utilization of one line on the high-speed line is Hactive / Htotal. For details, see Figure 1 .

[0008] With the popularity of fixed pixel displays such as liquid crystal displays (LCDs), there is no need for long retrace periods during horizontal and vertical blanking, as compared to cathode ray tubes (CRTs). In order to be able to send video that exceeds the bandwidth at the maximum rate of some interface protocol versions,

[0009] VESA (Video Electronics Standards Association) has added the video timing standard of Reduced Blanking. Because Htotal_time = Htotal x T_Pixel_clk, while ensuring that the total time of a row remains unchanged, by reducing the value of Htotal, the period of Pixel_clk can be increased, thereby reducing the frequency of Pxiel_clk, and achieving the purpose of reducing the bandwidth required for transmission. Among them, Hactive (effective pixels) cannot be reduced, only Hblank can be reduced, that is, blanking is reduced. The reduction of Hblank means that the proportion of Hactive in Htotal increases. Under the condition of unchanged high-speed rate, the bandwidth utilization rate of the corresponding transmission interface at high speed will be improved.

[0010] For example, based on DP1.4, 1lane has a maximum transmission rate of 8.1Gbps for 3840x2160@30hz (Htotal=4400, Hactive=3840, Hblank=560, pixel_clk=297Mhz) 24bpp video. Because the DP1.4 protocol uses 8b10b encoding, the bandwidth is 810MBps, which is less than the 891MBps required for 4K30hz transmission. If ReducedBlanking is used, Hblank is reduced from 560 to 86, and the reduced Htotal is 3926, the corresponding Pixel_Freq = 265M, and the bandwidth required for transmission is reduced to 265x24 / 8=795MBps, which can be transmitted. For details, see Figure 2 .

[0011] VESA's DMT (Display Mode Timing) contains predefined Reduced Blanking standards that can be used for standard timing in Extended Display Identification Data (EDID) or DTD (Display Transfer Data). The VESA CVT formula provides the option to create two levels of Reduced Blanking timings that can be used in DTD (Display Transfer Data).

[0012] Disadvantages of Reduced Blanking in Existing Technology:

[0013] 1. The video timing input to the transmitter also needs to be the video timing of RB;

[0014] 2. Poor compatibility. Not all EDID receiving display devices support RB video timing.

[0015] 3. Increase the complexity, the sender needs to tell the receiver that the video timing of RB is being transmitted. Summary of the invention

[0016] The purpose of the present invention is to provide a high bandwidth utilization transmission method and system for a video transmission interface in view of the deficiencies in the prior art.

[0017] To achieve the above object, in a first aspect, the present invention provides a high bandwidth utilization transmission method for a video transmission interface, comprising:

[0018] Identify the timing of standard video data, and extract valid data and video parameter information of the standard video data, wherein the video parameter information includes the number of valid pixels in a row, the total number of pixels in a row, the number of valid rows in a frame, the total number of rows in a frame, row synchronization, row synchronization leading edge, row synchronization trailing edge, field synchronization, field synchronization leading edge, and field synchronization trailing edge;

[0019] Receive the valid data and video parameter information, and cache the valid data in a sending buffer memory, and generate a sending buffer memory ready signal, and at the same time take the number of valid pixels in a row as the total data amount of a row, and in the process of reading data from the buffer memory, monitor the amount of data read, and generate a start signal and an end signal of a row according to the amount of data read, and then send the video parameter information, the sending buffer memory ready signal, the start signal and the end signal;

[0020] Receive the video parameter information, send a buffer memory ready signal, a start signal and an end signal, and read the cached valid video data from the buffer memory when receiving the send buffer memory ready signal, and encapsulate the valid video data and the video parameter information according to the set interface protocol data structure according to the start signal and the end signal to obtain a parameter data packet and a valid video data packet corresponding to the set interface protocol respectively;

[0021] Performing physical layer encoding on the encapsulated parameter data packet and valid video data packet according to the physical layer requirements of the interface protocol;

[0022] Send the encoded data through the serial interface;

[0023] Receiving data sent by the serial interface;

[0024] Perform physical layer decoding on the received data according to the physical layer requirements of the interface protocol to obtain parameter data packets and valid video data packets;

[0025] Decapsulate the parameter data packet and valid video data packet obtained by physical layer decoding according to the set interface protocol data structure to obtain valid video data and video parameter information, and send the decapsulated valid video data and video parameter information;

[0026] Receive the valid video data and video parameter information obtained by decapsulation, and cache the valid video data obtained by decapsulation in a receiving buffer memory, generate a receiving buffer memory ready signal when the cache reaches a set data amount threshold, and then send the video parameter information and the receiving buffer memory ready signal;

[0027] receiving video parameter information, and calculating a pixel clock frequency according to the received video parameter information;

[0028] The receiving buffer memory ready signal is received, and the cached valid video data is read from the receiving buffer memory, and then the standard video data is restored and generated according to the video parameter information, the pixel clock frequency and the valid video data.

[0029] Furthermore, the set interface protocol includes any one of DP protocol, eDP protocol, HDMI protocol, MIPI protocol, LVDS protocol and TTL protocol.

[0030] Furthermore, the pixel clock frequency is calculated as follows:

[0031] Pixel_Freq=Htotal*Vtotal*Frame_rate

[0032] Frame_rate=1s / t_Vsync

[0033] Among them, Pixel_Freq is the calculated pixel clock frequency, Htotal is the total number of pixels in a row, Vtotal is the total number of rows in a frame, Frame_rate is the frame rate, and t_Vsync is the time interval of the Vsync signal.

[0034] Furthermore, the set data volume threshold is the number of valid pixels in a row minus the amount of data sent by the serial interface in a time corresponding to the number of valid pixels in a row of a standard video timing.

[0035] In a second aspect, the present invention provides a high bandwidth utilization transmission system for a video transmission interface, comprising a transmitting end and a receiving end, wherein the transmitting end comprises:

[0036] A video processing module, for identifying the timing of standard video data, and extracting valid data and video parameter information of the standard video data, wherein the video parameter information includes the number of valid pixels in a row, the total number of pixels in a row, the number of valid rows in a frame, the total number of rows in a frame, row synchronization, row synchronization leading edge, row synchronization trailing edge, field synchronization, field synchronization leading edge and field synchronization trailing edge;

[0037] A first cache data volume control module is used to receive the valid data and video parameter information, cache the valid data in a sending buffer memory, generate a sending buffer memory ready signal, and use the number of valid pixels in a row as the total data volume of a row. During the data reading process of the buffer memory, the read data volume is monitored, and a start signal and an end signal of a row are generated according to the read data volume, and then the video parameter information, the sending buffer memory ready signal, the start signal and the end signal are sent out.

[0038] A data protocol layer packetization module, for receiving the video parameter information, sending a buffer memory ready signal, a start signal and an end signal, and reading cached valid video data from the buffer memory when receiving the send buffer memory ready signal, and encapsulating the valid video data and the video parameter information according to the set interface protocol data structure according to the start signal and the end signal, so as to obtain a parameter data packet and a valid video data packet corresponding to the set interface protocol respectively;

[0039] A physical layer encoding module is used to perform physical layer encoding on the encapsulated parameter data packets and valid video data packets according to the physical layer requirements of the interface protocol;

[0040] A sending module, used to send the encoded data through a serial interface;

[0041] The receiving end comprises:

[0042] A receiving module, used for receiving data on the serial interface;

[0043] A physical layer decoding module is used to perform physical layer decoding on the received data according to the physical layer requirements of the interface protocol to obtain parameter data packets and valid video data packets;

[0044] The data protocol layer unpacking module is used to unpack the parameter data packet and the valid video data packet obtained by decoding the physical layer according to the set interface protocol data structure to obtain the valid video data and video parameter information, and send out the unpacked valid video data and video parameter information;

[0045] A second cache data volume control module is used to receive the valid video data and video parameter information obtained by decapsulation, and cache the valid video data obtained by decapsulation into a receiving buffer memory, generate a receiving buffer memory ready signal when the cache reaches a set data volume threshold, and then send out the video parameter information and the receiving buffer memory ready signal;

[0046] A pixel clock recovery module, used for receiving video parameter information and calculating a pixel clock frequency according to the received video parameter information;

[0047] The video recovery module is used to receive the ready signal of the receiving buffer memory, read the cached valid video data from the receiving buffer memory, and then recover and generate standard video data according to the video parameter information, pixel clock frequency and valid video data.

[0048] Furthermore, the set interface protocol includes any one of DP protocol, eDP protocol, HDMI protocol, MIPI protocol, LVDS protocol and TTL protocol.

[0049] Furthermore, the pixel clock frequency is calculated as follows:

[0050] Pixel_Freq=Htotal*Vtotal*Frame_rate

[0051] Frame_rate=1s / t_Vsync

[0052] Among them, Pixel_Freq is the calculated pixel clock frequency, Htotal is the total number of pixels in a row, Vtotal is the total number of rows in a frame, Frame_rate is the frame rate, and t_Vsync is the time interval of the Vsync signal.

[0053] Furthermore, the set data volume threshold is the number of valid pixels in a row minus the amount of data sent by the serial interface in a time corresponding to the number of valid pixels in a row of a standard video timing.

[0054] Beneficial effects: 1. When the interface bandwidth is insufficient when transmitting the standard video timing of CTA (Consumer Technology Association) or VESA (Video Electronics Standards Association), the present invention uses the serial interface to send valid data during the blanking period of the video to realize the utilization of idle bandwidth, thereby improving the bandwidth utilization rate. The bandwidth required for video input only needs to consider that the effective data bandwidth is not greater than the interface transmission bandwidth;

[0055] 2. The video timing input to the transmitter is the standard CTA timing and VESA timing, and the receiver can restore the standard CTA timing and VESA timing, simplifying the system design and improving compatibility;

[0056] 3. It is suitable for transmission of fixed-speed interfaces such as DP, eDP, HDMI, MIPI, LVDS, TTL, etc. It can support physical layer data encoding and meet the requirements of DC balancing of high-speed links, such as 8b10b encoding and decoding in DP protocol and 16b / 18b encoding and decoding in HDMI protocol. It also supports physical layer scrambling and descrambling algorithms and FEC (Forward Error Correction) error correction algorithms; it may not support physical layer data encoding, such as the high-speed transmission mode in MIPI protocol to directly package valid data for transmission; it can also support LVDS and TTL interfaces to use fixed-speed mode to transmit video data. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a schematic diagram of a video transmission method in the prior art;

[0058] Figure 2 is a schematic diagram of a video transmission method for reducing blanking in the prior art;

[0059] Figure 3 is a schematic diagram of a high bandwidth utilization transmission method for a video transmission interface of the present application;

[0060] Figure 4 is a principle block diagram of a high bandwidth utilization transmission system for a video transmission interface of the present application;

[0061] Figure 5 is a schematic diagram of Case 1 of the present application;

[0062] Figure 6 It is a transmission schematic diagram of Case 2 of this application;

[0063] Figure 7 This is a transmission diagram of Case 3 of this application. DETAILED DESCRIPTION

[0064] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The embodiments are implemented based on the technical solution of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0065] See also Figure 3 The embodiment of the present invention provides a high bandwidth utilization transmission method for a video transmission interface, comprising:

[0066] The timing of standard video data is identified, and the valid data (DataEable) and video parameter information of the standard video data are extracted. The video parameter information includes the number of valid pixels in a line (Hactive), the total number of pixels in a line (Htotal), the number of valid lines in a frame (Vactive), the total number of lines in a frame (Vtotal), line synchronization (Hsync), line synchronization leading edge (Hfront), line synchronization back edge (Hback), field synchronization (Vsync), field synchronization leading edge (Vfront) and field synchronization back edge (Vback).

[0067] Receive valid data and video parameter information, cache the valid data into the transmit buffer memory (buffer), generate a transmit buffer memory ready signal (tx_buffer_ready), and use the number of valid pixels in a row as the total data amount of a row. During the data reading process of the buffer memory, monitor the amount of data read, and generate a start signal (h_begin) and end signal (h_end) of a row based on the amount of data read. Then send out the video parameter information, transmit buffer memory ready signal, start signal and end signal.

[0068] Receive video parameter information, send buffer memory ready signal, start signal and end signal, and read cached valid video data from the buffer memory when receiving the send buffer memory ready signal, and encapsulate the valid video data and video parameter information according to the set interface protocol data structure according to the start signal and the end signal, so as to obtain the parameter data packet and the valid video data packet corresponding to the set interface protocol. The above-mentioned set interface protocol includes any one of the video transmission protocols such as DP (display port) protocol, eDP (embedded display port) protocol, HDMI (high definition multimedia interface) protocol, MIPI (mobile industry processor interface) protocol, LVDS (low voltage differential signal) protocol and TTL (transistor-transistor logic level) protocol.

[0069] The encapsulated parameter data packet and valid video data packet are encoded at the physical layer according to the physical layer requirements of the interface protocol.

[0070] The encoded data is sent through the serial interface.

[0071] Receives data sent by the serial interface.

[0072] The received data is decoded at the physical layer according to the physical layer requirements of the interface protocol to obtain parameter data packets and valid video data packets.

[0073] The parameter data packet and valid video data packet obtained by physical layer decoding are decapsulated according to the set interface protocol data structure to obtain valid video data and video parameter information, and the decapsulated valid video data and video parameter information are sent out.

[0074] Receive the valid video data and video parameter information obtained by decapsulation, and cache the valid video data obtained by decapsulation into the receiving buffer memory, generate a receiving buffer memory ready signal (rx_buffer_ready) when the set data volume threshold is cached, and then send out the video parameter information and the receiving buffer memory ready signal. DE is continuous in a row of the standard video timing, and the video data rate during the recovery of DE is higher than the rate of receiving data on the high-speed line, so the above-set data volume threshold is preferably the number of valid pixels in a row - the amount of data sent by the serial interface during the duration (Hactive period) corresponding to the number of valid pixels in a row of the standard video timing, and can also be greater than the amount of data calculated in the above manner.

[0075] Receive video parameter information, and calculate the pixel clock frequency based on the received video parameter information. The video clock recovery method of the present invention no longer depends on the amount of data in the buffer, but requires the time interval between the unpacked video parameter information and the Vsync signal. The specific calculation method is as follows:

[0076] Pixel_Freq=Htotal*Vtotal*Frame_rate

[0077] Frame_rate=1s / t_Vsync

[0078] Among them, Pixel_Freq is the calculated pixel clock frequency, Htotal is the total number of pixels in a row, Vtotal is the total number of rows in a frame, Frame_rate is the frame rate, and t_Vsync is the time interval of the Vsync signal.

[0079] The buffer memory is ready and the cached valid video data is read from the receiving buffer memory, and then the standard video data is restored according to the video parameter information, pixel clock frequency and valid video data. The structure of the above standard video data is CLK / VS / HS / DE / DATA signal, where CLK represents the clock, VS represents the frame synchronization, HS represents the line synchronization, DE represents the data is valid, and DATA is the video valid data.

[0080] See also Figure 4Based on the above embodiments, those skilled in the art can easily understand that the present invention also provides a high bandwidth utilization transmission system for a video transmission interface, including a transmitting end 1 and a receiving end 2. The transmitting end includes a video processing module 11, a first cache data volume control module 12, a data protocol layer packetization module 13, a physical layer encoding module 14 and a transmitting module 15. The receiving end 2 includes a receiving module 21, a physical layer decoding module 22, a data protocol layer unpacking module 23, a second cache data volume control module 24, a pixel clock recovery module 25 and a video recovery module 26.

[0081] The video processing module 11 is used to identify the timing of standard video data and extract valid data (Data Eable) and video parameter information of the standard video data. The video parameter information includes the number of valid pixels in a row (Hactive), the total number of pixels in a row (Htotal), the number of valid rows in a frame (Vactive), the total number of rows in a frame (Vtotal), row synchronization (Hsync), row synchronization leading edge (Hfront), row synchronization trailing edge (Hback), field synchronization (Vsync), field synchronization leading edge (Vfront) and field synchronization trailing edge (Vback).

[0082] The first cache data volume control module 12 is used to receive valid data and video parameter information, cache the valid data into a transmit buffer memory (buffer), and generate a transmit buffer memory ready signal (tx_buffer_ready). At the same time, the number of valid pixels in a row is used as the total data volume of a row. During the data reading process of the buffer memory, the read data volume is monitored, and a start signal (h_begin) and an end signal (h_end) of a row are generated according to the read data volume, and then the video parameter information, the transmit buffer memory ready signal, the start signal and the end signal are sent out.

[0083] The data protocol layer packetization module 13 is used to receive video parameter information, send a buffer memory ready signal, a start signal and an end signal, and read the cached valid video data from the buffer memory when receiving the buffer memory ready signal, and encapsulate the valid video data and video parameter information according to the set interface protocol data structure according to the start signal and the end signal, so as to obtain the parameter data packet and the valid video data packet corresponding to the set interface protocol. The above-mentioned set interface protocol includes any one of the video transmission protocols such as DP (display port) protocol, eDP (embedded display port) protocol, HDMI (high definition multimedia interface) protocol, MIPI (mobile industry processor interface) protocol, LVDS (low voltage differential signal) protocol and TTL (transistor-transistor logic level) protocol.

[0084] The physical layer encoding module 14 is used to perform physical layer encoding on the encapsulated parameter data packet and valid video data packet according to the physical layer requirements of the interface protocol.

[0085] The sending module 15 is used to send the encoded data through a serial interface.

[0086] The receiving module 21 is used for receiving data on the serial interface.

[0087] The physical layer decoding module 22 is used to perform physical layer decoding on the received data according to the physical layer requirements of the interface protocol to obtain parameter data packets and valid video data packets.

[0088] The data protocol layer unpacking module 23 is used to unpack the parameter data packet and the valid video data packet obtained by physical layer decoding according to the set interface protocol data structure to obtain valid video data and video parameter information, and send out the unpacked valid video data and video parameter information.

[0089] The second cache data volume control module 24 is used to receive the valid video data and video parameter information obtained by decapsulation, and cache the valid video data obtained by decapsulation into the receiving buffer memory, and generate a receiving buffer memory ready signal (rx_buffer_ready) when the set data volume threshold is cached, and then send out the video parameter information and the receiving buffer memory ready signal. DE is continuous in a row of the standard video timing, and the video data rate during the recovery of DE is higher than the rate of receiving data on the high-speed line, so the above-set data volume threshold is preferably the number of valid pixels in a row-the amount of data sent by the serial interface during the duration (Hactive period) corresponding to the number of valid pixels in a row of the standard video timing, and can also be greater than the amount of data calculated in the above manner.

[0090] The pixel clock recovery module 25 is used to receive the video parameter information and calculate the pixel clock frequency according to the received video parameter information. The video clock recovery method of the present invention no longer depends on the amount of data in the buffer, but requires the time interval between the unpacked video parameter information and the Vsync signal. The specific calculation method is as follows:

[0091] Pixel_Freq=Htotal*Vtotal*Frame_rate

[0092] Frame_rate=1s / t_Vsync

[0093] Among them, Pixel_Freq is the calculated pixel clock frequency, Htotal is the total number of pixels in a row, Vtotal is the total number of rows in a frame, Frame_rate is the frame rate, and t_Vsync is the time interval of the Vsync signal.

[0094] The video recovery module 26 is used to receive the buffer memory ready signal, and read the cached valid video data from the receiving buffer memory, and then recover and generate standard video data according to the video parameter information, the pixel clock frequency and the valid video data. The structure of the above standard video data is CLK / VS / HS / DE / DATA signal, where CLK represents the clock, VS represents the frame synchronization, HS represents the line synchronization, DE represents the data is valid, and DATA is the video valid data.

[0095] For example:

[0096] Case 1: See Figure 5 , CTA 4K@30hz (Htotal=4400, Hactive=3840, Hblank=560, Pixel_Freq=297Mhz) 24bpp video based on DP1.4's 1 lane maximum 8.1Gbps transmission standard. Because the DP1.4 protocol uses 8b10b encoding, the bandwidth is 810MBps. The transmission bandwidth required for 4K@30hz-24bpp is 891MBps, which is greater than the interface transmission bandwidth of 810MBps. The effective data Hactive bandwidth is 3840 / 4400x891=777.6MBps, which is less than 810MBps, so it can be transmitted using the technical solution of this application. The amount of effective data in a row is 3840x24 / 8=11520 bytes, and the serial interface can send 12,000 bytes in one row.

[0097] Case 2: See Figure 6 , based on MIPI DSI's 1 lane maximum 2.5Gbps transmission standard CTA 1080P@60hz (Htotal=2200, Hactive=1920, Hblank=280, Pixel_Freq=148.5Mhz) 18bpp video. The transmission bandwidth required for 1080P@60hz-18bpp is 334.125MBps, which is greater than the interface transmission bandwidth of 312.5MBps. The effective data Hactive bandwidth is 1920 / 2200x148.5=291.6MBps, which is less than 312.5MBps, so it can be transmitted using the technical solution of this application. The amount of effective data in a row is 1920x18 / 8=4320 bytes, and the serial interface can send 4629 bytes in one row.

[0098] Case 3: See Figure 7, CTA 4K@120hz (Htotal=4400, Hactive=3840, Hblank=560, Pixel_Freq=1188Mhz) 24bpp video based on HDMI2.1's 4 lane rate 8Gbps transmission standard. Because the HDMI2.1 protocol uses 16b18b encoding, the corresponding effective bandwidth is 3555.5MBps. The transmission bandwidth required for 4K@120hz-24bpp is 3564MBps, which is greater than the total transmission bandwidth of the interface 3555.5MBps. The effective data Hactive bandwidth is 3840 / 4400x3564=3110.4MBps, which is less than 3555.5MBps, so it can be transmitted using the technical solution of this application. The amount of effective data in a row is 3840x24 / 8=11520 bytes, and 4 lanes can send 13168 bytes in a row of time on the serial interface.

[0099] The above is only a preferred embodiment of the present invention. It should be noted that for ordinary technicians in this technical field, other parts not specifically described belong to the prior art or common knowledge. Several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A high bandwidth utilization transmission method for a video transmission interface, characterized in that: include: Identify the timing of standard video data, and extract valid data and video parameter information of the standard video data, wherein the video parameter information includes the number of valid pixels in a row, the total number of pixels in a row, the number of valid rows in a frame, the total number of rows in a frame, row synchronization, row synchronization leading edge, row synchronization trailing edge, field synchronization, field synchronization leading edge, and field synchronization trailing edge; Receive the valid data and video parameter information, and cache the valid data in a sending buffer memory, and generate a sending buffer memory ready signal, and at the same time take the number of valid pixels in a row as the total data amount of a row, and in the process of reading data from the buffer memory, monitor the amount of data read, and generate a start signal and an end signal of a row according to the amount of data read, and then send the video parameter information, the sending buffer memory ready signal, the start signal and the end signal; Receive the video parameter information, send a buffer memory ready signal, a start signal and an end signal, and read the cached valid video data from the buffer memory when receiving the send buffer memory ready signal, and encapsulate the valid video data and the video parameter information according to the set interface protocol data structure according to the start signal and the end signal to obtain a parameter data packet and a valid video data packet corresponding to the set interface protocol respectively; Performing physical layer encoding on the encapsulated parameter data packet and valid video data packet according to the physical layer requirements of the interface protocol; Send the encoded data through the serial interface; Receiving data sent by the serial interface; Perform physical layer decoding on the received data according to the physical layer requirements of the interface protocol to obtain parameter data packets and valid video data packets; Decapsulate the parameter data packet and valid video data packet obtained by physical layer decoding according to the set interface protocol data structure to obtain valid video data and video parameter information, and send the decapsulated valid video data and video parameter information; Receive the valid video data and video parameter information obtained by decapsulation, and cache the valid video data obtained by decapsulation in a receiving buffer memory, generate a receiving buffer memory ready signal when the cache reaches a set data amount threshold, and then send the video parameter information and the receiving buffer memory ready signal; receiving video parameter information, and calculating a pixel clock frequency according to the received video parameter information; The receiving buffer memory ready signal is received, and the cached valid video data is read from the receiving buffer memory, and then the standard video data is restored and generated according to the video parameter information, the pixel clock frequency and the valid video data.

2. A high bandwidth utilization transmission method for a video transmission interface according to claim 1, characterized in that: The set interface protocol includes any one of DP protocol, eDP protocol, HDMI protocol, MIPI protocol, LVDS protocol and TTL protocol.

3. A high bandwidth utilization transmission method for a video transmission interface according to claim 1, characterized in that: The set data volume threshold is the number of valid pixels in a row minus the amount of data sent by the serial interface in a time corresponding to the number of valid pixels in a row of the standard video timing.

4. A high bandwidth utilization transmission system for a video transmission interface, comprising a transmitting end and a receiving end, characterized in that: The transmitting end comprises: A video processing module, for identifying the timing of standard video data, and extracting valid data and video parameter information of the standard video data, wherein the video parameter information includes the number of valid pixels in a row, the total number of pixels in a row, the number of valid rows in a frame, the total number of rows in a frame, row synchronization, row synchronization leading edge, row synchronization trailing edge, field synchronization, field synchronization leading edge and field synchronization trailing edge; A first cache data volume control module is used to receive the valid data and video parameter information, cache the valid data in a sending buffer memory, generate a sending buffer memory ready signal, and use the number of valid pixels in a row as the total data volume of a row. During the data reading process of the buffer memory, the read data volume is monitored, and a start signal and an end signal of a row are generated according to the read data volume, and then the video parameter information, the sending buffer memory ready signal, the start signal and the end signal are sent out. A data protocol layer packetization module, for receiving the video parameter information, sending a buffer memory ready signal, a start signal and an end signal, and reading cached valid video data from the buffer memory when receiving the send buffer memory ready signal, and encapsulating the valid video data and the video parameter information according to the set interface protocol data structure according to the start signal and the end signal, so as to obtain a parameter data packet and a valid video data packet corresponding to the set interface protocol respectively; A physical layer encoding module is used to perform physical layer encoding on the encapsulated parameter data packets and valid video data packets according to the physical layer requirements of the interface protocol; A sending module, used to send the encoded data through a serial interface; The receiving end comprises: A receiving module, used for receiving data on the serial interface; A physical layer decoding module is used to perform physical layer decoding on the received data according to the physical layer requirements of the interface protocol to obtain parameter data packets and valid video data packets; The data protocol layer unpacking module is used to unpack the parameter data packet and the valid video data packet obtained by decoding the physical layer according to the set interface protocol data structure to obtain the valid video data and video parameter information, and send out the unpacked valid video data and video parameter information; A second cache data volume control module is used to receive the valid video data and video parameter information obtained by decapsulation, and cache the valid video data obtained by decapsulation into a receiving buffer memory, generate a receiving buffer memory ready signal when the cache reaches a set data volume threshold, and then send out the video parameter information and the receiving buffer memory ready signal; A pixel clock recovery module, used for receiving video parameter information and calculating a pixel clock frequency according to the received video parameter information; The video recovery module is used to receive the ready signal of the receiving buffer memory, read the cached valid video data from the receiving buffer memory, and then recover and generate standard video data according to the video parameter information, pixel clock frequency and valid video data.

5. A high bandwidth utilization transmission system for a video transmission interface according to claim 4, characterized in that: The set interface protocol includes any one of DP protocol, eDP protocol, HDMI protocol, MIPI protocol, LVDS protocol and TTL protocol.

6. A high bandwidth utilization transmission system for a video transmission interface according to claim 4, characterized in that: The set data volume threshold is the number of valid pixels in a row minus the amount of data sent by the serial interface in a time corresponding to the number of valid pixels in a row of the standard video timing.

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