Memory chip, memory assembly, memory and electronic equipment

Abstract

The invention discloses a storage chip, a storage component, a memory and electronic equipment, which are used for reducing metal resources occupied by power supply wiring. Wherein the memory chip comprises a wafer and an active layer embedded in the wafer, the active layer comprises an active device, the active device is a device in a peripheral circuit of the memory chip, and a first electrode of the active device is in contact with a power supply on the back surface of the wafer or is grounded to realize power supply; and a storage array in the storage chip performs signal routing through metal resources on one side of the active surface of the wafer. Because the peripheral circuit and the storage array are distributed at different positions of the storage chip, the scheme of back power supply in the peripheral circuit can not influence the storage device in the storage array, thereby saving the metal resource which is originally used as the power supply wire at one side of the active surface of the wafer on the basis of keeping the read-write function of the storage chip, and reducing the cost. And the input and output line channels of the storage array in the storage chip are expanded, so that the bandwidth of the storage chip is increased.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory chip, a memory component, a memory and an electronic device. Background Art

[0002] In recent years, with the in-depth development of technologies such as intelligence, digitization and informatization, the demand for memory bandwidth in various fields has continued to increase. Among many memory products, random access memory (RAM) has become increasingly popular in the market due to its advantages such as fast access speed, low data loss, high integration and low power consumption, and has gradually become the mainstream technical solution in the memory field.

[0003] However, in traditional memory, power lines occupy a considerable proportion of each metal layer structure. For example, taking traditional dynamic random access memory (DRAM) as an example, its metal layer structure from bottom to top is generally W / Cu / Cu / Al, such as Figure 1a As shown, or W / Cu / Cu / Cu / Al, such as Figure 1b As shown. Among them, the surface of the first dielectric layer where W is located is all used for signal lines; about 20% of the lines on the surface of the second dielectric layer where Cu is located are used as power lines, while the local input / output (LIO) lines that affect the memory bandwidth account for only 5%; about 75% of the lines on the surface of the third dielectric layer where Cu is located are used as power lines, while the main input / output (MIO) lines that affect the memory bandwidth account for only 27%; if the surface of the fifth dielectric layer where Cu is located exists, it is all used for power lines; the surface of the fourth dielectric layer where Al is located is mainly used for packaging and introducing power lines and signal lines. It can be seen that in traditional DRAM, a large number of metal layer lines are used as power lines, while the LIO lines and MIO lines related to the memory bandwidth only account for a small part. A large number of power lines limit the expansion of LIO lines and MIO lines, and then limit the expansion of memory bandwidth, making high bandwidth memory (HBM) more and more difficult to achieve.

[0004] In summary, how to reduce the metal resources occupied by power lines is a technical problem that needs to be urgently solved in the field of memory technology. Summary of the invention

[0005] The present application provides a memory chip, a memory component, a memory and an electronic device for reducing the metal resources occupied by power lines.

[0006] In a first aspect, the present application provides a memory chip, comprising a wafer and an active layer buried in the wafer, the active layer comprising active devices, the active devices being devices in the peripheral circuit of the memory chip, the first electrode of the active device being powered by contacting a power source or ground on the back side of the wafer, and the memory array in the memory chip being wired for signals through metal resources on one side of the active surface of the wafer.

[0007] In the above design, by connecting the power supply signal from the back of the wafer to the active devices in the peripheral circuit of the memory chip, the metal resources originally used for power routing can be saved on the active side of the wafer, and these metal resources can be used to expand the IO lines of the storage array in the memory chip, thereby increasing the bandwidth of the memory chip. In addition, since the peripheral circuit and the memory array are distributed in different positions of the memory chip, the solution of setting the back power supply in the peripheral circuit will not affect the storage devices in the memory array, so that the solution can increase the bandwidth of the memory chip while maintaining the read and write functions of the memory chip.

[0008] In a possible design, the peripheral circuit may include a driving circuit, and the active device may be a device in the driving circuit, such as a device to be powered in the driving circuit stored in the hole area. In this way, by providing a contact hole in the hole area, the power supply signal is connected from the back side of the wafer to the driving circuit in the hole area, which can provide a strong power supply network for the driving circuit and realize the driving capability of the driving circuit.

[0009] In one possible design, there are many ways for the first electrode of the active device to contact the power or ground on the back side of the wafer, such as:

[0010] In design method 1, the memory chip may also include a dielectric layer structure disposed on the active surface of the wafer and a first metal disposed in the dielectric layer structure. The first electrode of the active device contacts the first metal through the first contact hole. The first metal also penetrates through the second contact hole to the back of the wafer and is connected to the power supply or ground. In this way, the power supply signal provided by the power supply or ground can be transmitted to the active device through the second contact hole, the first metal and the first contact hole in sequence, thereby realizing the connection between the active device and the power supply or ground.

[0011] In the second design, the wafer may include a third contact hole, one end of the third contact hole contacts the first electrode, and the other end of the third contact hole penetrates to the back of the wafer and is connected to the power supply or ground. In this way, the power supply signal provided by the power supply or ground can be directly transmitted to the active device through the third contact hole, thereby realizing the connection between the active device and the power supply or ground.

[0012] Optionally, in the above-mentioned design method 1, the contact area between the second contact hole and the first metal can be partially projected onto the first area, which is an area for storing the driving circuit in the memory chip, such as the Hole area. In this way, by introducing the second contact hole in the Hole area, the power supply network can be completely placed under the active device, which can not only provide a strong power supply network for various driving circuits in the Hole area, but also can not affect the layout of the memory array and other peripheral circuits in the memory chip, and avoid affecting the storage function in the memory chip.

[0013] Optionally, in the above-mentioned design mode 1, the dielectric layer structure may include at least two dielectric layers, and the first metal may be disposed in any intermediate dielectric layer except the uppermost dielectric layer, for example:

[0014] In a possible configuration, the dielectric layer structure may include a first dielectric layer, the first dielectric layer is located at the bottom layer of the dielectric layer structure, other dielectric layers may be stacked on the first dielectric layer, and the first metal is disposed on the surface of the first dielectric layer. In this way, power supply lines on the surfaces of other dielectric layers stacked on the first dielectric layer may be saved.

[0015] In another possible configuration, the dielectric layer structure includes a first dielectric layer and a second dielectric layer, the first dielectric layer is located at the bottom layer of the dielectric layer structure, the second dielectric layer is stacked above the first dielectric layer, and other dielectric layers may be stacked on the second dielectric layer, the first metal is disposed on the surface of the second dielectric layer, the second metal is disposed on the surface of the first dielectric layer, the first metal contacts the second metal through a first contact hole, and the second metal contacts the first electrode of the active device through a fourth contact hole. In this way, power lines on the surfaces of other dielectric layers stacked on the second dielectric layer can be saved. In addition, although this structure connects the power supply signal to the first metal on the surface of the second dielectric layer, the first metal directly contacts the second metal on the surface of the first dielectric layer through the contact hole. In other words, no power lines may be disposed on the surface of the second dielectric layer. Therefore, this method may also save power lines on the surface of the second dielectric layer.

[0016] It can be understood that the first metal can also be disposed on the surface of other non-top dielectric layers, which are not listed here one by one.

[0017] Optionally, there may be multiple possible structures for the second contact hole in the above-mentioned design mode 1 and the third contact hole in the above-mentioned design mode 2, such as:

[0018] Structure 1: The second contact hole or the third contact hole may include a power supply through hole and a first back metal layer. One end of the power supply through hole contacts the first metal in the above-mentioned design method 1 or the first electrode in the above-mentioned design method 2, and the other end of the power supply through hole penetrates the first back metal layer, and the first back metal layer is connected to the power supply or ground. With this structural design, the first back metal layer can provide a relatively wide plane. In this way, even if multiple active devices are set on the wafer, enough power supply through holes can be led out through the relatively wide plane to achieve the connection between multiple active devices and the power supply or ground, without having to set an external wiring connected to the power supply / ground for each active device, thereby helping to reduce the space occupied by the wiring.

[0019] Structure 2, the second contact hole or the third contact hole includes a power supply through hole, a first back metal layer, a first via hole, and a second back metal layer. The second back metal layer is arranged in the stacking direction of the first back metal layer and is spaced a certain distance from the first back metal layer. One end of the power supply through hole contacts the first metal in the above-mentioned design method 1 or the first electrode in the above-mentioned design method 2, and the other end of the power supply through hole penetrates the second back metal layer. The second back metal layer contacts the first back metal layer through the first via hole, and the first back metal layer is connected to the power supply or the ground. With this structural design, even if the plane provided by the first back metal layer is not sufficient to supply all active devices on the wafer, the second back metal layer can be expanded through the first via hole, so that two back metal layers are used to support more active devices on the wafer.

[0020] It can be understood that the second contact hole or the third contact hole may also include at least three back metal layers, which are not listed here one by one.

[0021] Further optionally, the first back metal layer or the second back metal layer may be spread over the back of the wafer, and the power supply via may be partially projected on the first area, such as only projecting the first area, wherein the first area is the area where the drive circuit in the memory chip is stored, such as the Hole area. In this way, not only can a strong power supply network be provided for various drive circuits in the Hole area, but the power supply via can also be completely placed under the drive circuit. Since the drive circuit and the memory array and other peripheral circuits are located in different areas, the power supply via located under the drive circuit will not affect the memory array and other peripheral circuits, thereby ensuring that the functions of the memory array and other peripheral circuits are not affected.

[0022] In a possible design, when the active device is a P-channel metal oxide semiconductor field effect transistor (PMOSFET), the first electrode can be a source, and the first electrode is powered by contacting a power source. In this way, the power output by the power source can be transmitted from the back side of the wafer to the source of the PMOS, so that the source of the PMOS is kept at a high level.

[0023] In another possible design, when the active device is an N-channel metal oxide semiconductor field effect transistor (NMOSFET), the first electrode can be a drain, and the first electrode is powered by contacting the ground. In this way, the low level of the ground can be transmitted from the back side of the wafer to the drain of the NMOS, so that the drain of the NMOS is kept at a low level.

[0024] In a second aspect, the present application provides a storage component, including a storage array and a peripheral circuit, the peripheral circuit including a storage chip designed in any one of the above-mentioned first aspects, and the peripheral circuit is used to transmit control signals for reading and writing the storage array between the storage array and a controller.

[0025] In a possible design, the peripheral circuit may include a signal enhancement circuit and a drive circuit, and the memory chip in any one of the designs of the first aspect may be located in the drive circuit. The signal enhancement circuit is connected to the memory array to enhance the control signal for reading and writing the memory array; the drive circuit is connected to the signal enhancement circuit to enhance the power supply of the signal enhancement circuit.

[0026] In a further possible design, the signal enhancement circuit may include a sub word line driver (SWD) circuit and a sense amplifier (SA) circuit, the SWD circuit and the SA circuit are located in the peripheral area of ​​the memory array, and the driving circuit is located in the intersection area of ​​the SWD circuit and the SA circuit.

[0027] In a further possible design, the memory array may include M×N memory cells, M word lines and N bit lines, and the M×N memory cells are located at the intersection of the M word lines and the N bit lines, where M and N are positive integers. The SWD circuit is connected to the M word lines to enhance the control signal transmitted on the enabled word lines; and the SA circuit is connected to the N bit lines to enhance the control signal transmitted on the enabled bit lines.

[0028] In a third aspect, the present application provides a memory, comprising a controller and a storage component as in any one of the designs of the second aspect, wherein the controller is connected to the storage component for performing read and write operations on the storage component.

[0029] In a fourth aspect, the present application provides an electronic device, comprising a processor and a memory as described in the third aspect above, wherein the processor and the memory are connected via an IO bus, and the processor is used to read and write data in the memory via the IO bus.

[0030] The beneficial effects of any design in the second to fourth aspects mentioned above can refer to the beneficial effects that can be achieved by the corresponding design in the first aspect mentioned above, and this application will not repeat them one by one. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1a A schematic diagram of the structure of a DRAM is shown as an example;

[0032] Figure 1b A schematic diagram showing the structure of another DRAM is shown as an example;

[0033] Figure 2a A schematic diagram showing an application scenario of a storage device to which the present application is applicable;

[0034] Figure 2b A schematic diagram of an application scenario of a terminal device provided by the present application is exemplified;

[0035] Figure 3a The structural diagram of a PMOS provided by the present application is exemplified;

[0036] Figure 3b The schematic diagram of the structure of an NMOS provided by the present application is exemplified;

[0037] Figure 4 A schematic diagram showing the structure of a memory chip provided by the present application is exemplified;

[0038] Figure 5 A schematic diagram of a partition structure of a wafer provided by the present application is exemplarily shown;

[0039] Figure 6a A schematic diagram showing the structure of another memory chip provided by the present application is exemplified;

[0040] Figure 6b A schematic diagram showing the structure of another memory chip provided by the present application is exemplified;

[0041] Figure 6c A schematic diagram showing the structure of another memory chip provided by the present application is exemplified;

[0042] Figure 7A schematic diagram showing the structure of another memory chip provided by the present application is exemplified;

[0043] Figure 8a A schematic diagram of the structure of a second contact hole provided by the present application is exemplarily shown;

[0044] Figure 8b A schematic diagram showing the structure of another second contact hole provided by the present application is exemplified;

[0045] Figure 8c A schematic diagram showing a structure of another second contact hole provided by the present application is exemplified;

[0046] Figure 9a A schematic diagram of a deformed structure of a memory chip provided by the present application is exemplarily shown;

[0047] Figure 9b A schematic diagram showing a deformed structure of another memory chip provided by the present application is exemplified;

[0048] Fig.10a An exemplary circuit structure diagram of an inverter provided by the present application is shown;

[0049] Fig.10b An exemplary three-dimensional layout structure diagram of an inverter provided by the present application is shown;

[0050] Fig.10c An exemplary plan view of an inverter provided by the present application is shown;

[0051] Fig.11 A circuit comparison schematic diagram for expanding the saved power supply wiring into IO wiring provided by the present application is exemplarily shown;

[0052] Fig.12 A schematic diagram showing a functional framework of a storage component provided by the present application is exemplified;

[0053] Fig.13 A schematic diagram showing a functional framework of a memory provided by the present application is exemplified;

[0054] Fig.14 The functional framework diagram of an electronic device provided by the present application is exemplified. DETAILED DESCRIPTION

[0055] The following is an introduction to possible application scenarios of this application.

[0056] In one possible application scenario, the memory chip in the present application may be integrated into a memory, such as a random access memory (RAM), which may be a DRAM or a static random access memory (SRAM). In some examples, the memory may also be integrated into a chip or device together with the processor. The chip may be, for example, a system on chip (SOC) chip. The device may be a device with only read and write functions, such as Figure 2a The storage device shown may be, for example, a disk, a hard disk, or a memory. Alternatively, the device may also be a device having a read and write function and other functions, such as Figure 2b The terminal device shown may include, for example, but is not limited to, a smart phone, a desktop computer, a wearable device (such as a smart helmet or a smart watch), a vehicle-mounted device, a notebook computer, a laptop computer, etc.

[0057] It should be understood that the possible application scenarios given above are only examples, and the memory chip provided in this application can also be applied to other possible scenarios, not limited to the scenarios given in the examples above, such as sensors, integrated circuits (ICs), etc.

[0058] The above text introduces the possible application scenarios of the present application, and the following is an explanation of some terms in the present application. It should be noted that these explanations are for the convenience of understanding by those skilled in the art, and do not constitute a limitation on the scope of protection claimed by the present application.

[0059] 1. Metal oxide semiconductor field effect transistor (MOSFET)

[0060] MOSFET is a field effect transistor widely used in memory. According to the polarity of its channel, it can be divided into "N-type" and "P-type", usually called NMOSFET and PMOSFET, sometimes also referred to as NMOS and PMOS. Any MOS in NMOS and PMOS includes three electrodes, namely source (source, S), drain (drain, D) and gate (gate, G). By applying a control signal between the gate G and the source S, the conduction and cutoff between the drain D and the source S can be changed. Among them, PMOS can usually be used to connect to the power supply, for example, see Figure 3a, the source S of the PMOS can be connected to the power supply VDD, the gate G of the PMOS can be connected to the signal input terminal, and the drain D of the PMOS can be connected to the signal output terminal. i When the input signal V is low, the source S and drain D of the PMOS are connected, so that the high level of the power supply VDD can be output from the drain D of the PMOS through the turned-on PMOS. i When the voltage is high, the source S and drain D of the PMOS are cut off, the PMOS is disconnected, and the drain D of the PMOS does not output a signal. Corresponding to the PMOS, the NMOS can usually be used to connect to the ground power supply, for example, see Figure 3b , the drain D of NMOS can be connected to the ground power supply VSS, the gate G of NMOS can be connected to the signal input terminal, and the source S of NMOS can be connected to the signal output terminal. i When the input signal is at a high level, the source S and drain D of the NMOS are connected, so that the low level of the ground power supply VSS can be output from the source S of the NMOS through the turned-on NMOS. Conversely, when the input signal is at a low level, the source S and drain D of the NMOS are cut off, the NMOS is disconnected, and the source S of the NMOS does not output a signal.

[0061] 2. Contact hole (CT) and through via (TV)

[0062] Contact holes can be considered as structures used to connect front-end devices and back-end metals in the back-end of line (BONL) process of semiconductor device manufacturing, and vias can be considered as structures used to connect different layers in semiconductor device manufacturing. Among them, the manufacturing process of semiconductor devices is divided into front-end of line (FONL) process and BONL process. FONL process refers to the process of preparing wafers and active devices in semiconductor devices, and BONL process refers to the process of preparing metal layer structures, such as Figure 1a or Figure 1b The process of the first to fourth dielectric layers and the metal on their surfaces is shown.

[0063] As described in the background technology, most of the metal layer structures in existing memories are occupied by power lines, which limits the expansion of IO lines (such as LIO lines and MIO lines), thereby limiting the expansion of memory bandwidth. The reason for this problem is that existing memories are connected from the top dielectric layer (such as Figure 1a or Figure 1bIn order to realize the power supply to the active devices in the wafer, it is necessary to set power lines on the surface of each dielectric layer so that the initial power lines introduced from the fourth dielectric layer can be connected to the active devices in the wafer after passing through the power lines on each dielectric layer and the contact holes between the metal surfaces of each dielectric layer.

[0064] In view of this, the present application provides a memory chip, which adjusts the power routing in the traditional memory chip and connects the power supply signal from the back side of the wafer to the active devices in the peripheral circuit of the memory chip, thereby saving more metal routing resources on the active side of the wafer to expand the IO lines corresponding to the storage array, thereby increasing the bandwidth of the memory chip.

[0065] It should be noted that although the Interuniversity Microelectronics Centre (IMEC) proposed the backside power delivery network (BSPDN) technology in 2019, the BSPDN technology is proposed for logic devices, which usually contain 15 to 20 metal layers (excluding the top metal layer used to introduce signals or power), and most of the devices that need power are scattered over the entire surface of the wafer. Therefore, the BSPDN technology proposes to move the power supply of all devices to be powered in the logic device to the back of the wafer to save the power supply voltage drop through 15 to 20 metal layers, thereby reducing power supply loss and cost. However, there are significant differences in structure between memory and logic devices. For example, the memory usually has only 3 to 4 metal layers, and the power supply voltage drop, power loss and cost of powering through 3 to 4 metal layers are not very high. Therefore, there is no need to perform back power supply in order to save power supply loss and cost. It is just considered that if the power routing is moved to the back of the wafer, the metal resources used as power routing in the traditional memory can be saved and used to expand more IO routing, so as to achieve the purpose of increasing bandwidth. Therefore, this application applies BSPDN technology in the memory. In addition, the structure of the memory is more complicated than that of the logic device. For example, some areas in the memory are placed with storage arrays, some areas are placed with driving circuits, and some areas are placed with signal enhancement circuits. Different devices are placed in each area. Some of these devices need power supply, and some devices do not need power supply. Therefore, when designing the back power supply of the memory, it is not as simple as applying the back power supply solution of the logic device to the memory. It is also necessary to consider how to layout the back power supply structure, such as where to place the back power supply structure, so as to achieve the back power supply while not affecting the signal routing and functions of other devices in the memory. This is the difficulty in the back power supply design of the memory.

[0066] In view of this, when designing the back power supply scheme of the memory, the inventor took into account that the memory array of the memory contains a large number of memory devices, and these memory devices interact with various signals through complex signal routing on the active side of the wafer to realize the data reading and writing functions of the memory. Therefore, in order to avoid affecting the memory devices in the memory array, the present application can only set the corresponding back power supply structure for the peripheral circuit of the memory, and does not set the back power supply structure for the memory array. Since the peripheral circuit and the memory array are distributed in different positions of the memory, the scheme of setting the back power supply structure in the peripheral circuit will not affect the memory devices in the memory array. Therefore, the scheme can save the metal resources originally used for the power supply of the peripheral circuit on the basis of maintaining the reading and writing functions of the memory, and these saved metal resources can also be expanded to new signal routing corresponding to the memory array, such as IO routing, to achieve the purpose of increasing the bandwidth of the memory chip.

[0067] Based on the above content, the following Figure 4 To Attachment Fig.14 , the embodiments of the present application are described in detail.

[0068] like Figure 4 As shown, it is a schematic diagram of the structure of a memory chip provided by the present application. The memory chip includes a wafer 410 and an active layer 420 buried in the wafer 410. The active layer 420 includes an active device 421. The active device 421 is a device in the peripheral circuit of the memory chip. The first electrode P1 of the active device 421 is powered by contacting the power supply or ground on the back of the wafer 410, and the memory array 440 in the memory chip is used for signal routing through the metal resources on the active side of the wafer. Among them, the active layer 420 is buried in the wafer 410, which can be understood as the active layer 420 is buried in the wafer 410 as a whole, and there is a surface exposed on a surface of the wafer 410. This surface of the wafer 410 is called the active surface of the wafer, such as the S1 side shown in the figure. The side opposite to the active surface of the wafer can be called the back of the wafer 410, such as the S0 side shown in the figure. It is understandable that a dielectric layer structure 430 is usually stacked on the active surface of the wafer. Therefore, the active surface of the wafer can also be understood as the surface of the wafer 410 in the stacking direction, and the back side of the wafer 410 can also be understood as the surface of the wafer 410 in the opposite direction of the stacking.

[0069] It should be noted that the power supply in the present application may refer to providing a power supply voltage or providing a ground voltage. For example, when the first electrode P1 of the active device 421 contacts the power supply on the back of the wafer 410, the power supply refers to providing a power supply voltage to the active device 421. When the first electrode P1 of the active device 421 contacts the ground on the back of the wafer 410, the power supply refers to providing a ground voltage to the active device 421.

[0070] In addition, the metal resources on the active surface side of the wafer can be understood as the metal in the dielectric layer structure 430 stacked on the active surface of the wafer and the connecting wires between the metals. Figure 4 The memory array 440 in the memory chip is connected to external signals through contact holes between the memory array 440 and metal 1, metal 1, contact holes between metal 1 and metal 2, metal 2, contact holes between metal 2 and metal 3, metal 3, connecting lines between metal 3 and metal 4, and metal 4. Therefore, the metal resources involved may include metal 1, metal 2, metal 3, metal 4, and connecting lines between metal 3 and metal 4.

[0071] In the present application, there are many solutions for the first electrode P1 to contact the power supply or ground on the back side of the wafer 410, such as:

[0072] For one possible solution, see Figure 4 In (A), the dielectric layer structure 430 includes a first metal M 11 The first electrode P1 of the active device 421 contacts the first metal M through the first contact hole V1. 11 , First Metal M 11 The second contact hole V2 also penetrates through the back of the wafer 410, and then conducts to the power supply or ground. In this way, the voltage signal provided by the power supply or ground can be sequentially transmitted through the second contact hole V2, the first metal M 11 and the first contact hole V1 to the first electrode P1;

[0073] For another possible solution, see Figure 4 In (B), the first electrode P1 of the active device 421 can directly pass through the third contact hole V3 to the back side of the wafer 410 and be connected to the power supply or ground. In this way, the voltage signal provided by the power supply or ground can be directly transmitted to the first electrode P1 through the third contact hole V3.

[0074] It should be noted that in Figure 4 In the scheme shown in (A), the first electrode P1 can be arranged on the top surface or inside of the active device 421, and Figure 4 In the solution shown in (B), the first electrode P1 can be arranged inside the active device or at the bottom as shown in the figure, and there is no specific limitation.

[0075] Understandably, Figure 4 The second contact hole V2 shown in (A) or Figure 4 The third contact hole V3 shown in (B) can be connected to the power supply or ground through a conductive medium, for example, a conductive wire can pass through the packaging interface of the memory chip to connect to an external power supply or contact the memory chip housing.

[0076] Below Figure 4Each functional component and structure involved is introduced and explained separately to provide an exemplary specific implementation scheme.

[0077] 1. Wafer

[0078] Wafer is the abbreviation of semiconductor crystal slices, which are usually cut from substrate materials (such as single crystal silicon) and appear as cylindrical thin slices. Wafers are usually used to prepare devices such as memory, computer chips, and solar cells. For example, storage media and I / O circuits are set on wafers and packaged to form memory. For another example, integrated circuit logic on a wafer can form a computer chip with computing functions. For another example, solar cells can be formed by depositing P-type and N-type films on a wafer. The most common wafers are silicon wafers, gallium nitride wafers, silicon carbide wafers, etc.

[0079] When preparing memory, a wafer is subjected to photolithography, doping and other methods, and lattice-shaped grains are formed on its surface. For example, see Figure 5, each square on the wafer can be considered as a grain, that is, a die, and each die may include multiple Banks and peripheral circuits. Among them, the peripheral circuits may include, for example, decoding circuits and signal conversion circuits, etc., which are used to realize the communication between the die and other dies. It can be understood that the diagram takes the peripheral circuits set in the center row direction of multiple Banks as an example, but the peripheral circuits can also be set at any or multiple positions in the upper, lower, left, right, center, etc., and the arrangement direction can be row direction, column direction, or both row direction and column direction. Furthermore, each Bank may include multiple Mats, and may also include decoders for controlling the storage units in multiple Mats to perform read and write operations, such as row decoders and column decoders. A Mat can be regarded as a rectangular grid array including multiple grids. The rectangular grid array includes a storage array and peripheral circuits located around it, such as a sub wordline driver (SWD) circuit placed in the row direction of the storage array (left and right direction in the figure) and a sense amplifier (SA) circuit placed in the column direction of the storage array (up and down direction in the figure). The SWD circuit and the SA circuit can also be collectively referred to as a signal enhancement circuit. Among them, the storage array may include multiple word lines (WL) and multiple bit lines (BL). A grid is distributed at the intersection of each WL and each BL. The grid is also called a storage unit and is used to store a binary data, such as "1" or "0". The row decoder in each Mat can be connected to the WL of all storage arrays included in the Mat, and the column decoder in each Mat can be connected to the BL of all storage arrays included in the Mat. When it is necessary to read or write data stored in a storage cell in a certain row or column, the row decoder in the Bank to which the storage cell belongs can first send an enable signal to the WL corresponding to the row where the storage cell is located to drive all storage cells on the row where the storage cell is located, and then send an enable signal to the BL corresponding to the column where the storage cell is located to drive the storage cell to turn on, and then perform read and write operations in the enabled storage cell.

[0080] It is understandable that two adjacent memory arrays in the row direction can share a SWD circuit. Figure 5 , a SWD circuit can be divided into a left half and a right half. The SWD circuit corresponding to each storage array includes the right half of the SWD circuit placed on its left side and the left half of the SWD circuit placed on its right side. The SWD circuit can be connected to the WL in the storage array to enhance the start signal sent by the row decoder to the WL so that the start signal can be successfully transmitted to all storage cells on the row corresponding to the WL. Similarly, two adjacent storage arrays in the column direction can share a SA circuit. For example, please continue to refer to Figure 5An SA circuit can be divided into an upper half and a lower half. The SA circuit corresponding to each storage array includes a lower half of the SA circuit placed above it and an upper half of the SA circuit placed below it. The SA circuit can be connected to the BL in the storage array to enhance the start signal sent to the BL by the column decoder, so that the start signal can be successfully transmitted to all storage cells on the column corresponding to the BL.

[0081] In addition, in each Mat, there will be intersections between the SWD circuit and the SA circuit, such as Figure 5 The positions of the four corners, upper left, lower left, upper right and lower right, are usually called hole areas. It should be emphasized that the hole area is not an actual hole, but a physical structure that encapsulates various types of driving circuits. It is generally used to store the driving circuits of key signals used by the SWD circuit and the SA circuit, such as the driving circuit of the PX signal used by the SWD circuit, and the driving circuits of the SAN signal and the SAP signal used by the SA circuit, wherein the SAN signal can be considered as the signal involved in the NMOS in the SA circuit, and the SAP signal can be considered as the signal involved in the PMOS in the SA circuit. Simply put, the hole area can be considered as the driving area of ​​the power supply. The driving circuits in the hole area are respectively connected to the power supply, the SWD circuit and the SA circuit, and are used to use the power provided by the power supply to enhance the power supply of the SWD circuit and the SA circuit, so that the SWD circuit can be driven by sufficient power to enhance the signal of the WL, and the SA circuit can be driven by sufficient power to enhance the signal of the BL.

[0082] It should be noted that the memory chip described in this application can be considered as Figure 5 As shown in a Mat, the memory chip includes a memory array and peripheral circuits, and the peripheral circuits may include a signal enhancement circuit and a driving circuit, wherein the signal enhancement circuit may include the aforementioned SWD circuit and SA circuit, and the driving circuit may include the circuit in the aforementioned Hole area.

[0083] 2. Active Devices

[0084] Exemplarily, the active device 421 may be a device in the drive circuit of the memory chip that needs to be powered, such as Figure 5 The device to be powered in the driving circuit is stored in the hole area shown in FIG. Figure 5Contact holes are set in the hole area of ​​the wafer shown in the figure, and the power supply signal is connected to the driving circuit in the hole area from the back side of the wafer. While providing a strong power supply network to drive the SWD circuit and the SA circuit through the back power supply, it can also not affect the storage devices as well as the SWD circuit and the SA circuit in the storage array. It helps to save the power supply wiring that originally shared the metal wiring resources with the signal on the active side of the wafer while maintaining the storage capacity, and use it to increase the IO line, thereby increasing the memory bandwidth.

[0085] It can be understood that in the Hole region, the driving circuit is usually composed of basic units such as inverters, counters, latches and triggers, and each basic unit is composed of one or more PMOS and / or one or more NMOS. Therefore, PMOS and NMOS can be considered as the smallest constituent units of the driving circuit in the Hole region. Based on this, the active device 421 can be considered as Figure 5 The PMOS or NMOS in the driving circuit is stored in the hole area shown.

[0086] Exemplary, combined together Figure 3a and Figure 4 When the active device 421 is a PMOS, the first electrode P1 may be a source electrode S, and the first metal M 11 It can be connected to the power source VDD on the back side of the wafer 410. In this way, the power output by the power source VDD can be transmitted from the back side of the wafer 410 to the source S of the PMOS, so that the source S of the PMOS is kept at a high level.

[0087] Exemplary, combined together Figure 3b and Figure 4 When the active device 421 is an NMOS, the first electrode P1 may be a drain D, and the first metal M 11 It can be connected to the ground power source VSS on the back side of the wafer 410. In this way, the low level of the ground power source VSS can be transmitted from the back side of the wafer 410 to the drain D of the NMOS, so that the drain D of the NMOS is kept at a low level.

[0088] 3. Dielectric layer structure

[0089] It is understandable that the dielectric layer structure 430 may include at least one dielectric layer. The dielectric layer may also be referred to as a dielectric layer, an interlayer dielectric layer or an inter-dielectric layer (ILD), which is an electrical insulating layer disposed between different layers of a memory chip and functions as an isolation film. Optionally, the dielectric layer may be composed of an oxide, such as silicon dioxide (SiO2).

[0090] For example, multiple blind holes of different sizes can be dug on the surface of any dielectric layer, and these blind holes are used to fill metal. The metal materials filled in a dielectric layer can be consistent or inconsistent. In some scenarios, the metal on the dielectric layer can also be called a metal plug, which is an electrode with conductive ability. Its implementation material may include copper, cobalt, tungsten, rubidium or other metal materials with strong conductivity.

[0091] It can be understood that when the first electrode P1 is Figure 4 When the power supply or ground on the back of the wafer 410 is connected in the manner shown in (B), no power supply wiring is required in the entire dielectric layer structure 430. However, when the first electrode P1 is connected in accordance with Figure 4 When the power supply or ground on the back of the wafer 410 is connected in the manner shown in (A), the power supply wiring required to be set in the dielectric layer structure 430 is connected to the first metal M 11 For example, the memory chip belongs to Figure 1a Taking the DRAM shown as an example, assuming that the dielectric layer structure 430 includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer stacked in sequence, considering that the surface of the first dielectric layer is entirely used for signal lines, and the fourth dielectric layer is used as a packaging layer, these two dielectric layers basically do not carry power lines. At present, most of the power lines are basically distributed in the second dielectric layer and the third dielectric layer. Therefore, the power supply signal can be connected to the metal on the surface of any dielectric layer in the first dielectric layer or the second dielectric layer from the back side of the wafer 410 to save the power lines in the second dielectric layer and / or the third dielectric layer.

[0092] Below through Figures 6a to 6c The connection method between the first electrode P1 and the power supply or ground is described in detail. It should be noted that, in order to facilitate the introduction of the scheme, Figures 6a to 6c The storage array and corresponding signal routing in the storage chip are omitted.

[0093] In one possible implementation, see Figure 6a , First Metal M 11 The first dielectric layer 431 may be provided on the surface of the first dielectric layer 431. In this way, the voltage signal of the power supply / ground can pass through the second contact hole V2 and the first metal M on the first dielectric layer 431. 11 This method can save power lines on the surfaces of other dielectric layers above the first dielectric layer 431 , such as the power lines on the surfaces of the second dielectric layer 432 and the third dielectric layer 433 .

[0094] In another possible implementation, see Figure 6b , First Metal M 11 The second dielectric layer 432 may be provided on the surface of the second dielectric layer 432, and the second metal M may be provided on the surface of the first dielectric layer 431.21 , First Metal M 11 The second metal M is contacted through the first contact hole V1 21 , the second metal M 21 The first electrode P1 of the active device 421 is contacted through the fourth contact hole V4. In this case, the voltage signal of the power supply / ground can be transmitted through the second contact hole V2 and the first metal M on the second dielectric layer 432. 11 , the first contact hole V1, the second metal M on the first dielectric layer 432 21 and the fourth contact hole V4 to the first electrode P1 of the active device 421. Although this method connects the power supply signal to the surface metal of the second dielectric layer 432, the surface metal directly contacts the surface metal of the first dielectric layer 431 through the contact hole. Therefore, this method can also save the power supply wiring on the surface of other dielectric layers above the first dielectric layer 431.

[0095] Similarly, if the memory chip belongs to Figure 1b In the DRAM shown in FIG. 4 , the dielectric layer structure 430 further includes a fifth dielectric layer stacked between the third dielectric layer and the fourth dielectric layer. In this case, the power supply lines are not only distributed in the second dielectric layer and the third dielectric layer, but the entire surface of the fifth dielectric layer is also used as the power supply lines. Therefore, in another possible implementation, the power supply signal can be connected to the metal on the surface of the third dielectric layer from the back of the wafer 410 to save the power supply lines in the fifth dielectric layer. For example, see Figure 6c , First Metal M 11 The surface of the third dielectric layer 433 may be provided, and the surface of the second dielectric layer 432 may be provided with a second metal M 21 A third metal M may be disposed on the surface of the first dielectric layer 431. 31 , First Metal M 11 The second metal M is contacted through the first contact hole V1 21 , the second metal M 21 The third metal M is contacted through the fourth contact hole V4 31 , the third metal M 31 The first electrode P1 of the active device 421 can be contacted through the fifth contact hole V5. In this case, the voltage signal of the power supply / ground can be transmitted through the second contact hole V2, the first metal M on the third dielectric layer 433, and the second metal M on the third dielectric layer 433. 11 , the first contact hole V1, the second metal M on the second dielectric layer 432 21 , the fourth contact hole V4, the third metal M on the first dielectric layer 431 31 The power supply lines on the surfaces of other dielectric layers above the third dielectric layer 433 , such as the power supply lines on the surface of the fifth dielectric layer 435 , can be saved through the fifth contact hole V5 and transmitted to the first electrode P1 of the active device 421 .

[0096] It is understandable that in other scenarios, power lines may also be arranged on the surface of the fourth dielectric layer 434. Therefore, in order to save power lines on the surface of the fourth dielectric layer 434, the first metal M 11 Can also be set in Figure 6a or Figure 6b On the surface of the third dielectric layer 433, or may also be arranged Figure 6c On the surface of the fifth dielectric layer 435, they are not listed one by one here.

[0097] It can be understood that in the aforementioned memory chip, when the memory chip belongs to DRAM, the metal set on the first dielectric layer 431 can be tungsten W, the metal set on the second dielectric layer 432, the third dielectric layer 433, and the fifth dielectric layer 435 can be copper Cu, and the metal set on the fourth dielectric layer 434 can be aluminum Al.

[0098] Understandably, the first metal M 11 The closer the dielectric layer is to the wafer 410, the more power lines can be saved. Figure 6a Taking the setting shown as an example, as described in the background technology, the power routing on the surface of the second dielectric layer 432 occupies 20% of the wiring, and the LIO routing occupies 5% of the wiring. After the power routing is changed to the back side of the wafer 410, the 20% of the wiring saved on the surface of the second dielectric layer 432 can be used to expand the LIO routing, thereby increasing the number of LIO routing by 4 times; similarly, the power routing on the surface of the third dielectric layer 433 occupies 75% of the wiring, and the MIO routing occupies 27% of the wiring. After the power routing is changed to the back side of the wafer 410, the 75% of the wiring saved on the surface of the third dielectric layer 433 can be used to expand the MIO routing, thereby increasing the number of MIO routing by approximately 2.77 times. Since the number of MIO lines and LIO lines in the memory chip must be consistent, in order to adapt to the 2.77 times of MIO lines expanded on the surface of the third dielectric layer 433, the LIO lines on the surface of the second dielectric layer 432 must also be expanded 2.77 times. In other words, the bandwidth of the memory chip can be expanded 2.77 times. In addition, after the bandwidth of the memory chip is expanded, some saved lines may remain on the surface of the second dielectric layer 432, which can be used as other types of lines or can be left idle.

[0099] To facilitate the introduction of the scheme, Figure 6a Taking the memory chip shown in the figure as an example, the possible structure of the dielectric layer is further described. It should be noted that for the sake of simplicity, other dielectric layers stacked on the first dielectric layer 431 are omitted in the following figure.

[0100] For example, see Figure 7 A metal M may also be disposed on the first dielectric layer 431.12 The second electrode P2 of the active device 421 contacts the metal M through the contact hole V6. 12 , the metal M 12 To receive the input signal V i . Optionally, the input signal V i It can be input from the peripheral circuit of the memory chip. For example, the input signal V i The signal line can pass through the packaging interface of the memory chip to reach the surface of the uppermost dielectric layer, and then connect to the metal M on the lowermost first dielectric layer 431 through the signal routing on the surface of each dielectric layer and the contact holes between each dielectric layer. 12 , then through the metal M 12 and contact hole V6 to the active device 421 .

[0101] Understandable, combined Figure 3a , Figure 3b and Figure 7 When the active device 421 is a PMOS or NMOS, the second electrode P2 may be a gate G. Thus, through the contact hole V6, the PMOS or NMOS may receive an input signal V on the gate G. i , providing support for controlling the conduction or cutoff between the source S and the drain D.

[0102] In one possible implementation, see Figure 7 A metal M may also be disposed on the first dielectric layer 431. 13 The third electrode P3 of the active device 421 contacts the metal M through the contact hole V7. 13 , the metal M 13 Used to send output signal V o Optionally, the output signal V o Can be output to the peripheral circuit of the memory chip, for example, the output signal V o The metal M on the bottom first dielectric layer 431 can be transmitted through the contact hole V7. 13 , and then connected to the surface of the top dielectric layer through the signal routing on the surface of each dielectric layer and the contact holes between the dielectric layers, and then output to the peripheral circuit after passing through the packaging interface of the memory chip.

[0103] Understandable, combined Figure 3a and Figure 7 When the active device 421 is a PMOS, the third electrode P3 may be a drain D. Thus, when the PMOS is turned on, the high level of the source S of the PMOS may be transmitted to the drain D through the turned-on PMOS, and then output to the peripheral circuit.

[0104] Understandable, combined Figure 3b and Figure 7When the active device 421 is an NMOS, the third electrode P3 may be the source S. Thus, when the NMOS is turned on, the low level of the drain D of the NMOS may be transmitted to the source S through the turned-on NMOS, and then output to the peripheral circuit.

[0105] 4. Second Contact Hole or Third Contact Hole

[0106] In one possible implementation, Figure 4 The second contact hole V2 shown in (A) and the first metal M 11 contact area or Figure 4 The contact area between the third contact hole V3 and the first electrode P1 shown in (B) can be at least partially projected on the first area, for example, can be fully projected on the first area. The first area is the area where the drive circuit in the memory chip is stored, for example Figure 5 The hole area shown in the figure. In other words, contact holes can be introduced in the hole area, and the power supply signal can be introduced from the back of the wafer to the active device through the contact holes, so that the power supply network is completely placed under the active device, so that there is no intersection between the power supply network and the memory array and other peripheral circuits. In this way, not only can a strong power supply network be provided for various driving circuits in the hole area, but also the layout of the memory array and other peripheral circuits in the memory chip will not be affected, avoiding affecting the storage function of the memory chip.

[0107] In the present application, the second contact hole V2 or the third contact hole V3 needs to penetrate to the back of the wafer 410. The second contact hole V2 or the third contact hole V3 can be a through hole with a relatively regular shape, or can be a special-shaped hole formed by different through holes and metal layers contacting each other. Figure 7 Taking the second contact hole V2 as an example, several possible structures of the second contact hole V2 are listed. It can be understood that the possible structure of the second contact hole V2 is also applicable to the third contact hole V3, the only difference is that one end of the second contact hole V2 contacts the first metal M 11 , but one end of the third contact hole V3 contacts the first electrode P1.

[0108] In one possible structure, see Figure 8a , the second contact hole V2 may include a power supply through hole V 21 And the first back metal layer BM1. Among them, the power supply through hole V 21 One end of the first metal M 11, and the other end penetrates to the first back metal layer BM1, which is arranged on the back of the wafer 410 and is connected to the power supply or ground. For example, the first back metal layer BM1 can be connected to the power supply or ground through a conductive medium, and the conductive medium can be a single medium or a mixed medium with conductive ability, such as metal, alloy (such as copper alloy or aluminum alloy, etc.), composite metal, conductive plastic, conductive rubber, conductive fiber fabric, conductive coating, conductive adhesive, transparent conductive film and its composite material, etc. With this structural design, the first metal M 11 Can be powered through V 21 The first back metal layer BM1 is connected to the power supply or ground, and the first back metal layer BM1 can provide a relatively wide plane, so that even if multiple active devices 421 are set on the wafer 410, enough power supply through holes V can be drawn through the relatively wide plane. 21 , multiple active devices are connected to the power supply or ground without having to set up external wiring connected to the power supply / ground for each active device, which helps to reduce the space occupied by the external wiring.

[0109] In another possible structure, see Figure 8b , the second contact hole V2 may include a power supply through hole V 21 , the second back metal layer BM2, the first via hole V 22 and a first back metal layer BM1, wherein the first back metal layer BM1 is disposed on the back side of the wafer 410 and is connected to the power supply or ground, the second back metal layer BM2 is disposed in the stacking direction of the first back metal layer BM1 and is spaced a certain distance from the first back metal layer BM1, and the power supply through hole V 21 One end of the first metal M 11 , the other end passes through the second back metal layer BM2, the first via hole V 22 One end of the first metal M contacts the second back metal layer BM2, and the other end contacts the first back metal layer BM1. 11 The power supply can be connected through the V 21 , the second back metal layer BM2, the first via hole V 22 The first back metal layer BM1 is connected to the power supply or ground, and even if the plane provided by the first back metal layer BM1 is not enough to supply all active devices 421 on the wafer 410, the first via hole V 22 The second back metal layer BM2 is extended, so that two back metal layers are used to support more active devices 421 on the wafer 410 .

[0110] In yet another possible structure, see Figure 8c , the second contact hole V2 may include a power supply through hole V 21 , the third back metal layer BM3, the second via hole V23 , the second back metal layer BM2, the first via hole V 22 The first back metal layer BM1 is disposed on the back of the wafer 410 and is connected to the power supply or ground. The second back metal layer BM2 is disposed in the stacking direction of the first back metal layer BM1 and is spaced a certain distance from the first back metal layer BM1. The third back metal layer BM3 is disposed in the stacking direction of the second back metal layer BM2 and is spaced a certain distance from the second back metal layer BM2. The power supply through hole V 21 One end of the first metal M 11 , the other end passes through the third back metal layer BM3, the second via hole V 23 One end of the first via hole V contacts the third back metal layer BM3, and the other end contacts the second back metal layer BM2. 22 One end of the first metal M contacts the second back metal layer BM2, and the other end contacts the first back metal layer BM1. 11 The power supply can be connected through the V 21 , the third back metal layer BM3, the second via hole V 23 , the second back metal layer BM2, the first via hole V 22 The first back metal layer BM1 is connected to the power supply or ground. With this structural design, even if the plane provided by the first back metal layer BM1 and the second back metal layer BM2 is not enough to supply all active devices 421 on the wafer 410, the second via hole V 23 The third back metal layer BM3 is further extended, so that three back metal layers are used to support more active devices 421 on the wafer 410 .

[0111] It should be noted that in the above structures, each back metal layer and each via hole can be distributed throughout the entire back side of the wafer 410, but the power supply via hole V 21 Only distributed in Figure 5 The Hole area shown in this way can not only provide a strong power supply network for various driving circuits in the Hole area, but also will not affect the positions of other devices in the memory array, thereby avoiding affecting the memory devices in the memory array.

[0112] In addition, the above only introduces three possible structures of the second contact hole V2 by way of example. In actual operation, there may be other structures. For example, it may include more than three back metal layers, for example, it may include four or five back metal layers. The more back metal layers are provided, the wider the plane can be provided to support more active devices 421, but its manufacturing process will also become more complicated.

[0113] Furthermore, the various implementation solutions described in this application may also be combined with each other. Figure 7 to Figure 8cAll are based on Figure 6a The structure of the memory chip shown is used as an example, but its solution can also be applied to Figure 6b or Figure 6c The structure of the memory chip shown, for example, Figure 8c The scheme shown is Figure 6b The structure of the memory chip shown in the figure can also be combined to obtain Figure 9a The structure of the memory chip shown. For example, Figures 6a to 8c All are based on Figure 4 The structure of the memory chip shown in (A) is used as an example, but its solution can also be applied to Figure 4 The structure of the memory chip shown in (B) is as follows. Figure 8c The scheme shown is Figure 4 The structure of the memory chip shown in (B) can also be combined to obtain Figure 9b It should be understood that there are many possible structures of the memory chip obtained by combining various implementation schemes, and this application will not list them one by one.

[0114] The above content introduces the structure of back power supply for a single active device in a memory chip, and the back power supply scheme of a basic unit composed of multiple active devices in a memory chip is introduced below. For example, the basic unit is an inverter in a driving circuit as an example.

[0115] See also Fig.10a , exemplarily showing a circuit diagram of an inverter provided by the present application. The inverter includes a PMOS and an NMOS, and the gate G of the PMOS P and the gate G of NMOS N Connected to receive input signal V i ; PMOS drain D P and the source S of the NMOS N Connected to send output signal V o ; Source S of PMOS P Connect the power supply VDD, the drain of NMOS N Connect to ground VSS. When the input signal V i When the voltage is high, the NMOS is turned on and the PMOS is turned off. Therefore, the low voltage of the ground terminal VSS can be output through the turned-on NMOS, making the inverter output and the input signal V i When the input signal V i When the voltage is low, the PMOS is turned on and the NMOS is turned off. Therefore, the high level of the power supply VDD can be output through the turned-on PMOS, making the inverter output and the input signal V i The opposite is high level.

[0116] For example, Figure 8cAs an example, based on the structure of the memory chip shown in Fig.10a , see Fig.10b , exemplarily showing a three-dimensional layout structure diagram of an inverter provided by the present application. In this three-dimensional layout, a first dielectric layer 431 is stacked on a wafer 410. An active layer is buried in the wafer 410, and a PMOS and an NMOS are arranged in the active layer. A plurality of back metal layers are also arranged in the wafer 410, including a back metal layer BM1P, a back metal layer BM2P and a back metal layer BM3P arranged for PMOS, and a back metal layer BM1N, a back metal layer BM2N and a back metal layer BM3N arranged for NMOS. The back metal layer BM1P is conducted to the power supply, and the back metal layer BM1N is conducted to the ground. The back metal layer BM1P and the back metal layer BM2P are connected via a via V 22P The back metal layer BM2P and the back metal layer BM3P are connected by vias V 23P The back metal layer BM1N and the back metal layer BM2N are connected by vias V 22N The back metal layer BM2N and the back metal layer BM3N are connected by vias V 23N Blind holes of different sizes are dug on the surface of the first dielectric layer 421, and metals are filled in the blind holes. These metals include metal M for PMOS. 11P 、Metal M 12P and Metal M 13P , and metal M for NMOS settings 11N 、Metal M 12N and Metal M 13N . Metal M 11P Power supply through via V 21P Contact the back metal layer BM3P and through the contact hole V 1P Contact the source S of PMOS P , Metal M 12P Through the contact hole V 6P Contact the gate G of PMOS P , Metal M 13P Through the contact hole V 7P Contact the drain D of PMOS P . Metal M 11N Power supply through via V 21N Contact the back metal layer BM3N and through the contact hole V 1N Contact the drain D of NMOS N , Metal M 12N Through the contact hole V 6N Contact the gate G of NMOS N , Metal M 13N Through the contact hole V 7N Contact the source S of NMOS N. Metal M 13P and Metal M 13N The metal on the second dielectric layer 432 is respectively connected through the contact holes on the second dielectric layer 432 and then connected to the signal output end, so that the drain D of the PMOS P and the source S of the NMOS N Conducted to the signal output terminal, metal M 12P and Metal M 12N The gate G of the PMOS is connected to the metal on the second dielectric layer 432 through the contact holes on the second dielectric layer 432 and then connected to the signal input terminal. P and the gate G of NMOS N It should be understood that the other dielectric layers stacked on the second dielectric layer 432 and the gate G of the PMOS are omitted in the figure. P 、Gate of NMOS N 、Drain of PMOS P , source S of NMOS N The connection method with metal in other dielectric layers.

[0117] According to the above three-dimensional layout structure, the back metal layers BM1P~BM3P are used as power supply metals, through the vias V 22P 、Via 23P and powered via V 21P The power source is connected to the metal M on the first dielectric layer 431. 11P The metal M on the first dielectric layer 431 is connected. 11P Then through the contact hole V 1P The source S of the PMOS P Similarly, the back metal layers BM1N~BM3N are used as power supply metals, and the vias V 22N 、Via 23N and powered via V 21N Connect the ground terminal to the metal M on the first dielectric layer 431 11N The metal M on the first dielectric layer 431 is connected. 11N Then through the contact hole V 1N The drain D of NMOS N In addition to the source S of the PMOS P Connection relationship with power supply and drain D of NMOS N Except for the connection relationship with the ground terminal, the connection relationship between the other electrodes of PMOS and NMOS and other signals remains unchanged. For example, the drain D of PMOS P Connection relationship with the signal output terminal, gate G of PMOS P Connection relationship with the signal input terminal, source S of NMOSN Connection relationship with the signal output terminal, gate G of NMOS N The connection relationship with the signal input terminal remains the same as that of the existing inverter.

[0118] For further information, see Fig.10c , exemplarily showing a plan layout of an inverter provided by the present application. The plan layout can be considered as a diagram seen after unfolding each layer of the inverter in a top-down direction, for example, Fig.10c (A) can be considered as a top view of the active layer on the wafer. Fig.10c (B) can be considered as a top view of the first dielectric layer. Fig.10c (C) in the figure can be considered as a top view of the second dielectric layer. Optionally, the inverter can be prepared on the active area of ​​the wafer. For example, the figure shows the preparation of the inverter on the P-type active area. In this scenario, the active area corresponding to the PMOS in the inverter needs to be doped with N-type materials to form an N-well, and the active area corresponding to the NMOS in the inverter does not need to be doped with other materials. However, this is only one possible implementation method. In other scenarios, the inverter can also be prepared using an N-type active area, and this application does not make specific limitations on this.

[0119] See also Fig.10c Middle (A) to Fig.10c In (C), the power supply signal VDD provided by the power supply terminal can be connected along the power supply through hole V 21 The current is transferred upward to the metal on the first dielectric layer 431, and then can be transferred downward to the source electrode S of the PMOS set on the wafer 410 through the contact hole V1 contacting the metal. P , realize the source S of PMOS P The high level, and the ground signal VSS provided by the ground terminal can be connected along the power supply through hole V 21 The current is transferred upward to the metal on the first dielectric layer 431, and then can be transferred downward to the drain electrode D of the NMOS set on the wafer 410 through the contact hole V1 contacting the metal. N , realize the drain D of NMOS N In addition, the drain D of the PMOS P and the source S of the NMOS N The gate G of the PMOS can be connected to the metal on the first dielectric layer 431 through the contact hole V7, and then can be transmitted upward through the contact hole on the second dielectric layer 432 that contacts the metal until it is connected to the signal output terminal outside the inverter. P and the gate G of NMOS NThe signal can be connected upwardly to the metal on the first dielectric layer 431 through the contact hole V6, and then can be transmitted upwardly through the contact hole on the second dielectric layer 432 in contact with the metal until it is connected to the signal input terminal outside the inverter. With the above layout, no metal wiring for transmitting the power signal VDD and the ground signal VSS will appear on the surface of the first dielectric layer 431 and the second dielectric layer 432, which can effectively save the metal wiring resources in the metal layer structure.

[0120] Furthermore, if these saved metal routing resources are used to expand more signal routing, such as adding IO routing, the memory bandwidth can be increased. For example, see Fig.11 , exemplarily showing a circuit comparison schematic diagram provided by the present application for expanding the saved power supply wiring into IO wiring, the diagram takes the data reading of 1 page (1 Page, including multiple Mats) in 1 Bank in x8 DRAM as an example, wherein, Fig.11 (A) shows the structure diagram of 1Page in the traditional x8 DRAM. Fig.11 (B) shows the schematic diagram of the 1Page structure after doubling the IO routing of the traditional x8 DRAM. Fig.11 Middle (A) and Fig.11 Middle (B):

[0121] like Fig.11 As shown in (A), in a traditional x8 DRAM, there are 8 Mats, namely Mat1 to Mat8. Each Mat corresponds to 8 LIO lines and 8 MIO lines, and the other lines are all used as power lines. Therefore, after 1 WL is turned on, each Mat can output 8 bits of data, and a Page can output 8×8 bits of data. For example, taking Mat1 as an example, assuming that 1 WL intersects with 64 BLs, when 1 WL is turned on, the 64 storage cells at the intersection of the WL and the 64 BLs are turned on, and the data in these 64 storage cells will be transmitted to the surrounding SA circuit along with the BL. The SA circuit selects 8 data from the 64 data and sends them to 8 LIOs (i.e. LIO0 to LIO7). The 8 LIOs amplify the 8 data transmitted and transmit them to 8 MIOs (i.e. MIO0 to MIO7). Therefore, in traditional x8 DRAM, 8 storage units correspond to one LIO, and each LIO can only select one of the 8 storage units for data output, so its memory bandwidth can only be 1 / 8;

[0122] like Fig.11As shown in (B), in the x8 DRAM after the IO routing is doubled, each Mat corresponds to 16 LIO routings and 16 MIO routings. Therefore, after one WL is turned on, each Mat can output 16 bits of data, and one Page can output 16×8 bits of data. For example, still taking Mat1 as an example, assuming that one WL intersects with 64 BLs, when one WL is turned on, the 64 storage cells at the intersection of the WL and the 64 BLs are turned on, and the data in these 64 storage cells will be transmitted to the surrounding SA circuit along with the BL. The SA circuit selects 16 data from the 64 data and sends them to the 16 LIOs. The 16 LIOs amplify the 16 data transmitted and transmit them to the 16 MIOs. It can be seen that in the x8 DRAM after the IO routing is doubled, 4 storage units correspond to one LIO, and each LIO can select one of the 4 storage units for data output. Therefore, its memory bandwidth can be doubled to 1 / 4 as the IO routing is doubled.

[0123] It should be understood that the above is just an example of IO routing doubling to introduce the effect of memory bandwidth increasing with the increase of IO routing. As mentioned above, according to the back routing scheme in this application, the IO routing can be increased by up to 2.77 times. Therefore, any value not greater than 2.77 times can be selected to increase the IO routing in the storage core so that the memory bandwidth increases by a corresponding multiple, and this application does not make specific limitations on this.

[0124] In addition, in the present application, the timing of preparing the second contact hole can be set by those skilled in the art based on experience, for example, Figure 4 Taking (A) as an example, in one preparation method, the wafer 410, the active layer 420, the active device 421, the dielectric layer structure 430, the first metal M 11 After the first contact hole V1 and the first contact hole V2 are prepared, the entire structure is turned over, and the second contact hole V2 is prepared from the back of the wafer 410; or, in another preparation method, the second contact hole V2 can be prepared on one side of the wafer 410, and then the wafer 410 is turned over, and the active layer 420, the active device 421, the dielectric layer structure 430, the first metal M 11 There are many possible preparation methods, which are not specifically limited in this application.

[0125] Based on the structure and functional principle of the memory chip described above, the present application may also provide a memory component, which may be a Mat in a memory, for example. Fig.12, is a possible functional framework diagram of a storage component provided by the present application, the storage component 1200 may include a storage array 1210 and a peripheral circuit 1220, and the peripheral circuit 1220 may include a storage chip as described in any of the above embodiments. Among them, one end of the peripheral circuit 1220 is connected to the storage array 1210, and the other end is connected to the controller (not shown in the figure), which is used to transmit control signals for reading and writing the storage array 1210 between the storage array 1210 and the controller.

[0126] In one possible implementation, see Fig.12 The peripheral circuit 1220 may include a signal enhancement circuit 1221 and a driving circuit 1222. The signal enhancement circuit 1221 may be connected to the storage array 1210 to enhance the control signal for reading and writing the storage array 1210; the driving circuit 1222 may be connected to the signal enhancement circuit 1221 to enhance the power supply to the signal enhancement circuit 1221. The storage chip described in any of the above embodiments may be specifically located in the driving circuit 1222. For example, the driving circuit 1222 may include the above Fig.10b The inverter shown is powered by a power signal or a ground signal introduced from the back of the wafer, so as to cooperate with other driving devices in the driving circuit 1222 to realize the driving function of the signal enhancement circuit 1221, so that the signal enhancement circuit 1221 can obtain sufficient electrical energy to enhance the control signal of the read-write storage array 1210.

[0127] For further possible implementations, please refer to Figure 5 and Fig.12 The signal enhancement circuit 1221 may include a SWD circuit and a SA circuit. The SWD circuit and the SA circuit may be located in the peripheral area of ​​the memory array 1210. The driving circuit 1222 may be located in the intersection area of ​​the SWD circuit and the SA circuit. Figure 5 The hole area is shown.

[0128] In one possible implementation, please refer to Figure 5 and Fig.12 , the memory array may include M×N memory cells, M WLs and N BLs, the M×N memory cells are located at the intersection of the M WLs and the N BLs, the SWD circuit is connected to the M WLs, and is used to enhance the control signal transmitted on the enabled word line; the SA circuit is connected to the N BLs, and is used to enhance the control signal transmitted on the enabled bit line. Wherein, M and N are positive integers.

[0129] Understandably, Fig.12The circuit diagram does not constitute a specific limitation on the storage component. In other embodiments of the present application, the storage component may include more or fewer components than shown, or combine certain components, or split certain components, or arrange the components differently, or arrange them in different positions, without specific limitation.

[0130] Based on the structure and functional principle of the storage component described above, the present application can also provide a storage device. For example, see Fig.13 , is a possible functional framework diagram of a memory provided by the present application, the memory 1300 may include a controller 1310 and T storage components as described in any of the above embodiments, such as storage component 1321, storage component 1322, ..., storage component 132T, T is a positive integer. Among them, the controller 1310 can be connected to any storage component for reading and writing any storage component.

[0131] In one possible implementation, please refer to Fig.13 and Figure 5 , the controller 1310 may include a row decoder and a column decoder, the row decoder is connected to the WL in each storage component, and the column decoder is connected to the BL in each storage component. When it is necessary to read and write a storage unit in a certain storage component, the controller 1310 may send an opening control signal to the WL and BL where the storage unit of the storage component is located, so that the control signal on the opened WL is enhanced by the signal of the SWD circuit in the storage component and the control signal on the opened BL is enhanced by the signal of the SA circuit in the storage component, which can drive the corresponding storage unit to open, thereby realizing the reading and writing operations on the storage unit.

[0132] It should be noted that Fig.13 The memory function framework provided is only an example, and in other examples, the memory 1300 may include more, fewer or different devices. In addition, the devices shown may be combined or divided in any manner, and this application does not make any specific limitation on this.

[0133] Exemplarily, the memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as SRAM, DRAM, flash eprom (FE), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct rambus RAM (DR RAM), as well as new types of memory such as ferroelectric random access memory (FeRAM), phase change random access memory (PCRAM), magnetic random access memory (MRAM) or resistive random access memory (ReRAM). The non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. It should be noted that the memory described in this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0134] Based on the structure and functional principle of the memory described above, the present application can also provide an electronic device. Optionally, the electronic device can be a storage device, such as but not limited to a mobile hard disk, a USB flash drive, a memory card or an optical disk. Alternatively, the electronic device can also be a terminal device, such as a mobile phone, a computer, a smart watch, a car device, a computer, a virtual reality device, a projector or a smart camera. See Fig.14, exemplarily showing a possible functional framework diagram of an electronic device provided by the present application, the electronic device 1400 may include a processor 1410 and a memory 1420, or may also include a transceiver 1430, and the memory 1420 may be a memory as described in any of the above embodiments. Among them, the processor 1410 and its peripheral components, such as the memory 1420 and the transceiver 1430, may be connected through a bus, such as through an IO bus. The processor 1410 can read and write data in the memory 1420 through the IO bus.

[0135] The processor 1410 includes one or more processing units, such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0136] The memory 1420 may be specifically an internal memory, which may be used to store computer executable program codes, and the executable program codes include instructions. The internal memory may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a call function, a time setting function, etc.), etc. The data storage area may store data created during the use of the electronic device (such as a phone book, world time, etc.), etc. In addition, the internal memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash memory (Universal Flash Storage, UFS), etc. The processor 1410 executes various functional applications and data processing of the electronic device 1400 by running instructions stored in the internal memory.

[0137] In some scenarios, the electronic device 1400 may further include an external memory interface, and the electronic device 1400 may be connected to an external memory card, such as a Micro SD card, through the external memory interface to expand its storage capacity. For example, the external memory card communicates with the processor 1410 through the external memory interface to implement a data storage function.

[0138] The transceiver 1430 can enable the electronic device 1400 to communicate wirelessly with the outside world, and can provide wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR) and other wireless communication solutions. The transceiver 1430 can be one or more devices integrating at least one communication processing module. The transceiver 1430 receives electromagnetic waves via an antenna, modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 1410. The transceiver 1430 can also receive the signal to be sent from the processor 1410, modulate and amplify it, and convert it into electromagnetic waves for radiation through the antenna.

[0139] It should be noted that Fig.14 The electronic device functional framework provided is only an example. In other embodiments of the present application, the electronic device may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0140] In the various embodiments of the present application, unless otherwise specified or provided in a logical conflict, the terms and / or descriptions between the different embodiments are consistent and may be referenced to each other, and the technical features in the different embodiments may be combined to form new embodiments according to their inherent logical relationships.

[0141] In the present application, "contact hole" does not refer to an absolutely regular hole, which can be understood as a hole of any shape that can connect the upper and lower parts, such as a special-shaped hole. "At least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple. In the text description of the present application, the character " / " generally indicates that the front and back associated objects are in an "or" relationship. In the formula of the present application, the character " / " indicates that the front and back associated objects are in a "division" relationship. In addition, in this application, the word "exemplarily" is used to mean an example, illustration or description. Any embodiment or design described as an "example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Alternatively, it can be understood that the use of the word "example" is intended to present concepts in a specific way and does not constitute a limitation on this application.

[0142] It is to be understood that the various digital numbers involved in the present application are only for the convenience of description and are not intended to limit the scope of the embodiments of the present application. The size of the sequence number of the above-mentioned processes does not mean the order of execution, and the order of execution of each process should be determined by its function and inherent logic. The terms "first", "second" and similar expressions are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or equipment are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

Claims

1. A memory chip, characterized in that: include: a wafer and an active layer buried in the wafer; The active layer includes active devices, the active devices are devices in the peripheral circuit of the memory chip, and the first electrodes of the active devices are powered by contacting a power source or a ground on the back side of the wafer; The memory array in the memory chip is routed through metal resources on one side of the active surface of the wafer.

2. The memory chip according to claim 1, wherein: The peripheral circuit includes a driving circuit, and the active device is a device in the driving circuit.

3. The memory chip according to claim 1 or 2, characterized in that: The memory chip further comprises a dielectric layer structure disposed on the active surface of the wafer and a first metal disposed in the dielectric layer structure; The first electrode of the active device contacts the first metal through a first contact hole. The first metal also penetrates through a second contact hole to the back side of the wafer and is conducted to the power source or the ground.

4. The memory chip according to claim 3, characterized in that: The contact area between the second contact hole and the first metal is at least partially projected onto the first area, and the first area is an area where a driving circuit in the memory chip is stored.

5. The memory chip according to claim 1 or 2, characterized in that: The wafer comprises a third contact hole, one end of the third contact hole contacts the first electrode, and the other end of the third contact hole penetrates to the back side of the wafer and is conducted to the power supply or the ground.

6. The memory chip according to any one of claims 3 to 5, characterized in that: For any one of the second contact hole or the third contact hole: It includes a power supply through hole and a first back metal layer, one end of the power supply through hole contacts the first metal or the first electrode, the other end of the power supply through hole penetrates the first back metal layer, and the first back metal layer is connected to the power supply or ground.

7. The memory chip according to claim 6, wherein: The first back metal layer is spread over the back side of the wafer, and the power supply through hole is at least partially projected onto a first area, where the first area is an area for storing a driving circuit in the memory chip.

8. A storage component, characterized in that: comprising a memory array and a peripheral circuit, wherein the peripheral circuit comprises a memory chip as claimed in any one of claims 1 to 7; The peripheral circuit is used to transmit control signals for reading and writing the storage array between the storage array and the controller.

9. The storage assembly according to claim 8, characterized in that The peripheral circuit includes a signal enhancement circuit and a driving circuit; The driving circuit is used to enhance the power supply of the signal enhancement circuit; The signal enhancement circuit is used to enhance the control signal for reading and writing the storage array.

10. The storage component according to claim 9, characterized in that The signal enhancement circuit includes a sub-word line driver SWD circuit and a sense amplifier SA circuit. The SWD circuit and the SA circuit are located in the peripheral area of ​​the memory array, and the driving circuit is located in the intersection area of ​​the SWD circuit and the SA circuit.

11. The storage component according to claim 10, characterized in that The memory array comprises M×N memory cells, M word lines and N bit lines, the M×N memory cells are located at the intersections of the M word lines and the N bit lines, the SWD circuit is connected to the M word lines, the SA circuit is connected to the N bit lines, and M and N are positive integers; The SWD circuit is used to enhance the control signal transmitted on the turned-on word line; The SA circuit is used to enhance the control signal transmitted on the turned-on bit line.

12. A memory, characterized in that: comprising a controller and a storage component as claimed in any one of claims 9 to 11, wherein the controller is connected to the storage component; The controller is used to perform read and write operations on the storage component.

13. An electronic device, characterized in that: comprising a processor and the memory as claimed in claim 12, wherein the processor and the memory are connected via an input / output IO bus; The processor is used to read and write data in the memory through the IO bus.

Images