Semiconductor structure and method for manufacturing the same

Abstract

The embodiment of the present disclosure relates to the technical field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises an array region and a peripheral region, and the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate, the substrate spans the array region and the peripheral region; forming a first diffusion barrier layer on the top surface of the substrate in the peripheral region; forming a second diffusion barrier layer, the second diffusion barrier layer is located on the top surface of the substrate away from the first diffusion barrier layer, and is located on the top surface of the substrate in the array region; and forming a conductive structure on the surface of the second diffusion barrier layer away from the top surface of the substrate. The embodiment of the present disclosure is at least beneficial to effectively avoid the diffusion of elements in the substrate in the peripheral region into the conductive structure while ensuring that the resistance of the electrical signal transmission between the conductive structure in the array region and the substrate is small.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the continuous optimization of dynamic random access memory (DRAM) manufacturing processes, the feature size of technology nodes has been further reduced. DRAM has put forward different requirements on the performance of similar film layers located in the array area and peripheral area, such as diffusion barrier layers.

[0003] However, currently some film layers are formed simultaneously in the array area and the peripheral area, which cannot meet the different performance requirements of the array area and the peripheral area for the film layers, and thus cannot further improve the electrical performance of the DRAM from this perspective. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which are at least beneficial for ensuring that the resistance of electrical signal transmission between the conductive structure in the array area and the substrate is small while effectively preventing elements in the substrate in the peripheral area from diffusing into the conductive structure.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, wherein the semiconductor structure includes an array region and a peripheral region, and the manufacturing method includes: providing a substrate, wherein the substrate spans the array region and the peripheral region; forming a first diffusion barrier layer on the top surface of the substrate in the peripheral region; forming a second diffusion barrier layer, wherein the second diffusion barrier layer is located at a top surface of the first diffusion barrier layer away from the substrate, and at the top surface of the substrate in the array region; and forming a conductive structure on a surface of the second diffusion barrier layer away from the top surface of the substrate.

[0006] In some embodiments, the first diffusion barrier layer is composed of nitrogen atoms, titanium atoms, and silicon atoms, and the second diffusion barrier layer is composed of nitrogen atoms and titanium atoms.

[0007] In some embodiments, the steps of forming the first diffusion barrier layer include: using a first deposition process to form a first sub-film layer on the top surface of the substrate in the peripheral area; using a second deposition process to form a second sub-film layer on the surface of the first sub-film layer away from the top surface of the substrate, and the material of the second sub-film layer is different from the material of the first sub-film layer; alternatingly performing the first deposition process and the second deposition process N times on the surface of the second sub-film layer away from the first sub-film layer, N is a positive integer, and the alternating stacked first sub-film layer and the second sub-film layer constitute the first diffusion barrier layer.

[0008] In some embodiments, forming the first sub-film layer using the first deposition process includes: performing the first sub-deposition process M times to form the first sub-film layer, where M is a positive integer; the first sub-deposition process includes: providing titanium tetrachloride gas and ammonia gas in sequence, and controlling the reaction temperature of the titanium tetrachloride gas and the ammonia gas to be 550°C~650°C; wherein the gas flow rate range of the titanium tetrachloride gas is 120sccm~180sccm, and the time range for providing the titanium tetrachloride gas is 0.03s~0.06s; the gas flow rate range of the ammonia gas is 3500sccm~5000sccm, and the time range for providing the ammonia gas is 0.2s~0.4s.

[0009] In some embodiments, the second deposition process includes: sequentially providing dichlorosilane gas and ammonia gas, and controlling the reaction temperature of the dichlorosilane gas and the ammonia gas to be 550°C~650°C; wherein, the gas flow rate range of the dichlorosilane gas is 80sccm~120sccm, and the time range for providing the dichlorosilane gas is 0.03s~0.06s; the gas flow rate range of the ammonia gas is 3500sccm~5000sccm, and the time range for providing the ammonia gas is 0.2s~0.4s.

[0010] In some embodiments, the step of forming the second diffusion barrier layer includes: forming a third sub-film layer using a first magnetron sputtering deposition process; forming a fourth sub-film layer on a surface of the third sub-film layer away from the substrate using a second magnetron sputtering deposition process, wherein argon gas is provided in the first magnetron sputtering deposition process, and argon gas and nitrogen gas are provided in the second magnetron sputtering deposition process.

[0011] In some embodiments, after forming the second diffusion barrier layer and before forming the conductive structure, the manufacturing method further includes: performing rapid thermal processing on the second diffusion barrier layer and the substrate to form a third diffusion barrier layer between the second diffusion barrier layer in the array region and the substrate.

[0012] In some embodiments, the direction of the substrate pointing to the first diffusion barrier layer is a first direction; the step of forming the second diffusion barrier layer includes: forming a second diffusion barrier film, the second diffusion barrier film is located on the top surface of the first diffusion barrier layer away from the substrate, and is located on the top surface of the substrate in the array area, the second diffusion barrier film in the array area serves as the second diffusion barrier layer in the array area; removing part of the thickness of the second diffusion barrier film in the peripheral area along the first direction, and the remaining second diffusion barrier film in the peripheral area serves as the second diffusion barrier layer in the peripheral area, along the first direction, the first thickness of the second diffusion barrier layer in the peripheral area is less than the second thickness of the second diffusion barrier layer in the array area.

[0013] In some embodiments, the step of providing the base includes: providing a substrate, the substrate spanning the array area and the peripheral area; forming a first semiconductor layer, the first semiconductor layer covering the top surface of the substrate; forming the first diffusion barrier layer on the top surface of the substrate in the peripheral area, including: forming a first diffusion barrier film, the first diffusion barrier film covering the surface of the first semiconductor layer away from the top surface of the substrate; and patterning the first diffusion barrier film to remove the first diffusion barrier film in the array area, and the remaining first diffusion barrier film in the peripheral area serves as the first diffusion barrier layer.

[0014] In some embodiments, the substrate in the array area has a plurality of active areas arranged at intervals; after forming the first diffusion barrier layer and before forming the second diffusion barrier layer, the method further includes: removing the first semiconductor layer in the array area; patterning the substrate in the array area to form a plurality of grooves extending from the top surface of the substrate to the inside of the substrate, the grooves corresponding to the active areas one-to-one, and the grooves exposing portions of the active areas; forming a second semiconductor layer, the second semiconductor layer filling the grooves; the step of forming the second diffusion barrier layer includes: forming the second diffusion barrier layer on a surface jointly formed by the second semiconductor layer and the remaining substrate.

[0015] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a semiconductor structure, which includes an array region and a peripheral region, and the semiconductor structure includes: a substrate, which spans the array region and the peripheral region; a first diffusion barrier layer, which is located on the top surface of the substrate in the peripheral region; a second diffusion barrier layer, which is located on the top surface of the first diffusion barrier layer away from the substrate, and on the top surface of the substrate in the array region, the first diffusion barrier layer has a higher diffusion blocking capability for doped ions than the second diffusion barrier layer, and the doped ions include N-type doped ions and P-type doped ions; and a conductive structure, which is located on the surface of the second diffusion barrier layer away from the top surface of the substrate.

[0016] In some embodiments, the first diffusion barrier layer includes a first sub-membrane layer and a second sub-membrane layer alternately stacked along a first direction, the material of the second sub-membrane layer is different from the material of the first sub-membrane layer, and the direction in which the substrate points to the first diffusion barrier layer is the first direction; wherein, along the first direction, the ratio of the third thickness of the first sub-membrane layer to the fourth thickness of the second sub-membrane layer is not less than 15.

[0017] In some embodiments, along a first direction, a first thickness of the second diffusion barrier layer in the peripheral region is smaller than a second thickness of the second diffusion barrier layer in the array region, and a direction from the substrate to the first diffusion barrier layer is the first direction.

[0018] In some embodiments, the semiconductor structure further includes: a third diffusion barrier layer located between the second diffusion barrier layer in the array region and the substrate, and along the first direction, a fifth thickness of the first diffusion barrier layer is greater than a sixth thickness of the third diffusion barrier layer.

[0019] In some embodiments, the second diffusion barrier layer is a single-layer structure, or the second diffusion barrier layer includes a third sub-layer and a fourth sub-layer stacked along the first direction.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0021] A second diffusion barrier layer is formed between the conductive structure in the array region and the substrate, while a first diffusion barrier layer and a second diffusion barrier layer are formed between the conductive structure in the peripheral region and the substrate. This results in a greater number of diffusion barrier layers between the conductive structure in the peripheral region and the substrate, further reducing the probability of element diffusion between the conductive structure in the peripheral region and the substrate, thereby improving the electrical performance of the conductive structure in the peripheral region. Furthermore, a smaller number of diffusion barrier layers is formed between the conductive structure in the array region and the substrate, thereby reducing the resistance of electrical signal transmission between the conductive structure in the array region and the substrate, namely, reducing the contact resistance between the conductive structure in the array region and the second diffusion barrier layer, as well as the contact resistance between the substrate and the second diffusion barrier layer. This effectively prevents elements in the substrate in the peripheral region from diffusing into the conductive structure while ensuring a low resistance for electrical signal transmission between the conductive structure in the array region and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figures 1 to 15 This is a schematic diagram of the cross-sectional structures corresponding to each step in the method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] As known from the background art, the electrical performance of semiconductor structures needs to be improved.

[0025] Analysis revealed that the bit line structure in a DRAM includes a diffusion barrier layer in contact with the substrate and a conductive layer located on the side of the diffusion barrier layer away from the substrate. For the bit line structure in the array area, it is desired that the resistance of electrical signal transmission between the conductive layer and the substrate is small, that is, it is desired that the contact resistance between the diffusion barrier layer and the substrate is small, and the contact resistance between the diffusion barrier layer and the conductive layer is small. For the gate structure in the peripheral area, which has a manufacturing process similar to that of the bit line structure, or a gate structure in which most processes are carried out simultaneously, it is desired that the diffusion barrier layer can effectively block the diffusion of elements between the conductive layer and the substrate to avoid degradation of the electrical performance of the conductive layer.

[0026] The present disclosure provides a semiconductor structure and a method for manufacturing the same. In the method, a second diffusion barrier layer is formed between the conductive structure in the array region and the substrate, and a first diffusion barrier layer and a second diffusion barrier layer are formed between the conductive structure in the peripheral region and the substrate. This results in a greater number of diffusion barrier layers being formed between the conductive structure in the peripheral region and the substrate, further reducing the probability of element diffusion between the conductive structure in the peripheral region and the substrate, thereby improving the electrical performance of the conductive structure in the peripheral region. Furthermore, a smaller number of diffusion barrier layers are formed between the conductive structure in the array region and the substrate, thereby reducing the resistance of electrical signal transmission between the conductive structure in the array region and the substrate, namely, reducing the contact resistance between the conductive structure in the array region and the second diffusion barrier layer, as well as the contact resistance between the substrate and the second diffusion barrier layer. Thus, while ensuring a low resistance for electrical signal transmission between the conductive structure in the array region and the substrate, the structure effectively prevents elements in the substrate in the peripheral region from diffusing into the conductive structure.

[0027] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0028] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figures 1 to 15 Schematic diagram of the cross-sectional structure corresponding to each step in the method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure. It should be noted that, in order to facilitate the description and clearly illustrate the steps of the method for manufacturing a semiconductor structure, Figures 1 to 15Both are schematic diagrams of local cross-sectional structures of semiconductor structures.

[0029] refer to Figures 1 to 15 The semiconductor structure includes an array region 110 and a peripheral region 120. The method for manufacturing the semiconductor structure includes the following steps:

[0030] S101: Reference Figure 1 , providing a substrate 100 , which spans the array region 110 and the peripheral region 120 .

[0031] S102: Reference Figure 2 or Figure 3 , a first diffusion barrier layer 101 is formed on the substrate top surface 100 b in the peripheral region 120 .

[0032] In some embodiments, reference Figure 3 , forming the first diffusion barrier layer 101 may include the following steps:

[0033] refer to Figure 3 A first deposition process is used to form a first sub-film layer 111 on the top surface 100b of the substrate in the peripheral area 120; a second deposition process is used to form a second sub-film layer 121 on the surface of the first sub-film layer 111 away from the top surface of the substrate 100, and the material of the second sub-film layer 121 is different from the material of the first sub-film layer 111; the first deposition process and the second deposition process are alternately performed N times on the surface of the second sub-film layer 121 away from the first sub-film layer 111, where N is a positive integer, and the alternately stacked first sub-film layer 111 and the second sub-film layer 121 constitute the first diffusion barrier layer 101.

[0034] In this way, the first diffusion barrier layer 101 is a stacked structure in which the first sub-layers 111 and the second sub-layers 121 are alternately stacked along the first direction X.

[0035] It should be noted that Figure 2 Only the overall structure of the first diffusion barrier layer 101 is illustrated, and the internal structure of the first diffusion barrier layer 101 is not drawn.

[0036] In some embodiments, the material of the first sub-layer 111 may be titanium nitride, and the material of the second sub-layer 121 may be silicon nitride. It is understood that the material of the first diffusion barrier layer 101 can be regarded as titanium nitride doped with silicon nitride. The doped silicon nitride improves the diffusion barrier capability of the first diffusion barrier layer 101 to elements, thereby further reducing the probability of element diffusion between the conductive structure 103 in the peripheral region 120 and the substrate 100, thereby facilitating improved electrical performance of the conductive structure 103 in the peripheral region 120.

[0037] It should be noted that the diffusion barrier capability of the first diffusion barrier layer 101 against elements includes its diffusion barrier capability against dopant ions, which include N-type dopant ions and P-type dopant ions. N-type dopant ions may include at least one of arsenic ions, phosphorus ions, or antimony ions; and P-type dopant ions may include at least one of boron ions, indium ions, or gallium ions. Furthermore, the diffusion barrier capability of each film layer described subsequently against elements includes its diffusion barrier capability against dopant ions.

[0038] In some embodiments, continue to refer to Figure 3 The direction from the substrate 100 to the first diffusion barrier layer 101 is the first direction X. Along the first direction X, the ratio of the third thickness T3 of the first sub-layer 111 to the fourth thickness T4 of the second sub-layer 121 is not less than 15.

[0039] It can be understood that, on the one hand, the conductivity of the first sub-film layer 111 is much higher than that of the second sub-film layer 121, and therefore the ratio of the third thickness T3 to the fourth thickness T4 is designed to be no less than 15, which is beneficial to ensuring the good overall conductivity of the first diffusion barrier layer 101, so as to reduce the resistance of electrical signal transmission between the conductive structure of the array area and the substrate; on the other hand, the diffusion barrier capability of the first sub-film layer 111 to elements is lower than the diffusion barrier capability of the second sub-film layer 121 to elements. Designing the second sub-film layer 121 to be very thin relative to the first sub-film layer 111 is beneficial to improving the overall diffusion barrier capability of the first diffusion barrier layer 101 to elements by means of the second sub-film layer 121, so as to further reduce the probability of element diffusion between the conductive structure 103 in the peripheral area 120 and the substrate 100, thereby helping to improve the electrical performance of the conductive structure 103 in the peripheral area 120 itself.

[0040] In this way, the ratio of the third thickness T3 to the fourth thickness T4 is designed to be no less than 15, which is beneficial for ensuring the overall good conductivity of the first diffusion barrier layer 101 while improving the overall diffusion barrier capability of the first diffusion barrier layer 101 to elements, thereby taking a two-pronged approach to enhance the electrical performance of the ultimately formed semiconductor structure.

[0041] In some embodiments, the first deposition process and the second deposition process are alternately performed N times on a surface of the second sub-film layer 121 away from the first sub-film layer 111, where the value of N ranges from 5 to 40. In practical applications, the number of times the first deposition process and the second deposition process are alternately performed can be selected according to actual needs. For example, N can be 6, 8, 10, 15, 17, 20, 25, 30, or 38.

[0042] In some embodiments, both the first deposition process and the second deposition process may be atomic layer deposition (ALD). It is understood that ALD is a method for depositing a substance layer by layer on a substrate surface in the form of a single atomic film.

[0043] In some embodiments, forming the first sub-layer 111 using the first deposition process may include the following steps: performing the first sub-deposition process M times to form the first sub-layer 111 , where M is a positive integer.

[0044] In some embodiments, the value of M ranges from 5 to 20. In practical applications, the number of times the first sub-deposition process is performed can be selected according to actual needs. For example, M can be 6, 7, 8, 10, 12, 13, 16, or 18.

[0045] In some embodiments, the first sub-deposition process may include the following steps: providing titanium tetrachloride gas and ammonia gas in sequence, and controlling the reaction temperature of the titanium tetrachloride gas and the ammonia gas to be 550°C~650°C; wherein the gas flow rate range of the titanium tetrachloride gas is 120sccm~180sccm, and the time range for providing the titanium tetrachloride gas is 0.03s~0.06s; the gas flow rate range of the ammonia gas is 3500sccm~5000sccm, and the time range for providing the ammonia gas is 0.2s~0.4s.

[0046] It can be understood that the substrate 100 of the peripheral area 120 can be set in the first reaction chamber. In this step, the substrate 100 of other areas, such as the substrate 100 of the array area 110, can also be located in the first reaction chamber, but the substrate 100 in the area other than the peripheral area 120 can be covered by the mask layer to avoid forming the first sub-membrane layer 111, or the substrate 100 in the area other than the peripheral area 120 forms the first sub-membrane layer 111 like the substrate 100 in the peripheral area 120, and the first sub-membrane layer 111 formed on the substrate 100 in the area other than the peripheral area 120 is subsequently removed.

[0047] In some embodiments, the step of providing titanium tetrachloride gas and ammonia gas may include: first providing titanium tetrachloride gas to the top surface 100b of the substrate in the peripheral region 120 located within the first reaction chamber. After the top surface 100b of the substrate in the peripheral region 120 adsorbs a portion of the titanium tetrachloride, the remaining titanium tetrachloride gas in the first reaction chamber is purged. Then, ammonia gas is provided to the top surface 100b of the substrate in the peripheral region 120 adsorbed with titanium tetrachloride, and the reaction temperature of the titanium tetrachloride gas and ammonia gas is controlled to be between 550°C and 650°C, so that the titanium tetrachloride gas and ammonia gas react to form a titanium nitride film layer, i.e., the first sub-film layer 111, at least on the top surface 100b of the substrate in the peripheral region 120. The reaction temperature of the titanium tetrachloride gas and ammonia gas can be controlled to be between 550°C and 650°C by controlling the temperature of the first reaction chamber. The remaining gas in the first reaction chamber is purged, and the remaining gas includes unreacted ammonia gas and hydrogen chloride gas, a byproduct of the formation of titanium nitride.

[0048] In some embodiments, the second deposition process may include the following steps: providing dichlorosilane gas and ammonia gas in sequence, and controlling the reaction temperature of the dichlorosilane gas and ammonia gas to be 550°C~650°C; wherein the gas flow rate range of the dichlorosilane gas is 80sccm~120sccm, and the time range for providing the dichlorosilane gas is 0.03s~0.06s; the gas flow rate range of the ammonia gas is 3500sccm~5000sccm, and the time range for providing the ammonia gas is 0.2s~0.4s.

[0049] It can be understood that after the first sub-film layer 111 is formed, the gas in the first reaction chamber is purged, and then the second deposition process can be continued in the first reaction chamber. In this step, the second deposition process only needs to be performed on the side of the first sub-film layer 111 away from the top surface 100b of the substrate. The other areas can be covered and the second sub-film layer 121 is not formed, or removed after the second sub-film layer 121 is formed.

[0050] In some embodiments, the step of providing dichlorosilane gas and ammonia gas may include: first providing dichlorosilane gas to a side of the first sub-film layer 111 in the peripheral region 120, located in the first reaction chamber, that is away from the substrate top surface 100b. After a portion of the dichlorosilane is adsorbed on the side of the first sub-film layer 111 in the peripheral region 120, that is away from the substrate top surface 100b, the remaining dichlorosilane gas in the first reaction chamber is removed. Then, ammonia gas is provided to the top surface of the first sub-film layer 111 adsorbed with the dichlorosilane, and the reaction temperature of the dichlorosilane gas and ammonia gas is controlled to be between 550°C and 650°C, so that the dichlorosilane gas and ammonia gas react, thereby forming a silicon nitride film layer, i.e., the second sub-film layer 121, at least on the first sub-film layer 111 in the peripheral region 120, that is away from the substrate top surface 100b. The reaction temperature of the dichlorosilane gas and ammonia gas can be controlled to be between 550°C and 650°C by controlling the temperature of the first reaction chamber. The remaining gas in the first reaction chamber is removed, wherein the remaining gas includes unreacted ammonia gas and hydrogen chloride gas, a byproduct after silicon nitride is generated.

[0051] In some embodiments, during the first deposition process and the second deposition process, a carrier gas may be introduced at all times, with a flow rate of the carrier gas ranging from 10,000 sccm to 20,000 sccm. The carrier gas may be nitrogen.

[0052] In some embodiments, along the first direction X, the thickness of the first diffusion barrier layer 101 ranges from 1 nm to 8 nm.

[0053] S103: Reference Figure 5 , forming a second diffusion barrier layer 102 , the second diffusion barrier layer 102 is located on the top surface 101 a of the first diffusion barrier layer 101 away from the substrate 100 , and on the top surface 100 a of the substrate in the array region 110 .

[0054] In some embodiments, the direction from the substrate 100 to the first diffusion barrier layer 101 is a first direction X; forming the second diffusion barrier layer 102 may include the following steps:

[0055] refer to Figure 4 , forming a second diffusion barrier film 132 , the second diffusion barrier film 132 is located on the top surface 101 a of the first diffusion barrier layer 101 away from the substrate 100 , and on the top surface 100 a of the substrate in the array region 110 .

[0056] Combined with reference Figure 4 and Figure 5, remove part of the thickness of the second diffusion barrier film 132 in the peripheral area 120 along the first direction X, and the remaining second diffusion barrier film 132 in the peripheral area 120 serves as the second diffusion barrier layer 102 in the peripheral area 120 , and the second diffusion barrier film 132 in the array area 110 serves as the second diffusion barrier layer 102 in the array area 110 .

[0057] refer to Figure 5 Along the first direction X, the first thickness T1 of the second diffusion barrier layer 102 in the peripheral region 120 is less than the second thickness T2 of the second diffusion barrier layer 102 in the array region 110. It will be appreciated that, compared to the array region 110, the peripheral region 120 has an additional first diffusion barrier layer 101 on the substrate 100. Thus, designing the first thickness T1 to be less than the second thickness T2 helps reduce the difference between the overall thickness of the first diffusion barrier layer 101 and the second diffusion barrier layer 102 in the peripheral region 120 and the second thickness T2, thereby reducing the thickness difference between the peripheral region 120 and the array region 110 in the resulting semiconductor structure, thereby improving the structural stability of the resulting semiconductor structure.

[0058] In some embodiments, the thickness of the entire first diffusion barrier layer 101 and the second diffusion barrier layer 102 in the peripheral region 120 may be consistent with the second thickness T2 .

[0059] It should be noted that Figure 4 and Figure 5 Only the overall structure of the second diffusion barrier layer 102 is illustrated, and the internal structure of the second diffusion barrier layer 102 is not drawn.

[0060] In some embodiments, forming the second diffusion barrier layer 102 may include the following steps:

[0061] refer to Figure 6 A first magnetron sputtering deposition process is used to form a third sub-film layer 112; a second magnetron sputtering deposition process is used to form a fourth sub-film layer 122 on a surface of the third sub-film layer 112 away from the substrate, wherein argon is provided in the first magnetron sputtering deposition process, and argon and nitrogen are provided in the second magnetron sputtering deposition process.

[0062] In this way, the second diffusion barrier layer 102 is a stacked structure in which the third sub-layer 112 and the fourth sub-layer 122 are stacked along the first direction X.

[0063] In some embodiments, along the first direction X, the thickness of the second diffusion barrier layer 102 ranges from 2 nm to 10 nm.

[0064] In some embodiments, the material of the third sub-layer 112 may be titanium, and the material of the fourth sub-layer 122 may be titanium nitride. It is understood that the material of the second diffusion barrier layer 102 can be considered to be titanium doped with titanium nitride. On the one hand, the conductivity of the third sub-layer 112 is higher than that of the fourth sub-layer 122, and the contact between the third sub-layer 112 and the substrate 100 in the array area 110 helps reduce the contact resistance between the second diffusion barrier layer 102 and the substrate 100. On the other hand, the diffusion barrier capability of the third sub-layer 112 is lower than that of the fourth sub-layer 122, and the doped titanium nitride ensures the diffusion barrier capability of the second diffusion barrier layer 102. This helps ensure the good overall conductivity of the second diffusion barrier layer 102 while improving its overall diffusion barrier capability, achieving a two-pronged approach to enhance the electrical performance of the resulting semiconductor structure.

[0065] In some embodiments, along the first direction X, the thickness of the third sub-layer 112 is less than the thickness of the fourth sub-layer 122 .

[0066] In some embodiments, the first magnetron sputtering deposition process and the second magnetron sputtering deposition process may employ a DC magnetron sputtering method.

[0067] In some embodiments, forming the third sub-layer 112 by using the first magnetron sputtering deposition process may include the following steps:

[0068] The semiconductor structure with the first diffusion barrier layer 101 is placed in a second reaction chamber. A target made of titanium is positioned at the top of the second reaction chamber. A first strong electric field is applied to the second reaction chamber, and argon gas is supplied thereto. Electrons are accelerated by the first strong electric field and collide with argon atoms, ionizing a large number of argon ions and electrons. The argon ions are accelerated by the electric field and bombard the target, sputtering a large number of target atoms. These neutral target atoms (or molecules) are deposited on the semiconductor structure to form a film, forming a third sub-film layer 112 on the top surface 101a of the first diffusion barrier layer 101 away from the substrate 100 and on the top surface 100a of the substrate in the array region 110.

[0069] Among them, the power of the equipment used to apply the first strong electric field is 1500W~2500W, the gas flow range of argon is 8sccm~15sccm, the gas pressure in the second reaction chamber is 4torr, and the duration of forming the third sub-film layer 112 using the first magnetron sputtering deposition process is 2s~42s.

[0070] In some embodiments, forming the fourth sub-layer 122 using the second magnetron sputtering deposition process may include the following steps:

[0071] It is understandable that after the third sub-film layer 112 is formed, the second magnetron sputtering deposition process may be continued to be performed in the second reaction chamber.

[0072] A second strong electric field is applied to the second reaction chamber, and argon and nitrogen are provided into the second reaction chamber. Under the action of the electric field, electrons are accelerated and collide with argon atoms and nitrogen atoms, ionizing a large number of argon ions, nitrogen ions and electrons. Under the action of the electric field, the argon ions are accelerated to bombard the target material, sputtering a large number of target atoms. The neutral target atoms (or molecules) react with the nitrogen or nitrogen ions to form a fourth sub-film layer 122 on the side of the third sub-film layer 112 away from the substrate 100.

[0073] Among them, the power of the equipment used to apply the second strong electric field is 10000W~15000W, the gas flow range of argon is 5sccm~10sccm, the gas flow range of nitrogen is 40sccm~65sccm, the gas pressure in the second reaction chamber is 4torr, and the duration of forming the fourth sub-film layer 122 using the second magnetron sputtering deposition process is 50s~200s.

[0074] It should be noted that Figure 4 The second diffusion barrier film 132 formed in the above embodiment may also be formed in the same manner as the second diffusion barrier layer 102 in the above embodiment.

[0075] It can be understood that a second diffusion barrier layer 102 is formed on the substrate 100 of the array area 110, and a first diffusion barrier layer 101 and a second diffusion barrier layer 102 are formed on the substrate of the peripheral area 120. In this way, there are more layers of diffusion barrier layers between the conductive structure of the peripheral area 120 formed subsequently and the substrate 100, so as to further reduce the probability of element diffusion between the conductive structure in the peripheral area 120 and the substrate 100, thereby facilitating the improvement of the electrical performance of the conductive structure of the peripheral area 120 itself; at the same time, there are fewer layers of diffusion barrier layers between the conductive structure of the array area 110 and the substrate 100, which is beneficial to reducing the resistance of electrical signal transmission between the conductive structure of the array area 110 and the substrate 100, that is, reducing the contact resistance between the conductive structure of the array area 110 and the second diffusion barrier layer 102 and the contact resistance between the substrate 100 and the second diffusion barrier layer 102. Therefore, it is beneficial to ensure that the resistance of electrical signal transmission between the conductive structure of the array area 110 and the substrate 100 is low while effectively preventing elements in the substrate 100 of the peripheral area 120 from diffusing into the conductive structure.

[0076] It should be noted that the above “more layers” and “fewer layers” are both for the peripheral area 120 and the array area 110 .

[0077] In some embodiments, the first diffusion barrier layer 101 has a higher diffusion barrier capability for the diffusion of the doped ions than the second diffusion barrier layer 102, the doped ions including N-type doped ions and P-type doped ions. In this way, the diffusion barrier capability of the diffusion barrier layer between the conductive structure of the peripheral region 120 and the substrate 100 is further increased, so as to further reduce the probability of element diffusion between the conductive structure and the substrate 100 in the peripheral region 120, thereby facilitating improvement of the electrical performance of the conductive structure of the peripheral region 120.

[0078] In some embodiments, with reference to Figure 7 After the second diffusion barrier layer 102 is formed, before the conductive structure is formed, the manufacturing method can further include: performing rapid thermal processing on the second diffusion barrier layer 102 and the substrate 100, so as to form a third diffusion barrier layer 104 between the second diffusion barrier layer 102 and the substrate 100 of the array region 110.

[0079] In some embodiments, the material type of the substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide, or indium gallium, etc. The following is described by taking silicon as an example.

[0080] The substrate 100 includes silicon atoms, the second diffusion barrier layer 102 includes titanium atoms, the second diffusion barrier layer 102 and the substrate 100 of the array region 110 are in direct contact, the rapid thermal processing is performed on the second diffusion barrier layer 102 and the substrate 100, the silicon atoms in the substrate 100 and the titanium atoms in the second diffusion barrier layer 102 react, and a third diffusion barrier layer 104 including titanium silicide can be formed between the second diffusion barrier layer 102 and the substrate 100 of the array region 110.

[0081] It is understood that titanium silicide has a very low electrical resistance, typically around 20 μΩ·cm. Thus, forming a third diffusion barrier layer 104 between the second diffusion barrier layer 102 in the array region 110 and the substrate 100 facilitates further reducing the contact resistance between the diffusion barrier layer in the array region 110 and the substrate 100 via the third diffusion barrier layer 104, thereby further reducing the resistance of electrical signal transmission between the subsequently formed conductive structures in the array region 110 and the substrate 100. Furthermore, since the third diffusion barrier layer 104 is formed based on the second diffusion barrier layer 102 and the substrate 100, it does not significantly affect the thickness of the resulting semiconductor structure in the first direction X. Specifically, it prevents the resulting semiconductor structure from being excessively thick in the first direction X, thereby facilitating the stability of the resulting semiconductor structure. It should be noted that the diffusion barrier layer in the array region 110 includes the second diffusion barrier layer 102 and the third diffusion barrier layer 104.

[0082] In some embodiments, the step of performing rapid thermal treatment on the second diffusion barrier layer 102 and the substrate 100 may include: maintaining the second diffusion barrier layer 102 and the substrate 100 at a preset temperature for a preset time; wherein the preset temperature ranges from 700°C to 900°C, and the preset time ranges from 30s to 40s.

[0083] In some embodiments, continue to refer to Figure 7 , along the first direction X, the fifth thickness T5 of the first diffusion barrier layer 101 is greater than the sixth thickness T6 of the third diffusion barrier layer 104 .

[0084] S104: Combined with reference Figure 5 and Figure 8 A conductive structure 103 is formed on a surface of the second diffusion barrier layer 102 away from the substrate top surface 100 a .

[0085] In some embodiments, continue to refer to Figure 8 The step of forming the conductive structure 103 may include: along the first direction X, sequentially stacking a first conductive layer 113, a second conductive layer 123 and an isolation layer 133 on a surface of the second diffusion barrier layer 102 away from the substrate top surface 100a.

[0086] In some embodiments, the material of the first conductive layer 113 may be tungsten silicide, the material of the second conductive layer 123 may be tungsten, and the material of the isolation layer 133 may be silicon nitride.

[0087] In some embodiments, along the first direction X, the thickness of the second conductive layer 123 may be in a range of 20 nm to 25 nm.

[0088] It should be noted that Figure 8In the figure, the conductive structure 103 is only taken as a stacked structure in which a first conductive layer 113, a second conductive layer 123 and an isolation layer 133 are stacked along the first direction X. In actual applications, depending on actual needs, the conductive structure 103 can also be a single-layer structure or a multi-layer structure with other numbers of layers.

[0089] The manufacturing method provided by an embodiment of the present disclosure is described in detail below through a specific application scenario.

[0090] In some embodiments, providing the substrate 100 may include the following steps:

[0091] refer to Figure 9 A substrate 130 is provided, and the substrate 130 spans the array region 110 and the peripheral region 120. In practical applications, the semiconductor structure may further include a transition region (not shown) located between the array region 110 and the peripheral region 120 to connect the array region 110 and the peripheral region 120.

[0092] In some embodiments, continue to refer to Figure 9 The substrate 130 of the array region 110 has a plurality of active regions 140 arranged at intervals. Shallow trench isolation structures 160 are provided between adjacent active regions 140 .

[0093] In some embodiments, continue to refer to Figure 9 The substrate 130 in the peripheral region 120 also has a plurality of active regions 140 arranged at intervals. Shallow trench isolation structures 160 are provided between adjacent active regions 140. It is understood that the substrate 130 may further include a support portion 170 that supports the active regions 140 and the shallow trench isolation structures 160.

[0094] It should be noted that Figure 9 The active area 140 and the support portion 170 are separated by a dotted line.

[0095] Continue to refer Figure 9 , forming a first semiconductor layer 105 , the first semiconductor layer 105 covering the substrate top surface 130 a . It is understood that the first semiconductor layer 105 can be used to form a gate structure in the peripheral region 120 later.

[0096] It should be noted that the manufacturing method may further include forming a gate dielectric layer (not shown) between the first semiconductor layer 105 in the peripheral region 120 and the active region 140 .

[0097] In some embodiments, the step of forming the first diffusion barrier layer 101 on the top surface of the substrate 100 in the peripheral region 120 may include: referring to Figure 10, forming a first diffusion barrier film 131, the first diffusion barrier film 131 covers the surface of the first semiconductor layer 105 away from the substrate top surface 130a; combined with reference Figure 10 and Figure 11 The first diffusion barrier film 131 is patterned to remove the first diffusion barrier film 131 in the array region 110 , and the remaining first diffusion barrier film 131 in the peripheral region 120 serves as the first diffusion barrier layer 101 .

[0098] It should be noted that Figure 10 The first diffusion barrier film 131 formed in the above embodiment may also be formed in the same manner as the first diffusion barrier layer 101 in the above embodiment.

[0099] In some embodiments, after forming the first diffusion barrier layer 101 and before forming the second diffusion barrier layer 102, the manufacturing method may further include the following steps:

[0100] Combined with reference Figure 11 and Figure 12 , the first semiconductor layer 105 in the array area 110 is removed.

[0101] Continue to refer Figure 12 The substrate 130 of the array area 110 is patterned to form a plurality of grooves 150 extending from the substrate top surface 130 a into the substrate 130 . The grooves 150 correspond to the active areas 140 one by one, and the grooves 150 expose portions of the active areas 140 .

[0102] It should be noted that, based on the arrangement of the active area 140, Figure 12 The cross-sectional structural diagram shown only shows part of the groove 150, namely Figure 12 Among the plurality of active regions 140 , only the grooves 150 corresponding to some of the active regions 140 are shown schematically.

[0103] refer to Figures 12 to 14 , forming the second semiconductor layer 106, the second semiconductor layer 106 fills the groove 150. In some embodiments, the step of forming the second semiconductor layer 106 may include: combining the reference Figure 12 and Figure 13 , forming a second semiconductor film 116, the second semiconductor film 116 not only fills the groove 150, but is also located on the top surface of the substrate 130 of the array region 110; Figure 13 and Figure 14 The second semiconductor film 116 is etched back until the top surface of the substrate 130 in the array region 110 is exposed, and the remaining second semiconductor film 116 serves as the second semiconductor layer 106 .

[0104] On this basis, the steps of forming the second diffusion barrier layer 102 may include: referring to Figure 14A second diffusion barrier layer 102 is formed on the surface formed by the second semiconductor layer 106 and the remaining substrate 130. It should be noted that the steps of forming the second diffusion barrier layer 102 are the same as or corresponding to those in the above embodiment and are not described in detail here.

[0105] In some embodiments, continue to refer to Figure 14 A conductive structure 103 is formed on the surface of the second diffusion barrier layer 102 away from the top surface of the substrate. It should be noted that the steps of forming the conductive structure 103 are the same as or corresponding to those in the above embodiment and are not described in detail here.

[0106] In some embodiments, the first semiconductor layer 105, the second semiconductor layer 106, the first diffusion barrier layer 101, the second diffusion barrier layer 102 and the conductive structure 103 constitute a composite film layer (not shown in the figure); after forming the conductive structure 103, the manufacturing method may further include: Figure 14 and Figure 15 The combined film layer is patterned to form a plurality of bit line structures 107 spaced apart along the second direction Y in the array region 110 , and a gate structure 108 in the peripheral region 120 .

[0107] From the above analysis, it can be seen that the number of diffusion barrier layers between the conductive structures in the peripheral region 120 and the substrate 100 is greater than the number of diffusion barrier layers between the conductive structures in the array region 110 and the substrate 100. This helps ensure low resistance in electrical signal transmission between the conductive structures in the array region 110 and the substrate 100 while effectively preventing elements in the substrate 100 from diffusing into the conductive structures in the peripheral region 120. Furthermore, compared to the small size of the bitline structures 107 in the array region 110, the gate structures 108 in the peripheral region 120 are larger. In other words, compared to the contact area between the bitline structures 107 in the array region 110 and the second diffusion barrier layer 102, the contact area between the gate structures 108 in the peripheral region 120 and the second diffusion barrier layer 102 is larger. Based on this, even if there are more layers of diffusion barrier layers between the gate structure 108 in the peripheral region 120 and the substrate 100, the resistance of electrical signal transmission between the gate structure 108 in the peripheral region 120 and the substrate 100 will not be greatly affected by the increase in the number of diffusion barrier layers, as compensated by the sufficiently large contact area between the gate structure 108 and the second diffusion barrier layer 102.

[0108] In other words, the contact area between the bit line structure 107 and the second diffusion barrier layer 102 in the array region 110 is relatively small, and the increase in the number of diffusion barrier layers has a greater impact on the magnitude of the resistance of electrical signal transmission between the bit line structure 107 and the substrate 100. In comparison, the contact area between the gate structure 108 and the second diffusion barrier layer 102 in the peripheral region 120 is relatively large, so that the resistance of electrical signal transmission between the gate structure 108 in the peripheral region 120 and the substrate 100 is less affected by the number of diffusion barrier layers.

[0109] In summary, a second diffusion barrier layer 102 is formed between the conductive structure 103 in the array area 110 and the substrate 100, and a first diffusion barrier layer 101 and a second diffusion barrier layer 102 are formed between the conductive structure 103 in the peripheral area 120 and the substrate 100. In this way, more diffusion barrier layers are formed between the conductive structure 103 in the peripheral area 120 and the substrate 100, thereby further reducing the probability of element diffusion between the conductive structure 103 in the peripheral area 120 and the substrate 100, thereby facilitating improvement of the electrical performance of the conductive structure 103 in the peripheral area 120. At the same time, fewer diffusion barrier layers are formed between the conductive structure 103 in the array area 110 and the substrate 100, thereby facilitating reduction of the resistance of electrical signal transmission between the conductive structure 103 in the array area 110 and the substrate 100, i.e., reducing the contact resistance between the conductive structure 103 in the array area 110 and the second diffusion barrier layer 102, as well as the contact resistance between the substrate 100 and the second diffusion barrier layer 102. Therefore, it is beneficial to ensure that the resistance of electrical signal transmission between the conductive structure 103 in the array area 110 and the substrate 100 is low while effectively preventing elements in the substrate 100 in the peripheral area 120 from diffusing into the conductive structure 103 .

[0110] Another embodiment of the present disclosure further provides a semiconductor structure formed by the manufacturing method provided in the aforementioned embodiment. The semiconductor structure provided in another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are identical or corresponding to the aforementioned embodiments are not described in detail here.

[0111] refer to Figure 8The semiconductor structure includes an array region 110 and a peripheral region 120. The semiconductor structure may include: a substrate 100, the substrate 100 spanning the array region 110 and the peripheral region 120; a first diffusion barrier layer 101, located on a top surface 100b of the substrate in the peripheral region 120; a second diffusion barrier layer 102, located on a top surface 101a of the first diffusion barrier layer 101 away from the substrate 100, and located on the top surface 100a of the substrate in the array region 110, the first diffusion barrier layer 101 having a higher diffusion barrier capability for doped ions than the second diffusion barrier layer 102, and the doped ions include N-type doped ions and P-type doped ions; and a conductive structure 103, located on a surface of the second diffusion barrier layer 102 away from the top surface of the substrate 100.

[0112] In this way, the use of the first diffusion barrier layer 101 is beneficial to further increase the diffusion barrier capability of the diffusion barrier layer between the conductive structure of the peripheral area 120 and the substrate 100 formed subsequently, so as to further reduce the probability of element diffusion between the conductive structure in the peripheral area 120 and the substrate 100, thereby helping to improve the electrical performance of the conductive structure of the peripheral area 120 itself.

[0113] In some embodiments, the first diffusion barrier layer 101 is composed of nitrogen atoms, titanium atoms, and silicon atoms, and the second diffusion barrier layer 102 is composed of nitrogen atoms and titanium atoms. It is understood that the material of the first diffusion barrier layer 101 can be considered as titanium nitride doped with silicon nitride. The doped silicon nitride improves the diffusion barrier capability of the first diffusion barrier layer 101 against elements, thereby further reducing the probability of element diffusion between the conductive structure 103 in the peripheral region 120 and the substrate 100, thereby improving the electrical performance of the conductive structure 103 in the peripheral region 120.

[0114] Furthermore, the material of the second diffusion barrier layer 102 can be considered titanium doped with titanium nitride. On the one hand, the conductivity of the third sub-layer 112 is higher than that of the fourth sub-layer 122, and the contact between the third sub-layer 112 and the substrate 100 in the array region 110 helps reduce the contact resistance between the second diffusion barrier layer 102 and the substrate 100. On the other hand, the diffusion barrier capability of the third sub-layer 112 is lower than that of the fourth sub-layer 122, and the doped titanium nitride ensures the diffusion barrier capability of the second diffusion barrier layer 102. This helps ensure the good conductivity of the second diffusion barrier layer 102 while improving its overall diffusion barrier capability, achieving a two-pronged approach to enhance the overall electrical performance of the semiconductor structure.

[0115] In some embodiments, reference Figure 3The first diffusion barrier layer 101 may include a first sub-membrane layer 111 and a second sub-membrane layer 121 alternately stacked along a first direction X, the material of the second sub-membrane layer 121 is different from the material of the first sub-membrane layer 111, and the direction in which the substrate 100 points to the first diffusion barrier layer 101 is the first direction X; wherein, along the first direction X, the ratio of the third thickness T3 of the first sub-membrane layer 111 to the fourth thickness T4 of the second sub-membrane layer 121 is not less than 15.

[0116] This helps, on the one hand, ensure good overall conductivity of the first diffusion barrier layer 101, thereby reducing the resistance of electrical signal transmission between the conductive structures in the array region and the substrate. Furthermore, designing the second sub-layer 121 to be significantly thinner than the first sub-layer 111 helps, through the second sub-layer 121, enhance the overall diffusion barrier capability of the first diffusion barrier layer 101 against elements, further reducing the probability of element diffusion between the conductive structures 103 in the peripheral region 120 and the substrate 100, thereby improving the electrical performance of the conductive structures 103 in the peripheral region 120. Thus, while ensuring good overall conductivity of the first diffusion barrier layer 101, the overall diffusion barrier capability of the first diffusion barrier layer 101 against elements is enhanced, achieving a two-pronged approach to enhance the overall electrical performance of the semiconductor structure.

[0117] In some embodiments, reference Figure 5 Along the first direction, the first thickness T1 of the second diffusion barrier layer 102 in the peripheral region 120 is less than the second thickness T2 of the second diffusion barrier layer 102 in the array region 110. The direction from the substrate 100 to the first diffusion barrier layer 101 is the first direction X. This helps reduce the difference between the overall thickness of the first diffusion barrier layer 101 and the second diffusion barrier layer 102 in the peripheral region 120 and the second thickness T2, thereby reducing the overall thickness difference of the semiconductor structure between the peripheral region 120 and the array region 110, and improving the overall structural stability of the semiconductor structure.

[0118] In some embodiments, reference Figure 7The semiconductor structure may further include a third diffusion barrier layer 104 located between the second diffusion barrier layer 102 in the array region 110 and the substrate 100. Along the first direction X, the fifth thickness T5 of the first diffusion barrier layer 101 is greater than the sixth thickness T6 of the third diffusion barrier layer 104. This facilitates further reducing the contact resistance between the diffusion barrier layer in the array region 110 and the substrate 100 via the third diffusion barrier layer 104, thereby further reducing the resistance of electrical signal transmission between subsequently formed conductive structures in the array region 110 and the substrate 100. Furthermore, since the third diffusion barrier layer 104 is formed based on the second diffusion barrier layer 102 and the substrate 100, it does not significantly affect the thickness of the overall semiconductor structure in the first direction X. Specifically, it prevents the overall thickness of the semiconductor structure in the first direction X from being excessively thick, thereby ensuring the overall structural stability of the semiconductor structure.

[0119] In some embodiments, reference Figure 8 , the second diffusion barrier layer 102 may be a single film layer structure; in other embodiments, refer to Figure 6 The second diffusion barrier layer 102 includes a third sub-layer 112 and a fourth sub-layer 122 stacked along the first direction X.

[0120] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The semiconductor structure includes an array region and a peripheral region, and the manufacturing method includes: Providing a substrate, the substrate spanning the array region and the peripheral region; forming a first diffusion barrier layer on a top surface of the substrate in the peripheral region; A second diffusion barrier layer is formed, the second diffusion barrier layer being located on a top surface of the first diffusion barrier layer away from the substrate and on the top surface of the substrate in the array region; the first diffusion barrier layer has a higher diffusion barrier capability for doped ions than the second diffusion barrier layer, the doped ions including N-type doped ions and P-type doped ions; and a conductive structure is formed on a surface of the second diffusion barrier layer away from the top surface of the substrate.

2. The manufacturing method according to claim 1, characterized in that The first diffusion barrier layer is composed of nitrogen atoms, titanium atoms, and silicon atoms, and the second diffusion barrier layer is composed of nitrogen atoms and titanium atoms.

3. The manufacturing method according to claim 1 or 2, characterized in that: The step of forming the first diffusion barrier layer includes: Forming a first sub-film layer on the top surface of the substrate in the peripheral area using a first deposition process; forming a second sub-film layer on a surface of the first sub-film layer away from the top surface of the substrate using a second deposition process, wherein the material of the second sub-film layer is different from that of the first sub-film layer; The first deposition process and the second deposition process are alternately performed N times on the surface of the second sub-film layer away from the first sub-film layer, where N is a positive integer. The alternately stacked first sub-film layer and the second sub-film layer constitute the first diffusion barrier layer.

4. The manufacturing method according to claim 3, characterized in that Forming the first sub-film layer by using the first deposition process includes: performing the first sub-deposition process M times to form the first sub-film layer, where M is a positive integer; The first sub-deposition process includes: providing titanium tetrachloride gas and ammonia gas in sequence, and controlling the reaction temperature of the titanium tetrachloride gas and the ammonia gas to be 550°C~650°C; wherein the gas flow rate range of the titanium tetrachloride gas is 120sccm~180sccm, and the time range of providing the titanium tetrachloride gas is 0.03s~0.06s; the gas flow rate range of the ammonia gas is 3500sccm~5000sccm, and the time range of providing the ammonia gas is 0.2s~0.4s.

5. The manufacturing method according to claim 3, characterized in that The second deposition process includes: sequentially providing dichlorosilane gas and ammonia gas, and controlling the reaction temperature of the dichlorosilane gas and the ammonia gas to be 550° C. to 650° C.; The gas flow rate of the dichlorosilane gas is in the range of 80 sccm to 120 sccm, and the time for providing the dichlorosilane gas is in the range of 0.03 s to 0.06 s; the gas flow rate of the ammonia gas is in the range of 3500 sccm to 5000 sccm, and the time for providing the ammonia gas is in the range of 0.2 s to 0.4 s.

6. The manufacturing method according to claim 1 or 2, characterized in that: The step of forming the second diffusion barrier layer includes: forming a third sub-film layer by adopting a first magnetron sputtering deposition process; A fourth sub-film layer is formed on a surface of the third sub-film layer away from the substrate by a second magnetron sputtering deposition process, wherein argon gas is provided in the first magnetron sputtering deposition process, and argon gas and nitrogen gas are provided in the second magnetron sputtering deposition process.

7. The manufacturing method according to claim 1 or 2, characterized in that: After forming the second diffusion barrier layer and before forming the conductive structure, the method further includes: The second diffusion barrier layer and the substrate are subjected to a rapid thermal process to form a third diffusion barrier layer between the second diffusion barrier layer in the array region and the substrate.

8. The manufacturing method according to claim 1 or 2, characterized in that: The direction from the substrate to the first diffusion barrier layer is a first direction; The step of forming the second diffusion barrier layer includes: forming a second diffusion barrier film, wherein the second diffusion barrier film is located on a top surface of the first diffusion barrier layer away from the substrate and on a top surface of the substrate in the array region, and the second diffusion barrier film in the array region serves as the second diffusion barrier layer in the array region; Part of the thickness of the second diffusion barrier film in the peripheral area along the first direction is removed, and the remaining second diffusion barrier film in the peripheral area serves as the second diffusion barrier layer in the peripheral area. Along the first direction, the first thickness of the second diffusion barrier layer in the peripheral area is less than the second thickness of the second diffusion barrier layer in the array area.

9. The manufacturing method according to claim 1 or 2, characterized in that: The step of providing the substrate comprises: providing a substrate, the substrate spanning the array region and the peripheral region; forming a first semiconductor layer, wherein the first semiconductor layer covers the top surface of the substrate; The first diffusion barrier layer is formed on the top surface of the substrate in the peripheral area, including: forming a first diffusion barrier film, the first diffusion barrier film covering the surface of the first semiconductor layer away from the top surface of the substrate; and performing patterning on the first diffusion barrier film to remove the first diffusion barrier film in the array area, and the remaining first diffusion barrier film in the peripheral area serves as the first diffusion barrier layer.

10. The manufacturing method according to claim 9, characterized in that: The substrate of the array region has a plurality of active regions arranged at intervals; after forming the first diffusion barrier layer and before forming the second diffusion barrier layer, the method further includes: removing the first semiconductor layer in the array area; Performing a patterning process on the substrate in the array region to form a plurality of grooves extending from the top surface of the substrate into the substrate, wherein the grooves correspond to the active regions one by one and the grooves expose a portion of the active regions; forming a second semiconductor layer, wherein the second semiconductor layer completely fills the groove; The step of forming the second diffusion barrier layer includes: forming the second diffusion barrier layer on a surface jointly formed by the second semiconductor layer and the remaining substrate.

11. A semiconductor structure, characterized in that The semiconductor structure includes an array region and a peripheral region, and the semiconductor structure includes: a substrate spanning the array region and the peripheral region; a first diffusion barrier layer located on the top surface of the substrate in the peripheral region; a second diffusion barrier layer, located on a top surface of the first diffusion barrier layer away from the substrate and on the top surface of the substrate in the array region, wherein the first diffusion barrier layer has a higher diffusion barrier capability for dopant ions than the second diffusion barrier layer, and the dopant ions include N-type dopant ions and P-type dopant ions; The conductive structure is located on a surface of the second diffusion barrier layer away from the top surface of the substrate.

12. The semiconductor structure according to claim 11, wherein: The first diffusion barrier layer includes a first sub-film layer and a second sub-film layer alternately stacked along a first direction, the material of the second sub-film layer is different from the material of the first sub-film layer, and the direction from the substrate to the first diffusion barrier layer is the first direction; Wherein, along the first direction, the ratio of the third thickness of the first sub-film layer to the fourth thickness of the second sub-film layer is not less than 15.

13. The semiconductor structure according to claim 11, wherein: Along a first direction, a first thickness of the second diffusion barrier layer in the peripheral region is smaller than a second thickness of the second diffusion barrier layer in the array region. The direction from the substrate to the first diffusion barrier layer is the first direction.

14. The semiconductor structure according to any one of claims 11 to 13, characterized in that Also includes: The third diffusion barrier layer is located between the second diffusion barrier layer in the array region and the substrate. Along the first direction, a fifth thickness of the first diffusion barrier layer is greater than a sixth thickness of the third diffusion barrier layer.

15. The semiconductor structure according to any one of claims 11 to 13, characterized in that The second diffusion barrier layer is a single-layer structure, or the second diffusion barrier layer includes a third sub-layer and a fourth sub-layer stacked along the first direction.

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