Semiconductor device, manufacturing method thereof and memory system

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method thereof and a memory system. The semiconductor device comprises a first semiconductor structure; the first semiconductor structure comprises a transistor, a first capacitor and a second capacitor; wherein the first capacitor is located at one end of the transistor; the connecting layer is located between the first capacitor and the transistor; the connecting part is positioned between the first capacitor and the transistor; the connecting part penetrates through the connecting layer; one end of the connecting part is coupled with the first capacitor, and the other end of the connecting part is coupled with a first active region of the transistor; the first interconnection part penetrates through the connection layer; the first contact structure and the second capacitor are located on the two opposite sides of the connecting layer respectively; wherein one end of the first interconnection part is coupled with the second capacitor, and the other end of the first interconnection part is coupled with the first contact structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof, and a memory system. Background Art

[0002] Some semiconductor devices, such as dynamic random access memory (DRAM), may include a storage array and a control circuit. The control circuit may control the storage array and operate the storage array to read, write or erase.

[0003] The control circuit includes different capacitors to realize various electrical functions of the control circuit, thereby controlling the memory array. As the integration of the memory array increases, the integration of the control circuit also needs to be continuously improved to meet the control of the highly integrated memory array, so the integration of the capacitor in the control circuit also increases accordingly. Therefore, how to improve the integration of the capacitor becomes a problem to be solved urgently. Summary of the invention

[0004] According to some aspects of the embodiments of the present disclosure, there is provided a semiconductor device, including:

[0005] A first semiconductor structure; the first semiconductor structure comprises:

[0006] A transistor, a first capacitor and a second capacitor; wherein the first capacitor is located at one end of the transistor;

[0007] A connecting layer, located between the first capacitor and the transistor;

[0008] A connecting portion, located between the first capacitor and the transistor; the connecting portion passes through the connecting layer; one end of the connecting portion is coupled to the first capacitor, and the other end is coupled to the first active region of the transistor;

[0009] A first interconnection portion, penetrating the connection layer;

[0010] The first contact structure and the second capacitor are respectively located on opposite sides of the connection layer; wherein one end of the first interconnection portion is coupled to the second capacitor, and the other end is coupled to the first contact structure.

[0011] In some embodiments, the semiconductor device further comprises:

[0012] The second semiconductor structure is located at one side of the first semiconductor structure, and the second semiconductor structure is bonded to the first semiconductor structure; wherein the second semiconductor structure is coupled to the second capacitor.

[0013] In some embodiments, the second semiconductor structure includes a first CMOS structure and a second CMOS structure, and the first contact structure is located between the second CMOS structure and the first interconnection portion; wherein the second active region of the transistor is coupled to the first CMOS structure; one end of the first contact structure is coupled to the first interconnection portion, and the other end is coupled to the second CMOS structure.

[0014] In some embodiments, the first semiconductor structure includes an array region and a peripheral region; wherein the first capacitor is located in the array region, and the second capacitor is located in the peripheral region; the connection layer is located in the array region and the peripheral region, and the first interconnection portion is located in the peripheral region.

[0015] In some embodiments, the second capacitor is located on a side of the first interconnection portion away from the transistor, and the second capacitor has the same structure as the first capacitor.

[0016] In some embodiments, along a direction parallel to the connection layer, the first capacitor includes:

[0017] A first electrode, and a first dielectric layer surrounding the first electrode and a second electrode; the first dielectric layer is located between the first electrode and the second electrode.

[0018] In some embodiments, the second electrode of the first capacitor is coupled to the connecting portion; and the second electrode of the second capacitor is coupled to the first interconnecting portion.

[0019] In some embodiments, the first semiconductor structure further comprises:

[0020] The first interconnection layer is located at one end of the first capacitor and the second capacitor away from the transistor; the first interconnection layer is coupled to the electrode of the first capacitor away from the transistor, and the first interconnection layer is coupled to the electrode of the second capacitor away from the first interconnection portion.

[0021] In some embodiments, the first interconnect layer includes:

[0022] A first interconnection sublayer and a second interconnection sublayer are electrically isolated from each other; the first interconnection sublayer is coupled to an electrode of the first capacitor away from the transistor, and the second interconnection sublayer is coupled to an electrode of the second capacitor away from the first interconnection portion.

[0023] In some embodiments, the first semiconductor structure further comprises:

[0024] The bit line is located at a side of the transistor close to the second semiconductor structure; the bit line is coupled to the second active region of the transistor.

[0025] In some embodiments, the bit line is coupled to the first CMOS structure.

[0026] In some embodiments, the transistor includes:

[0027] A semiconductor column extending along a first direction perpendicular to the connection layer; a first active region and a second active region of the transistor are respectively located at two opposite ends of the semiconductor column in the first direction;

[0028] A gate dielectric layer and a gate; wherein the gate and the gate dielectric layer at least cover one side of the semiconductor column, and the gate dielectric layer is located between the semiconductor column and the gate.

[0029] According to some aspects of the embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided to form a first semiconductor structure. The method for forming the first semiconductor structure includes:

[0030] forming a transistor;

[0031] forming a connection layer on the transistor;

[0032] forming a connecting portion and a first interconnecting portion penetrating the connecting layer;

[0033] A first capacitor is formed on the connecting portion, and a second capacitor is formed on the first interconnecting portion; wherein one end of the connecting portion is coupled to the first capacitor, and the other end is coupled to the first active area of ​​the transistor;

[0034] A first contact structure is formed on a side of the first interconnection portion away from the second capacitor; wherein one end of the first interconnection portion is coupled to the second capacitor, and the other end is coupled to the first contact structure.

[0035] In some embodiments, the manufacturing method further comprises:

[0036] forming a second semiconductor structure;

[0037] The second semiconductor structure is bonded to the first semiconductor structure; wherein the second semiconductor structure is coupled to the second capacitor.

[0038] In some embodiments, the connection layer includes an array region and a peripheral region; and a method of forming the connection portion and the first interconnection portion includes:

[0039] forming a mask layer on the connection layer, and forming a first pattern in a region of the mask layer located in the array region;

[0040] forming a photoresist layer on the mask layer including the first pattern, wherein the photoresist layer covers the first pattern and a region of the mask layer located in the peripheral area;

[0041] Forming a second pattern in a region of the photoresist layer located in the array region, wherein the second pattern reveals the first pattern; forming the second pattern in a region of the photoresist layer located in the peripheral region;

[0042] Using the photoresist layer including the second pattern and the mask layer including the first pattern as etching masks, etching the connection layer to form a first opening and a second opening penetrating the connection layer; wherein the first opening is located in the array region and exposes the first active region of the transistor, and the second opening is located in the peripheral region;

[0043] The connecting portion is formed in the first opening, and the first interconnection portion is formed in the second opening.

[0044] In some embodiments, a method of forming the first capacitor and the second capacitor includes:

[0045] Forming a second dielectric layer on the connecting portion and the first interconnecting portion, forming a first capacitor hole and a second capacitor hole penetrating the second dielectric layer; wherein the first capacitor hole exposes the connecting portion, and the second capacitor hole exposes the first interconnecting portion;

[0046] The first capacitor is formed in the first capacitor hole, and the second capacitor is formed in the second capacitor hole; wherein, along a direction parallel to the connecting layer, the first capacitor includes a first electrode, and a first dielectric layer and a second electrode surrounding the first electrode; the first dielectric layer is located between the first electrode and the second electrode, and the second electrode is coupled to the connecting portion;

[0047] The structure of the second capacitor is the same as that of the first capacitor, and the second electrode of the second capacitor is coupled to the first interconnection portion.

[0048] In some embodiments, the method of forming the first semiconductor structure further includes:

[0049] A first interconnection layer is formed on a side of the first capacitor and the second capacitor away from the connection layer; wherein the first interconnection layer is coupled to an electrode of the second capacitor away from the first interconnection portion, and the first interconnection layer is coupled to an electrode of the first capacitor away from the transistor.

[0050] In some embodiments, the method of forming the first semiconductor structure further includes:

[0051] A bit line is formed at one end of the transistor away from the first capacitor, and the bit line is coupled to the second active region of the transistor.

[0052] In some embodiments, a method of forming the transistor includes:

[0053] forming a semiconductor column extending in a first direction perpendicular to the connection layer; doping two ends of the semiconductor column in the first direction to form a first active region and a second active region;

[0054] forming a gate dielectric layer on the side of the semiconductor column;

[0055] forming a gate on the gate dielectric layer;

[0056] Wherein, the gate dielectric layer is located between the semiconductor column and the gate.

[0057] According to some aspects of the embodiments of the present disclosure, there is provided a memory system, including:

[0058] One or more semiconductor devices as described above; and

[0059] A memory controller is coupled to the semiconductor device and controls the semiconductor device.

[0060] In the embodiment of the present disclosure, a transistor, a first capacitor and a second capacitor are arranged in the first semiconductor structure. The first capacitor is coupled with the transistor to form a capacitor for storing data. The second capacitor is coupled with the first interconnection portion to be configured as a capacitor in a CMOS control circuit. A first contact structure is arranged to couple with the first interconnection portion to lead out the signal of the second capacitor to interconnect with other semiconductor structures. Compared with the solution of arranging the second capacitor in other semiconductor structures to form a control circuit, the size and arrangement of the second capacitor in the embodiment of the present disclosure will not limit the improvement of the integration of other control circuit devices in other semiconductor structures, and while improving the integration of the second capacitor, the integration of the control circuit can be maintained or even improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure;

[0062] Figure 2 is a schematic diagram of a first capacitor according to an embodiment of the present disclosure;

[0063] Figure 3 is a schematic diagram of another first capacitor according to an embodiment of the present disclosure;

[0064] Figure 4 is a schematic diagram of a manufacturing process of a first semiconductor structure according to an embodiment of the present disclosure;

[0065] Figure 5a to Figure 5c is a schematic diagram of a method for manufacturing a first semiconductor structure according to an embodiment of the present disclosure;

[0066] Figures 6a to 6f is a schematic diagram of a method for manufacturing a connecting portion and a first interconnecting portion according to an embodiment of the present disclosure;

[0067] Figures 7a to 7e is a schematic diagram of another method for manufacturing a connecting portion and a first interconnecting portion according to an embodiment of the present disclosure;

[0068] Figure 8a to Figure 8g is a schematic diagram of a method for manufacturing a semiconductor device having a second semiconductor structure according to an embodiment of the present disclosure;

[0069] Fig. 9 is a schematic diagram of a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0070] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0071] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0072] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0073] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0074] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0075] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0076] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0077] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0078] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0079] In a dynamic random access memory, the memory array and the control circuit may be arranged in different areas of the same substrate, and the control circuit may include a CMOS control circuit having a CMOS structure. For example, the memory array and the control circuit may be arranged horizontally in parallel, that is, the control circuit may be arranged at one end of the memory array. Alternatively, the memory array and the circuit may be arranged on different substrates, and then the memory array and the circuit may be interconnected by electrical signals through a bonding process, and the control circuit may be located above or below the memory array.

[0080] As a part of the control circuit, the capacitor is often manufactured together with other components of the control circuit. The capacitor may include a first electrode, a dielectric layer and a second electrode, wherein the dielectric layer electrically isolates the first electrode from the second electrode, and different voltages may be applied to the first electrode and the second electrode, respectively, and the dielectric layer includes an insulating material or an air gap.

[0081] Compared to the size of the gate and other components in the CMOS transistor in the control circuit, the first electrode, dielectric layer and second electrode of the capacitor have larger sizes to obtain a larger electrode facing area (the area where the first electrode overlaps with the second electrode), thereby maintaining a higher capacitance and a higher withstand voltage, and reducing the risk of the capacitor being broken down by high voltage. In some control circuits, multiple capacitors are often connected in series or in parallel to configure circuits with different functions, so the capacitor will occupy a part of the area of ​​the control circuit, which will limit the improvement of the integration of devices such as CMOS transistors. And when the integration of the capacitor increases, the area occupied by the capacitor in the control circuit will further increase, further compressing the production area of ​​other devices in the control circuit, hindering the improvement of the integration of the control circuit.

[0082] As the integration of DRAM memory arrays continues to increase, the integration of control circuits is also increasing, and the integration of capacitors is also increasing. In this regard, an embodiment of the present disclosure provides a semiconductor device.

[0083] According to some aspects of the embodiments of the present disclosure, Figure 1 A semiconductor device 100 is provided. Figure 1 As shown, the semiconductor device 100 includes:

[0084] A first semiconductor structure 101; the first semiconductor structure 101 comprises:

[0085] A transistor 111, a first capacitor 112 and a second capacitor 113; wherein the first capacitor 112 is located at one end of the transistor 111;

[0086] A connection layer 115, located between the first capacitor 112 and the transistor 111;

[0087] The connecting portion 116 is located between the first capacitor 112 and the transistor 111; the connecting portion 116 penetrates the connecting layer 115; one end of the connecting portion 116 is coupled to the first capacitor 112, and the other end is coupled to the first active region of the transistor 111;

[0088] A first interconnection portion 117, penetrating the connection layer 115;

[0089] The first contact structure 1141 and the second capacitor 113 are respectively located on two opposite sides of the connection layer 115 ; wherein one end of the first interconnection portion 117 is coupled to the second capacitor 113 , and the other end is coupled to the first contact structure 1141 .

[0090] Reference Figure 1 As shown, the z direction can be the first direction, and the x direction is perpendicular to the z direction and can be the second direction. In the first semiconductor structure 101, the first capacitor 112 and the transistor 111 are stacked in the z direction, and the first capacitor 112 is coupled to the first active region of the transistor 111. The first active region is located at one end of the transistor 111 in the positive z direction, and the second active region is located at one end of the transistor 111 in the negative z direction. The first capacitor 112 can be configured as a capacitor for storing data. A first capacitor 112 and a transistor 111 can constitute a DRAM storage unit. The first capacitor 112 can be selected or deselected by turning on and off the transistor 111, thereby realizing the read, write or update operation of the selected storage unit. Specifically, the first capacitor 112 may include two electrically isolated electrodes, such as Figure 2The first electrode 1121 and the second electrode 1123 of the example, the second electrode 1123 is coupled to the first active region (source) of the transistor 111, the first electrode 1121 of the first capacitor 112 can be grounded or applied with other operating voltages (such as Vcc / 2); the second active region (drain) of the transistor 111 is coupled to the bit line 119. The disclosed embodiment does not show the number of the first capacitor 112 and the transistor 111, and the first capacitor 112 array can be coupled to the transistor 111 array to form a DRAM storage array. The source and drain of the transistor 111 in the disclosed embodiment are interchangeable.

[0091] In some embodiments, the first capacitor 112 represents logical 1 and 0 by the amount of charge stored therein, or the high and low voltage difference across the capacitor structure. Specifically, a voltage signal can be applied to the gate 1112 of the transistor 111 through a word line to control the on or off of the transistor 111, thereby selecting or deselecting the capacitor structure, and then reading the data information stored in the capacitor structure through the bit line 119, or writing the data into the capacitor through the bit line 119 for storage.

[0092] The second capacitor 113 may not be coupled to the transistor 111. The second capacitor 113 may be configured as a capacitor in a control circuit (eg, a CMOS control circuit). Other components of the CMOS control circuit may be connected to other semiconductor structures (eg, Figure 1 The CMOS control circuit can be used to control the operation of the transistor 111, and can also be used to provide a ground voltage or other operating voltage (such as Vcc / 2) to the first electrode 1121 of the first capacitor 112 that is not coupled to the transistor 111.

[0093] In some embodiments, the second capacitor 113 may be configured as a capacitor of a charge pump to achieve voltage step-up or step-down or negative voltage conversion to provide different operating voltages for the memory array.

[0094] In some embodiments, the second capacitor 113 may be configured as a decoupling capacitor to reduce noise interference between different voltages of different modules within the device.

[0095] In the embodiment of the present disclosure, a transistor 111, a first capacitor 112 and a second capacitor 113 are arranged in the first semiconductor structure 101. The first capacitor 112 is coupled with the transistor 111 to form a capacitor for storing data. The second capacitor 113 is coupled with the first interconnection 117 to be configured as a capacitor in a CMOS control circuit. A first contact structure 1141 is arranged to couple with the first interconnection 117 to lead out a signal of the second capacitor 113 to interconnect with other semiconductor structures. Compared with the solution of arranging the second capacitor 113 in other semiconductor structures to form a control circuit, the size and arrangement of the second capacitor 113 in the embodiment of the present disclosure will not limit the improvement of the integration of other control circuit devices in other semiconductor structures, and the integration of the control circuit can be maintained or even improved while improving the integration of the second capacitor 113.

[0096] In some embodiments, reference Figure 1 As shown, the first semiconductor structure 101 includes an array area 1011 and a peripheral area 1012 ; wherein the first capacitor 112 is located in the array area 1011 , and the second capacitor 113 is located in the peripheral area 1012 ; the connection layer 115 is located in the array area 1011 and the peripheral area 1012 , and the first interconnection portion 117 is located in the peripheral area 1012 .

[0097] exist Figure 1 The first capacitor 112 and the second capacitor 113 may be arranged along the x direction, without Figure 1 The first capacitor 112 and the second capacitor 113 shown in the figure can be arranged along the y direction perpendicular to the x direction, that is, the first capacitor 112 is arranged in an array, and the second capacitor 113 is arranged in an array. The structures of the first capacitor 112 and the second capacitor 113 can be the same, and the bottoms of the first capacitor 112 and the second capacitor 113 can be located at the same level of the first semiconductor structure 101, such as Figure 1 The bottoms of the first capacitor 112 and the second capacitor 113 are located above the top surface of the connection layer 115, and the top surface of the connection layer 115 is a side surface of the connection layer 115 in the positive z direction. The tops of the first capacitor 112 and the second capacitor 113 can also be at the same level of the first semiconductor structure 101.

[0098] The constituent materials of the connection layer 115 may include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide. The connection layer 115 extends from the array area 1011 to the peripheral area 1012, covering the transistor 111. The size of the connection layer 115 in the x direction is not specifically limited. The connection portion 116 is located in the array area 1011, passes through the connection layer 115, and can couple the first active area of ​​the transistor 111 and the second electrode 1123 of the first capacitor 112. One connection portion 116 is coupled to one first capacitor 112. The first interconnection portion 117 is located in the peripheral area 1012, passes through the connection layer 115, and can couple the second electrodes 1123 of multiple second capacitors 113. One first interconnection portion 117 can couple multiple second capacitors 113 in series to increase the voltage load of the capacitor. Figure 1 In the z direction, the top surface of the connecting portion 116 may be flush with the top surface of the connecting layer 115, and the bottom surface of the connecting portion 116 may be flush with the bottom surface of the connecting layer 115; the top surface of the first interconnecting portion 117 may be flush with the top surface of the connecting layer 115, and the bottom surface of the first interconnecting portion 117 may be flush with the bottom surface of the connecting layer 115.

[0099] The first contact structure 1141 can lead out the electrical signal of the second capacitor 113 by coupling with the first interconnection portion 117 , and can be coupled with other devices by hybrid bonding.

[0100] In some embodiments, the constituent materials of the connection portion 116 include, but are not limited to, conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, aluminum, or doped polysilicon. The constituent materials of the first interconnection portion 117 and the first contact structure 1141 may include, but are not limited to, conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, or aluminum. Compared with setting heavily doped polysilicon or other heavily doped semiconductor materials in the peripheral area 1012 to couple the second capacitor 113, for example, heavily doped polysilicon can be formed at the location of the connection layer 115; the embodiment of the present disclosure may set a metal first interconnection portion 117, the first interconnection portion 117 is located in the peripheral area 1012 and penetrates the connection layer 115 of the peripheral area 1012, and is electrically isolated from the connection portion 116 of the array area 1011 through the connection layer 115. The metal first interconnection portion 117 provides better electrical connection performance while also providing better physical support for the second capacitor 113, thereby improving structural stability.

[0101] In some embodiments, when the connection portion 116 is a metal material, a transition layer may be provided between the connection portion 116 and the connection layer 115, the transition layer may at least surround the sidewall and bottom of the connection portion 116, and the transition layer may include metal silicide to increase the adhesion between the connection portion 116 and the connection layer 115, increase the adhesion between the connection portion 116 and the first active region of the transistor 111, and reduce the contact resistance between the connection portion 116 and the first active region of the transistor 111. When the first interconnection portion 117 is a metal material, a transition layer may be provided between the first interconnection portion 117 and the connection layer 115, the transition layer may at least surround the sidewall of the first interconnection portion 117, and increase the adhesion between the first interconnection portion 117 and the connection layer 115. Exemplarily, the connection portion 116 and the first interconnection portion 117 may include tungsten, and the transition layer may include tungsten silicide or titanium silicide.

[0102] In some embodiments, transistor 111 may include transistor 111 of various physical forms, Figure 1 The vertical transistor 111 shown is an example. Figure 1 As shown, the transistor 111 includes:

[0103] The semiconductor column 1111 extends along a first direction (z direction) perpendicular to the connection layer 115; the first active region and the second active region of the transistor 111 are respectively located at two opposite ends of the semiconductor column 1111 in the first direction;

[0104] A gate dielectric layer 1113 and a gate electrode 1112 ; wherein the gate electrode 1112 and the gate dielectric layer 1113 at least cover one side of the semiconductor column 1111 , and the gate dielectric layer 1113 is located between the semiconductor column 1111 and the gate electrode 1112 .

[0105] The transistor 111 includes a semiconductor column 1111 extending along the z direction. The semiconductor column 1111 has a first active region and a second active region of the same doping type at both ends in the z direction. One of the first active region and the second active region is a source, and the other is a drain. The doping type of the semiconductor column 1111 region between the first active region and the second active region is opposite to that of the first active region, and serves as a channel of the transistor 111. For example, the first active region and the second active region are n-type doped, and the channel is p-type doped; or, the first active region and the second active region are p-type doped, and the channel is n-type doped. A gate dielectric layer 1113 and a gate 1112 are provided on the side of the semiconductor column 1111. The gate dielectric layer 1113 is located between the gate 1112 and the semiconductor column 1111, and the gate 1112 and the gate dielectric layer 1113 at least cover a portion of the channel.

[0106] In some embodiments, the gate 1112 may be located on one side of the semiconductor column 1111, and one gate 1112 controls one transistor 111. Multiple gates 1112 may also be arranged on the four sides of the semiconductor column 1111, such as two gates 1112 arranged opposite to each other in the x direction with respect to the semiconductor column 1111, and the two gates 1112 control one transistor 111. If one gate 1112 fails, the other gate 1112 can still control the transistor 111, thereby improving stability. In some other implementations, the gate 1112 may be a surrounding gate structure, that is, the gate 1112 surrounds the four sides of the semiconductor column 1111, and the semiconductor column 1111 passes through the gate 1112, thereby improving the control ability of the gate 1112 over the channel. The embodiment of the present disclosure does not limit the arrangement and number of transistors 111. The gate 1112 can extend along the y direction as a word line, or extend along a direction with a certain angle with the y direction. A word line can connect multiple transistors 111 in series in its extension direction. The extension direction of the bit line 119 intersects with the word line extension direction and connects multiple transistors 111 in series in its extension direction. The transistor 111 at the intersection of the word line and the bit line 119 can be selected. The bit line 119 of the embodiment of the present disclosure can extend along the x direction.

[0107] Exemplarily, the constituent materials of the semiconductor pillar 1111 may include: single-element semiconductor materials (such as silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials or other semiconductor materials known in the art. The constituent materials of the gate dielectric layer 1113 may include: insulating materials such as silicon oxide, silicon oxynitride, silicon nitride or aluminum oxide. The constituent materials of the gate 1112 may include: conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium or nickel.

[0108] In some embodiments, reference Figure 1 As shown, the gate dielectric layer 1113 may include a multilayer structure, for example, silicon oxide and aluminum oxide, and the aluminum oxide may be located between the gate 1112 and the silicon oxide, and the aluminum oxide is a kind of high dielectric material. Under the premise of achieving the same insulation performance, the film thickness required for the high dielectric material is thinner than the film thickness of the silicon oxide, which is conducive to improving the integration of the semiconductor pillar 1111 and the gate 1112.

[0109] In some embodiments, an insulating filling layer 1114 is provided between adjacent transistors 111, and the filling layer 1114 is used to support the transistors 111 and form electrical isolation. The filling layer 1114 has an air gap to reduce the dielectric constant of the filling layer 1114, reduce the parasitic capacitance between adjacent transistors 111, and improve the stability of the device. The constituent materials of the filling layer 1114 may include: silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane or polysilazane. In some other embodiments, in Figure 1In the embodiment, the filling layer 1114 between two adjacent semiconductor pillars 1111 may include a conductive material (e.g., copper, aluminum, etc.) with an air gap, and the conductive material is in contact with the side of the semiconductor pillar 1111 where the gate 1112 is not set, thereby utilizing the lower dielectric constant of the metal material to reduce the parasitic capacitance between the semiconductor pillars 1111; because the transistor 111 is turned on individually, the conductive material will not leak the electrons of the turned-on transistor 111 to the unturned transistor 111, thereby causing the unselected first capacitor 112 to malfunction. When the conductive material in this implementation is a metal material, it can also provide better mechanical support. The filling layer 1114 portion on the side of the semiconductor pillar 1111 where the gate 1112 is set is an insulating material to electrically isolate the gate 1112, thereby enabling each gate 1112 to individually control the transistor 111.

[0110] In some embodiments, the transistor 111 may include a planar transistor 111, the first active region, the channel and the second active region of the transistor 111 extend on the xoy plane, and the first active region and the first capacitor 112 may be coupled via a conductive plug or wire extending along the z direction.

[0111] In some embodiments, in the z direction, the second capacitor 113 is located on a side of the first interconnection portion 117 away from the transistor 111 , and the second capacitor 113 has the same structure as the first capacitor 112 .

[0112] In some embodiments, along a direction parallel to the connection layer 115, the first capacitor 112 includes:

[0113] A first electrode 1121 , and a first dielectric layer 1122 and a second electrode 1123 surrounding the first electrode 1121 ; the first dielectric layer 1122 is located between the first electrode 1121 and the second electrode 1123 .

[0114] The first capacitor 112 can be arranged in an array area 1011 on the connection layer 115 in an array manner, and the second capacitor 113 can be arranged in an array manner in the peripheral area 1012 on the connection layer 115. The first capacitor 112 and the second capacitor 113 can extend along the z direction. The single capacitor structure of the first capacitor 112 and the second capacitor 113 of the embodiment of the present disclosure can be the same. Take the first capacitor 112 as an example to explain, and the structure of the second capacitor 113 is the same as the first capacitor 112. The positive projection shape of the first capacitor 112 in the z direction may include: circular, elliptical, rectangular or other irregular shapes, which is not limited in the embodiment of the present disclosure.

[0115] In some embodiments, Figure 2 1 shows a cross-sectional view of the first capacitor 112 at the xoz plane, and also shows a cross-sectional view of the first capacitor 112 at the xoy plane. Figure 2As shown, along the radial direction (x direction) of the first capacitor 112, the first capacitor 112 includes: a first electrode 1121, a first dielectric layer 1122 surrounding the first electrode 1121, and a second electrode 1123; wherein the first dielectric layer 1122 is located between the first electrode 1121 and the second electrode 1123. The first electrode 1121 is a columnar structure, and the first dielectric layer 1122 and the second electrode 1123 are film layer structures surrounding the first electrode 1121.

[0116] In some other embodiments, referring to Figure 3 As shown, along the radial direction of the first capacitor 112, the first capacitor 112 may further include a core 1124, and the first electrode 1121, the first dielectric layer 1122 and the second electrode 1123 are arranged around the core 1124. The core 1124 is a columnar structure, and the first electrode 1121, the first dielectric layer 1122 and the second electrode 1123 are all film structures.

[0117] Exemplarily, the constituent materials of the first electrode 1121 and the second electrode 1123 may include, but are not limited to, conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium or nickel. The constituent materials of the first dielectric layer 1122 and the core 1124 may include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide.

[0118] Compared to a flat plate capacitor structure in which the electrodes are flat plate structures, the first capacitor 112 in this embodiment can have a larger area of ​​the first electrode 1121 and the second electrode 1123 when occupying the same device area, so as to obtain a larger electrode facing area (the area where the first electrode 1121 overlaps with the second electrode 1123), thereby maintaining a higher capacitance and a higher withstand voltage, and reducing the risk of the capacitor being broken down by high voltage. Therefore, under the premise of the same capacitance, compared to a flat plate capacitor, the capacitor of this embodiment can occupy a smaller device area, which is conducive to improving the integration of the capacitor. The structure of the second capacitor 113 is the same as that of the first capacitor 112, and the second capacitor 113 may include Figure 2 and Figure 3 Compared with conventional flat capacitors, the second capacitor 113 adopts the capacitor structure of the first capacitor 112, which is conducive to improving the integration of the capacitor. In addition, the second capacitor 113 can be manufactured simultaneously with the first capacitor 112 using the same manufacturing process, which is conducive to manufacturing process integration and reducing manufacturing costs.

[0119] In some embodiments, the second electrode 1123 of the first capacitor 112 is coupled to the connection portion 116; the second electrode 1123 of the second capacitor 113 is coupled to the first interconnection portion 117. The second electrode 1123 of the first capacitor 112 is coupled to the first active region of the transistor 111 through the connection portion 116, the second electrode 1123 of the second capacitor 113 is coupled to the first interconnection portion 117, the first interconnection portion 117 is coupled to the first contact structure 1141, and the first contact structure 1141 leads the signal of the second capacitor 113 to couple with other device structures to configure the control circuit.

[0120] In some embodiments, one first capacitor 112 is coupled to one connection portion 116, and one connection portion 116 is coupled to one transistor 111. In some embodiments, multiple second capacitors 113 may be coupled to a common first interconnection portion 117, so as to connect multiple second capacitors 113 in series to configure control circuits with different functions. Exemplarily, the shape of the connection portion 116 may include a rectangle or a circle, and the shape of the first interconnection portion 117 may include a bar or a circle.

[0121] In some embodiments, reference Figure 1 As shown, the semiconductor device further includes:

[0122] The second semiconductor structure 102 is located at one side of the first semiconductor structure 101 , and the second semiconductor structure 102 is bonded to the first semiconductor structure 101 ; wherein the second semiconductor structure 102 is coupled to the second capacitor 113 .

[0123] The second semiconductor structure 102 includes various devices including a CMOS structure, and the second capacitor 113 is coupled to the second semiconductor structure 102 to form a control circuit to control the read, write or erase operation of the storage array. In the z direction, the first semiconductor structure 101 and the second semiconductor structure 102 can be stacked and interconnected by electrical signals by bonding technology, and the bonding technology can include hybrid bonding.

[0124] In some embodiments, reference Figure 1 As shown, the first semiconductor structure 101 further includes:

[0125] The bit line 119 is located at a side of the transistor 111 close to the second semiconductor structure 102 ; the bit line 119 is coupled to the second active region of the transistor 111 .

[0126] The bit line 119 may extend along the x-direction or in a direction having a certain angle with the x-direction. The orthographic projections of the bit line 119 and the gate 1112 in the z-direction intersect, and the intersection includes being vertical or having other angles. The embodiment of the present disclosure does not limit the intersection angle. The bit line 119 couples the second active regions of the plurality of transistors 111 to achieve coupling and control of the transistor 111 array. Specifically, a bit line 119 may be turned on, and when a turn-on voltage is applied to a gate 1112, a transistor 111 in the transistor 111 array may be turned on, and a first capacitor 112 may be selected, and further operations such as reading and writing of the storage unit may be achieved.

[0127] In some embodiments, reference Figure 1 As shown, the second semiconductor structure 102 includes a first CMOS structure 121 and a second CMOS structure 122, and the first contact structure 1141 is located between the second CMOS structure 122 and the first interconnection portion 117; wherein the second active region of the transistor 111 is coupled to the first CMOS structure 121; one end of the first contact structure 1141 is coupled to the first interconnection portion 117, and the other end is coupled to the second CMOS structure 122.

[0128] In some embodiments, the bit line 119 is coupled to the first CMOS structure 121 . In the z direction, one end of the bit line 119 is coupled to the second active region of the transistor 111 , and the other end of the bit line 119 is coupled to the first CMOS structure 121 via a conductive plug 1142 .

[0129] Specifically, refer to Figure 1 As shown, before bonding is completed, the planes to be bonded of the first semiconductor structure 101 and the second semiconductor structure 102 respectively have bonding contacts 132, and the bonding contacts 132 lead the electrical signals of the semiconductor structures to the bonding planes. The bonding contacts 132 may include conductive structures such as pads, conductive wires, and conductive plugs. Figure 1 The pads shown in the figure are only examples. The planes to be bonded of the first semiconductor structure 101 and the second semiconductor structure 102 are bonded, and the interface where the planes to be bonded of the two semiconductor structures are in contact is the bonding interface 131. The bonding contacts 132 of the first semiconductor structure 101 and the second semiconductor structure 102 are in contact at the bonding interface 131, so as to realize the electrical signal interconnection between the first semiconductor structure 101 and the second semiconductor structure 102.

[0130] The constituent materials of the bonding contact 132 may include: conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium or nickel. The constituent materials of the bonding interface 131 may include: silicon oxide, silicon nitride or metal silicide. In the embodiment of the present disclosure, the bonding interface 131 includes metal silicide, which can increase the bonding force with the bonding contact 132, reduce the stress of the bonding interface 131, reduce the bending deformation of the bonding interface 131, and improve the manufacturing yield.

[0131] For example, a conductive plug 1142 may be provided to lead out the electrical signal of the bit line 119 and couple it to the pad on the surface to be bonded of the first semiconductor structure 101. A conductive plug 1143 may be provided to lead out the electrical signal of the first CMOS structure 121 and the second CMOS structure 122 in the second semiconductor structure 102, respectively, and couple it to the pad on the surface to be bonded of the second semiconductor structure 102. In the z direction, the pad of the first semiconductor structure 101 and the pad on the second semiconductor structure 102 serve as bonding contacts 132, and after bonding, the electrical signals of the two semiconductor structures are interconnected. The first contact structure 1141 is coupled to the first interconnection portion 117, and the electrical signal of the second electrode 1123 of the second capacitor 113 is led out, and bonding is performed to the second semiconductor structure 102 through the pad, so as to achieve coupling of the second capacitor 113 with the second CMOS structure 122.

[0132] In some embodiments, reference Figure 1 As shown, the first semiconductor structure 101 further includes:

[0133] The first interconnection layer 118 is located at one end of the first capacitor 112 and the second capacitor 113 away from the transistor 111; the first interconnection layer 118 is coupled to the electrode of the first capacitor 112 away from the transistor 111, and the first interconnection layer 118 is coupled to the electrode of the second capacitor 113 away from the first interconnection portion 117. Figure 2 and Figure 3 As shown, the second electrode 1123 of the first capacitor 112 is coupled to the connecting portion 116, and the electrode of the first capacitor 112 away from the transistor 111 is the first electrode 1121; the second electrode 1123 of the second capacitor 113 is coupled to the first interconnecting portion 117, and the electrode of the second capacitor 113 away from the transistor 111 is the first electrode 1121.

[0134] The constituent material of the first interconnect layer 118 may include conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium or nickel.

[0135] The first interconnection layer 118 may include a plurality of interconnection structures, which may realize unified power supply to the first electrode 1121 of the first capacitor 112 and the first electrode 1121 of the second capacitor 113, or separate power supply to the first capacitor 112 and the second capacitor 113. The electrical signal of the first interconnection layer 118 may be led out to the bonding interface 131 through the conductive plug 1144 to realize electrical signal interconnection with the second semiconductor structure 102.

[0136] In some embodiments, the first active region of the transistor 111 can provide a high voltage to the second electrode 1123 of the first capacitor 112, and the first interconnect layer 118 can provide a low voltage, such as a ground voltage, to the first electrode 1121 of the first capacitor 112. The first interconnect portion 117 provides a high voltage to the second electrode 1123 of the second capacitor 113, and the first interconnect layer 118 provides a low voltage, such as a ground voltage, to the first electrode 1121 of the second capacitor 113. Therefore, the first interconnect layer 118 can simultaneously couple the first electrode 1121 of the first capacitor 112 and the second capacitor 113, and provide the same voltage, such as a ground voltage, to the first capacitor 112 and the second capacitor 113.

[0137] The first interconnect layer 118 may include a plurality of electrically isolated interconnect structures to provide separate power supplies to the first capacitor 112 and the second capacitor 113. Figure 1 As shown, the first interconnect layer 118 includes:

[0138] The first interconnection sublayer 1181 and the second interconnection sublayer 1182 are electrically isolated from each other; the first interconnection sublayer 1181 is coupled to the electrode of the first capacitor 112 away from the transistor 111, and the second interconnection sublayer 1182 is coupled to the electrode of the second capacitor 113 away from the first interconnection portion 117. The first interconnection sublayer 1181 and the second interconnection sublayer 1182 can be located at the same film layer height of the first semiconductor structure 101.

[0139] In some embodiments, reference Figure 1 As shown, an interconnection structure 133 is also provided on the side of the first semiconductor structure 101 away from the bonding interface 131. The interconnection structure 133 can be coupled to the first interconnection layer 118 to supply power to the first interconnection layer 118. In some other embodiments, the interconnection structure can also be coupled to other interconnection layers through a conductive plug for power supply. The interconnection structure 133 can serve as an IO interface of the semiconductor device 100 for external power supply or external communication of the semiconductor device 100. The interconnection structure 133 may include a pad.

[0140] In the embodiment of the present disclosure, the first semiconductor structure 101 is bonded to the second semiconductor structure 102, and a transistor 111, a first capacitor 112, and a second capacitor 113 are arranged in the first semiconductor structure 101. The first capacitor 112 and the transistor 111 are coupled to form a capacitor for storing data, and the second capacitor 113 is configured as a capacitor in a CMOS control circuit. Compared with the solution of arranging the second capacitor 113 in the second semiconductor structure 102 to form a control circuit, the size and arrangement of the second capacitor 113 in the embodiment of the present disclosure will not limit the improvement of the integration of other control circuit devices in the second semiconductor structure 102, and the integration of the control circuit can be maintained or even improved while improving the integration of the second capacitor 113.

[0141] According to some aspects of the embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, forming a first semiconductor structure, referring to Figure 4 As shown, the method for forming the first semiconductor structure includes:

[0142] forming a transistor;

[0143] forming a connection layer on the transistor;

[0144] forming a connecting portion and a first interconnecting portion penetrating the connecting layer;

[0145] A first capacitor is formed on the connecting portion, and a second capacitor is formed on the first interconnecting portion; wherein one end of the connecting portion is coupled to the first capacitor, and the other end is coupled to the first active area of ​​the transistor;

[0146] A first contact structure is formed on a side of the first interconnection portion away from the second capacitor; wherein one end of the first interconnection portion is coupled to the second capacitor, and the other end is coupled to the first contact structure.

[0147] In the embodiment of the present disclosure, the connecting portion and the first interconnecting portion can be manufactured at the same time, and the first capacitor and the second capacitor can be manufactured at the same time, so as to reduce the manufacturing cost.

[0148] Specifically, refer to Figure 5a As shown, the first substrate 110 is divided into an array area 1011 and a peripheral area 1012, and a transistor 111 is formed on the array area 1011. The method of forming the transistor 111 may include:

[0149] Reference Figure 5a As shown, a semiconductor column 1111 is formed, and the semiconductor column 1111 extends along a first direction (z direction) perpendicular to the connection layer 115; both ends of the semiconductor column 1111 in the first direction are doped to form a first active region and a second active region;

[0150] Reference Figure 5bAs shown, a gate dielectric layer 1113 is formed on the side of the semiconductor column 1111 ; a gate 1112 is formed on the gate dielectric layer 1113 ; wherein the gate dielectric layer 1113 is located between the semiconductor column 1111 and the gate 1112 .

[0151] Reference Figure 5a As shown, a semiconductor layer may be formed on a first substrate 110, and the semiconductor layer may be etched to form semiconductor pillars 1111, and the semiconductor pillars 1111 may extend along the z direction. In some embodiments, the semiconductor layer may be etched once to form semiconductor pillars 1111. In other embodiments, the semiconductor layer may be etched once to form a first groove penetrating the semiconductor layer, and then the remaining semiconductor layer may be etched a second time to form a second groove penetrating the semiconductor layer, and the second groove intersects the first groove vertically to divide the semiconductor layer into semiconductor pillars 1111. The etching process may include: dry etching, wet etching, or any combination thereof.

[0152] The two ends of the semiconductor column 1111 are doped with n-type, a first active region is formed at one end of the semiconductor column 1111 away from the first substrate 110, and a second active region is formed at one end of the semiconductor column 1111 close to the first substrate 110. The region of the semiconductor column 1111 between the first active region and the second active region is doped with p-type to form a channel of the transistor 111. Alternatively, the two ends of the semiconductor column 1111 are doped with p-type, and the region of the semiconductor column 1111 between the source and the drain is doped with n-type. The positions of the first active region and the second active region can be interchanged.

[0153] Exemplarily, the doping process may include: ion implantation, diffusion or any combination thereof. The n-type doping element includes a pentavalent element, such as nitrogen, phosphorus or arsenic. The p-type doping element includes a trivalent element, such as boron, gallium or indium.

[0154] Reference Figure 5b As shown, a gate dielectric layer 1113 is formed on one side surface of the semiconductor column 1111 , the gate dielectric layer 1113 covers one side surface of the semiconductor column 1111 , and the gate 1112 covers the gate dielectric layer 1113 .

[0155] After the gate 1112 is fabricated, the gaps between the semiconductor pillars 1111 are covered with insulating material to form a filling layer 1114 to support and electrically isolate the semiconductor pillars 1111 and the gate 1112. An air gap is formed in the filling layer 1114 to reduce the dielectric constant of the filling layer 1114, reduce the parasitic capacitance between adjacent transistors 111, and improve device stability.

[0156] The process of forming the gate dielectric layer 1113, the gate 1112 and the filling layer 1114 may include: low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, atomic layer deposition or plasma enhanced chemical vapor deposition. The process of forming the filling layer 1114 may also include a spin coating insulating dielectric process.

[0157] exist Figure 5b In the embodiment, the filling layer 1114 between two adjacent semiconductor pillars 1111 may include a conductive material (e.g., copper, aluminum, etc.) with an air gap, and the conductive material is in contact with the side of the semiconductor pillar 1111 where the gate 1112 is not set, thereby reducing the parasitic capacitance between the semiconductor pillars 1111 by utilizing the lower dielectric constant of the metal material; because the transistor 111 is turned on individually, the conductive material will not leak the electrons of the turned-on transistor 111 to the unturned transistor 111, thereby causing the unselected first capacitor 112 to malfunction. When the conductive material in this implementation is a metal material, it can also provide better mechanical support. The filling layer 1114 portion on the side of the semiconductor pillar 1111 where the gate 1112 is set is an insulating material, which is used to electrically isolate the gate 1112, thereby realizing the individual control of each gate 1112 over the transistor 111.

[0158] Reference Figure 5c As shown, a connection layer 115 is formed on a side of the transistor 111 away from the first substrate 110 , and the connection layer 115 covers the transistor 111 . The connection layer 115 extends from the array region 1011 to the peripheral region 1012 .

[0159] In some embodiments, the connection layer 115 includes an array region 1011 and a peripheral region 1012; and a method of forming the connection portion 116 and the first interconnection portion 117 includes:

[0160] Reference Figure 6a As shown, a mask layer 141 is formed on the connection layer 115, and a first pattern 1411 is formed in a region of the mask layer 141 located in the array region 1011; a photoresist layer 142 is formed on the mask layer 141 including the first pattern 1411, and the photoresist layer 142 covers the first pattern 1411 and a region of the mask layer 141 located in the peripheral region 1012;

[0161] Reference Figure 6b As shown, a second pattern 1412 is formed in the region of the photoresist layer 142 located in the array region 1011 , and the second pattern 1412 reveals the first pattern 1411 ; and a second pattern 1412 is formed in the region of the photoresist layer 142 located in the peripheral region 1012 ;

[0162] Reference Figure 6c As shown, Figure 6bThe photoresist layer 142 including the second pattern 1412 and the mask layer 141 including the first pattern 1411 are used as etching masks, and the connection layer 115 is etched to form a first opening 1151 and a second opening 1152 penetrating the connection layer 115; wherein the first opening 1151 is located in the array region 1011 and exposes the first active region of the transistor 111, and the second opening 1152 is located in the peripheral region 1012; Figure 6d Shows Figure 6c A top view of the array of first openings 1151 and second openings 1152 in the xoy plane;

[0163] Reference Figure 6e As shown, a connecting portion 116 is formed in the first opening 1151 , and a first interconnecting portion 117 is formed in the second opening 1152 ; Figure 6f Shows Figure 6e A top view of the array of connection portions 116 and the first interconnection portions 117 in the xoy plane.

[0164] exist Figure 6a In the embodiment, the mask layer 141 may include a multi-layer film structure, including but not limited to an anti-reflection layer 1413, an amorphous carbon layer 1412 and other film layers, to improve the photolithography accuracy and the blocking performance of the mask to the etchant. The first pattern 1411 is located on the top of the mask layer 141 to form an etching mask for the connection portion 116, and the first pattern 1411 may be an opening array. Figure 6b After the photoresist is photolithographically developed, a second pattern 1412 is formed in both the array region 1011 and the peripheral region 1012. The second pattern 1412 may be a larger opening than the opening size in the first pattern 1411. The second pattern 1412 in the array region 1011 exposes the first pattern 1411. Figure 6b After the structure in the embodiment is etched, the first pattern 1411 is transferred to the connection layer 115 to form a first opening 1151 (first opening 1151 array); Figure 6b After the second pattern 1412 in the middle peripheral region 1012 is etched, the second pattern 1412 is transferred into the connection layer 115 to form a second opening 1152 . Figure 6c The structure in FIG. 1 is a structure after the first opening 1151 and the second opening 1152 are formed and the photoresist layer 142 and the mask layer 141 are removed. The removal process may include ashing, cleaning, chemical mechanical polishing and other processes.

[0165] Before forming the connecting portion 116 and the first interconnecting portion 117, polycrystalline silicon, single crystal silicon or amorphous silicon may be deposited on the side walls and the bottom of the first opening 1151 and the second opening 1152 of the connecting layer 115, and then a metal material may be deposited to form the connecting portion 116 and the first interconnecting portion 117. After heat treatment, the metal material and silicon form a transition layer of metal silicide to increase the adhesion with the connecting layer 115 and reduce the contact resistance.

[0166] In this embodiment, one connection portion 116 is coupled to one transistor 111 , and a plurality of second capacitors 113 may be coupled to share a first interconnection portion 117 , so as to connect a plurality of capacitors in series to increase the capacitor load voltage.

[0167] In some embodiments, on a plane perpendicular to the z direction, the first capacitors 112 may be arranged in a 4 by 5 array, wherein four first capacitors 112 are arranged in a row along the x direction, and five rows of four first capacitors 112 are arranged along the y direction or in a direction having a certain angle with the y direction. The array of the second capacitors 113 may also be the same as that of the first capacitors 112. Figure 6f As shown, corresponding to the 4×5 array of the first capacitors 112 , the connection portions 116 are also arranged in a 4×5 array, with 4 connection portions 116 arranged in a row along the x direction and 5 rows arranged along the y direction, for a total of 20 connection portions 116 . Figure 6f The arrangement of the transistors 111 coupled to the connecting portion 116 is also a 4×5 array. One connecting portion 116 is coupled to the first active region of one transistor 111. One first capacitor 112, one connecting portion 116 and one transistor 111 can constitute a DRAM storage unit.

[0168] The second capacitor 113 array may also be arranged in the same manner as the 4×5 first capacitor 112 array. Figure 6f In the embodiment, a first interconnection 117 may be provided to couple 20 second capacitors 113, and the first interconnection 117 may be a circular or rectangular conductive structure. Alternatively, five first interconnections 117 extending along the x direction may be provided, each of which is coupled to four second capacitors 113, as described below. Figure 7e shown.

[0169] In some embodiments, reference Figure 7a As shown, the mask layer 141 further includes a third pattern 1413 located in the peripheral area 1012, the third pattern 1413 is a strip array, and the photoresist layer 142 covers the mask layer including the first pattern 1411 and the third pattern 1413. Figure 7b As shown, the photoresist layer 142 is photolithographically developed to form a second pattern 1412 in both the array region 1011 and the peripheral region 1012, and the second pattern 1412 reveals the first pattern 1411 and the third pattern 1413. Figure 7b The structure in the embodiment is etched to transfer the first pattern 1411 to the connection layer 115 to form Figure 7c The first opening 1151 in the connecting layer 115 is used to transfer the third pattern 1413 to the connecting layer 115 to form Figure 7c The second opening 1152 in FIG. Figure 7d7c shows a top view of the first opening 1151 array and the second opening 1152 array in the xoy plane. The second opening 1152 can be a strip extending along the x direction. The five second openings 1152 are arranged in the y direction, thereby reducing the etching amount when forming the second openings 1152, reducing the etching load effect, and facilitating the control of the process size of the first opening 1151, thereby improving the manufacturing yield. Figure 7e As shown, the formed 4×5 connection portion 116 array is coupled to the first capacitor 112 array one by one, and one first interconnection portion 117 can be coupled to four second capacitors 113 arranged along the x direction. In other embodiments, there are more second capacitors 113, and one interconnection portion can be coupled to more second capacitors 113.

[0170] In some embodiments, a method of forming the first capacitor 112 and the second capacitor 113 includes:

[0171] Reference Figure 8a As shown, a second dielectric layer 151 is formed on the connecting portion 116 and the first interconnecting portion 117, and a first capacitor hole and a second capacitor hole penetrating the second dielectric layer 151 are formed; wherein the first capacitor hole exposes the connecting portion 116, and the second capacitor hole exposes the first interconnecting portion 117;

[0172] A first capacitor 112 is formed in the first capacitor hole, and a second capacitor 113 is formed in the second capacitor hole; wherein, along a direction parallel to the connection layer 115 (which may be an x ​​direction), the first capacitor 112 includes a first electrode 1121, and a first dielectric layer 1122 and a second electrode 1123 surrounding the first electrode 1121; the first dielectric layer 1122 is located between the first electrode 1121 and the second electrode 1123, and the second electrode 1123 is coupled to the connection portion 116;

[0173] The structure of the second capacitor 113 is the same as that of the first capacitor 112. The second electrode 1123 of the second capacitor 113 is coupled to the first interconnection portion 117. Taking the first capacitor 112 as an example, Figure 2 and Figure 3 The structure of the first capacitor 112 is shown in FIG.

[0174] In some embodiments, the structure of the first capacitor 112 (or the second capacitor 113) is as follows: Figure 2 As shown, the first electrode 1121 is a columnar structure, and the first electrode 1121 and the second electrode 1123 are film structures surrounding the first electrode 1121. In some other embodiments, the first capacitor 112 may further include a core 1124, and the first electrode 1121, the dielectric layer, and the second electrode 1123 are arranged around the core 1124. The core 1124 is a columnar structure, and the first electrode 1121, the dielectric layer, and the second electrode 1123 are all film structures.

[0175] In some embodiments, the method of forming the first semiconductor structure 101 further includes:

[0176] Reference Figure 8a As shown, a first interconnection layer 118 is formed on a side of the first capacitor 112 and the second capacitor 113 away from the connection layer 115; wherein the first interconnection layer 118 is coupled to an electrode of the second capacitor 113 away from the first interconnection portion 117, and the first interconnection layer 118 is coupled to an electrode of the first capacitor 112 away from the transistor 111.

[0177] The first interconnection layer 118 may include a plurality of interconnection structures, which may realize unified power supply to the first electrode 1121 of the first capacitor 112 and the first electrode 1121 of the second capacitor 113, or separate power supply to the first capacitor 112 and the second capacitor 113. The electrical signal of the first interconnection layer 118 may be led out to the bonding interface 131 through the first contact structure 1141 to realize electrical signal interconnection with the second semiconductor structure 102. The first contact structure 1141 may be a conductive structure such as a conductive plug.

[0178] In some embodiments, the method of forming the first contact structure 1141 may include:

[0179] Reference Figure 8b As shown, a surface of the first semiconductor structure 101 that is away from the first substrate 110 is bonded to the carrier 190;

[0180] Reference Figure 8c As shown, after the first semiconductor structure 101 is bonded to the carrier 190 , the first substrate 110 is removed.

[0181] The bonding process between the first semiconductor structure 101 and the carrier 190 may include direct bonding by thermal compression, or bonding may be performed by bonding adhesive. The carrier 190 provides support for the first semiconductor structure 101 and facilitates the removal of the first substrate 110. The constituent material of the carrier 190 may be the same as that of the first substrate 110.

[0182] Exemplarily, the process of removing the first substrate 110 includes grinding, dry etching, wet etching or chemical mechanical polishing.

[0183] In some embodiments, reference Figure 8d As shown, the method for forming the first semiconductor structure 101 further includes:

[0184] A bit line 119 is formed at one end of the transistor 111 away from the first capacitor 112 , and the bit line 119 is coupled to the second active region of the transistor 111 .

[0185] In some embodiments, reference Figure 8dAs shown, a conductive plug 1142 is formed to couple with the bit line 119, a first contact structure 1141 is formed to couple with the first interconnection portion 117, and a conductive plug 1144 is formed to couple with the first interconnection layer 118. A metal silicide bonding interface 131 is formed on the surface of the first semiconductor structure 101 away from the carrier 190, and a bonding contact 132 is formed that penetrates the bonding interface 131 and is respectively coupled with the first contact structure 1141, the conductive plug 1142, and the conductive plug 1144.

[0186] In some embodiments, the manufacturing method further comprises:

[0187] Reference Figure 8e As shown, a second semiconductor structure 102 is formed;

[0188] Reference Figure 8f As shown, the second semiconductor structure 102 is bonded to the first semiconductor structure 101 ; wherein the second semiconductor structure 102 is coupled to the second capacitor 113 .

[0189] Reference Figure 8e As shown, a first CMOS structure 121 and a second CMOS structure 122 are formed on and / or in the second substrate 120. Two conductive plugs 1143 are formed in the second semiconductor structure 102, which are connected to the first CMOS structure 121 and the second CMOS structure 122 respectively. Bonding contacts 132 are formed on the conductive plugs 1143, and the bonding contacts 132 are coupled to the conductive plugs 1143.

[0190] Reference Figure 8f As shown, a side surface of the second semiconductor structure 102 away from the second substrate 120 is bonded to a side surface of the first semiconductor structure 101 away from the carrier 190, and the two semiconductor structures are in contact at the bonding interface 131 through the bonding contact 132 to achieve electrical signal interconnection of the two semiconductor structures. Among them, the first CMOS structure 121 is coupled to the bit line 119 through the conductive plug 1142, and the second CMOS structure 122 is coupled to the first interconnection portion 117. After the second semiconductor structure 102 is bonded to the first semiconductor structure 101, the first contact structure 1141 is located between the second CMOS structure 122 and the first interconnection portion 117.

[0191] Reference Figure 8g As shown, the manufacturing method also includes:

[0192] After the second semiconductor structure 102 and the first semiconductor structure 101 are bonded, the carrier 190 is removed.

[0193] After the second semiconductor structure 102 and the first semiconductor structure 101 are bonded by thermocompression, they can be debonded by heating to remove the carrier 190. After the second semiconductor structure 102 and the first semiconductor structure 101 are bonded by bonding adhesive, the bonding adhesive can be debonded by heating or ultraviolet irradiation to remove the carrier 190. The above process of debonding and separating the first semiconductor structure 101 and the carrier 190 can be reused after cleaning after separation to continue bonding with other semiconductor structures. In some other embodiments, the carrier 190 can also be removed by grinding, etching, and chemical mechanical grinding.

[0194] In some embodiments, Figure 8g An interconnection structure 133 is formed on the first semiconductor structure 101 to obtain Figure 1 The semiconductor device shown. The interconnection structure 133 may be coupled to the first interconnection layer 118 to supply power to the first interconnection layer 118. In some other embodiments, the interconnection structure 133 may also be coupled to other interconnection layers through a conductive plug for power supply. The interconnection structure 133 may serve as an IO interface of the semiconductor device for external power supply or external communication of the semiconductor device. The interconnection structure 133 may include a pad.

[0195] According to some aspects of the embodiments of the present disclosure, referring to Fig. 9 As shown, a memory system 900 is provided, including:

[0196] One or more semiconductor devices 100; and

[0197] The memory controller 904 is coupled to the semiconductor device and controls the semiconductor device 100 .

[0198] The semiconductor device or structure involved in the embodiments of the present disclosure is to be used in subsequent processes to form at least a portion of a final device structure. Here, the final device may include a memory device 902 .

[0199] In some specific examples, the semiconductor device or structure can be used as a computer memory in a memory system or as a buffer in a memory system.

[0200] In some specific examples, semiconductor devices or structures can be used as auxiliary devices in solid-state drives, which can improve the reading and writing of solid-state drives. Currently, high-end solid-state drive products mostly choose to embed DRAM to improve product performance and random reading and writing speeds. For example, when writing files, especially small files, small files are processed by DRAM and then stored in Flash, making the solid-state drive storage more efficient and faster.

[0201] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0202] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0203] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: a first semiconductor structure; The first semiconductor structure comprises: A transistor, a first capacitor and a second capacitor; wherein the first capacitor is located at one end of the transistor; A connecting layer, located between the first capacitor and the transistor; A connecting portion, located between the first capacitor and the transistor; the connecting portion passes through the connecting layer; one end of the connecting portion is coupled to the first capacitor, and the other end is coupled to the first active region of the transistor; A first interconnection portion, penetrating the connection layer; The first contact structure and the second capacitor are respectively located on opposite sides of the connection layer; wherein one end of the first interconnection portion is coupled to the second capacitor, and the other end is coupled to the first contact structure.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: The second semiconductor structure is located at one side of the first semiconductor structure, and the second semiconductor structure is bonded to the first semiconductor structure; wherein the second semiconductor structure is coupled to the second capacitor.

3. The semiconductor device according to claim 2, characterized in that The second semiconductor structure includes a first CMOS structure and a second CMOS structure, and the first contact structure is located between the second CMOS structure and the first interconnection portion; wherein the second active region of the transistor is coupled to the first CMOS structure; one end of the first contact structure is coupled to the first interconnection portion, and the other end is coupled to the second CMOS structure.

4. The semiconductor device according to claim 1, wherein: The first semiconductor structure includes an array region and a peripheral region; wherein the first capacitor is located in the array region, and the second capacitor is located in the peripheral region; the connection layer is located in the array region and the peripheral region, and the first interconnection portion is located in the peripheral region.

5. The semiconductor device according to claim 1, wherein: The second capacitor is located at a side of the first interconnection portion away from the transistor, and the second capacitor has the same structure as the first capacitor.

6. The semiconductor device according to claim 5, characterized in that Along a direction parallel to the connection layer, the first capacitor includes: A first electrode, and a first dielectric layer surrounding the first electrode and a second electrode; the first dielectric layer is located between the first electrode and the second electrode.

7. The semiconductor device according to claim 6, characterized in that The second electrode of the first capacitor is coupled to the connecting portion; the second electrode of the second capacitor is coupled to the first interconnecting portion.

8. The semiconductor device according to claim 1, wherein: The first semiconductor structure further comprises: The first interconnection layer is located at one end of the first capacitor and the second capacitor away from the transistor; the first interconnection layer is coupled to the electrode of the first capacitor away from the transistor, and the first interconnection layer is coupled to the electrode of the second capacitor away from the first interconnection portion.

9. The semiconductor device according to claim 8, characterized in that The first interconnection layer comprises: A first interconnection sublayer and a second interconnection sublayer are electrically isolated from each other; the first interconnection sublayer is coupled to an electrode of the first capacitor away from the transistor, and the second interconnection sublayer is coupled to an electrode of the second capacitor away from the first interconnection portion.

10. The semiconductor device according to claim 3, wherein: The first semiconductor structure further comprises: The bit line is located at a side of the transistor close to the second semiconductor structure; the bit line is coupled to the second active region of the transistor.

11. The semiconductor device according to claim 10, characterized in that The bit line is coupled to the first CMOS structure.

12. The semiconductor device according to claim 1, wherein: The transistor comprises: A semiconductor column extending along a first direction perpendicular to the connection layer; a first active region and a second active region of the transistor are respectively located at two opposite ends of the semiconductor column in the first direction; A gate dielectric layer and a gate; wherein the gate and the gate dielectric layer at least cover one side of the semiconductor column, and the gate dielectric layer is located between the semiconductor column and the gate.

13. A method for manufacturing a semiconductor device, characterized in that: A first semiconductor structure is formed, wherein the method of forming the first semiconductor structure comprises: forming a transistor; forming a connection layer on the transistor; forming a connecting portion and a first interconnecting portion penetrating the connecting layer; A first capacitor is formed on the connecting portion, and a second capacitor is formed on the first interconnecting portion; wherein one end of the connecting portion is coupled to the first capacitor, and the other end is coupled to the first active area of ​​the transistor; A first contact structure is formed on a side of the first interconnection portion away from the second capacitor; wherein one end of the first interconnection portion is coupled to the second capacitor, and the other end is coupled to the first contact structure.

14. The manufacturing method according to claim 13, characterized in that: The production method further comprises: forming a second semiconductor structure; The second semiconductor structure is bonded to the first semiconductor structure; wherein the second semiconductor structure is coupled to the second capacitor.

15. The manufacturing method according to claim 13, characterized in that: The connection layer includes an array region and a peripheral region; and the method for forming the connection portion and the first interconnection portion includes: forming a mask layer on the connection layer, and forming a first pattern in a region of the mask layer located in the array region; forming a photoresist layer on the mask layer including the first pattern, wherein the photoresist layer covers the first pattern and a region of the mask layer located in the peripheral area; Forming a second pattern in a region of the photoresist layer located in the array region, wherein the second pattern reveals the first pattern; forming the second pattern in a region of the photoresist layer located in the peripheral region; Using the photoresist layer including the second pattern and the mask layer including the first pattern as etching masks, etching the connection layer to form a first opening and a second opening penetrating the connection layer; wherein the first opening is located in the array region and exposes the first active region of the transistor, and the second opening is located in the peripheral region; The connecting portion is formed in the first opening, and the first interconnection portion is formed in the second opening.

16. The manufacturing method according to claim 13, characterized in that: The method of forming the first capacitor and the second capacitor includes: Forming a second dielectric layer on the connecting portion and the first interconnecting portion, forming a first capacitor hole and a second capacitor hole penetrating the second dielectric layer; wherein the first capacitor hole exposes the connecting portion, and the second capacitor hole exposes the first interconnecting portion; The first capacitor is formed in the first capacitor hole, and the second capacitor is formed in the second capacitor hole; wherein, along a direction parallel to the connecting layer, the first capacitor includes a first electrode, and a first dielectric layer and a second electrode surrounding the first electrode; the first dielectric layer is located between the first electrode and the second electrode, and the second electrode is coupled to the connecting portion; The structure of the second capacitor is the same as that of the first capacitor, and the second electrode of the second capacitor is coupled to the first interconnection portion.

17. The manufacturing method according to claim 13, characterized in that: The method of forming the first semiconductor structure further includes: A first interconnection layer is formed on a side of the first capacitor and the second capacitor away from the connection layer; wherein the first interconnection layer is coupled to an electrode of the second capacitor away from the first interconnection portion, and the first interconnection layer is coupled to an electrode of the first capacitor away from the transistor.

18. The manufacturing method according to claim 14, characterized in that: The method of forming the first semiconductor structure further includes: A bit line is formed at one end of the transistor away from the first capacitor, and the bit line is coupled to the second active region of the transistor.

19. The method according to claim 13, characterized in that: The method of forming the transistor includes: forming a semiconductor column extending in a first direction perpendicular to the connection layer; doping two ends of the semiconductor column in the first direction to form a first active region and a second active region; forming a gate dielectric layer on the side of the semiconductor column; forming a gate on the gate dielectric layer; Wherein, the gate dielectric layer is located between the semiconductor column and the gate.

20. A memory system, characterized in that: include: One or more semiconductor devices according to any one of claims 1 to 12; as well as A memory controller is coupled to the semiconductor device and controls the semiconductor device.

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