Semiconductor structure, method of forming a semiconductor structure, and memory

Abstract

The present disclosure provides a semiconductor structure, a method for forming a semiconductor structure and a memory, and relates to the technical field of semiconductor. The semiconductor structure comprises: a substrate, a first trench is formed in the substrate; a dielectric layer, covering the inner surface of the first trench, the dielectric layer at least comprises a sidewall dielectric layer located on the sidewall of the first trench and a bottom dielectric layer located on the bottom of the first trench; the sidewall dielectric layer and the bottom dielectric layer located in the same first trench form a word line trench, the word line trench comprises an edge region close to the sidewall dielectric layer and an intermediate region between the edge regions; a word line structure located in the word line trench, the word line structure comprises an edge word line layer located in the edge region and an intermediate word line layer located in the intermediate region; the upper surface of the intermediate word line layer is not lower than the upper surface of the edge word line layer. The present disclosure can improve the GIDL problem of semiconductor devices.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor structure, a forming method of the semiconductor structure and a memory. BACKGROUND

[0002] A field effect transistor (MOS) is a commonly used element in semiconductor devices such as DRAM (Dynamic Random Access Memory), and by controlling the gate potential of the field effect transistor, the conduction or cutoff between the source and the drain can be controlled.

[0003] GIDL (Gate-Induced Drain Leakage) is an important defect in field effect transistors. With the development of semiconductor manufacturing technology, the size of field effect transistors is continuously reduced, and the GIDL problem becomes more and more serious, resulting in increased power consumption and decreased performance of semiconductor devices. SUMMARY

[0004] The present disclosure provides a semiconductor structure, a forming method of the semiconductor structure and a memory to at least partially improve the GIDL problem of semiconductor devices.

[0005] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate, a first trench being formed in the substrate; a dielectric layer covering an inner surface of the first trench, the dielectric layer at least comprising a sidewall dielectric layer located on a sidewall of the first trench and a bottom dielectric layer located at a bottom of the first trench; the sidewall dielectric layer and the bottom dielectric layer located in the same first trench form a word line trench, the word line trench comprising an edge region close to the sidewall dielectric layer and an intermediate region between the edge regions; a word line structure located in the word line trench, the word line structure comprising an edge word line layer located in the edge region and an intermediate word line layer located in the intermediate region; an upper surface of the intermediate word line layer is not lower than an upper surface of the edge word line layer.

[0006] Optionally, the upper surface of the intermediate word line layer is arc-shaped or triangular, and the lowest point of the arc-shaped or triangular is not lower than the upper surface of the edge word line layer.

[0007] Optionally, the edge word line layer is a work function layer, and the intermediate word line layer is a metal layer.

[0008] According to a second aspect of the present disclosure, a forming method of a semiconductor structure is provided, comprising:

[0009] A substrate is provided, in which a first trench is formed, and an inner surface of the first trench is covered with a dielectric layer; the dielectric layer at least includes a sidewall dielectric layer on a sidewall of the first trench and a bottom dielectric layer on a bottom of the first trench; the sidewall dielectric layer and the bottom dielectric layer in the same first trench enclose a word line trench, which includes an edge region close to the sidewall dielectric layer and an intermediate region between the edge regions; one or more word line materials are filled in the word line trench; a first mask layer is formed above the substrate, a missing part of the first mask layer is directly above the edge region; the word line material directly above the edge region is etched using the first mask layer; the first mask layer is removed, and the remaining word line material is etched back, and the etched-back word line material forms a word line structure; the word line structure includes an edge word line layer at the edge region and an intermediate word line layer at the intermediate region, and an upper surface of the intermediate word line layer is not lower than an upper surface of the edge word line layer.

[0010] Optionally, the forming of the first mask layer above the substrate includes: coating a photoresist material above the substrate, and removing the photoresist material directly above the edge region by exposure and development, and the remaining photoresist material forms the first mask layer.

[0011] Optionally, the forming of the first mask layer above the substrate includes: forming a second mask layer above the substrate; a second trench is formed in the second mask layer, and the second trench is directly above the word line trench; a sidewall spacer layer is formed covering the sidewall of the second trench, and the sidewall spacer layer is directly above the edge region; a third mask layer is formed, and at least fills the second trench; a third trench is formed in the second mask layer and the third mask layer by removing the sidewall spacer layer, and the third trench is directly above the edge region and has a bottom on an upper surface of the word line material; the remaining second mask layer and the third mask layer form a composite layer as the first mask layer; or the second mask layer and the third mask layer are etched back to remove the third mask layer, and the remaining second mask layer is used as the first mask layer.

[0012] Optionally, the forming of the third trench in the second mask layer and the third mask layer by removing the sidewall spacer layer includes: removing the sidewall spacer layer, and etching the second mask layer along a space formed by removing the sidewall spacer layer with the word line material as an etching stop layer, to form the third trench.

[0013] Optionally, the second mask layer is a stacked structure, and a lowermost layer of the second mask layer is a first hard mask layer; and the etching back the second mask layer and the third mask layer to remove the third mask layer comprises: etching back the second mask layer and the third mask layer with the first hard mask layer as an etching stop layer, to remove the third mask layer and remove a portion of the first mask layer above the first hard mask layer.

[0014] Optionally, the second mask layer is a stacked structure, and an uppermost layer of the second mask layer is a second hard mask layer; and the forming the third mask layer to fill at least the second trench comprises: depositing or coating a third mask material to fill at least the second trench; and etching back the third mask material or the third mask material and a spacer layer on the second mask layer with the second hard mask layer as an etching stop layer, to expose the sidewall spacer layer, and the remaining third mask material forms the third mask layer.

[0015] Optionally, when the one or more word line materials are filled in the word line trench, the word line material also covers above the substrate; and the etching the word line material above the edge position with the first mask layer comprises: etching the word line material directly above the edge region with the first mask layer, and controlling the etching end point to be not lower than the top of the word line trench.

[0016] Optionally, the word line material comprises a metal material and a work function material; and the filling the one or more word line materials in the word line trench comprises: filling the work function material in the edge region of the word line trench, and filling the metal material in the middle region of the word line trench.

[0017] According to a third aspect of the present disclosure, a memory is provided, comprising the semiconductor structure of the first aspect.

[0018] The technical solution of the present disclosure has the following beneficial effects:

[0019] The word line structure is divided into an edge word line layer and a middle word line layer, and the upper surface of the middle word line layer is controlled to be not lower than the upper surface of the edge word line layer, so that the upper surface of the word line structure forms a flat structure or an Ω-shaped structure, etc., the contact surface with the dielectric layer of the sidewall is reduced, which is beneficial to improve the GIDL problem, reduce the leakage current and power consumption, and improve the performance of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A schematic diagram of a semiconductor structure is shown.

[0021] Figure 2 A top view of a semiconductor structure in the present exemplary embodiment is shown.

[0022] Figure 3 A cross-sectional view of a semiconductor structure in the present example embodiment is shown.

[0023] Figure 4 A cross-sectional view of another semiconductor structure in the present example embodiment is shown.

[0024] Figure 5A A cross-sectional view of a semiconductor structure with a planar top surface in the present example embodiment is shown.

[0025] Figure 5B A cross-sectional view of a semiconductor structure with an Ω-shaped top surface in the present example embodiment is shown.

[0026] Figure 6A A cross-sectional view of another semiconductor structure with a planar top surface in the present example embodiment is shown.

[0027] Figure 6B A cross-sectional view of another semiconductor structure with an Ω-shaped top surface in the present example embodiment is shown.

[0028] Figure 7 A flow chart of a method of forming a semiconductor structure in the present example embodiment is shown.

[0029] Figure 8 A schematic diagram of filling a word line material in the present example embodiment is shown.

[0030] Figure 9A A schematic diagram of filling a work function material and a metal material in the present example embodiment is shown.

[0031] Figure 9B A schematic diagram of filling another work function material and a metal material in the present example embodiment is shown.

[0032] Figure 10 A schematic diagram of coating a photoresist material over a substrate in the present example embodiment is shown.

[0033] Figure 11 A schematic diagram of forming a first mask layer from the photoresist material in the present example embodiment is shown.

[0034] Figure 12 A flow chart of forming a first mask layer in the present example embodiment is shown.

[0035] Figure 13 A schematic diagram of forming a second mask layer in the present example embodiment is shown.

[0036] Figure 14A diagram illustrating coating a photoresist material over the second mask layer in the present example embodiment is shown.

[0037] Figure 15 A diagram illustrating forming a photoresist layer in the present example embodiment is shown.

[0038] Figure 16 A diagram illustrating forming a second trench in the present example embodiment is shown.

[0039] Figure 17 A diagram illustrating forming a spacer layer in the present example embodiment is shown.

[0040] Figure 18 A diagram illustrating filling a third mask material in the present example embodiment is shown.

[0041] Figure 19 A diagram illustrating forming a third mask layer in the present example embodiment is shown.

[0042] Figure 20 A diagram illustrating one way of forming a third trench in the present example embodiment is shown.

[0043] Figure 21 A diagram illustrating another way of forming a third trench in the present example embodiment is shown.

[0044] Figure 22 A diagram illustrating forming a first mask layer from a first hard mask layer in the present example embodiment is shown.

[0045] Figure 23A A diagram illustrating a first way of etching a word line material directly above an edge region in the present example embodiment is shown.

[0046] Figure 23B A diagram illustrating a second way of etching a word line material directly above an edge region in the present example embodiment is shown.

[0047] Figure 23C A diagram illustrating a third way of etching a word line material directly above an edge region in the present example embodiment is shown.

[0048] Figure 23D A diagram illustrating a fourth way of etching a word line material directly above an edge region in the present example embodiment is shown.

[0049] Figure 24A A diagram illustrating one way of removing a first mask layer in the present example embodiment is shown.

[0050] Figure 24B A diagram illustrating another way of removing a first mask layer in the present example embodiment is shown.

[0051] The reference signs are as follows:

[0052] 101: substrate; 102: first trench; 103: dielectric layer; 1031: sidewall dielectric layer; 1032: bottom dielectric layer; 1033: dielectric layer on substrate; 104: word line trench; 1041: edge region; 1042: middle region; 105: isolation structure; 106: first mask layer; 107: word line structure; 1071: edge word line layer; 1072: middle word line layer; 108: second mask layer; 1081: first hard mask layer; 1082: second hard mask layer; 1083: middle mask layer; 109: photoresist layer; 110: second trench; 111: spacer layer; 1111: sidewall spacer layer; 1112: bottom spacer layer; 1113: spacer layer on second mask layer; 112: third mask layer; 113: third trench; 114: active region; 115: word line material; 1151: metal material; 1152: work function material; 116: photoresist material; 117: third mask material. DETAILED DESCRIPTION

[0053] Example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.

[0054] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate certain non-limiting embodiments of the present disclosure. The technical solutions of the present disclosure can be implemented in various ways, and should not be construed as being limited to the examples set forth herein. The features, structures, or characteristics described in the present disclosure can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. One skilled in the relevant art, however, will recognize that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, etc. instead.

[0055] Figure 1 A schematic diagram of a semiconductor structure is shown. Trenches are formed in a substrate, and gate oxide layers and word line structures are formed in the trenches. During etching of the word line structures, ion bombardment has directionality, and the word line material located at the positions on both sides of the deeper part of the trench has less etchant to contact due to the shielding of the sidewall of the trench, so that the etching rate at the positions on both sides is lower than that at the middle position, resulting in that the middle position of the word line structure is lower than the positions on both sides after etching, forming a V-shaped (or concave) upper surface topography. The contact area between the word line structure and the gate oxide layer of the sidewall increases, which will cause the GIDL to increase.

[0056] In view of the above problems, the present disclosure provides a semiconductor structure, which can be a partial structure of a semiconductor device such as a DRAM, an SRAM (Static Random Access Memory), a Flash, etc. The semiconductor structure can include: a substrate 101 in which a first trench 102 is formed; a dielectric layer 103 covering an inner surface of the first trench 102, the dielectric layer 103 including at least a sidewall dielectric layer 1031 on a sidewall of the first trench 102 and a bottom dielectric layer 1032 at a bottom of the first trench 102; the sidewall dielectric layer 1031 and the bottom dielectric layer 1032 in the same first trench 102 enclosing a word line trench 104, the word line trench 104 including an edge region 1041 close to the sidewall dielectric layer 1031 and an intermediate region 1042 between the edge regions 1041; a word line structure 107 in the word line trench 104, the word line structure 107 including an edge word line layer 1071 at the edge region 1041 and an intermediate word line layer 1072 at the intermediate region 1042; and an upper surface of the intermediate word line layer 1072 being not lower than an upper surface of the edge word line layer 1071.

[0057] Figure 2 A top view of the semiconductor structure is shown. In the substrate 101, an active region 114 and an isolation structure 105 are formed. The substrate 101 is usually located at the bottom of a wafer and provides a base for forming a semiconductor device. The substrate 101 can be formed of silicon (such as single crystal silicon, polycrystalline silicon, amorphous silicon), germanium, silicon-germanium compound, group III-V compound (such as gallium arsenide), etc. The substrate 101 can have an epitaxial layer or be a silicon-on-insulator substrate (i.e., an SOI substrate). The present disclosure does not limit the specific structure in the substrate 101. The isolation structure 105 is used to separate different active regions, and the isolation structure 105 can be a shallow trench isolation (STI) structure.

[0058] In the present exemplary embodiment, four directions can be defined. The first direction can be the direction in which a word line (WL) extends, and the second direction can be the direction in which a bit line (BL) extends, the first direction being perpendicular to the second direction. The third direction can be the direction in which an active region extends, and the fourth direction can be the direction perpendicular to the third direction.

[0059] Reference Figure 2 As shown, the word line structure 107 can pass through the active region 114 along the first direction, and each active region 114 can intersect with two word lines. Of course, the present disclosure does not limit this, and each active region 114 can also intersect with only one word line or three or more word lines. Figure 2The first trench 102, dielectric layer 103, and word line trench 104 are not shown. The word line trench 104 is located in the same position as the word line structure 107. Figure 3 As shown, the dielectric layer 103 can be located on both sides and the bottom of the entire word line structure 107, or it can be located only on both sides and the bottom of the intersection of the word line structure 107 and the active region 114. The first trench 102 is located in the same position as the "dielectric layer 103 + word line trench 104".

[0060] Figure 3 , Figure 4 , Figure 5A and Figure 5B This is a cross-sectional view of the semiconductor structure along a third direction. Among them, Figure 3 and Figure 4 The semiconductor structure without word line structure 107 is shown to illustrate the first trench 102 and word line trench 104. Figure 5A and Figure 5B A semiconductor structure with word line structure 107 formed is shown, namely the semiconductor structure in this exemplary embodiment.

[0061] The first trench 102 is a space in the substrate 101 used to accommodate the dielectric layer 103 and the word line structure 107. The size of the first trench 102 can be determined by the size of the semiconductor device product, the critical dimensions that can be achieved in the process, etc. For example, the depth of the first trench 102 can be 50-300 nm, and the width along the second direction can be 20-100 nm.

[0062] The dielectric layer 103 covers the inner surface of the first trench 102, constituting the dielectric between the gate and the channel region in the field-effect transistor. This disclosure does not limit the size of the dielectric layer 103; for example, the thickness of the dielectric layer 103 can be 1–20 nm. The dielectric layer 103 can be made of an insulating material such as silicon oxide (SiO2). In one embodiment, the dielectric layer 103 can be made of a high-k dielectric material, such as hafnium oxide (HfO2), hafnium silicate nitride (HfSiO4), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium zirconate (HfZrO4), yttrium oxide (Y2O3), strontium titanate (SrTiO3), or lead zirconate titanate (PbZr). x Ti 1-x Materials such as O3 are used. Employing high dielectric constant materials can effectively reduce leakage current and power consumption.

[0063] refer to Figure 3 As shown, the dielectric layer 103 may include a sidewall dielectric layer 1031 located on the sidewall of the first trench 102 and a bottom dielectric layer 1032 located at the bottom of the first trench 102. In one embodiment, referring to... Figure 4As shown, the dielectric layer 103 can also cover over the substrate 101, and this part of the dielectric layer 103 can be referred to as the over-substrate dielectric layer 1033.

[0064] The word line trench 104 is the space in the first trench 102 except for the dielectric layer 103, and is the space for accommodating the word line structure 107, and can be regarded as a subspace of the first trench 102. Referring to FIG. 1B, Figure 3 or Figure 4 As shown, the word line trench 104 can be composed of two parts, the edge region 1041 and the middle region 1042. The edge region 1041 is close to the sidewall dielectric layer 1031 on both sides of the word line trench 104, and the middle region 1042 is located between the edge regions 1041. The size of the edge region 1041 and the middle region 1042, or the division ratio of the two, can be determined according to the depth of the word line trench 104 or the first trench 102, the height of the word line structure 107, etc. Generally, the greater the depth of the word line trench 104 or the first trench 102, the smaller the height of the word line structure 107, and the greater the proportion of the edge region 1041 in the word line trench 104. For example, the width of the edge region 1041 on both sides of the word line trench 104 can be 25%, and the width of the edge region 1041 on both sides adds up to 50%. Alternatively, the width of a single edge region 1041 can be no more than 20 nm.

[0065] The word line structure 107 is located in the word line trench 104, and can partially fill the word line trench 104, so that a certain space is left in the upper part of the word line trench 104, which can be used for subsequent formation of a barrier layer to isolate the word line structure 107 from the structure above. Since in this exemplary embodiment, the word line trench 104 or the first trench 102 is located in the substrate 101, the word line structure 107 is a Buried Word Line (BWL) structure.

[0066] The word line structure 107 can include an edge word line layer 1071 and a middle word line layer 1072. The edge word line layer 1071 is located in the edge region 1041, and the middle word line layer 1072 is located in the middle region 1042. The upper surface of the middle word line layer 1072 is not lower than the upper surface of the edge word line layer 1071. It can be understood that the lowest point of the upper surface of the middle word line layer 1072 is not lower than the highest point of the upper surface of the edge word line layer 1071, or the average height of the upper surface of the middle word line layer 1072 is not lower than the average height of the upper surface of the edge word line layer 1071.

[0067] In an embodiment, referring to FIG. 1B, Figure 5A As shown, the upper surface of the middle word line layer 1072 and the upper surface of the edge word line layer 1071 are both flat and flush, which means that the height of the upper surface of the middle word line layer 1072 is equal to the height of the upper surface of the edge word line layer 1071, and the upper surface of the entire word line structure 107 is a flat structure.

[0068] In another embodiment, the upper surface of the middle word line layer 1072 is arc-shaped or triangular, and the lowest point of the arc-shaped or triangular is not lower than the upper surface of the edge word line layer 1071. As shown in FIG. 7B, the upper surface of the edge word line layer 1071 is planar, the upper surface of the middle word line layer 1072 is upwardly convex arc-shaped, and the upper surface of the whole word line structure 107 is Ω-shaped (or convex) structure. Figure 5B

[0069] Based on the semiconductor structure in the present exemplary embodiment, the word line structure 107 is divided into the edge word line layer 1071 and the middle word line layer 1072, and the upper surface of the middle word line layer 1072 is controlled to be not lower than the upper surface of the edge word line layer 1071, so that the upper surface of the word line structure 107 forms a planar structure or an Ω-shaped structure, etc., the contact area with the dielectric layer 103 of the sidewall is reduced, which is beneficial to improve the GIDL problem, reduce the leakage current and power consumption, and improve the performance of the semiconductor device.

[0070] In one embodiment, the materials of the edge word line layer 1071 and the middle word line layer 1072 can be the same, such as both using polycrystalline silicon or titanium nitride, etc. In another embodiment, as shown in FIG. 7C, the materials of the edge word line layer 1071 and the middle word line layer 1072 can also be different, such as the edge word line layer 1071 can be a work function layer using work function material such as titanium nitride (TiN), and the middle word line layer 1072 can be a metal layer using metal material such as tungsten (W) or alloy material of multiple metals. The existence of the work function layer can improve the adhesion between the metal layer and the dielectric layer 103, and further reduce the leakage current. Figure 6A Figure 6B

[0071] The present disclosure also provides a forming method of a semiconductor structure. As shown in FIG. 8, the forming method of the semiconductor structure can include the following steps S710-S750: Figure 7

[0072] S710, providing a substrate, a first trench is formed in the substrate, and the inner surface of the first trench is covered with a dielectric layer; the dielectric layer at least includes a sidewall dielectric layer on the sidewall of the first trench and a bottom dielectric layer on the bottom of the first trench; the sidewall dielectric layer and the bottom dielectric layer in the same first trench enclose a word line trench, and the word line trench includes an edge region close to the sidewall dielectric layer and a middle region between the edge regions.

[0073] ​​​​Wherein, before forming the first trench 102, the substrate 101 has formed therein an active region 114 and an isolation structure 105. The source region, the drain region, and the channel region can be formed in the active region 114 by ion implantation or other processes. Alternatively, the source region, the drain region, and the channel region can be formed in the active region 114 after forming the word line structure 107. The first trench 102 can be formed along the first direction, passing through the active region 114. The first trench 102 can be formed by photolithography and etching processes or the like.

[0074] After forming the first trench 102, a dielectric layer 103 can be formed on the inner surface of the first trench 102 by chemical vapor deposition (CVD), atomic layer deposition (ALD) or other processes, including a sidewall dielectric layer 1031 and a bottom dielectric layer 1032. The dielectric layer 103 can also cover the upper surface of the substrate 101, forming a substrate upper dielectric layer 1033.

[0075] The structure of the first trench 102, the dielectric layer 103, and the word line trench 104 can refer to the above Figure 3 or Figure 4 .

[0076] Step S720, filling one or more word line materials in the word line trench.

[0077] Wherein, the word line material 115 can fill the word line trench 104 entirely or partially. If the word line material 115 partially fills the word line trench 104, the height of the word line material 115 needs to exceed the height of the required word line structure 107. In an embodiment, as shown in Figure 8 , the word line material 115 can cover the substrate 101 in addition to filling the word line trench 104 entirely, which leaves sufficient margin for the subsequent two times of etching the word line material 115, making the etching process easier to control. The upper surface of the word line material 115 can be planarized by chemical mechanical polishing or other processes to facilitate the subsequent formation of the first mask layer 106.

[0078] It should be understood that if only one word line material 115 is filled in the word line trench 104, the subsequently formed word line structure 107 is a single material film layer, and if multiple word line materials 115 are filled in the word line trench 104, the subsequently formed word line structure 107 is a composite material film layer.

[0079] In an embodiment, the word line material 115 can include a metal material 1151 and a work function material 1152. The above step of filling one or more word line materials 115 in the word line trench 104 can include the following steps:

[0080] The work function material 1152 is filled in the edge region 1041 of the word line trench 104, and the metal material 1151 is filled in the middle region 1042 of the word line trench 104.

[0081] refer to Figure 4 and Figure 9A As shown, a work function material 1152 can first be formed using processes such as chemical vapor deposition and diffusion to completely fill the word line trenches 104 and cover the top of the substrate 101. The surface of the work function material 1152 can then be planarized using processes such as chemical mechanical polishing (CMP). Next, a mask with an inverted pattern of the central region 1042 is used to etch the work function material 1152, leaving the central region 1042 exposed. Subsequently, a metal material 1151 can be formed using processes such as physical vapor deposition (PVD) to completely fill the central region 1042 and also cover the top of the work function material 1152. Finally, the surface of the metal material 1151 can be planarized using processes such as chemical mechanical polishing, or even completely removed from the top of the work function material 1152 to simplify subsequent etching processes.

[0082] refer to Figure 9B As shown, a metal material 1151 can first be formed using processes such as physical vapor deposition to completely fill the word line trenches 104 and cover the substrate 101. The surface of the metal material 1151 can then be planarized using processes such as chemical mechanical polishing. Next, a mask with an inverted pattern of edge regions 1041 is used to etch the metal material 1151, leaving the edge regions 1041 exposed. Following this, a work function material 1152 can be formed using processes such as chemical vapor deposition, diffusion, and atomic layer deposition to completely fill the edge regions 1041 and also cover the metal material 1151. Finally, the surface of the work function material 1152 can be planarized using processes such as chemical mechanical polishing, or even completely polished away from the metal material 1151 to simplify subsequent etching processes.

[0083] Step S730: A first mask layer is formed above the substrate, wherein the missing portion in the first mask layer is located directly above the edge region, such as... Figure 4 and Figure 11 As shown.

[0084] The first mask layer 106 can be made of photoresist material 116 or inorganic material, and its missing part is located directly above the edge region 1041, that is, the first mask layer 106 has the inverse pattern of the edge region 1041.

[0085] The first mask layer 106 is formed above the substrate 101. It should be understood that if there are no other films on the substrate 101, the first mask layer 106 is located on the substrate 101 and in contact with the substrate 101. If there are other films on the substrate 101 (such as the dielectric layer 1033 on the substrate, the word line material 115 located above the substrate 101, etc.), the first mask layer 106 may be located on the other films and not in contact with the substrate 101.

[0086] In one embodiment, forming the first mask layer 106 above the substrate 101 may include the following steps:

[0087] A photoresist material 116 is coated on top of the substrate 101, and the photoresist material 116 directly above the edge region 1041 is removed by exposure and development. The remaining photoresist material 116 forms the first mask layer 106.

[0088] refer to Figure 10 As shown, a photoresist material 116 is coated, completely covering the top of the substrate 101, such as on the word line material 115 located above the substrate 101. (See reference.) Figure 11 As shown, a photomask with an edge region 1041 pattern can be used to remove the photoresist material 116 directly above the edge region 1041 through exposure and development. This results in the remaining photoresist material 116 having an inverse pattern of the edge region 1041, thereby forming the first mask layer 106. Considering the small width of the edge region 1041, EUV (Extreme Ultra-Violet) lithography can be used to expose and develop the photoresist material 116, which can precisely form a small-sized pattern in the photoresist material 116, allowing the missing portion in the first mask layer 106 to be precisely aligned with the edge region 1041.

[0089] In one implementation, reference Figure 12 As shown, forming a first mask layer 106 above the substrate 101 may include the following steps S1210 to S1260:

[0090] Step S1210: A second mask layer is formed on top of the substrate.

[0091] The second mask layer 108 can be made of inorganic mask material, such as a hard mask layer. The second mask layer 108 can be a single-layer structure or a multi-layer structure. In one embodiment, the second mask layer can be a stacked structure, where the bottom layer is the first hard mask layer 1081, or the top layer is the second hard mask layer 1082. (See reference) Figure 13As shown, the lowermost layer of the second mask layer 108 is a first hard mask layer 1081, the uppermost layer is a second hard mask layer 1082, and one or more intermediate mask layers 1083 are between the first hard mask layer 1081 and the second hard mask layer 1082. Exemplarily, the first hard mask layer 1081 and the second hard mask layer 1082 can both be silicon oxynitride (SiON) layers, and the intermediate mask layers 1083 can be spin-on hard mask (SOH) layers.

[0092] The second mask layer 108 is formed above the substrate 101. It should be understood that if there is no other film layer on the substrate 101, the second mask layer 108 is on the substrate 101 and in contact with the substrate 101. If there is another film layer (such as the substrate upper dielectric layer 1033, the word line material 115 above the substrate 101, etc.) on the substrate 101, the second mask layer 108 can be on the other film layer and not in contact with the substrate 101.

[0093] In an embodiment, the first hard mask layer 1081 can be formed by depositing silicon oxynitride through a chemical vapor deposition process, the intermediate mask layer 1083 can be formed by forming a spin-on hard mask layer through a spin coating process, and the second hard mask layer 1082 can be formed by depositing silicon oxynitride through a chemical vapor deposition process, thereby obtaining the complete second mask layer 108.

[0094] At step S1220, a second trench is formed in the second mask layer, and the second trench is directly above the word line trench.

[0095] The second trench 110 can be aligned with the word line trench 104 in the vertical direction (i.e., the direction perpendicular to the plane of the substrate 101). The second trench 110 can be formed by a photolithography and etching process. Exemplarily, referring to FIG. 11B, a photoresist layer 109 is formed on the second mask layer 108. The photoresist layer 109 can have a pattern that is the inverse of the pattern of the word line trench 104. The photoresist layer 109 can be formed by coating a photoresist material 116 on the second mask layer 108, and then removing the photoresist material 116 directly above the word line trench 104 by exposure and development using a mask having the pattern of the word line trench 104. Figure 14 As shown, a photoresist material 116 is coated on the second mask layer 108 (which can be the same as or different from the photoresist material 116 coated on the first mask layer 106 described above). Referring to FIG. 11B, the photoresist material 116 is coated on the second mask layer 108. Figure 15 As shown, a photoresist layer 109 is formed by removing the photoresist material 116 directly above the word line trench 104 by exposure and development using a mask having the pattern of the word line trench 104. Referring to FIG. 11B, the photoresist layer 109 has a pattern that is the inverse of the pattern of the word line trench 104. Figure 16 As shown, the second trench 110 is formed in the second mask layer 108 by etching the second mask layer 108 through the photoresist layer 109, so that the second trench 110 is directly above the word line trench 104.

[0096] The disclosure does not limit the depth of the second trench 110. In an embodiment, the first hard mask layer 1081 can be used as an etching stop layer, and the second trench 110 can be formed by etching the second mask layer 108 through the photoresist layer 109, so that the bottom of the second trench 110 is located on the upper surface of the first hard mask layer 1081.

[0097] Step S1230: A sidewall spacer layer is formed covering the sidewall of the second trench, the sidewall spacer layer being located directly above the edge region.

[0098] The sidewall spacer layer 1111 is used to define the pattern of the edge region 1041. The sidewall spacer layer 1111 is located directly above the edge region 1041, and the two are aligned vertically. Since the edge region 1041 is typically small in width, this means the sidewall spacer layer 1111 needs to have a small thickness. Therefore, atomic layer deposition (ALD) can be used to prepare the sidewall spacer layer 1111, resulting in an ultrathin layer, such as one with a thickness not exceeding 20 nm. Alternatively, if the thickness requirement for the sidewall spacer layer 1111 is not high, processes such as chemical vapor deposition (CVD) can also be used to prepare it.

[0099] In one implementation, reference Figure 17 As shown, during the formation of the sidewall spacer layer 1111, a film layer, referred to as the bottom spacer layer 1112, may also be formed at the bottom of the second trench 110. Alternatively, a film layer, referred to as the upper spacer layer 1113, may also be formed on the upper surface of the second mask layer 108. One or more of the sidewall spacer layer 1111, the bottom spacer layer 1112, and the upper spacer layer 1113 constitute the spacer layer 111.

[0100] Step S1240: Form a third mask layer, which at least fills the second trench.

[0101] The third mask layer 112 can fill the space outside the spacer layer 111 in the second trench 110. The third mask layer 112 can be made of inorganic mask material, such as a spin-coated hard mask layer. Of course, the third mask layer 112 can also be a multilayer structure formed by multiple mask materials.

[0102] In one embodiment, the second mask layer 108 is a stacked structure, wherein the uppermost layer is a second hard mask layer 1082. The formation of the third mask layer 112, which at least fills the second trench 110, may include the following steps:

[0103] Deposit or coat a third mask material 117 to at least fill the second trench 110;

[0104] Using the second hard mask layer 1082 as the etching stop layer, the third mask material 117 or the third mask material 117 and the spacer layer 111 located on the second mask layer 108 are etched back to expose the sidewall spacer layer 111, and the remaining third mask material 117 forms the third mask layer 112.

[0105] The third mask material 117 refers to the material of the third mask layer 112, which can be the same as or different from the material of the second mask layer 108. For example, the second mask layer 108 can include multiple mask materials, and the third mask material 117 can be one of them, such as the third mask material 117 being the same as the material of the intermediate mask layer 1083.

[0106] The third mask material 117 can be deposited by a chemical vapor deposition process or coated by a spin coating process. Referring to FIG. 11B, the third mask material 117 can fill the second trench 110 and cover the top of the second mask layer 108. If the second mask upper spacer layer 1113 exists on the second mask layer 108, the third mask material 117 covers the upper surface of the second mask upper spacer layer 1113. Figure 18

[0107] Referring to FIG. 11B, the third mask material 117 can fill the second trench 110 and cover the top of the second mask layer 108. If the second mask upper spacer layer 1113 exists on the second mask layer 108, the third mask material 117 covers the upper surface of the second mask upper spacer layer 1113. Figure 19 Referring to FIG. 11B, the third mask material 117 can fill the second trench 110 and cover the top of the second mask layer 108. If the second mask upper spacer layer 1113 exists on the second mask layer 108, the third mask material 117 covers the upper surface of the second mask upper spacer layer 1113.

[0108] Of course, after depositing or coating the third mask material 117, the third mask material 117 can be surface planarized by a chemical mechanical polishing process, and the third mask material 117 and the second mask upper spacer layer 1113 above the second mask layer 108 can be polished away, and the remaining third mask material 117 forms the third mask layer 112.

[0109] In step S1250, a third trench is formed in the second mask layer and the third mask layer by removing the sidewall spacer layer, the third trench being located directly above the edge region and having a bottom on the upper surface of the word line material.

[0110] The sidewall spacer layer 1111 can be removed by an etching process (including dry etching and wet etching). An etching material with high etching selectivity to the sidewall spacer layer 1111 compared to the second mask layer 108 and the third mask layer 112 can be selected, so that when the sidewall spacer layer 1111 is etched, the second mask layer 108 and the third mask layer 112 on both sides are less affected, which is beneficial to improve the position and size accuracy of the third trench 113.

[0111] ​In one embodiment, if the bottom of the sidewall spacer 1111 is located on the upper surface of the word line material 115, the space formed after removing the sidewall spacer 1111 has its bottom also located on the upper surface of the word line material 115, which can be used as the third trench 113.

[0112] In another embodiment, if the bottom of the sidewall spacer 1111 does not reach the upper surface of the word line material 115, such as when there is another film layer (e.g., the first hard mask layer 1081) between the sidewall spacer 1111 and the upper surface of the word line material 115, the above-mentioned forming the third trench in the second mask layer and the third mask layer by removing the sidewall spacer can include the following steps:

[0113] Removing the sidewall spacer 1111 and etching the second mask layer 108 along the space formed by removing the sidewall spacer 1111 with the word line material 115 as the etching stop layer to form the third trench 113.

[0114] That is, two-step etching can be performed, the first step being to etch the sidewall spacer 1111. After removing the sidewall spacer 1111, the second step is to further etch the second mask layer 108 downward along the space formed until the upper surface of the word line material 115 is reached. In this way, a trench is formed in the second mask layer 108 and the third mask layer 112, i.e., the third trench 113. Referring to Figure 20 In the two-step etching process, the second mask layer 108 and the third mask layer 112 on both sides can be unaffected. Alternatively, referring to Figure 21 In the second etching process, a portion of the second mask layer 108 or the third mask layer 112 on both sides can be etched away at the same time, such as when the first hard mask layer 1081 and the second hard mask layer 1082 are made of the same material, the second hard mask layer 1082 will also be etched away when etching the first hard mask layer 1081 along the space formed by removing the sidewall spacer 1111, and a portion of the third mask layer 112 or the intermediate mask layer 1083 can also be etched away.

[0115] In step S1260, the remaining composite layer formed by the second mask layer and the third mask layer is used as the first mask layer, or the second mask layer and the third mask layer are etched back to remove the third mask layer, and the remaining second mask layer is used as the first mask layer.

[0116] In one embodiment, after forming the third trench 113 with its bottom reaching the upper surface of the word line material 115, the composite layer formed by all the film layers above the word line material 115 can be used as the first mask layer 106, and the first mask layer 106 has an inverse pattern of the edge region 1041. For example, the composite layer can include the remaining second mask layer 108 and the third mask layer 112, referring to Figure 20As shown in FIG. 21, the bottom spacer layer 1112 can also be included. That is, Figure 20 In FIG. 21, the remaining second mask layer 108, the third mask layer 112, and the bottom spacer layer 1112 can collectively form the first mask layer 106.

[0117] In an embodiment, the composite layer above the word line material 115 can also be etched back to simplify the composite layer structure and facilitate subsequent etching of the word line material 115. For example, if the composite layer includes the remaining second mask layer 108 and the third mask layer 112, the second mask layer 108 and the third mask layer 112 are etched back. If the composite layer also includes the bottom spacer layer 1112, the bottom spacer layer 1112 is also etched back. The third mask layer 112 can be completely removed, or the third mask layer 112 and the bottom spacer layer 1112 can be completely removed, and the remaining second mask layer 108 can be used as the first mask layer 106.

[0118] In an embodiment, the second mask layer 108 is a stacked structure, in which the lowermost layer is the first hard mask layer 1081. The second mask layer 108 and the third mask layer 112 are etched back to remove the third mask layer 112, which can include the following steps:

[0119] The first hard mask layer 1081 is used as an etching stop layer, and the second mask layer 108 and the third mask layer 112 are etched back to remove the third mask layer 112 and remove the portion of the first mask layer 106 above the first hard mask layer 1081.

[0120] In etching back the second mask layer 108 and the third mask layer 112, if the bottom spacer layer 1112 is also present in the second mask layer 108, the bottom spacer layer 1112 can also be etched back. The first hard mask layer 1081 is used as an etching stop layer, and the film layer above the first hard mask layer 1081 can be completely removed. Referring to Figure 22 As shown in FIG. 21, after the third mask layer 112, the bottom spacer layer 1112, and the portion of the first mask layer 106 above the first hard mask layer 1081 are etched away, only the first hard mask layer 1081 remains in the second mask layer 108, which can be used as the first mask layer 106. In this way, the material of the first mask layer 106 is relatively simple, which facilitates the selection of a suitable etching material when etching the word line material 115.

[0121] In Figure 12In the method shown, the pattern of the edge region 1041 is determined by forming a sidewall spacer layer 1111, and a first mask layer 106 with the inverse pattern of the edge region 1041 is formed by etching and other processes. Instead of using photolithography to determine the pattern of the edge region 1041, the pattern of the second trench 110 can be determined using photolithography. Since the size of the second trench 110 is much larger than the size of the edge region 1041, the precision requirements of the photolithography process are greatly reduced, eliminating the need for high-cost photolithography processes such as EUV, which helps to reduce production costs.

[0122] Step S740: Use the first mask layer to etch the word line material located directly above the edge region.

[0123] The first mask layer 106 exposes the word line material 115 located directly above the edge region 1041. By etching downwards using the first mask layer 106, the word line material 115 located directly above the edge region 1041 can be etched away, forming a recessed structure directly above the edge region 1041. In other words, before the final etching of the word line material 115 to form the word line structure 107, the word line material 115 located directly above the edge region 1041 is pre-etched to compensate for the inconsistent etching rates between the edge region 1041 and the middle region 1042 during the final etching process. Therefore, the required depth of the recessed structure can be determined based on the difference in etching rates between the edge region 1041 and the middle region 1042, the structural and dimensional parameters of the word line trench 104, and product requirements. Furthermore, by controlling process parameters such as etching time in step S740, the recessed structure can achieve the required depth.

[0124] In one embodiment, when one or more word line materials 115 are filled into the word line trench 104, the word line material 115 also covers the substrate 101, as shown in the reference. Figure 8 As shown, the word line material 115 extends beyond the word line trench 104, covering the upper surface of the substrate dielectric layer 1033 above the substrate 101. The etching of the word line material 115 located above the edge position using the first mask layer includes:

[0125] The word line material 115 located directly above the edge region 1041 is etched using the first mask layer 106, and the etching endpoint is controlled to be no lower than the top of the word line trench 104.

[0126] In other words, the bottom of the recessed structure formed by etching the character line material 115 is not lower than the top of the character line groove 104. For example, the bottom of the recessed structure can be flush with the top of the character line groove 104 or higher than the top of the character line groove 104. This avoids over-etching of the character line material 115 directly above the edge region 1041, which could result in an unintended character line structure 107.

[0127] refer to Figure 23A As shown, using a first mask layer 106 formed of photoresist material 116 as a mask, word line material 115 is etched, with the etching endpoint controlled to be higher than the top of the word line trench 104 (i.e., the top of the sidewall dielectric layer 1031). (See reference...) Figure 23B As shown, using the first mask layer 106 formed of photoresist material 116 as a mask, the word line material 115 is etched, controlling the etching endpoint to be flush with the top of the word line trench 104. (Reference) Figure 23C As shown, using the first mask layer 106 formed by the first hard mask layer 1081 as a mask, the word line material 115 is etched, and the etching endpoint is controlled to be higher than the top of the word line trench 104. (Reference) Figure 23D As shown, the first mask layer 106 formed by the first hard mask layer 1081 is used as a mask to etch the word line material 115, and the etching endpoint is controlled to be flush with the top of the word line groove 104.

[0128] Step S750: Remove the first mask layer and etch back the remaining word line material. The etched word line material forms a word line structure. The word line structure includes an edge word line layer located in the edge region and an intermediate word line layer located in the middle region. The upper surface of the intermediate word line layer is not lower than the upper surface of the edge word line layer.

[0129] The first mask layer 106 can be removed by processes such as cleaning, wet etching, and dry etching. The appropriate process can be selected according to the material of the first mask layer 106. Figure 23A and Figure 23C The semiconductor structure shown can be referenced after removing the first mask layer 106. Figure 24A As shown, Figure 23B and Figure 23D The semiconductor structure shown can be referenced after removing the first mask layer 106. Figure 24B As shown.

[0130] After removing the first mask layer 106, the remaining word line material 115 is etched back. This etches away the word line material 115 located outside the word line trench 104, while simultaneously etching the word line material 115 within the word line trench 104 to the required height. Process parameters such as the etch back time can be controlled according to the required height of the word line structure 107, ensuring that the remaining word line material 115 reaches that height. The remaining word line material 115 ultimately forms the word line structure 107. For example, Figure 24A The semiconductor structure shown can be referenced after etching back the word line material 115. Figure 5A As shown, Figure 24B The semiconductor structure shown can be referenced after etching back the word line material 115. Figure 5BAs shown in FIG. 10B, the upper surface of the middle word line layer 1072 is protruded, so that the upper surface of the word line structure 107 forms a flat structure or an Ω-shaped structure, which is beneficial to reduce the contact area of the word line structure 107 with the dielectric layer 103 of the sidewall, improve the GIDL problem, and reduce the leakage current and power consumption. In addition, by controlling the etching back process, the cross-sectional area of the word line structure 107 can be kept unchanged or at a suitable level, i.e., the total amount of the word line material 115 in the word line structure 107 is not reduced, so as not to affect the electrical properties such as the resistivity of the word line. Figure 5A As shown in FIG. 10B, the upper surface of the middle word line layer 1072 is protruded, so that the upper surface of the word line structure 107 forms a flat structure or an Ω-shaped structure, which is beneficial to reduce the contact area of the word line structure 107 with the dielectric layer 103 of the sidewall, improve the GIDL problem, and reduce the leakage current and power consumption. In addition, by controlling the etching back process, the cross-sectional area of the word line structure 107 can be kept unchanged or at a suitable level, i.e., the total amount of the word line material 115 in the word line structure 107 is not reduced, so as not to affect the electrical properties such as the resistivity of the word line. Figure 5B As shown in FIG. 10B, the upper surface of the middle word line layer 1072 is protruded, so that the upper surface of the word line structure 107 forms a flat structure or an Ω-shaped structure, which is beneficial to reduce the contact area of the word line structure 107 with the dielectric layer 103 of the sidewall, improve the GIDL problem, and reduce the leakage current and power consumption. In addition, by controlling the etching back process, the cross-sectional area of the word line structure 107 can be kept unchanged or at a suitable level, i.e., the total amount of the word line material 115 in the word line structure 107 is not reduced, so as not to affect the electrical properties such as the resistivity of the word line.

[0131] In an embodiment, if there are multiple word line materials 115, such as the above-mentioned Figure 9A or Figure 9B As shown in FIG. 10B, the upper surface of the middle word line layer 1072 is protruded, so that the upper surface of the word line structure 107 forms a flat structure or an Ω-shaped structure, which is beneficial to reduce the contact area of the word line structure 107 with the dielectric layer 103 of the sidewall, improve the GIDL problem, and reduce the leakage current and power consumption. In addition, by controlling the etching back process, the cross-sectional area of the word line structure 107 can be kept unchanged or at a suitable level, i.e., the total amount of the word line material 115 in the word line structure 107 is not reduced, so as not to affect the electrical properties such as the resistivity of the word line. Figure 6A or Figure 6B As shown in FIG. 10B, the upper surface of the middle word line layer 1072 is protruded, so that the upper surface of the word line structure 107 forms a flat structure or an Ω-shaped structure, which is beneficial to reduce the contact area of the word line structure 107 with the dielectric layer 103 of the sidewall, improve the GIDL problem, and reduce the leakage current and power consumption. In addition, by controlling the etching back process, the cross-sectional area of the word line structure 107 can be kept unchanged or at a suitable level, i.e., the total amount of the word line material 115 in the word line structure 107 is not reduced, so as not to affect the electrical properties such as the resistivity of the word line.

[0132] In summary, in the method shown in Figure 7 As shown in FIG. 10B, the upper surface of the middle word line layer 1072 is protruded, so that the upper surface of the word line structure 107 forms a flat structure or an Ω-shaped structure, which is beneficial to reduce the contact area of the word line structure 107 with the dielectric layer 103 of the sidewall, improve the GIDL problem, and reduce the leakage current and power consumption. In addition, by controlling the etching back process, the cross-sectional area of the word line structure 107 can be kept unchanged or at a suitable level, i.e., the total amount of the word line material 115 in the word line structure 107 is not reduced, so as not to affect the electrical properties such as the resistivity of the word line.

[0133] Exemplary embodiments of the present disclosure also provide a memory which can include any of the semiconductor structures in the present exemplary embodiments. The memory can be a volatile memory such as a DRAM, or a non-volatile memory such as a NAND Flash, etc. The memory has a lower GIDL and a better performance.

[0134] It is to be understood that the present disclosure is not limited to the precise structures herein described and illustrated in the drawings, and that various modifications and changes can be made without departing from its scope. The application is intended to cover any adaptations or variations of the technology encompassed by the foregoing disclosure and patent claims, including such as are within the ordinary skills of those in the art. The contents of this specification are to be considered merely as exemplary and in no way limiting, the scope and spirit of the disclosure being indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, comprising: providing a substrate, a first trench being formed in the substrate, an inner surface of the first trench being covered with a dielectric layer, the dielectric layer including at least a sidewall dielectric layer on sidewalls of the first trench and a bottom dielectric layer on a bottom of the first trench; the sidewall dielectric layer and the bottom dielectric layer in the same first trench enclosing a word line trench, the word line trench including edge regions near the sidewall dielectric layer and intermediate regions between the edge regions; filling one or more word line materials in the word line trench; forming a first mask layer above the substrate, a missing portion of the first mask layer being directly above the edge regions; etching the word line materials directly above the edge regions using the first mask layer, and controlling an etching end point to be no lower than a top of the word line trench; removing the first mask layer, and back-etching the remaining word line materials, the back-etched word line materials forming a word line structure; the word line structure including edge word line layers at the edge regions and intermediate word line layers at the intermediate regions, an upper surface of the intermediate word line layers being no lower than an upper surface of the edge word line layers.

2. The method of claim 1, wherein: the forming a first mask layer above the substrate comprises: coating a photoresist material above the substrate, and removing the photoresist material directly above the edge regions by exposure and development, the remaining photoresist material forming the first mask layer.

3. The method of claim 1, wherein: the forming a first mask layer above the substrate comprises: forming a second mask layer above the substrate; opening a second trench in the second mask layer, the second trench being directly above the word line trench; forming a sidewall spacer covering sidewalls of the second trench, the sidewall spacer being directly above the edge regions; forming a third mask layer, the third mask layer at least filling the second trench; forming a third trench in the second mask layer and the third mask layer by removing the sidewall spacer, the third trench being directly above the edge regions and having a bottom at an upper surface of the word line materials; using the remaining second mask layer and the third mask layer as the first mask layer, or back-etching the second mask layer and the third mask layer to remove the third mask layer, and using the remaining second mask layer as the first mask layer.

4. The method of claim 3, wherein: the forming a third trench in the second mask layer and the third mask layer by removing the sidewall spacer comprises: removing the sidewall spacer, and etching the second mask layer along a space formed by removing the sidewall spacer using the word line materials as an etching stop layer to form the third trench.

5. The method of claim 3, wherein: ​ The second mask layer is a laminated structure, wherein the lowermost layer is a first hard mask layer; the back-etching of the second mask layer and the third mask layer to remove the third mask layer comprises: The first hard mask layer is used as an etching stop layer, and the second mask layer and the third mask layer are back-etched to remove the third mask layer and the part of the first mask layer above the first hard mask layer.

6. The method of claim 3, wherein, The second mask layer is a laminated structure, wherein the uppermost layer is a second hard mask layer; The third mask layer is formed to at least fill the second trench, comprising: A third mask material is deposited or coated to at least fill the second trench; The second hard mask layer is used as an etching stop layer, and the third mask material or the third mask material and a spacer layer located on the second mask layer are back-etched to expose the sidewall spacer layer, and the remaining third mask material forms the third mask layer.

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