Method for manufacturing a memory device

Abstract

The present application discloses a method for manufacturing a memory device, comprising: providing a substrate, the substrate comprising a first region, a second region, and a third region, wherein a first polysilicon layer is formed on a pad oxide layer in the first region, a second polysilicon layer is formed above the first polysilicon layer, a third polysilicon layer is formed on the pad oxide layer in the second region, and a fourth polysilicon layer is formed on the pad oxide layer in the third region; forming an etching protection layer and a cap layer on the second polysilicon layer, the third polysilicon layer, and the fourth polysilicon layer in sequence; removing the etching protection layer and the cap layer from the second and third regions; forming a first trench in the first region, a second trench in the second region, and a third trench in the third region; forming an isolation layer around the memory cell, the gate of the first logic device, and the gate of the second logic device; forming an interlayer dielectric layer; and forming a through hole for a contact hole.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a method for manufacturing a memory device. Background Art

[0002] Non-volatile memory (NVM) is a widely used information storage device that stores 0 / 1 information by storing charge on a floating gate (FG). It also has good resistance to magnetic interference when there is no power maintenance.

[0003] Among NVM memories, NOR (not-or) flash memory is based on Intel's tunnel oxide (ETOX) non-volatile memory structure. It is a voltage-controlled device that uses hot electron injection to write data and tunneling to erase data. Its notable feature is its fast random read speed. As an NVM memory, NOR flash memory offers high device density, low power consumption, and electrical rewritability. It is widely used in electronic storage devices such as smartphones, tablets, digital cameras, and USB flash drives (U disks).

[0004] Typically, a substrate used to integrate NOR flash memory is integrated with an array of memory cell devices and peripheral circuits composed of logic devices. During the fabrication of NOR flash memory, a high nitride / oxide etch selectivity is required during the etching of self-aligned contacts (SAC). If the nitride / oxide etch selectivity is relatively low, the nitride cap layer above the memory cell control gate (CG) may be undercut, thereby causing bridging between the subsequently formed contact hole and the control gate. If the nitride / oxide etch selectivity is relatively high, incomplete etching may occur, affecting subsequent filling. Summary of the Invention

[0005] The present application provides a method for manufacturing a memory device, which can solve the problem in the related art that the control gate is easily exposed during the through-hole etching process of the contact hole, thereby affecting reliability and yield. The method includes:

[0006] A substrate is provided, wherein regions of the substrate for forming a semiconductor device include a first region, a second region, and a third region, the first region being used to form a memory cell device, the second region being used to form a first logic device, and the third region being used to form a second logic device, a pad oxide layer being formed on the substrate, a first polysilicon layer being formed on the pad oxide layer in the first region, a second polysilicon layer being formed above the first polysilicon layer, a first isolation layer being formed between the first polysilicon layer and the second polysilicon layer, a third polysilicon layer being formed on the pad oxide layer in the second region, and a fourth polysilicon layer being formed on the pad oxide layer in the third region;

[0007] forming an etching protection layer on the second polysilicon layer, the third polysilicon layer, and the fourth polysilicon layer;

[0008] forming a cap layer on the etching protection layer;

[0009] removing the etching protection layer and the cap layer from the second region and the third region;

[0010] Performing etching to form a first trench in the first region, a second trench in the second region, and a third trench in the third region, exposing the substrate at the bottom of the first trench, the substrate at the bottom of the second trench, and the substrate at the bottom of the third trench, the remaining first polysilicon layer forming a floating gate of a memory cell, the remaining second polysilicon layer forming a control gate of the memory cell, the remaining third polysilicon layer forming a gate of a first logic device, and the remaining fourth polysilicon layer forming a gate of a second logic device;

[0011] forming a second isolation layer around the memory cell, forming a third isolation layer around the gate of the first logic device, and forming a fourth isolation layer around the gate of the second logic device;

[0012] forming an interlayer dielectric layer, wherein the height of the interlayer dielectric layer is higher than the second isolation layer, the third isolation layer, and the fourth isolation layer;

[0013] Etching is performed to form a first through hole in the first trench, a second through hole in the second trench, and a third through hole in the third trench, wherein the substrate at the bottom of the first through hole is exposed, the substrate at the bottom of the second through hole is exposed, and the substrate at the bottom of the third through hole is exposed, and the first through hole, the second through hole, and the third through hole are used to form contact holes.

[0014] In some embodiments, the etch protection layer includes an oxide layer.

[0015] In some embodiments, the cap layer includes a nitride layer.

[0016] In some embodiments, a thickness of the pad oxide layer in the second region is greater than a thickness of the pad oxide layer in the first region and a thickness of the pad oxide layer in the third region.

[0017] In some embodiments, before forming the interlayer dielectric layer, the method further includes:

[0018] A fifth isolation layer is formed, where the fifth isolation layer covers the memory cell, the first logic device, and the second logic device.

[0019] The technical solution of this application has at least the following advantages:

[0020] During the manufacturing process of the memory device, before forming the cap layer of the memory cell device, an etching protection layer is formed on the control gate polysilicon layer, and then subsequent gate etching, isolation layer formation, interlayer dielectric layer filling and contact hole etching are carried out. Since the etching protection layer is formed on the control gate, the probability of corner cutting is reduced while ensuring a high etching selectivity, thereby improving the reliability and yield of the device to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 is a flow chart of a method for manufacturing a memory device provided by an exemplary embodiment of the present application;

[0023] Figures 2 to 7 It is a schematic diagram of a manufacturing process of a memory device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0024] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0025] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0027] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0028] Step S1, providing a substrate, the substrate including regions for forming semiconductor devices including a first region, a second region and a third region, the first region being used to form a memory cell device, the second region being used to form a first logic device, and the third region being used to form a second logic device, a pad oxide layer being formed on the substrate, a first polysilicon layer being formed on the pad oxide layer in the first region, a second polysilicon layer being formed above the first polysilicon layer, a first isolation layer being formed between the first polysilicon layer and the second polysilicon layer, a third polysilicon layer being formed on the pad oxide layer in the second region, and a fourth polysilicon layer being formed on the pad oxide layer in the third region.

[0029] Step S2 , forming an etching protection layer on the second polysilicon layer, the third polysilicon layer and the fourth polysilicon layer.

[0030] Step S3: forming a cap layer on the etching protection layer.

[0031] refer to Figure 2 , which shows a cross-sectional schematic diagram after the cap layer is formed. For example, Figure 2As shown, the region of the substrate 210 used to form the semiconductor device includes a first region 201, a second region 202 and a third region 203. The first region 201 is used to form a memory cell device, the second region 202 is used to form a first logic device, and the third region 203 is used to form a second logic device. The first logic device and the second logic device can be devices with different operating voltages. A pad oxide is formed on the substrate 210. A first polysilicon layer 2311 is formed on the pad oxide layer 221 of the first region 201, a second polysilicon layer 232 is formed above the first polysilicon layer 2311, and a first isolation layer (the isolation layer may be an oxide-nitride-oxide (ONO) layer, which includes, from bottom to top, an oxide layer 2221, a nitride layer 2222, and an oxide layer 2223) is formed between the first polysilicon layer 2311 and the second polysilicon layer 232. A third polysilicon layer 2312 is formed on the pad oxide layer 222 of the second region 202, and a fourth polysilicon layer 2313 is formed on the pad oxide layer 223 of the third region 203. The second polysilicon layer 232, the third polysilicon layer 2312, and the fourth polysilicon layer 2313 are thin film layers of the same layer formed by the same deposition process.

[0032] The etch protection layer 230 comprises an oxide layer, and the cap layer 240 comprises a nitride layer. The thickness of the pad oxide layer 222 in the second region 202 is greater than the thickness of the pad oxide layer 223 in the third region 203. A first doped region 2011 (which can serve as a well region of a memory cell device) is formed in the substrate 210 of the first region 201. A second doped region 2012 (which can serve as a well region of the memory cell device) is formed in the first doped region 2011. A third doped region 2013 (which can serve as a cell voltage (CVT) region) is formed in the second doped region 2012. A fourth doped region 2021 (which can serve as a well region of a first logic device) is formed in the substrate 210 of the second region 201. A fifth doped region 2031 (which can serve as a well region of a second logic device) is formed in the substrate 210 of the third region 203.

[0033] Step S4, removing the etching protection layer and the cap layer in the second area and the third area.

[0034] refer to Figure 3 , which shows a cross-sectional schematic diagram after removing the etching protection layer and the cap layer in the second and third regions. Figure 3 As shown, the etching protection layer 230 and the cap layer 240 in the second region 202 and the third region 203 may be removed by dry etching and / or wet etching.

[0035] In step S5, etching is performed to form a first trench in the first area, a second trench in the second area, and a third trench in the third area. The substrate at the bottom of the first trench is exposed, the substrate at the bottom of the second trench is exposed, and the substrate at the bottom of the third trench is exposed. The remaining first polysilicon layer forms a floating gate of the memory cell, the remaining second polysilicon layer forms a control gate of the memory cell, the remaining third polysilicon layer forms a gate of the first logic device, and the remaining fourth polysilicon layer forms a gate of the second logic device.

[0036] refer to Figure 4 , which shows a cross-sectional schematic diagram after forming the first trench, the second trench and the third trench. Figure 4 As shown, a photoresist layer can be placed over the substrate 210. The photoresist layer in the target area (the area corresponding to the first trench 301, the second trench 302, and the third trench 303) can be removed by exposure and development. Etching is then performed to form a first trench 301 in the first area 201, a second trench 302 in the second area 202, and a third trench 303 in the third area 203. The substrate 210 at the bottom of the first trench 301, the bottom of the second trench 302, and the bottom of the third trench 303 are exposed. The remaining first polysilicon layer 2311 forms the floating gate of the memory cell, the remaining second polysilicon layer 232 forms the control gate of the memory cell, the remaining third polysilicon layer 2312 forms the gate of the first logic device, and the remaining fourth polysilicon layer 2313 forms the gate of the second logic device. A set of adjacent floating gates and control gates can serve as a memory cell.

[0037] Step S6 , forming a second isolation layer around the memory cell, forming a third isolation layer around the gate of the first logic device, and forming a fourth isolation layer around the gate of the second logic device.

[0038] refer to Figure 5 , which shows a cross-sectional schematic diagram after forming the second isolation layer, the third isolation layer and the fourth isolation layer. Figure 5 As shown, the second isolation layer includes an oxide layer 251, a nitride layer 252 and an oxide layer 253 from the inside to the outside, and the outermost oxide layer 253 of the storage unit can be removed by etching. The third isolation layer includes an oxide layer 251, a nitride layer 252 and an oxide layer 253 from the inside to the outside, and the fourth isolation layer includes an oxide layer 251, a nitride layer 252 and an oxide layer 253 from the inside to the outside.

[0039] For example, before forming the second, third, and fourth isolation layers, lightly doped drain (LDD) regions 2014 may be formed in the substrate 210 on both sides of the memory device and in the substrate 210 between two columns of floating gates within the memory device. A sixth doped region 2016 and a seventh doped region 2015 may be formed in the substrate 210 between the two columns of floating gates within the memory device, with the LDD region 2014 located within the seventh doped region 2015. Heavily doped regions 2020 may be formed in the substrate 210 on both sides of the memory device, the first logic device, and the second logic device. The impurity concentration in the heavily doped regions 2020 is greater than the impurity concentration in other doped regions. Optionally, a metal silicide layer 260 may be formed in the heavily doped regions 2020 and in the gates of the first and second logic devices.

[0040] Step S7 , forming an interlayer dielectric layer, wherein the height of the interlayer dielectric layer is higher than the second isolation layer, the third isolation layer, and the fourth isolation layer.

[0041] For example, after forming the second isolation layer, the third isolation layer and the fourth isolation layer, a fifth isolation layer may be formed to cover the second isolation layer, the third isolation layer and the fourth isolation layer, referring to Figure 6 , which shows a cross-sectional schematic diagram after forming a fifth isolation layer and an interlayer dielectric (ILD) layer 270, as shown Figure 6 As shown, the fifth isolation layer includes an oxynitride layer 254 and a nitride layer 255 from bottom to top. The nitride layer 255 between the memory cells and the logic devices can be removed by etching. The interlayer dielectric layer 270 may include an oxide layer.

[0042] In step S8, etching is performed to form a first through hole in the first trench, a second through hole in the second trench, and a third through hole in the third trench. The substrate at the bottom of the first through hole is exposed, the substrate at the bottom of the second through hole is exposed, and the substrate at the bottom of the third through hole is exposed. The first through hole, the second through hole, and the third through hole are used to form contact holes.

[0043] refer to Figure 7 , which shows a cross-sectional schematic diagram after forming the first through hole, the second through hole and the third through hole. Figure 7 As shown, after the first through hole 3011, the second through hole 3012 and the third through hole 3013 are formed, due to the presence of the etching protection layer 230, an etching process with a relatively large etching selectivity can be used for etching, while ensuring the etching completion, and effectively avoiding the corner from being missing and exposing the control gate 232 (such as Figure 7 (shown by the dashed line).

[0044] In summary, in the embodiments of the present application, during the manufacturing process of the memory device, before forming the cap layer of the memory cell device, an etching protection layer is formed on the control gate polysilicon layer, and then subsequent gate etching, isolation layer formation, interlayer dielectric layer filling and contact hole etching are performed. Since the etching protection layer is formed on the control gate, the probability of corner cutting can be reduced while ensuring a high etching selectivity, thereby improving the reliability and yield of the device to a certain extent.

[0045] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for manufacturing a memory device, characterized in that: include: A substrate is provided, wherein regions of the substrate for forming a semiconductor device include a first region, a second region, and a third region, the first region being used to form a memory cell device, the second region being used to form a first logic device, and the third region being used to form a second logic device, a pad oxide layer being formed on the substrate, a first polysilicon layer being formed on the pad oxide layer in the first region, a second polysilicon layer being formed above the first polysilicon layer, a first isolation layer being formed between the first polysilicon layer and the second polysilicon layer, a third polysilicon layer being formed on the pad oxide layer in the second region, and a fourth polysilicon layer being formed on the pad oxide layer in the third region; forming an etching protection layer on the second polysilicon layer, the third polysilicon layer, and the fourth polysilicon layer; forming a cap layer on the etching protection layer; removing the etching protection layer and the cap layer from the second region and the third region; Performing etching to form a first trench in the first region, a second trench in the second region, and a third trench in the third region, exposing the substrate at the bottom of the first trench, the substrate at the bottom of the second trench, and the substrate at the bottom of the third trench, the remaining first polysilicon layer forming a floating gate of a memory cell, the remaining second polysilicon layer forming a control gate of the memory cell, the remaining third polysilicon layer forming a gate of a first logic device, and the remaining fourth polysilicon layer forming a gate of a second logic device; forming a second isolation layer around the memory cell, forming a third isolation layer around the gate of the first logic device, and forming a fourth isolation layer around the gate of the second logic device; forming an interlayer dielectric layer, wherein the height of the interlayer dielectric layer is higher than the second isolation layer, the third isolation layer, and the fourth isolation layer; Etching is performed to form a first through hole in the first trench, a second through hole in the second trench, and a third through hole in the third trench, wherein the substrate at the bottom of the first through hole is exposed, the substrate at the bottom of the second through hole is exposed, and the substrate at the bottom of the third through hole is exposed, and the first through hole, the second through hole, and the third through hole are used to form contact holes.

2. The method according to claim 1, characterized in that The etching protection layer includes an oxide layer.

3. The method according to claim 2, characterized in that The cap layer includes a nitride layer.

4. The method according to claim 3, characterized in that The thickness of the pad oxide layer in the second region is greater than the thickness of the pad oxide layer in the first region and the thickness of the pad oxide layer in the third region.

5. The method according to any one of claims 1 to 4, characterized in that: Before forming the interlayer dielectric layer, the method further includes: A fifth isolation layer is formed, where the fifth isolation layer covers the memory cell, the first logic device, and the second logic device.

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