An IGBT structure and semiconductor device

Abstract

This application discloses an IGBT structure and semiconductor device. The IGBT structure includes: a substrate, a drift region of a first conductivity type, a collector region of a second conductivity type, an active gate, a body region of a second conductivity type, a first doped region of a second conductivity type, an emitter region of a first conductivity type, and a second doped region of a second conductivity type. The active gate extends from a first main surface to a second main surface into the drift region. The first doped region and the body region are respectively disposed on both sides of the active gate and are located on the side of the drift region facing the first main surface. The emitter region is located on the side of the body region facing the first main surface and is located between two adjacent active gates. The emitter region includes a first emitter region and a second emitter region, and the first emitter region and the second emitter region respectively cover at least partially the first body region and the second body region. The doping concentration of the second doped region is greater than the doping concentration of the body region. According to the IGBT structure and semiconductor device of this application, conductivity modulation caused by narrow mesa between active gates can be effectively avoided, thus preventing the CIBL effect.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to an IGBT structure and semiconductor device. Background Technology

[0002] Currently, IGBT (Insulated Gate Bipolar Transistor) is a MOS-bipolar composite transistor developed based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). It has the advantages of both power bipolar transistors and power MOSFETs, but has different advantages in on-state voltage drop and switching, thus becoming a core device in power supply, drive, and control circuits.

[0003] In related technologies, ultra-narrow mesa structure IGBTs can achieve the theoretical silicon limit, and this structure effectively reduces conduction losses. However, due to the excessively narrow mesa, the entire P-body region is inverted into an N-type electron channel. Holes are injected into the N-type electron channel from the back side, resulting in conductivity modulation within the channel (generally referring to the phenomenon that the resistivity of semiconductor materials decreases significantly with increasing carrier concentration under high injection conditions). This leads to the problem of collector-induced barrier lowering (CIBL).

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To at least partially solve the above problems, according to a first aspect of this application, an IGBT structure is provided, comprising:

[0007] A substrate having a first main surface and a second main surface located on the opposite side of the first main surface, the first main surface and the second main surface being spaced apart along a first direction;

[0008] A drift region of a first conductivity type is provided between the first main surface and the second main surface;

[0009] The current collector region of the second conductivity type is located on the side of the drift region facing the second main surface;

[0010] An active gate extends from the first main surface to the second main surface into the drift region;

[0011] A body region of a second conductivity type is disposed in the substrate outside the active gate and located on the side of the drift region facing the first main surface. The body region includes a first body region and a second body region spaced apart along the second direction, wherein the second direction is perpendicular to the first direction.

[0012] The first doped region of the second conductivity type is located on both sides of the active gate, and the first doped region and the body region are respectively located on the side of the drift region facing the first main surface.

[0013] The emitter region of the first conductivity type is located on the side of the body region facing the first main surface and between two adjacent active gates. The emitter region includes a first emitter region and a second emitter region, which are spaced apart in a second direction. The first emitter region and the second emitter region respectively cover at least part of the first body region and the second body region.

[0014] A virtual gate extends from the first main surface to the second main surface into the drift region. The virtual gate and the active gate are spaced apart along a third direction. The first doped region is located outside the virtual gate. The third direction is perpendicular to the first direction and the second direction.

[0015] A second doped region of a second conductivity type is disposed between the first body region and the second body region, and is located on the side of the drift region facing the first main surface. The doping concentration of the second doped region is greater than the doping concentration of the body region.

[0016] The above technical solution has the following advantages and beneficial effects: According to the IGBT structure of the present invention, the first emitter region and the second emitter region respectively cover the first body region and the second body region. A second doped region is provided between the first body region and the second body region, and the doping concentration of the second doped region is greater than that of the first body region and the second body region. Therefore, the injected carriers (such as holes) can be dispersed to the low-potential second doped region, thereby reducing the number of holes flowing through the first body region and the second body region. This can effectively limit the conductivity modulation of the narrow mesa between the active gates and prevent the CIBL effect from occurring.

[0017] Optionally, the doping concentration of the first doped region is greater than the doping concentration of the body region.

[0018] The above technical solution has the following advantages and beneficial effects: by making the doping concentration of the first doped region greater than that of the body region, the holes injected from the back side can be dispersed to the low-potential first doped region (e.g., the P+ region) in the third direction, thereby reducing the number of holes flowing through the body region, effectively limiting the conductance modulation of the narrow mesa between the gates, and thus limiting the CIBL effect.

[0019] Optionally, it further includes a third doped region disposed between the first body region and the second body region, wherein the doping concentration of the third doped region is less than the doping concentration of the body region, and wherein the third doped region and the second doped region are disposed in contact along the third direction.

[0020] The above technical solution has the following advantages and beneficial effects: During the IGBT turn-on process, as the active gate voltage rises, due to the low doping concentration of the third doped region, an electron channel will be generated first. Electrons flow laterally (in the second direction) through the third doped region channel from the first and second emitter regions, and then flow longitudinally (in the first direction) to the drift region, accumulating below the third doped region, which accelerates the disappearance of the depletion region and solves the problem of voltage drop tailing between the collector and emitter regions during the turn-on process.

[0021] Optionally, the number of third doped regions is at least two, and along the third direction, the third doped regions are located on both sides of the second doped region.

[0022] The above technical solution has the following advantages and beneficial effects: With this setting, electrons can flow laterally (in the second direction) through the third doped region channel from the first and second emitter regions, and then flow longitudinally (in the first direction) to the drift region, where they accumulate below the third doped region, accelerating the disappearance of the depletion region and solving the problem of voltage drop tailing from the collector region to the emitter region during the turn-on process.

[0023] Optionally, the number of the third doped region is at least two, the number of the second doped region is at least two, and the second doped region and the third doped region are alternately arranged along the third direction.

[0024] The above technical solution has the following advantages and beneficial effects: by setting the third doped region and the third doped region in this way, it is also possible to effectively limit the conductivity modulation of the narrow mesa between the gates, thereby limiting the CIBL effect, and solving the problem of voltage drop tailing of the collector-emitter region during the turn-on process.

[0025] Optionally, the IGBT structure further includes: an insulating layer disposed on the first main surface, the insulating layer having a contact hole on the portion corresponding to the emitter area; and an emitter metal disposed on the side of the insulating layer away from the second main surface, the emitter area contacting the emitter metal through the contact hole.

[0026] The above technical solution has the following advantages and beneficial effects: the insulating layer electrically isolates the emitter region and the active gate, while the emitter metal enables the emitter region to be brought out, thereby facilitating its connection with external circuits.

[0027] Optionally, the virtual gate is disposed in a first gate trench, the first gate trench extending from the first main surface to the second main surface into the drift region, the virtual gate including a first gate dielectric layer located on the inner surface of the first gate trench and a first polysilicon gate located on the side of the first gate dielectric layer away from the inner surface of the first gate trench and filling the first gate trench; the first polysilicon gate is electrically connected to the emitter metal.

[0028] The above technical solution has the following advantages and beneficial effects: The first polysilicon gate is electrically connected to the emitter metal, that is, the dummy gate is short-circuited with the emitter region. By short-circuiting the dummy gate with the emitter region, the dummy gate and the emitter region can be made to have the same properties and be negatively charged. This can attract some holes to transfer to the dummy gate, thereby reducing the number of holes flowing below the emitter region, that is, reducing the number of holes flowing in the channel, reducing the risk of latch-up under high current conditions, and also reducing the feedback capacitance of the IGBT, thereby reducing switching losses.

[0029] Optionally, the active gate is disposed in the second gate trench, the second gate trench extends from the first main surface to the second main surface into the drift region, and the active gate includes a second gate dielectric layer located on the inner surface of the second gate trench and a second polysilicon gate located on the side of the second gate dielectric layer away from the inner surface of the second gate trench and filling the second gate trench.

[0030] The above technical solution has the following advantages and beneficial effects: the active gate plays a control role in the IGBT and is a gate structure capable of forming a conductive channel. When a gate voltage is applied to the active gate, a conductive channel can be formed around the active gate, allowing electrons and holes to move in the channel, thereby controlling the IGBT's turn-on and turn-off.

[0031] Optionally, it also includes:

[0032] The field cutoff region is located on the side of the drift region away from the first main surface;

[0033] The collector region is located on the side of the field cutoff region away from the first main surface; and

[0034] Collector metal, the collector metal being disposed on the second main surface and covering at least a portion of the collector region.

[0035] The above technical solution has the following advantages and beneficial effects: The main function of the field cutoff region is to terminate the electric field in the IGBT turn-off state, prevent the electric field from penetrating into the collector region, thereby improving the device's withstand voltage capability.

[0036] The semiconductor device according to an embodiment of the present invention includes the above-described IGBT structure.

[0037] The above technical solution has the following advantages and beneficial effects: Since the semiconductor device according to the present invention includes the aforementioned IGBT structure, it also has the advantages and beneficial effects of the aforementioned IGBT structure. Attached Figure Description

[0038] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain the application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0039] Figure 1 A top view of the IGBT structure in the related technology is shown.

[0040] Figure 2 The IGBT structure is shown along Figure 1 A sectional view along the A-A1 direction.

[0041] Figure 3 The IGBT structure is shown along Figure 1 A sectional view along the B-B1 direction.

[0042] Figure 4 A top view of the IGBT structure in an embodiment of this application is shown.

[0043] Figure 5 The IGBT structure shown in the embodiment of this application is along Figure 4 A sectional view along the A-A1 direction.

[0044] Figure 6 The IGBT structure shown in the embodiment of this application is along Figure 4 A sectional view along the B-B1 direction.

[0045] Figure 7 The IGBT structure shown in the embodiment of this application is along Figure 4 A sectional view along the C-C1 direction.

[0046] Figure 8 The IGBT structure shown in the embodiment of this application is along Figure 4 A cross-sectional view along the D-D1 direction.

[0047] Figure label:

[0048] 100, Substrate; 101, First principal surface; 102, Second principal surface; 110, Drift region; 120, Collector region; 130, Active gate; 140, Virtual gate; 150, Body region; 151, First body region; 152, Second body region; 161, First doped region; 162, Second doped region; 163, Third doped region; 170, Emitter region; 171, First emitter region; 172, Second emitter region; 180, Insulating layer; 200, Emitter metal; 300, Collector metal; 400, Field cutoff region. Detailed Implementation

[0049] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0050] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0051] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0052] Spatial relation terms such as "below," "under," "below," "under," "above," and "above" are used here for convenience to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of devices in use and operation.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application. Thus, variations in the shown shape are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the figures are substantially schematic, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of this application.

[0055] First, it should be noted that in this article, N and P represent the conductivity type of the semiconductor. The following explanation will use N-type as the first conductivity type and P-type as the second conductivity type.

[0056] like Figures 1-3 As shown, the narrow mesa IGBT structure in the related technology includes: a virtual gate 10, an active gate 11, a body region 12, an emitter region 13, a drift region 14, and a collector region 15. The virtual gate 10 and the active gate 11 extend into the drift region 14. The virtual gate 10 and the active gate 11 are arranged alternately. A body region 12 of a second conductivity type is provided between the virtual gate 10 and the active gate 11. A body region 12 is also provided between the active gates 11. The drift region 14 is located between the body region 12 and the collector region 15. An emitter region 13 of a first conductivity type is also provided between the active gates 11. The emitter region 13 is located on the side of the body region 12 away from the drift region 14.

[0057] like Figure 3 As shown, adjacent emission regions 13 are arranged at intervals, and at least a portion of the body region 12 is provided between emission regions 13.

[0058] When the IGBT structure in the related technology is turned on, due to the narrow mesa, the body region 12 of the second conductivity type is completely inverted into an electron channel of the first conductivity type. Charge carriers (such as holes) on the back side are injected into the electron channel and conductivity modulation occurs in the channel, resulting in the CIBL effect. This leads to an increase in the transconductance of the device, a decrease in the threshold voltage, and extremely poor short-circuit withstand capability.

[0059] To improve short-circuit capability, the channel density can be reduced (by increasing the spacing between emitter regions 13). However, when the IGBT is turned on, electrons drift longitudinally from the emitter region 13 through the body region 12 below it to the drift region 14 and accumulate. In the drift region 14 below the body region 12 between the two emitter regions 13, there is no direct accumulation of drifting electrons; only lateral diffusion of electrons below the emitter region 13 occurs. Therefore, the depletion region in this area disappears relatively slowly. This easily leads to collector-emitter voltage tailing during the turn-on process, increasing turn-on losses and significantly limiting the application of narrow mesa structure IGBTs.

[0060] like Figures 4 to 8 As shown, to solve the above problems, this application provides an IGBT structure, including: a substrate 100, a drift region 110 of a first conductivity type, a collector region 120 of a second conductivity type, an active gate 130, a body region 150 of a second conductivity type, a first doped region 161 of a second conductivity type, an emitter region 170 of a first conductivity type, and a second doped region 162 of a second conductivity type.

[0061] The substrate 100 has a first main surface 101 and a second main surface 102 located on the opposite side of the first main surface 101, the first main surface 101 and the second main surface 102 being along a first direction ( Figure 5 The vertical (or vertical) spacing settings are configured.

[0062] For example, the substrate 100 may be any suitable semiconductor substrate, such as a silicon substrate, and may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures made of these semiconductor materials, or silicon on insulator (SOI), silicon on insulator stacked on insulator (SSOI), silicon on insulator stacked on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI).

[0063] The drift region 110 is located between the first main surface 101 and the second main surface 102. The drift region 110 determines the saturation voltage drop and voltage level of the IGBT and is the main region affecting the switching speed of the IGBT. The conductivity type of the drift region 110 is the first conductivity type.

[0064] A collector region 120 of the second conductivity type is disposed on the side of the drift region 110 facing the second main surface 102, and the side of the collector region 120 away from the drift region 110 constitutes at least a portion of the second main surface 102. An active gate 130 extends from the first main surface 101 to the second main surface 102 into the drift region 110. The active gate 130 plays a control role in the IGBT and is a gate structure capable of forming a conductive channel. When a gate voltage is applied to the active gate 130, a conductive channel can be formed around the active gate 130, allowing electrons and holes to move within the channel, thereby controlling the IGBT's turn-on and turn-off.

[0065] Please refer to Figure 5 and Figure 6 The second conductivity type body region 150 is disposed within the substrate 100 outside the active gate 130, and is located on the side of the drift region 110 facing the first main surface 101. The body region 150 includes a portion along the second direction ( Figure 6 The first body area 151 and the second body area 152 are set at intervals in the left and right directions.

[0066] The first conductivity type of emission region 170 is located on the side of the body region 150 facing the first main surface 101 and between two adjacent active gates 130. The emission region 170 includes a first emission region 171 and a second emission region 172. The first emission region 171 and the second emission region 172 are spaced apart in a second direction. The first emission region 171 and the second emission region 172 respectively cover at least part of the first body region 151 and the second body region 152.

[0067] The first doped region 161 and the body region 150 of the second conductivity type are respectively disposed on both sides of the active gate 130 and located on the side of the drift region 110 facing the first main surface 101. In some embodiments, the first doped region 161 is disposed between adjacent active gates 130 and dummy gates 140. Exemplarily, the doping concentration of the first doped region 161 is greater than the doping concentration of the body region 150. By making the doping concentration of the first doped region 161 greater than the doping concentration of the body region 150, holes injected from the back side can be dispersed to the low-potential first doped region 161 (e.g., the P+ region) in the third direction, thereby reducing the number of holes flowing through the body region, effectively limiting the conductivity modulation of the narrow mesa between the gates, and thus limiting the CIBL effect.

[0068] The virtual gate 140 extends from the first principal surface 101 to the second principal surface 102 into the drift region 110, and the virtual gate 140 and the active gate 130 are along the third direction ( Figure 5The virtual gate 160 is spaced apart in the left-right direction. The first doped region 161 is located outside the virtual gate 140, that is, the first doped region 161 is located between the adjacent virtual gate 140 and the active gate 130. The virtual gate 140 is a gate structure that exists in the IGBT structure but does not directly participate in conduction. It usually cannot form a conductive channel. By setting the virtual gate 140 and connecting it to the emitter, the feedback capacitance of the IGBT (that is, the gate-collector capacitance) can be reduced, thereby reducing switching losses. For example, the virtual gate 140 can also be called a dummy gate.

[0069] In some embodiments, a second doped region 162 of the second conductivity type is disposed between the first body region 151 and the second body region 152, and is located on the side of the drift region 110 facing the first main surface 101, and the doping concentration of the second doped region 162 is greater than the doping concentration of the body region 150.

[0070] In some embodiments, a first doped region 161 is formed on both sides of the active gate 130, and a first emitter region 171 and a second emitter region 172 respectively cover the first body region 151 and the second body region 152. A second doped region 162 is provided between the first body region 151 and the second body region 152, and the doping concentration of the first doped region 161 and the second doped region 162 is greater than that of the first body region 151 and the second body region 152. Therefore, the injected carriers (such as holes) can be dispersed to the low-potential first doped region 161 and the second doped region 162, thereby reducing the number of holes flowing through the first body region 151 and the second body region 152. This can effectively limit the conductivity modulation of the narrow mesa between the active gates 130 and prevent the CIBL effect.

[0071] On one hand, when the IGBT is in the on state, the body region 150 inverts to generate an electron channel. Electrons are emitted from the emitter region 170 through the channel to the drift region 110 to form an electron current. Backside charge carriers (such as holes) are injected from the collector region 120 into the drift region 110, pass through the body region 150, and reach the emitter region 170 to form a hole current. In this embodiment, the doping concentration of the first doped region 161 between the active gate 130 and the dummy gate 140 is higher than the doping concentration of the body region 150 between the active gates 130. On the other hand, the backside injected holes can be dispersed to the lower potential of the first doped region 161, thereby reducing the number of holes flowing through the body region 150.

[0072] On the other hand, the doping concentration of the second doped region 162 between the first emitter region 171 and the second emitter region 172 is greater than the doping concentration of the body region 150 below the emitter region 170. In the second direction, the holes injected from the back side can be dispersed to the lower potential second doped region 162, thereby reducing the number of holes flowing through the body region 150. Therefore, the IGBT structure in this embodiment can effectively limit the conductivity modulation of the narrow mesa between the active gates 130 and prevent the CIBL effect.

[0073] Furthermore, in this embodiment, the second direction is perpendicular to the first direction, and the third direction is perpendicular to both the first and second directions. The third and second directions can also be directions parallel to the first and / or second principal surfaces of the substrate, such as... Figure 4 As shown, the first direction is the Z direction, the second direction is the Y direction, and the third direction is the X direction.

[0074] Please continue to refer to Figure 5 Furthermore, the IGBT structure also includes: an insulating layer 180, an emitter metal 200, and a collector metal 300.

[0075] An insulating layer 180 is disposed on the first main surface 101, and a contact hole is provided on the portion of the insulating layer 180 corresponding to the emitter region 170. The bottom of the contact hole exposes the emitter region 170. An emitter metal 200 is disposed on the side of the insulating layer 180 away from the first main surface 101. The emitter region 170 contacts the emitter metal 200 through the contact hole to form a conductive connection, thereby enabling the emitter region 170 to be led out, thus facilitating its connection with external circuits. Optionally, the material of the insulating layer 180 may include silicon oxide, silicon nitride, or any other suitable insulating material. By providing the insulating layer 180, the emitter metal and the active gate can be electrically isolated.

[0076] In some embodiments, the collector metal 300 is disposed on the second main surface 102 and contacts the collector region 120, i.e., covers at least a portion of the collector region 120, forming a conductive connection. The collector metal 300 is used to realize the electrical lead-out of the collector region 120, thereby facilitating its connection with external circuits.

[0077] Furthermore, the IGBT structure also includes a field stop region of the first conductivity type, located on the side of the drift region 110 away from the first main surface 101. The field stop region 400 is disposed between the collector region 120 and the drift region 110. The doping concentration of the field stop region 400 is higher than that of the drift region 110. Optionally, the field stop region 400 has the same conductivity type as the drift region 110. The main function of the field stop region 400 is to terminate the electric field in the IGBT turn-off state, preventing the electric field from penetrating to the collector region 120, thereby improving the device's withstand voltage capability. When a high voltage is applied, the field stop region 400 can withstand a portion of the electric field, causing the electric field to gradually weaken before reaching the collector region 120, limiting the breakdown of the collector region 120. The field stop region 400 can also reduce the duration and amplitude of the tail current by adjusting the carrier distribution and extraction speed. The reduction of the tail current helps to reduce turn-off losses.

[0078] Furthermore, a first gate trench is formed in the substrate, extending from the first main surface 101 to the second main surface 102 into the drift region 110. A virtual gate 140 is disposed in the first gate trench. The virtual gate 140 includes a first gate dielectric layer located on the inner surface of the first gate trench and a first polysilicon gate located on the side of the first gate dielectric layer away from the inner surface of the first gate trench and filling the first gate trench. The first polysilicon gate is in contact (i.e. electrically connected) with the emitter metal 200. The electrical connection between the emitter metal 200 and the virtual gate and the emitter region can be achieved, which can reduce the feedback capacitance of the IGBT, thereby reducing switching losses.

[0079] In some embodiments, a second gate trench is further formed in the substrate, extending from the first main surface 101 to the second main surface 102 into the drift region 110. The active gate 130 includes a second gate dielectric layer located on the inner surface of the second gate trench and a second polysilicon gate located on the side of the second gate dielectric layer away from the inner surface of the second gate trench and filling the second gate trench.

[0080] The first polysilicon gate is in contact with the emitter metal 200, meaning the dummy gate 140 is short-circuited to the emitter region. By short-circuiting the dummy gate 140 to the emitter region, the dummy gate 140 can have the same properties as the emitter region, carrying a negative charge. This can attract some holes to be transferred to the dummy gate 140, thereby reducing the number of holes flowing below the emitter region 170, and thus reducing the number of holes flowing in the channel. This lowers the risk of latch-up under high current conditions and also reduces the IGBT's feedback capacitance, thereby reducing switching losses.

[0081] In some embodiments, the first polysilicon gate in the virtual gate 140 can be a floating gate, that is, the first polysilicon gate is a gate that is not directly electrically connected to an external circuit. It is surrounded by an insulating layer (i.e., the gate oxide layer and the insulating layer 180) and is in a "floating" state, not directly connected to a fixed potential point such as power supply or ground.

[0082] It is worth mentioning that the arrangement of the active gate 130 and the virtual gate 140 can be reasonably set according to needs. For example, a virtual gate 140 can be set on the outside of the two active gates 130 respectively.

[0083] like Figures 7-8 As shown, the IGBT structure in this embodiment further includes a third doped region 163 disposed between the first body region 151 and the second body region 152. The doping concentration of the third doped region 163 is less than the doping concentration of the first body region 151 and the second body region 152. The third doped region 163 and the second doped region 162 are contacted along a third direction. Optionally, there can be two third doped regions 163, located in the third direction of the second doped region 162. Figure 7The two sides (in the left and right directions) of the region. Optionally, it can also have a first doped region 161 and a second doped region 162.

[0084] Furthermore, the width (width along the third direction) of the first doped region 161 between the active gate 130 and the dummy gate 140 ranges from 0.1µm to 0.6µm, for example, 0.1µm, 0.2µm, 0.3µm, 0.4µm, 0.5µm, or 0.6µm. Along the third direction, the width of the third doped region 163 is smaller than the width of the second doped region 162. For example, the width of the third doped region 163 is between 0.1µm and 0.3µm, for example, 0.1µm, 0.2µm, or 0.3µm. The width of the second doped region 162 between the third doped regions 163 is between 0.2µm and 0.4µm, for example, 0.2µm, 0.3µm, or 0.4µm. The above width range of the doped regions is only an example and can be reasonably set according to actual needs; no specific limitation is made here.

[0085] In some embodiments, during the IGBT turn-on process, as the voltage of the active gate 130 increases, due to the low doping concentration of the third doped region 163, an electron channel is first generated. Electrons flow laterally (in the second direction) through the channel of the third doped region 163 from the first emitter region 171 and the second emitter region 172, and then flow longitudinally (in the first direction) to the drift region 110, accumulating below the third doped region 163. This accelerates the disappearance of the depletion region and solves the problem of voltage drop tailing from the collector region 120 to the emitter region during the turn-on process.

[0086] In some embodiments, the number of third doped regions 163 may be at least two, the number of second doped regions 162 may be at least two, and the second doped regions 162 and third doped regions 163 may be alternately arranged along a third direction. Optionally, when the number of second doped regions 162 is at least two, the widths of these second doped regions 162 may be the same or different, and when the number of third doped regions 163 is at least two, the widths of these third doped regions 163 may be the same or different.

[0087] In some embodiments, the third doped region 163 and the second doped region 162 are arranged at a distance along a third direction, and there is a preset distance between the third doped region 163 and the second doped region 162, or the two can be in contact connection.

[0088] In some embodiments, in the third direction, the emitter region may cover the entire body region or a portion of the body region. When covering a portion of the body region, there may be a gap between the emitter region, the second doped region, and the third doped region, which is a portion of the body region.

[0089] In the IGBT structure of this application embodiment, the doping concentration of the first doped region 161 between the active gate 130 and the dummy gate 140 is higher than the doping concentration of the body region between the active gate 130. In the on state, the holes injected from the back side can be dispersed to the low-potential first doped region 161, thereby reducing the number of holes flowing through the body region.

[0090] The doping concentration of the second doped region 162 between the first emitter region 171 and the second emitter region 172 is greater than that of the body region below the emitter region. Holes can disperse to the lower potential of the second doped region 162, further reducing the number of holes flowing through the body region. This effectively limits the conductivity modulation of the narrow mesa between the active gates 130, preventing the CIBL effect. Furthermore, because the doping concentration of the third doped region 163 is low, an electron channel is generated first. Electrons flow from the emitter region through the channel of the third doped region 163 and then flow longitudinally to the drift region 110, accumulating below the third doped region 163. This accelerates the disappearance of the depletion region and solves the problem of voltage drop tailing from the collector region 120 to the emitter region during turn-on.

[0091] This application also provides a semiconductor device comprising the IGBT structure described above. The semiconductor device may be a power semiconductor device.

[0092] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0093] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0094] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0095] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0096] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0097] The above are merely specific embodiments or descriptions of specific embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.

Claims

1. An IGBT structure, characterized in that, include: A substrate having a first main surface and a second main surface located on the opposite side of the first main surface, the first main surface and the second main surface being spaced apart along a first direction; A drift region of a first conductivity type is provided between the first main surface and the second main surface; The current collector region of the second conductivity type is located on the side of the drift region facing the second main surface; An active gate extends from the first main surface to the second main surface into the drift region; A body region of a second conductivity type is disposed in the substrate outside the active gate and located on the side of the drift region facing the first main surface. The body region includes a first body region and a second body region spaced apart along a second direction, wherein the second direction is perpendicular to the first direction. The first doped region of the second conductivity type, the first doped region, the first body region and the second body region are respectively disposed on both sides of the active gate, and are located on the side of the drift region facing the first main surface; The first conductivity type of emitter region is located on the side of the first body region and the second body region facing the first main surface and between two adjacent active gates. The emitter region includes a first emitter region and a second emitter region. The first emitter region and the second emitter region are spaced apart in a second direction. The first emitter region and the second emitter region respectively cover at least part of the first body region and the second body region. A virtual gate extends from the first main surface to the second main surface into the drift region. The virtual gate and the active gate are spaced apart along a third direction. The first doped region is located outside the virtual gate. The third direction is perpendicular to the first direction and the second direction. A second doped region of the second conductivity type is disposed between the first body region and the second body region, and is located on the side of the drift region facing the first main surface. The doping concentration of the second doped region is greater than the doping concentration of the first body region and greater than the doping concentration of the second body region.

2. The IGBT structure according to claim 1, characterized in that, The doping concentration of the first doped region is greater than the doping concentration of the first body region and greater than the doping concentration of the second body region.

3. The IGBT structure according to claim 1, characterized in that, It also includes a third doped region disposed between the first body region and the second body region, wherein the doping concentration of the third doped region is less than the doping concentration of the first body region and less than the doping concentration of the second body region, wherein the third doped region and the second doped region are disposed in contact along the third direction.

4. The IGBT structure according to claim 3, characterized in that, The number of the third doped regions is at least two, and along the third direction, the third doped regions are located on both sides of the second doped region.

5. The IGBT structure according to claim 3, characterized in that, The number of the third doped region is at least two, and the number of the second doped region is at least two, with the second doped region and the third doped region being alternately arranged along the third direction.

6. The IGBT structure according to claim 1, characterized in that, The IGBT structure also includes: An insulating layer is disposed on the first main surface, and the portion of the insulating layer corresponding to the first emitting region and the second emitting region is provided with contact holes; An emitter metal is disposed on the side of the insulating layer away from the second main surface, and the first emitting region and the second emitting region are in contact with the emitter metal through the contact hole.

7. The IGBT structure according to claim 6, characterized in that, The virtual gate is disposed in the first gate trench, the first gate trench extends from the first main surface to the second main surface into the drift region, and the virtual gate includes a first gate dielectric layer located on the inner surface of the first gate trench and a first polysilicon gate located on the side of the first gate dielectric layer away from the inner surface of the first gate trench and filling the first gate trench. The first polysilicon gate is electrically connected to the emitter metal.

8. The IGBT structure according to claim 6, characterized in that, The active gate is disposed in the second gate trench, which extends from the first main surface to the second main surface into the drift region. The active gate includes a second gate dielectric layer located on the inner surface of the second gate trench and a second polysilicon gate located on the side of the second gate dielectric layer away from the inner surface of the second gate trench and filling the second gate trench.

9. The IGBT structure according to any one of claims 1-7, characterized in that, Also includes: The field cutoff region is located on the side of the drift region away from the first main surface; The collector region is located on the side of the field cutoff region away from the first main surface; as well as Collector metal, the collector metal being disposed on the second main surface and covering at least a portion of the collector region.

10. A semiconductor device, characterized in that, The semiconductor device comprises the IGBT structure according to any one of claims 1-9.

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